From f03cd7c3ba9184ab7ffb33670a1d742b148ec12d Mon Sep 17 00:00:00 2001 From: Michael Timothy Grimes Date: Wed, 12 Sep 2018 20:22:12 -0700 Subject: [PATCH] Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules. --- compiler/options.py | 2 - compiler/tests/04_precharge_test.py | 28 ++++++------ .../tests/04_single_level_column_mux_test.py | 30 ++++++------- .../tests/06_hierarchical_decoder_test.py | 23 ++++++++++ .../06_hierarchical_predecode2x4_test.py | 11 +++++ .../06_hierarchical_predecode3x8_test.py | 11 +++++ .../07_single_level_column_mux_array_test.py | 44 +++++++++---------- compiler/tests/08_precharge_array_test.py | 29 ++++++------ compiler/tests/08_wordline_driver_test.py | 19 ++++---- compiler/tests/09_sense_amp_array_test.py | 25 ++++++----- compiler/tests/10_write_driver_array_test.py | 25 ++++++----- 11 files changed, 144 insertions(+), 103 deletions(-) mode change 100755 => 100644 compiler/tests/06_hierarchical_decoder_test.py mode change 100755 => 100644 compiler/tests/06_hierarchical_predecode2x4_test.py mode change 100755 => 100644 compiler/tests/06_hierarchical_predecode3x8_test.py diff --git a/compiler/options.py b/compiler/options.py index 4d522465..5298c00f 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -50,8 +50,6 @@ class options(optparse.Values): analytical_delay = True # Purge the temp directory after a successful run (doesn't purge on errors, anyhow) purge_temp = True - # Determines whether multi-port portion of unit tests are run or not - multiport_check = True # These are the configuration parameters num_rw_ports = 1 diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index a68585bb..02de2efd 100644 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -18,24 +18,24 @@ class precharge_test(openram_test): import precharge import tech + # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") tx = precharge.precharge(name="precharge_driver", size=1) self.local_check(tx) - if OPTS.multiport_check: - debug.info(2, "Checking precharge for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(tx) - - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1") - self.local_check(tx) - - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(tx) + # check precharge in multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + debug.info(2, "Checking precharge for pbitcell (innermost connections)") + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + debug.info(2, "Checking precharge for pbitcell (outermost connections)") + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 6437c58d..3a7d6399 100644 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -19,25 +19,25 @@ class single_level_column_mux_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import single_level_column_mux import tech - + + # check single level column mux in single port debug.info(2, "Checking column mux") tx = single_level_column_mux.single_level_column_mux(tx_size=8) self.local_check(tx) - if OPTS.multiport_check: - debug.info(2, "Checking column mux for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(tx) - - tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl1", bitcell_br="br1") - self.local_check(tx) - - tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(tx) + # check single level column mux in multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + debug.info(2, "Checking column mux for pbitcell (innermost connections)") + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + debug.info(2, "Checking column mux for pbitcell (outermost connections)") + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py old mode 100755 new mode 100644 index ab4f5f90..513e07a8 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -28,6 +28,7 @@ class hierarchical_decoder_test(openram_test): # a = hierarchical_decoder.hierarchical_decoder(rows=8) # self.local_check(a) + # check hierarchical decoder for single port debug.info(1, "Testing 16 row sample for hierarchical_decoder") a = hierarchical_decoder.hierarchical_decoder(rows=16) self.local_check(a) @@ -43,6 +44,28 @@ class hierarchical_decoder_test(openram_test): debug.info(1, "Testing 512 row sample for hierarchical_decoder") a = hierarchical_decoder.hierarchical_decoder(rows=512) self.local_check(a) + + # check hierarchical decoder for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") + a = hierarchical_decoder.hierarchical_decoder(rows=16) + self.local_check(a) + + debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)") + a = hierarchical_decoder.hierarchical_decoder(rows=32) + self.local_check(a) + + debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)") + a = hierarchical_decoder.hierarchical_decoder(rows=128) + self.local_check(a) + + debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)") + a = hierarchical_decoder.hierarchical_decoder(rows=512) + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py old mode 100755 new mode 100644 index 80b95b46..bcfd207a --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -18,10 +18,21 @@ class hierarchical_predecode2x4_test(openram_test): import hierarchical_predecode2x4 as pre import tech + # checking hierarchical precode 2x4 for single port debug.info(1, "Testing sample for hierarchy_predecode2x4") a = pre.hierarchical_predecode2x4() self.local_check(a) + # checking hierarchical precode 2x4 for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)") + a = pre.hierarchical_predecode2x4() + self.local_check(a) + globals.end_openram() # instantiate a copdsay of the class to actually run the test diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py old mode 100755 new mode 100644 index 0974ced3..b89f4bea --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -18,9 +18,20 @@ class hierarchical_predecode3x8_test(openram_test): import hierarchical_predecode3x8 as pre import tech + # checking hierarchical precode 3x8 for single port debug.info(1, "Testing sample for hierarchy_predecode3x8") a = pre.hierarchical_predecode3x8() self.local_check(a) + + # checking hierarchical precode 3x8 for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)") + a = pre.hierarchical_predecode3x8() + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index 77a1358e..63f69bc5 100644 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -16,6 +16,7 @@ class single_level_column_mux_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import single_level_column_mux_array + # check single level column mux array in single port debug.info(1, "Testing sample for 2-way column_mux_array") a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8) self.local_check(a) @@ -28,32 +29,27 @@ class single_level_column_mux_test(openram_test): a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4) self.local_check(a) - if OPTS.multiport_check: - debug.info(2, "Checking column mux array for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - - debug.info(1, "Testing sample for 2-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(a) + # check single level column mux array in multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") + a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) - debug.info(1, "Testing sample for 4-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(a) + debug.info(1, "Testing sample for 4-way column_mux_array in multi-port") + a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) - debug.info(1, "Testing sample for 8-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(a) - - debug.info(1, "Testing sample for 8-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl1", bitcell_br="br1") - self.local_check(a) - - debug.info(1, "Testing sample for 8-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(a) + debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index 1e82c69b..be8fc9d7 100644 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -18,25 +18,24 @@ class precharge_test(openram_test): import precharge_array import tech + # check precharge array in single port debug.info(2, "Checking 3 column precharge") pc = precharge_array.precharge_array(columns=3) self.local_check(pc) - if OPTS.multiport_check: - debug.info(2, "Checking precharge array for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - - pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(pc) - - pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl1", bitcell_br="br1") - self.local_check(pc) - - pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(pc) + # check precharge array in multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(pc) + + debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)") + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(pc) globals.end_openram() diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index f69a3c02..7f0ca275 100644 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -20,19 +20,20 @@ class wordline_driver_test(openram_test): import wordline_driver import tech + # check wordline driver for single port debug.info(2, "Checking driver") tx = wordline_driver.wordline_driver(rows=8) self.local_check(tx) - if OPTS.multiport_check: - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(2, "Checking driver (multi-port case)") - tx = wordline_driver.wordline_driver(rows=8) - self.local_check(tx) + # check wordline driver for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(2, "Checking driver (multi-port case)") + tx = wordline_driver.wordline_driver(rows=8) + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index d167a752..af2c974c 100644 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -17,6 +17,7 @@ class sense_amp_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import sense_amp_array + # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2) self.local_check(a) @@ -25,19 +26,19 @@ class sense_amp_test(openram_test): a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4) self.local_check(a) - if OPTS.multiport_check: - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") - a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2) - self.local_check(a) + # check sense amp array for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") + a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2) + self.local_check(a) - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") - a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4) - self.local_check(a) + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") + a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4) + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 7ede24dd..ab9dc615 100644 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -17,6 +17,7 @@ class write_driver_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import write_driver_array + # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") a = write_driver_array.write_driver_array(columns=8, word_size=8) self.local_check(a) @@ -25,19 +26,19 @@ class write_driver_test(openram_test): a = write_driver_array.write_driver_array(columns=16, word_size=8) self.local_check(a) - if OPTS.multiport_check: - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") - a = write_driver_array.write_driver_array(columns=8, word_size=8) - self.local_check(a) + # check write driver array for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") + a = write_driver_array.write_driver_array(columns=8, word_size=8) + self.local_check(a) - debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") - a = write_driver_array.write_driver_array(columns=16, word_size=8) - self.local_check(a) + debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") + a = write_driver_array.write_driver_array(columns=16, word_size=8) + self.local_check(a) globals.end_openram()