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make split wl specific to each port

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This commit is contained in:
jcirimel
2020-09-23 00:08:34 -07:00
parent fb6a665514
commit efdc171b14
12 changed files with 74 additions and 46 deletions
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compiler/modules/bitcell_array.py
+2 -2
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@@ -47,7 +47,7 @@ class bitcell_array(bitcell_base_array):
def add_modules(self):
""" Add the modules used in this design """
if not props.use_custom_bitcell_array(props.bitcell_array.use_custom_cell_arrangement):
if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
self.cell = factory.create(module_type="bitcell")
self.add_mod(self.cell)
@@ -74,7 +74,7 @@ class bitcell_array(bitcell_base_array):
def create_instances(self):
""" Create the module instances used in this design """
self.cell_inst = {}
if not props.use_custom_bitcell_array(props.bitcell_array.use_custom_cell_arrangement):
if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)