diff --git a/.vscode/launch.json b/.vscode/launch.json index 2ba2b9c2..e057ef0f 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -51,7 +51,7 @@ "name": "decoder", "type": "python", "request": "launch", - "program": "/home/jesse/openram/compiler/tests/05_bitcell_array_test.py", + "program": "/home/jesse/openram/compiler/tests/05_bitcell_array_1rw_1r_test.py", "console": "integratedTerminal", "args": ["-s", "ngspice", "-d", "-t", "sky130", "-v"] } diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index acb5f701..d0244aaa 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -175,7 +175,7 @@ class cell_properties(): def bitcell_array(self): return self._bitcell_array - def use_custom_bitcell_array(self, port_list): + def compare_ports(self, port_list): use_custom_arrangement = False for ports in port_list: if ports == "{}R_{}W_{}RW".format(OPTS.num_r_ports, OPTS.num_w_ports, OPTS.num_rw_ports): diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index a8e48de6..48467121 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -23,7 +23,7 @@ class bitcell(bitcell_base.bitcell_base): # If we have a split WL bitcell, if not be backwards # compatible in the tech file - if props.bitcell.split_wl: + if props.compare_ports(props.bitcell.split_wl): pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] else: @@ -55,7 +55,7 @@ class bitcell(bitcell_base.bitcell_base): def get_all_wl_names(self): """ Creates a list of all wordline pin names """ - if props.bitcell.split_wl: + if props.compare_ports(props.bitcell.split_wl): row_pins = ["wl0", "wl1"] else: row_pins = [props.bitcell.cell_6t.pin.wl] @@ -87,7 +87,7 @@ class bitcell(bitcell_base.bitcell_base): def get_wl_name(self, port=0): """Get wl name""" - if props.bitcell.split_wl: + if props.compare_ports(props.bitcell.split_wl): return "wl{}".format(port) else: debug.check(port == 0, "One port for bitcell only.") diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py index ff9bc382..b8d5d7ff 100644 --- a/compiler/bitcells/replica_bitcell.py +++ b/compiler/bitcells/replica_bitcell.py @@ -20,7 +20,7 @@ class s8_replica_bitcell(design.design): is a hand-made cell, so the layout and netlist should be available in the technology library. """ - if cell_properties.bitcell.split_wl: + if cell_properties.compare_ports(cell_properties.bitcell.split_wl): pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"] else: diff --git a/compiler/custom/s8_bitcell.py b/compiler/custom/s8_bitcell.py index ff930c21..2905924a 100644 --- a/compiler/custom/s8_bitcell.py +++ b/compiler/custom/s8_bitcell.py @@ -23,7 +23,7 @@ class s8_bitcell(bitcell_base.bitcell_base): # If we have a split WL bitcell, if not be backwards # compatible in the tech file - if props.bitcell.split_wl: + if props.compare_ports(props.bitcell.split_wl): pin_names = ["bl0", "bl1", "wl0", "wl1", "vpwr", "vgnd"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] else: @@ -66,7 +66,7 @@ class s8_bitcell(bitcell_base.bitcell_base): def get_all_wl_names(self): """ Creates a list of all wordline pin names """ - if props.bitcell.split_wl: + if props.compare_ports(props.bitcell.split_wl): row_pins = ["wl0", "wl1"] else: row_pins = [props.bitcell.s8_sp.pin.wl] @@ -98,7 +98,7 @@ class s8_bitcell(bitcell_base.bitcell_base): def get_wl_name(self, port=0): """Get wl name""" - if props.bitcell.split_wl: + if props.compare_ports(props.bitcell.split_wl): return "wl{}".format(port) else: debug.check(port == 0, "One port for bitcell only.") diff --git a/compiler/custom/s8_replica_bitcell.py b/compiler/custom/s8_replica_bitcell.py index 479883d9..dd8fae0c 100644 --- a/compiler/custom/s8_replica_bitcell.py +++ b/compiler/custom/s8_replica_bitcell.py @@ -20,7 +20,7 @@ class replica_bitcell(design.design): is a hand-made cell, so the layout and netlist should be available in the technology library. """ - if cell_properties.bitcell.split_wl: + if props.compare_ports(props.bitcell.split_wl): pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"] else: diff --git a/compiler/example_configs/s8config.py b/compiler/example_configs/s8config.py index f4f0a77d..7c0de527 100644 --- a/compiler/example_configs/s8config.py +++ b/compiler/example_configs/s8config.py @@ -2,7 +2,7 @@ word_size = 16 num_words = 16 num_rw_ports = 1 -num_r_ports = 0 +num_r_ports = 1 num_w_ports = 0 tech_name = "sky130" diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index f51796f9..d66c04cd 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -47,7 +47,7 @@ class bitcell_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ - if not props.use_custom_bitcell_array(props.bitcell_array.use_custom_cell_arrangement): + if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement): self.cell = factory.create(module_type="bitcell") self.add_mod(self.cell) @@ -74,7 +74,7 @@ class bitcell_array(bitcell_base_array): def create_instances(self): """ Create the module instances used in this design """ self.cell_inst = {} - if not props.use_custom_bitcell_array(props.bitcell_array.use_custom_cell_arrangement): + if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement): for col in range(self.column_size): for row in range(self.row_size): name = "bit_r{0}_c{1}".format(row, col) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index ff8a361f..2181df10 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -26,7 +26,7 @@ class bitcell_base_array(design.design): self.column_offset = column_offset # Bitcell for port names only - if OPTS.tech_name != "sky130": + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): self.cell = factory.create(module_type="bitcell") else: self.cell = factory.create(module_type="s8_bitcell", version="opt1") @@ -56,7 +56,7 @@ class bitcell_base_array(design.design): self.wordline_names = [[] for port in self.all_ports] for row in range(self.row_size): for port in self.all_ports: - if not cell_properties.bitcell.split_wl: + if not cell_properties.compare_ports(cell_properties.bitcell.split_wl): self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) else: self.wordline_names[port].append("wl0_{0}_{1}".format(port, row)) @@ -76,7 +76,7 @@ class bitcell_base_array(design.design): return self.wordline_names[port] def add_pins(self): - if OPTS.tech_name != "sky130": + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): for bl_name in self.get_bitline_names(): self.add_pin(bl_name, "INOUT") for wl_name in self.get_wordline_names(): @@ -104,7 +104,7 @@ class bitcell_base_array(design.design): def add_layout_pins(self): """ Add the layout pins """ - if OPTS.tech_name != "sky130": + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): bitline_names = self.cell.get_all_bitline_names() for col in range(self.column_size): for port in self.all_ports: @@ -196,7 +196,7 @@ class bitcell_base_array(design.design): def place_array(self, name_template, row_offset=0): # We increase it by a well enclosure so the precharges don't overlap our wells - if not cell_properties.use_custom_bitcell_array(cell_properties.bitcell_array.use_custom_cell_arrangement): + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): self.height = self.row_size * self.cell.height self.width = self.column_size * self.cell.width diff --git a/compiler/sram_0.05/sram_16_16_sky130_0.05.log b/compiler/sram_0.05/sram_16_16_sky130_0.05.log index 13dbd2dd..b1a019e0 100644 --- a/compiler/sram_0.05/sram_16_16_sky130_0.05.log +++ b/compiler/sram_0.05/sram_16_16_sky130_0.05.log @@ -1,7 +1,9 @@ [globals/init_openram]: Initializing OpenRAM... +[globals/setup_paths]: Setting up paths... [globals/setup_paths]: Temporary files saved in /home/jesse/output/ [globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py [globals/read_config]: Output saved in /home/jesse/openram/compiler/sram_0.05/ +[globals/import_tech]: Importing technology: sky130 [globals/import_tech]: Adding technology path: /home/jesse/openram/technology [globals/init_paths]: Creating temp directory: /home/jesse/output/ [characterizer/]: Initializing characterizer... @@ -10,7 +12,7 @@ [verify/]: LVS/DRC/PEX disabled. WARNING: file __init__.py: line 79: Did not find Magic. -[globals/setup_bitcell]: Using bitcell: bitcell +[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r |==============================================================================| |========= OpenRAM v1.1.6 =========| |========= =========| @@ -23,7 +25,7 @@ WARNING: file __init__.py: line 79: Did not find Magic. |========= Temp dir: /home/jesse/output/ =========| |========= See LICENSE for license info =========| |==============================================================================| -** Start: 09/02/2020 02:58:03 +** Start: 09/22/2020 23:33:27 Technology: sky130 Total size: 256 bits Word size: 16 @@ -31,11 +33,12 @@ Words: 16 Banks: 1 Write size: 8 RW ports: 1 -R-only ports: 0 +R-only ports: 1 W-only ports: 0 DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). +[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port [sram_config/recompute_sizes]: Recomputing with words per row: 1 [sram_config/recompute_sizes]: Rows: 16 Cols: 16 [sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4 @@ -50,19 +53,64 @@ Output files are: /home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.log /home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.lef /home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.gds +[sram/__init__]: create sram of size 16 with 16 num of words 1 banks [dff_array/__init__]: Creating row_addr_dff rows=4 cols=1 [dff_array/__init__]: Creating data_dff rows=1 cols=16 [dff_array/__init__]: Creating wmask_dff rows=1 cols=2 +[bank/__init__]: create sram of size 16 with 16 words +[port_data/__init__]: create data port of size 16 with 1 words per row +[precharge/__init__]: creating precharge cell precharge +[pgate/best_bin]: binning pmos tx, target: 0.55, found 1 x 0.55 = 0.55 [precharge_array/__init__]: Creating precharge_array +[precharge/__init__]: creating precharge cell precharge_0 [sense_amp_array/__init__]: Creating sense_amp_array +[sense_amp/__init__]: Create sense_amp [write_driver_array/__init__]: Creating write_driver_array +[write_driver/__init__]: Create write_driver [write_mask_and_array/__init__]: Creating write_mask_and_array [pand2/__init__]: Creating pand2 pand2 +[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1 +[pgate/best_bin]: binning nmos tx, target: 0.74, found 1 x 0.74 = 0.74 +[pgate/best_bin]: binning nmos tx, target: 0.74, found 1 x 0.74 = 0.74 +[pgate/best_bin]: binning pmos tx, target: 1.12, found 1 x 1.12 = 1.12 [pdriver/__init__]: creating pdriver pdriver +[pinv/__init__]: creating pinv structure pinv with size of 2.0 +[pgate/best_bin]: binning nmos tx, target: 0.36, found 1 x 0.36 = 0.36 +[pgate/best_bin]: binning pmos tx, target: 0.36, found 1 x 0.42 = 0.42 +[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000 +[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 2.0 x 2 = 4.0 +[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74 +[pinv/determine_tx_mults]: pinv bin count: 2 pinv bin error: 0.8796296296296295 percent error 0.43981481481481477 +[pgate/best_bin]: binning nmos tx, target: 0.74, found 1 x 0.74 = 0.74 +[pgate/best_bin]: binning pmos tx, target: 2.0, found 1 x 2.0 = 2.0 +[port_data/__init__]: create data port of size 16 with 1 words per row +[precharge_array/__init__]: Creating precharge_array_0 +[precharge/__init__]: creating precharge cell precharge_1 +[port_address/__init__]: create data port of cols 16 rows 16 [and2_dec/__init__]: Creating and2_dec and2_dec +[pinv_dec/__init__]: creating pinv_dec structure pinv_dec with size of 1 +[pinv/__init__]: creating pinv structure pinv_dec with size of 1 +[pgate/best_bin]: binning nmos tx, target: 0.36, found 1 x 0.36 = 0.36 +[pgate/best_bin]: binning pmos tx, target: 1.12, found 1 x 1.12 = 1.12 [and3_dec/__init__]: Creating and3_dec and3_dec [wordline_driver_array/__init__]: Creating wordline_driver_array [wordline_driver/__init__]: Creating wordline_driver wordline_driver +[pinv_dec/__init__]: creating pinv_dec structure pinv_dec_0 with size of 16 +[pinv/__init__]: creating pinv structure pinv_dec_0 with size of 16 +[pgate/best_bin]: binning nmos tx, target: 7.0, found 1 x 7.0 = 7.0 +[pgate/best_bin]: binning pmos tx, target: 7.0, found 1 x 7.0 = 7.0 [bitcell_base_array/__init__]: Creating replica_bitcell_array 16 x 16 -ERROR: file vlsiLayout.py: line 609: Error: s8sram_cell_opt1.cell_size information not found yet +[replica_bitcell_array/__init__]: Creating replica_bitcell_array 16 x 16 +[bitcell_base_array/__init__]: Creating bitcell_array 16 x 16 +[replica_bitcell_1rw_1r/__init__]: Create replica bitcell 1rw+1r object +[dummy_bitcell_1rw_1r/__init__]: Create dummy bitcell 1rw+1r object +[col_cap_bitcell_1rw_1r/__init__]: Create col_cap bitcell 1rw+1r object +ERROR: file hierarchy_spice.py: line 176: Connection mismatch: +Inst (6) -> Mod (5) +bl_0_0 -> bl0 +br_0_0 -> br0 +bl_1_0 -> bl1 +br_1_0 -> br1 +vdd -> vdd +gnd -> diff --git a/compiler/tests/sram_1b_16_1rw_sky130.log b/compiler/tests/sram_1b_16_1rw_sky130.log index 2644f2d5..506212d1 100644 --- a/compiler/tests/sram_1b_16_1rw_sky130.log +++ b/compiler/tests/sram_1b_16_1rw_sky130.log @@ -1,25 +1,4 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /home/jesse/output/ -[globals/read_config]: Configuration file is /home/jesse/openram/compiler/tests/configs/config.py -[globals/read_config]: Output saved in /home/jesse/openram/compiler/tests/./ -[globals/import_tech]: Adding technology path: /home/jesse/openram/technology -[globals/init_paths]: Creating temp directory: /home/jesse/output/ -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: Finding DRC/LVS/PEX tools. -[globals/get_tool]: Using DRC: /usr/local/bin/magic -[globals/get_tool]: Using LVS: /usr/local/bin/netgen -[globals/get_tool]: Using PEX: /usr/local/bin/magic -[globals/get_tool]: Using GDS: /usr/local/bin/magic -[bitcell_base_array/__init__]: Creating bitcell_array 8 x 8 -ERROR: file hierarchy_spice.py: line 307: bitcell_array : Not all instance pins (192) are connected (64). +WARNING: file magic.py: line 210: DRC Errors bitcell_array 9424 -ERROR: file hierarchy_spice.py: line 310: Instances: -[( inst: bit_r0_c0 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r1_c0 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r2_c0 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r3_c0 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r4_c0 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r5_c0 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r6_c0 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r7_c0 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r0_c1 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r1_c1 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r2_c1 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r3_c1 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r4_c1 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r5_c1 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r6_c1 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r7_c1 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r0_c2 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r1_c2 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r2_c2 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r3_c2 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r4_c2 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r5_c2 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r6_c2 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r7_c2 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r0_c3 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r1_c3 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r2_c3 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r3_c3 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r4_c3 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r5_c3 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r6_c3 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r7_c3 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r0_c4 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r1_c4 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r2_c4 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r3_c4 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r4_c4 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r5_c4 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r6_c4 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r7_c4 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r0_c5 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r1_c5 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r2_c5 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r3_c5 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r4_c5 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r5_c5 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r6_c5 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r7_c5 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r0_c6 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r1_c6 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r2_c6 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r3_c6 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r4_c6 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r5_c6 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r6_c6 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r7_c6 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r0_c7 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r1_c7 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r2_c7 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r3_c7 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r4_c7 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r5_c7 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r6_c7 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: bit_r7_c7 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_0, col_0 @v[0.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_0, col_1 @v[1.2,0.0] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_0, col_2 @v[2.5,0.0] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_0, col_3 @v[3.7,0.0] mod=s8sram_wlstrap R0 R=0), ( inst: row_0, col_4 @v[5.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_0, col_5 @v[6.2,0.0] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_0, col_6 @v[7.5,0.0] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_0, col_7 @v[8.700000000000001,0.0] mod=s8sram_wlstrap R0 R=0), ( inst: row_0, col_8 @v[10.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_0, col_9 @v[11.200000000000001,0.0] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_0, col_10 @v[12.5,0.0] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_0, col_11 @v[13.700000000000001,0.0] mod=s8sram_wlstrap R0 R=0), ( inst: row_0, col_12 @v[15.0,0.0] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_0, col_13 @v[16.2,0.0] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_0, col_14 @v[17.5,0.0] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_0, col_15 @v[18.7,0.0] mod=s8sram_wlstrap R0 R=0), ( inst: row_1, col_0 @v[0.0,1.58] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_1, col_1 @v[1.2,1.58] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_1, col_2 @v[2.5,1.58] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_1, col_3 @v[3.7,1.58] mod=s8sram_wlstrap R0 R=0), ( inst: row_1, col_4 @v[5.0,1.58] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_1, col_5 @v[6.2,1.58] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_1, col_6 @v[7.5,1.58] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_1, col_7 @v[8.700000000000001,1.58] mod=s8sram_wlstrap R0 R=0), ( inst: row_1, col_8 @v[10.0,1.58] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_1, col_9 @v[11.200000000000001,1.58] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_1, col_10 @v[12.5,1.58] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_1, col_11 @v[13.700000000000001,1.58] mod=s8sram_wlstrap R0 R=0), ( inst: row_1, col_12 @v[15.0,1.58] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_1, col_13 @v[16.2,1.58] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_1, col_14 @v[17.5,1.58] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_1, col_15 @v[18.7,1.58] mod=s8sram_wlstrap R0 R=0), ( inst: row_2, col_0 @v[0.0,3.16] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_2, col_1 @v[1.2,3.16] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_2, col_2 @v[2.5,3.16] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_2, col_3 @v[3.7,3.16] mod=s8sram_wlstrap R0 R=0), ( inst: row_2, col_4 @v[5.0,3.16] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_2, col_5 @v[6.2,3.16] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_2, col_6 @v[7.5,3.16] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_2, col_7 @v[8.700000000000001,3.16] mod=s8sram_wlstrap R0 R=0), ( inst: row_2, col_8 @v[10.0,3.16] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_2, col_9 @v[11.200000000000001,3.16] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_2, col_10 @v[12.5,3.16] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_2, col_11 @v[13.700000000000001,3.16] mod=s8sram_wlstrap R0 R=0), ( inst: row_2, col_12 @v[15.0,3.16] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_2, col_13 @v[16.2,3.16] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_2, col_14 @v[17.5,3.16] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_2, col_15 @v[18.7,3.16] mod=s8sram_wlstrap R0 R=0), ( inst: row_3, col_0 @v[0.0,4.74] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_3, col_1 @v[1.2,4.74] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_3, col_2 @v[2.5,4.74] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_3, col_3 @v[3.7,4.74] mod=s8sram_wlstrap R0 R=0), ( inst: row_3, col_4 @v[5.0,4.74] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_3, col_5 @v[6.2,4.74] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_3, col_6 @v[7.5,4.74] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_3, col_7 @v[8.700000000000001,4.74] mod=s8sram_wlstrap R0 R=0), ( inst: row_3, col_8 @v[10.0,4.74] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_3, col_9 @v[11.200000000000001,4.74] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_3, col_10 @v[12.5,4.74] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_3, col_11 @v[13.700000000000001,4.74] mod=s8sram_wlstrap R0 R=0), ( inst: row_3, col_12 @v[15.0,4.74] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_3, col_13 @v[16.2,4.74] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_3, col_14 @v[17.5,4.74] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_3, col_15 @v[18.7,4.74] mod=s8sram_wlstrap R0 R=0), ( inst: row_4, col_0 @v[0.0,6.32] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_4, col_1 @v[1.2,6.32] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_4, col_2 @v[2.5,6.32] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_4, col_3 @v[3.7,6.32] mod=s8sram_wlstrap R0 R=0), ( inst: row_4, col_4 @v[5.0,6.32] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_4, col_5 @v[6.2,6.32] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_4, col_6 @v[7.5,6.32] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_4, col_7 @v[8.700000000000001,6.32] mod=s8sram_wlstrap R0 R=0), ( inst: row_4, col_8 @v[10.0,6.32] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_4, col_9 @v[11.200000000000001,6.32] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_4, col_10 @v[12.5,6.32] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_4, col_11 @v[13.700000000000001,6.32] mod=s8sram_wlstrap R0 R=0), ( inst: row_4, col_12 @v[15.0,6.32] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_4, col_13 @v[16.2,6.32] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_4, col_14 @v[17.5,6.32] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_4, col_15 @v[18.7,6.32] mod=s8sram_wlstrap R0 R=0), ( inst: row_5, col_0 @v[0.0,7.9] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_5, col_1 @v[1.2,7.9] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_5, col_2 @v[2.5,7.9] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_5, col_3 @v[3.7,7.9] mod=s8sram_wlstrap R0 R=0), ( inst: row_5, col_4 @v[5.0,7.9] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_5, col_5 @v[6.2,7.9] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_5, col_6 @v[7.5,7.9] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_5, col_7 @v[8.700000000000001,7.9] mod=s8sram_wlstrap R0 R=0), ( inst: row_5, col_8 @v[10.0,7.9] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_5, col_9 @v[11.200000000000001,7.9] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_5, col_10 @v[12.5,7.9] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_5, col_11 @v[13.700000000000001,7.9] mod=s8sram_wlstrap R0 R=0), ( inst: row_5, col_12 @v[15.0,7.9] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_5, col_13 @v[16.2,7.9] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_5, col_14 @v[17.5,7.9] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_5, col_15 @v[18.7,7.9] mod=s8sram_wlstrap R0 R=0), ( inst: row_6, col_0 @v[0.0,9.48] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_6, col_1 @v[1.2,9.48] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_6, col_2 @v[2.5,9.48] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_6, col_3 @v[3.7,9.48] mod=s8sram_wlstrap R0 R=0), ( inst: row_6, col_4 @v[5.0,9.48] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_6, col_5 @v[6.2,9.48] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_6, col_6 @v[7.5,9.48] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_6, col_7 @v[8.700000000000001,9.48] mod=s8sram_wlstrap R0 R=0), ( inst: row_6, col_8 @v[10.0,9.48] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_6, col_9 @v[11.200000000000001,9.48] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_6, col_10 @v[12.5,9.48] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_6, col_11 @v[13.700000000000001,9.48] mod=s8sram_wlstrap R0 R=0), ( inst: row_6, col_12 @v[15.0,9.48] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_6, col_13 @v[16.2,9.48] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_6, col_14 @v[17.5,9.48] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_6, col_15 @v[18.7,9.48] mod=s8sram_wlstrap R0 R=0), ( inst: row_7, col_0 @v[0.0,11.06] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_7, col_1 @v[1.2,11.06] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_7, col_2 @v[2.5,11.06] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_7, col_3 @v[3.7,11.06] mod=s8sram_wlstrap R0 R=0), ( inst: row_7, col_4 @v[5.0,11.06] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_7, col_5 @v[6.2,11.06] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_7, col_6 @v[7.5,11.06] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_7, col_7 @v[8.700000000000001,11.06] mod=s8sram_wlstrap R0 R=0), ( inst: row_7, col_8 @v[10.0,11.06] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_7, col_9 @v[11.200000000000001,11.06] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_7, col_10 @v[12.5,11.06] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_7, col_11 @v[13.700000000000001,11.06] mod=s8sram_wlstrap R0 R=0), ( inst: row_7, col_12 @v[15.0,11.06] mod=s8sram_cell_opt1 R0 R=0), ( inst: row_7, col_13 @v[16.2,11.06] mod=s8sram16x16_wlstrap_p R0 R=0), ( inst: row_7, col_14 @v[17.5,11.06] mod=s8sram_cell_opt1a R0 R=0), ( inst: row_7, col_15 @v[18.7,11.06] mod=s8sram_wlstrap R0 R=0)] - -ERROR: file hierarchy_spice.py: line 311: ----- - -ERROR: file hierarchy_spice.py: line 312: Connections: -[['bl_0_0', 'br_0_0', 'wl0_0_0', 'wl1_0_0', 'vdd', 'gnd'], ['bl_0_0', 'br_0_0', 'wl0_0_1', 'wl1_0_1', 'vdd', 'gnd'], ['bl_0_0', 'br_0_0', 'wl0_0_2', 'wl1_0_2', 'vdd', 'gnd'], ['bl_0_0', 'br_0_0', 'wl0_0_3', 'wl1_0_3', 'vdd', 'gnd'], ['bl_0_0', 'br_0_0', 'wl0_0_4', 'wl1_0_4', 'vdd', 'gnd'], ['bl_0_0', 'br_0_0', 'wl0_0_5', 'wl1_0_5', 'vdd', 'gnd'], ['bl_0_0', 'br_0_0', 'wl0_0_6', 'wl1_0_6', 'vdd', 'gnd'], ['bl_0_0', 'br_0_0', 'wl0_0_7', 'wl1_0_7', 'vdd', 'gnd'], ['bl_0_1', 'br_0_1', 'wl0_0_0', 'wl1_0_0', 'vdd', 'gnd'], ['bl_0_1', 'br_0_1', 'wl0_0_1', 'wl1_0_1', 'vdd', 'gnd'], ['bl_0_1', 'br_0_1', 'wl0_0_2', 'wl1_0_2', 'vdd', 'gnd'], ['bl_0_1', 'br_0_1', 'wl0_0_3', 'wl1_0_3', 'vdd', 'gnd'], ['bl_0_1', 'br_0_1', 'wl0_0_4', 'wl1_0_4', 'vdd', 'gnd'], ['bl_0_1', 'br_0_1', 'wl0_0_5', 'wl1_0_5', 'vdd', 'gnd'], ['bl_0_1', 'br_0_1', 'wl0_0_6', 'wl1_0_6', 'vdd', 'gnd'], ['bl_0_1', 'br_0_1', 'wl0_0_7', 'wl1_0_7', 'vdd', 'gnd'], ['bl_0_2', 'br_0_2', 'wl0_0_0', 'wl1_0_0', 'vdd', 'gnd'], ['bl_0_2', 'br_0_2', 'wl0_0_1', 'wl1_0_1', 'vdd', 'gnd'], ['bl_0_2', 'br_0_2', 'wl0_0_2', 'wl1_0_2', 'vdd', 'gnd'], ['bl_0_2', 'br_0_2', 'wl0_0_3', 'wl1_0_3', 'vdd', 'gnd'], ['bl_0_2', 'br_0_2', 'wl0_0_4', 'wl1_0_4', 'vdd', 'gnd'], ['bl_0_2', 'br_0_2', 'wl0_0_5', 'wl1_0_5', 'vdd', 'gnd'], ['bl_0_2', 'br_0_2', 'wl0_0_6', 'wl1_0_6', 'vdd', 'gnd'], ['bl_0_2', 'br_0_2', 'wl0_0_7', 'wl1_0_7', 'vdd', 'gnd'], ['bl_0_3', 'br_0_3', 'wl0_0_0', 'wl1_0_0', 'vdd', 'gnd'], ['bl_0_3', 'br_0_3', 'wl0_0_1', 'wl1_0_1', 'vdd', 'gnd'], ['bl_0_3', 'br_0_3', 'wl0_0_2', 'wl1_0_2', 'vdd', 'gnd'], ['bl_0_3', 'br_0_3', 'wl0_0_3', 'wl1_0_3', 'vdd', 'gnd'], ['bl_0_3', 'br_0_3', 'wl0_0_4', 'wl1_0_4', 'vdd', 'gnd'], ['bl_0_3', 'br_0_3', 'wl0_0_5', 'wl1_0_5', 'vdd', 'gnd'], ['bl_0_3', 'br_0_3', 'wl0_0_6', 'wl1_0_6', 'vdd', 'gnd'], ['bl_0_3', 'br_0_3', 'wl0_0_7', 'wl1_0_7', 'vdd', 'gnd'], ['bl_0_4', 'br_0_4', 'wl0_0_0', 'wl1_0_0', 'vdd', 'gnd'], ['bl_0_4', 'br_0_4', 'wl0_0_1', 'wl1_0_1', 'vdd', 'gnd'], ['bl_0_4', 'br_0_4', 'wl0_0_2', 'wl1_0_2', 'vdd', 'gnd'], ['bl_0_4', 'br_0_4', 'wl0_0_3', 'wl1_0_3', 'vdd', 'gnd'], ['bl_0_4', 'br_0_4', 'wl0_0_4', 'wl1_0_4', 'vdd', 'gnd'], ['bl_0_4', 'br_0_4', 'wl0_0_5', 'wl1_0_5', 'vdd', 'gnd'], ['bl_0_4', 'br_0_4', 'wl0_0_6', 'wl1_0_6', 'vdd', 'gnd'], ['bl_0_4', 'br_0_4', 'wl0_0_7', 'wl1_0_7', 'vdd', 'gnd'], ['bl_0_5', 'br_0_5', 'wl0_0_0', 'wl1_0_0', 'vdd', 'gnd'], ['bl_0_5', 'br_0_5', 'wl0_0_1', 'wl1_0_1', 'vdd', 'gnd'], ['bl_0_5', 'br_0_5', 'wl0_0_2', 'wl1_0_2', 'vdd', 'gnd'], ['bl_0_5', 'br_0_5', 'wl0_0_3', 'wl1_0_3', 'vdd', 'gnd'], ['bl_0_5', 'br_0_5', 'wl0_0_4', 'wl1_0_4', 'vdd', 'gnd'], ['bl_0_5', 'br_0_5', 'wl0_0_5', 'wl1_0_5', 'vdd', 'gnd'], ['bl_0_5', 'br_0_5', 'wl0_0_6', 'wl1_0_6', 'vdd', 'gnd'], ['bl_0_5', 'br_0_5', 'wl0_0_7', 'wl1_0_7', 'vdd', 'gnd'], ['bl_0_6', 'br_0_6', 'wl0_0_0', 'wl1_0_0', 'vdd', 'gnd'], ['bl_0_6', 'br_0_6', 'wl0_0_1', 'wl1_0_1', 'vdd', 'gnd'], ['bl_0_6', 'br_0_6', 'wl0_0_2', 'wl1_0_2', 'vdd', 'gnd'], ['bl_0_6', 'br_0_6', 'wl0_0_3', 'wl1_0_3', 'vdd', 'gnd'], ['bl_0_6', 'br_0_6', 'wl0_0_4', 'wl1_0_4', 'vdd', 'gnd'], ['bl_0_6', 'br_0_6', 'wl0_0_5', 'wl1_0_5', 'vdd', 'gnd'], ['bl_0_6', 'br_0_6', 'wl0_0_6', 'wl1_0_6', 'vdd', 'gnd'], ['bl_0_6', 'br_0_6', 'wl0_0_7', 'wl1_0_7', 'vdd', 'gnd'], ['bl_0_7', 'br_0_7', 'wl0_0_0', 'wl1_0_0', 'vdd', 'gnd'], ['bl_0_7', 'br_0_7', 'wl0_0_1', 'wl1_0_1', 'vdd', 'gnd'], ['bl_0_7', 'br_0_7', 'wl0_0_2', 'wl1_0_2', 'vdd', 'gnd'], ['bl_0_7', 'br_0_7', 'wl0_0_3', 'wl1_0_3', 'vdd', 'gnd'], ['bl_0_7', 'br_0_7', 'wl0_0_4', 'wl1_0_4', 'vdd', 'gnd'], ['bl_0_7', 'br_0_7', 'wl0_0_5', 'wl1_0_5', 'vdd', 'gnd'], ['bl_0_7', 'br_0_7', 'wl0_0_6', 'wl1_0_6', 'vdd', 'gnd'], ['bl_0_7', 'br_0_7', 'wl0_0_7', 'wl1_0_7', 'vdd', 'gnd']] +ERROR: file magic.py: line 285: bitcell_array LVS mismatch (results in /home/jesse/output/bitcell_array.lvs.report) diff --git a/sram_1b_16_1rw_sky130.log b/sram_1b_16_1rw_sky130.log index 4af9187d..85b20c99 100644 --- a/sram_1b_16_1rw_sky130.log +++ b/sram_1b_16_1rw_sky130.log @@ -12,4 +12,5 @@ [globals/get_tool]: Using LVS: /usr/local/bin/netgen [globals/get_tool]: Using PEX: /usr/local/bin/magic [globals/get_tool]: Using GDS: /usr/local/bin/magic -[bitcell_base_array/__init__]: Creating bitcell_array 8 x 8 +[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r +[bitcell_base_array/__init__]: Creating bitcell_array 4 x 4