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make split wl specific to each port

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This commit is contained in:
jcirimel
2020-09-23 00:08:34 -07:00
parent fb6a665514
commit efdc171b14
12 changed files with 74 additions and 46 deletions
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compiler/custom/s8_bitcell.py
+3 -3
View File
@@ -23,7 +23,7 @@ class s8_bitcell(bitcell_base.bitcell_base):
# If we have a split WL bitcell, if not be backwards
# compatible in the tech file
if props.bitcell.split_wl:
if props.compare_ports(props.bitcell.split_wl):
pin_names = ["bl0", "bl1", "wl0", "wl1", "vpwr", "vgnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
else:
@@ -66,7 +66,7 @@ class s8_bitcell(bitcell_base.bitcell_base):
def get_all_wl_names(self):
""" Creates a list of all wordline pin names """
if props.bitcell.split_wl:
if props.compare_ports(props.bitcell.split_wl):
row_pins = ["wl0", "wl1"]
else:
row_pins = [props.bitcell.s8_sp.pin.wl]
@@ -98,7 +98,7 @@ class s8_bitcell(bitcell_base.bitcell_base):
def get_wl_name(self, port=0):
"""Get wl name"""
if props.bitcell.split_wl:
if props.compare_ports(props.bitcell.split_wl):
return "wl{}".format(port)
else:
debug.check(port == 0, "One port for bitcell only.")
compiler/custom/s8_replica_bitcell.py
+1 -1
View File
@@ -20,7 +20,7 @@ class replica_bitcell(design.design):
is a hand-made cell, so the layout and netlist should be available in
the technology library. """
if cell_properties.bitcell.split_wl:
if props.compare_ports(props.bitcell.split_wl):
pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"]
else: