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@@ -6,6 +6,7 @@
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# All rights reserved.
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#
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# This file aiming to create the sram module without routing
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# provide methods of seperated lef file generation
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import datetime
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from math import ceil
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from importlib import import_module, reload
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@@ -253,35 +254,7 @@ class sram_1bank(design, verilog, lef):
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design=self)
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pl.add_io_pins(pins_to_route)
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#pl.design.remove_layout_pin("wmask0[0]") # this could use for deleting pins
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'''
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# add the corresponding pin to the edge, the io pin will be put defaut as the nearest edge
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for pin_name in pins_to_route:
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ll, ur = bbox
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pin = self.get_pin(pin_name)
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print(pin)
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c = pin.center()
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# Find the closest edge
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edge, vertical = self.get_closest_edge(c,bbox=bbox)
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# Keep the fake pin out of the SRAM layout are so that they won't be
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# blocked by previous signals if they're on the same orthogonal line
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if edge == "left":
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fake_center = vector(ll.x - rtr.track_wire * 2, c.y)
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if edge == "bottom":
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fake_center = vector(c.x, ll.y - rtr.track_wire * 2)
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if edge == "right":
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fake_center = vector(ur.x + rtr.track_wire * 2, c.y)
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if edge == "top":
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fake_center = vector(c.x, ur.y + rtr.track_wire * 2)
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# Create the fake pin shape
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layer = rtr.get_layer(int(not vertical))
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self.add_layout_pin_rect_center(text=pin_name + "_IO",
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layer=layer,
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offset=fake_center)
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rtr.add_perimeter_fake_pins()
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'''
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def get_closest_edge(self, point, bbox):
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""" Return a point's the closest edge and the edge's axis direction. """
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