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This commit is contained in:
FriedrichWu
2024-09-17 11:54:30 +02:00
parent 20e454925a
commit ee6be23cfa
6 changed files with 2387 additions and 32 deletions
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+1 -28
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@@ -6,6 +6,7 @@
# All rights reserved.
#
# This file aiming to create the sram module without routing
# provide methods of seperated lef file generation
import datetime
from math import ceil
from importlib import import_module, reload
@@ -253,35 +254,7 @@ class sram_1bank(design, verilog, lef):
design=self)
pl.add_io_pins(pins_to_route)
#pl.design.remove_layout_pin("wmask0[0]") # this could use for deleting pins
'''
# add the corresponding pin to the edge, the io pin will be put defaut as the nearest edge
for pin_name in pins_to_route:
ll, ur = bbox
pin = self.get_pin(pin_name)
print(pin)
c = pin.center()
# Find the closest edge
edge, vertical = self.get_closest_edge(c,bbox=bbox)
# Keep the fake pin out of the SRAM layout are so that they won't be
# blocked by previous signals if they're on the same orthogonal line
if edge == "left":
fake_center = vector(ll.x - rtr.track_wire * 2, c.y)
if edge == "bottom":
fake_center = vector(c.x, ll.y - rtr.track_wire * 2)
if edge == "right":
fake_center = vector(ur.x + rtr.track_wire * 2, c.y)
if edge == "top":
fake_center = vector(c.x, ur.y + rtr.track_wire * 2)
# Create the fake pin shape
layer = rtr.get_layer(int(not vertical))
self.add_layout_pin_rect_center(text=pin_name + "_IO",
layer=layer,
offset=fake_center)
rtr.add_perimeter_fake_pins()
'''
def get_closest_edge(self, point, bbox):
""" Return a point's the closest edge and the edge's axis direction. """