mirror of https://github.com/VLSIDA/OpenRAM.git
269 lines
11 KiB
Python
269 lines
11 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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# This file generate sram part, aiming at using openroad to do the P&R
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import os
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import shutil
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import datetime
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from openram import debug
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from openram import sram_config as config
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from openram import OPTS, print_time
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class sram():
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"""
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This is not a design module, but contains an SRAM design instance.
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It could later try options of number of banks and organization to compare
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results.
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We can later add visualizer and other high-level functions as needed.
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"""
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def __init__(self, sram_config=None, name=None, mod=0):
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# Create default configs if custom config isn't provided
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if sram_config is None:
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sram_config = config(word_size=OPTS.word_size,
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num_words=OPTS.num_words,
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write_size=OPTS.write_size,
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num_banks=OPTS.num_banks,
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words_per_row=OPTS.words_per_row,
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num_spare_rows=OPTS.num_spare_rows,
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num_spare_cols=OPTS.num_spare_cols)
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# maybe this part should be put after set_local_config, so we could calculate the number of port and define file name
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if name is None:
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#name = OPTS.output_name
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if mod == 0:
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name = OPTS.output_name + "_bank_" + "0"
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elif mod == 1:# not consider multi-port yet!!!!!!
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name = OPTS.output_name + "_control_" + "0"
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elif mod == 2:
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name = OPTS.output_name + "_row_addr_dff_" + "0"
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elif mod == 3:
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name = OPTS.output_name + "_col_addr_dff_" + "0"
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elif mod == 4:
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name = OPTS.output_name + "_data_dff_" + "0"
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elif mod == 5:
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name = OPTS.output_name + "_wmask_dff_" + "0"
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elif mod == 6:
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name = OPTS.output_name + "_spare_wen_dff_" + "0"
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sram_config.set_local_config(self)
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# reset the static duplicate name checker for unit tests
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# in case we create more than one SRAM
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from openram.base import design
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design.name_map=[]
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debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size,
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self.num_words,
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self.num_banks))
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start_time = datetime.datetime.now()
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self.name = name
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#from openram.modules.sram_1bank import sram_1bank as sram
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from openram.modules.sram_for_road import sram_for_road as sram
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self.s = sram(name, sram_config)
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def get_sp_name(self):
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if OPTS.use_pex:
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# Use the extracted spice file
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return self.pex_name
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else:
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# Use generated spice file for characterization
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return self.sp_name
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def sp_write(self, name, lvs=False, trim=False):
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self.s.sp_write(name, lvs, trim)
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def lef_write(self, name):
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self.s.lef_write(name)
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def gds_write(self, name):
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self.s.gds_write(name)
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def verilog_write(self, name):
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self.s.verilog_write(name)
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if self.num_banks != 1:
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from openram.modules.sram_multibank import sram_multibank
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mb = sram_multibank(self.s)
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mb.verilog_write(name[:-2] + '_top.v')
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def extended_config_write(self, name):
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"""Dump config file with all options.
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Include defaults and anything changed by input config."""
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f = open(name, "w")
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var_dict = dict((name, getattr(OPTS, name)) for name in dir(OPTS) if not name.startswith('__') and not callable(getattr(OPTS, name)))
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for var_name, var_value in var_dict.items():
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if isinstance(var_value, str):
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f.write(str(var_name) + " = " + "\"" + str(var_value) + "\"\n")
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else:
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f.write(str(var_name) + " = " + str(var_value)+ "\n")
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f.close()
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def generate_files(self):
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"""use to generate gds, lef files for one certain layout"""
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# Import this at the last minute so that the proper tech file
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# is loaded and the right tools are selected
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from openram import verify
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from openram.characterizer import functional
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from openram.characterizer import delay
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# Save the spice file
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start_time = datetime.datetime.now()
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spname = OPTS.output_path + self.s.name + ".sp"
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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# Save trimmed spice file
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temp_trim_sp = "{0}trimmed.sp".format(OPTS.output_path)
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self.sp_write(temp_trim_sp, lvs=False, trim=True)
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if not OPTS.netlist_only:
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# Write the layout
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start_time = datetime.datetime.now()
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gdsname = OPTS.output_path + self.s.name + ".gds"
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debug.print_raw("GDS: Writing to {0}".format(gdsname))
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self.gds_write(gdsname)
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if OPTS.check_lvsdrc:
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verify.write_drc_script(cell_name=self.s.name,
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gds_name=os.path.basename(gdsname),
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extract=True,
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("GDS", datetime.datetime.now(), start_time)
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# Create a LEF physical model
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start_time = datetime.datetime.now()
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lefname = OPTS.output_path + self.s.name + ".lef"
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debug.print_raw("LEF: Writing to {0}".format(lefname))
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self.lef_write(lefname)
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print_time("LEF", datetime.datetime.now(), start_time)
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# Save the LVS file
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start_time = datetime.datetime.now()
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lvsname = OPTS.output_path + self.s.name + ".lvs.sp"
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debug.print_raw("LVS: Writing to {0}".format(lvsname))
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self.sp_write(lvsname, lvs=True)
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if not OPTS.netlist_only and OPTS.check_lvsdrc:
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verify.write_lvs_script(cell_name=self.s.name,
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gds_name=os.path.basename(gdsname),
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sp_name=os.path.basename(lvsname),
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("LVS writing", datetime.datetime.now(), start_time)
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# Save the extracted spice file
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if OPTS.use_pex:
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start_time = datetime.datetime.now()
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# Output the extracted design if requested
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pexname = OPTS.output_path + self.s.name + ".pex.sp"
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spname = OPTS.output_path + self.s.name + ".sp"
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verify.run_pex(self.s.name, gdsname, spname, output=pexname)
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sp_file = pexname
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print_time("Extraction", datetime.datetime.now(), start_time)
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else:
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# Use generated spice file for characterization
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sp_file = spname
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# Write the config file
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start_time = datetime.datetime.now()
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try:
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from shutil import copyfile
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copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
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except shutil.SameFileError:
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pass
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debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
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print_time("Config", datetime.datetime.now(), start_time)
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# Write a verilog model
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start_time = datetime.datetime.now()
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vname = OPTS.output_path + self.s.name + '.v'
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debug.print_raw("Verilog: Writing to {0}".format(vname))
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self.verilog_write(vname)
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print_time("Verilog", datetime.datetime.now(), start_time)
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# Write out options if specified
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if OPTS.output_extended_config:
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start_time = datetime.datetime.now()
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oname = OPTS.output_path + OPTS.output_name + "_extended.py"
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debug.print_raw("Extended Config: Writing to {0}".format(oname))
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self.extended_config_write(oname)
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print_time("Extended Config", datetime.datetime.now(), start_time)
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def save(self, mod=0):
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""" Save all the output files while reporting time to do it as well. """
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if mod == 0:
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self.s.create_netlist_bank()
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if not OPTS.netlist_only:
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self.s.create_layout_bank_only()
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self.generate_files()
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elif mod == 1:
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self.s.create_netlist_control()
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if not OPTS.netlist_only:
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for port in self.s.all_ports:
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self.s.create_layout_control_only(instance_index=port)
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self.generate_files()
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else:
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for port in self.s.all_ports:
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self.generate_files()
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elif mod == 2:
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self.s.create_netlist_row_addr_dff()
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if not OPTS.netlist_only:
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for port in self.s.all_ports:
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self.s.create_layout_row_addr_dff_only(instance_index=port)
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self.generate_files()
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else:
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for port in self.s.all_ports:
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self.generate_files()
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elif mod == 3:
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if self.s.create_netlist_col_addr_dff() == False:
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pass#continue # do not need col addr dff
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elif not OPTS.netlist_only:
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for port in self.s.all_ports:
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self.create_layout_col_addr_dff_only(instance_index=port)
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self.generate_files()
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else:
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self.generate_files()
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elif mod == 4:
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self.s.create_netlist_data_dff()
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if not OPTS.netlist_only:
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for port in self.s.all_ports:
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self.s.create_layout_data_dff_only(instance_index=port)
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self.generate_files()
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else:
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for port in self.s.all_ports:
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self.generate_files()
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elif mod == 5:
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if self.s.create_netlist_wmask_dff() == False:
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pass#continue # do not need wmask dff
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elif not OPTS.netlist_only:
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for port in self.s.all_ports:
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self.s.create_layout_wmask_dff_only(instance_index=port)
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self.generate_files()
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else:
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for port in self.s.all_ports:
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self.generate_files()
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elif mod == 6:
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if self.s.create_netlist_spare_wen_dff() == False:
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pass#continue # do not need spare wen dff
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elif not OPTS.netlist_only:
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for port in self.s.all_ports:
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self.s.create_layout_spare_wen_dff_only(instance_index=port)
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self.generate_files()
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else:
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for port in self.s.all_ports:
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self.generate_files()
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