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Merged with dev and fixed conflicts.

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This commit is contained in:
Hunter Nichols
2019-04-03 16:45:01 -07:00
parent cc5b347f42 df4e2fead8
commit edac60d2a8
165 changed files with 820 additions and 12572 deletions
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compiler/modules/control_logic.py
+1 -1
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@@ -14,7 +14,7 @@ class control_logic(design.design):
Dynamically generated Control logic for the total SRAM circuit.
"""
def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw"):
def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""):
""" Constructor """
name = "control_logic_" + port_type
design.design.__init__(self, name)
compiler/modules/tri_gate_array.py
+2 -2
View File
@@ -10,9 +10,9 @@ class tri_gate_array(design.design):
Dynamically generated tri gate array of all bitlines. words_per_row
"""
def __init__(self, columns, word_size):
def __init__(self, columns, word_size, name):
"""Intial function of tri gate array """
design.design.__init__(self, "tri_gate_array")
design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name))
self.columns = columns