write_driver/sense_amp/precharge arrays: Allow y axis mirroring

since the bitlines alternate in the bitcell array we also need to mirror the port_data elements. Signed-off-by: Bastian Koppelmann <[email protected]>
2026-08-30 01:48:33 +02:00 · 2020-01-28 15:51:39 +01:00
parent dd1afe0313
commit ed66fca031
3 changed files with 39 additions and 7 deletions
@@ -107,9 +107,19 @@ class precharge_array(design.design):

    def place_insts(self):
        """ Places precharge array by horizontally tiling the precharge cell"""
+        from tech import cell_properties
+        xoffset = 0
        for i in range(self.columns):
-            offset = vector(self.pc_cell.width * i, 0)
-            self.local_insts[i].place(offset)                                   
+            tempx = xoffset
+            if cell_properties.bitcell.mirror.y and (i + 1) % 2:
+                mirror = "MY"
+                tempx = tempx + self.pc_cell.width
+            else:
+                mirror = ""
+
+            offset = vector(tempx, 0)
+            self.local_insts[i].place(offset=offset, mirror=mirror)
+            xoffset = xoffset + self.pc_cell.width

    def get_en_cin(self):
        """Get the relative capacitance of all the clk connections in the precharge array"""