diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py
index c2617f50..54ed2690 100644
--- a/compiler/modules/precharge_array.py
+++ b/compiler/modules/precharge_array.py
@@ -107,9 +107,19 @@ class precharge_array(design.design):
 
     def place_insts(self):
         """ Places precharge array by horizontally tiling the precharge cell"""
+        from tech import cell_properties
+        xoffset = 0
         for i in range(self.columns):
-            offset = vector(self.pc_cell.width * i, 0)
-            self.local_insts[i].place(offset)                                   
+            tempx = xoffset
+            if cell_properties.bitcell.mirror.y and (i + 1) % 2:
+                mirror = "MY"
+                tempx = tempx + self.pc_cell.width
+            else:
+                mirror = ""
+
+            offset = vector(tempx, 0)
+            self.local_insts[i].place(offset=offset, mirror=mirror)
+            xoffset = xoffset + self.pc_cell.width
 
     def get_en_cin(self):
         """Get the relative capacitance of all the clk connections in the precharge array"""        
diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py
index 2447e4b8..fcb68792 100644
--- a/compiler/modules/sense_amp_array.py
+++ b/compiler/modules/sense_amp_array.py
@@ -84,14 +84,27 @@ class sense_amp_array(design.design):
                                "en", "vdd", "gnd"])
 
     def place_sense_amp_array(self):
-            
+        from tech import cell_properties
         if self.bitcell.width > self.amp.width:
             amp_spacing = self.bitcell.width * self.words_per_row
         else:
             amp_spacing = self.amp.width * self.words_per_row
+
         for i in range(0,self.word_size):
-            amp_position = vector(amp_spacing * i, 0)
-            self.local_insts[i].place(amp_position)
+            xoffset = amp_spacing * i
+
+            # align the xoffset to the grid of bitcells. This way we
+            # know when to do the mirroring.
+            grid_x = int(xoffset / self.amp.width)
+
+            if cell_properties.bitcell.mirror.y and grid_x % 2:
+                mirror = "MY"
+                xoffset = xoffset + self.amp.width
+            else:
+                mirror = ""
+
+            amp_position = vector(xoffset, 0)
+            self.local_insts[i].place(offset=amp_position,mirror=mirror)
 
         
     def add_layout_pins(self):
diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py
index ac4dab00..cac9b396 100644
--- a/compiler/modules/write_driver_array.py
+++ b/compiler/modules/write_driver_array.py
@@ -106,14 +106,23 @@ class write_driver_array(design.design):
 
 
     def place_write_array(self):
+        from tech import cell_properties
         if self.bitcell.width > self.driver.width:
             self.driver_spacing = self.bitcell.width
         else:
             self.driver_spacing = self.driver.width
         for i in range(0,self.columns,self.words_per_row):
             index = int(i/self.words_per_row)
-            base = vector(i * self.driver_spacing, 0)
-            self.driver_insts[index].place(base)
+            xoffset = i * self.driver_spacing
+
+            if cell_properties.bitcell.mirror.y and i % 2:
+                mirror = "MY"
+                xoffset = xoffset + self.driver.width
+            else:
+                mirror = ""
+
+            base = vector(xoffset, 0)
+            self.driver_insts[index].place(offset=base, mirror=mirror)
 
             
     def add_layout_pins(self):