luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Redefined write_size inrecompute_sizes() to take the new word_size()

This commit is contained in:
jsowash 2019-07-15 14:41:26 -07:00
parent dfa2b29b8f
commit ea2f786dcf
4 changed files with 15 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
compiler/characterizer/functional.py
View File

@ -57,7 +57,6 @@ class functional(simulation):
self.wmask[self.num_wmask-1 - bit] = 1 self.wmask[self.num_wmask-1 - bit] = 1
else: else:
self.wmask[self.num_wmask-1 - bit] = 0 self.wmask[self.num_wmask-1 - bit] = 0
print(self.wmask)
def run(self, feasible_period=None): def run(self, feasible_period=None):
if feasible_period: #period defaults to tech.py feasible period otherwise. if feasible_period: #period defaults to tech.py feasible period otherwise.
@ -110,7 +109,7 @@ class functional(simulation):
elif bit == 0: elif bit == 0:
word = old_word[lower:upper+1] + word [upper+1:self.word_size] word = old_word[lower:upper+1] + word [upper+1:self.word_size]
else: else:
word = word[0:lower] + old_word[lower:upper+1] + word [upper+1:self.word_size]cfusms word = word[0:lower] + old_word[lower:upper+1] + word [upper+1:self.word_size]
#word = word.replace(word[lower:upper+1],old_word[lower:upper+1],1) #word = word.replace(word[lower:upper+1],old_word[lower:upper+1],1)
self.stored_words[addr] = word self.stored_words[addr] = word
else: else:

8
compiler/modules/port_data.py
View File

@ -56,8 +56,11 @@ class port_data(design.design):
self.create_write_driver_array() self.create_write_driver_array()
if (self.word_size != self.write_size): if (self.word_size != self.write_size):
self.create_write_mask_array() self.create_write_mask_array()
else:
self.write_mask_array_inst = None
else: else:
self.write_driver_array_inst = None self.write_driver_array_inst = None
self.write_mask_array_inst = None
if self.column_mux_array: if self.column_mux_array:
self.create_column_mux_array() self.create_column_mux_array()
@ -173,9 +176,12 @@ class port_data(design.design):
word_size=self.word_size, word_size=self.word_size,
write_size=self.write_size) write_size=self.write_size)
self.add_mod(self.write_driver_array) self.add_mod(self.write_driver_array)
else:
self.write_mask_array_inst = None
else: else:
self.write_driver_array = None self.write_driver_array = None
self.write_mask_array = None
def precompute_constants(self): def precompute_constants(self):
""" Get some preliminary data ready """ """ Get some preliminary data ready """

1
compiler/options.py
View File

@ -142,4 +142,5 @@ class options(optparse.Values):
wordline_driver = "wordline_driver" wordline_driver = "wordline_driver"
write_driver_array = "write_driver_array" write_driver_array = "write_driver_array"
write_driver = "write_driver" write_driver = "write_driver"
write_mask_array = "write_mask_array"

4
compiler/sram/sram_config.py
View File

@ -73,6 +73,10 @@ class sram_config:
SRAM for testing. SRAM for testing.
""" """
# This function is ran without the write mask option, but word_size can be redefined
# which makes the tests think there is a write mask.
self.write_size = self.word_size
# If the banks changed # If the banks changed
self.num_words_per_bank = self.num_words/self.num_banks self.num_words_per_bank = self.num_words/self.num_banks
self.num_bits_per_bank = self.word_size*self.num_words_per_bank self.num_bits_per_bank = self.word_size*self.num_words_per_bank