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Separate WL via from bitell array to avoid grounded WLs

This commit is contained in:
mrg 2020-09-15 13:38:28 -07:00
parent 5e94d76127
commit e7ad22ff69
2 changed files with 8 additions and 7 deletions
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14
compiler/modules/bank.py
View File

@ -861,11 +861,13 @@ class bank(design.design):
bitcell_wl_pos = bitcell_wl_pin.lc() bitcell_wl_pos = bitcell_wl_pin.lc()
mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].rx() + 0.5 * self.bitcell_array_inst.lx(), 0) mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].rx() + 0.5 * self.bitcell_array_inst.lx(), 0)
mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0.5, 1) mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0.5, 1)
self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2])
# Via is non-preferred direction because mid1->mid2 is non-preferred direction
self.add_via_stack_center(from_layer=driver_wl_pin.layer, self.add_via_stack_center(from_layer=driver_wl_pin.layer,
to_layer=bitcell_wl_pin.layer, to_layer=bitcell_wl_pin.layer,
offset=bitcell_wl_pos, offset=mid2,
directions=("H", "H")) directions="nonpref")
self.add_path(bitcell_wl_pin.layer, [mid2, bitcell_wl_pos])
def route_port_address_right(self, port): def route_port_address_right(self, port):
""" Connecting Wordline driver output to Bitcell WL connection """ """ Connecting Wordline driver output to Bitcell WL connection """
@ -879,11 +881,11 @@ class bank(design.design):
bitcell_wl_pos = bitcell_wl_pin.rc() bitcell_wl_pos = bitcell_wl_pin.rc()
mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].lx() + 0.5 * self.bitcell_array_inst.rx(), 0) mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].lx() + 0.5 * self.bitcell_array_inst.rx(), 0)
mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0, 1) mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0, 1)
self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2])
self.add_via_stack_center(from_layer=driver_wl_pin.layer, self.add_via_stack_center(from_layer=driver_wl_pin.layer,
to_layer=bitcell_wl_pin.layer, to_layer=bitcell_wl_pin.layer,
offset=bitcell_wl_pos, offset=mid2)
directions=("H", "H")) self.add_path(bitcell_wl_pin.layer, [mid2, bitcell_wl_pos])
def route_column_address_lines(self, port): def route_column_address_lines(self, port):
""" Connecting the select lines of column mux to the address bus """ """ Connecting the select lines of column mux to the address bus """

1
compiler/modules/replica_bitcell_array.py
View File

@ -455,7 +455,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
for pin in pin_list: for pin in pin_list:
self.add_power_pin(name=pin_name, self.add_power_pin(name=pin_name,
loc=pin.center(), loc=pin.center(),
directions=("V", "V"),
start_layer=pin.layer) start_layer=pin.layer)
for inst in self.replica_col_insts: for inst in self.replica_col_insts: