From e7ad22ff69b8603af8769cd3b847d2261d5c7c6a Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 15 Sep 2020 13:38:28 -0700 Subject: [PATCH] Separate WL via from bitell array to avoid grounded WLs --- compiler/modules/bank.py | 14 ++++++++------ compiler/modules/replica_bitcell_array.py | 1 - 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index c7b019d7..51f6c19b 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -861,11 +861,13 @@ class bank(design.design): bitcell_wl_pos = bitcell_wl_pin.lc() mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].rx() + 0.5 * self.bitcell_array_inst.lx(), 0) mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0.5, 1) - self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) + self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2]) + # Via is non-preferred direction because mid1->mid2 is non-preferred direction self.add_via_stack_center(from_layer=driver_wl_pin.layer, to_layer=bitcell_wl_pin.layer, - offset=bitcell_wl_pos, - directions=("H", "H")) + offset=mid2, + directions="nonpref") + self.add_path(bitcell_wl_pin.layer, [mid2, bitcell_wl_pos]) def route_port_address_right(self, port): """ Connecting Wordline driver output to Bitcell WL connection """ @@ -879,11 +881,11 @@ class bank(design.design): bitcell_wl_pos = bitcell_wl_pin.rc() mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].lx() + 0.5 * self.bitcell_array_inst.rx(), 0) mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0, 1) - self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) + self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2]) self.add_via_stack_center(from_layer=driver_wl_pin.layer, to_layer=bitcell_wl_pin.layer, - offset=bitcell_wl_pos, - directions=("H", "H")) + offset=mid2) + self.add_path(bitcell_wl_pin.layer, [mid2, bitcell_wl_pos]) def route_column_address_lines(self, port): """ Connecting the select lines of column mux to the address bus """ diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index f6b50f0c..6c2d54a7 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -455,7 +455,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): for pin in pin_list: self.add_power_pin(name=pin_name, loc=pin.center(), - directions=("V", "V"), start_layer=pin.layer) for inst in self.replica_col_insts: