Separate WL via from bitell array to avoid grounded WLs

2026-09-02 11:08:01 +02:00 · 2020-09-15 13:38:28 -07:00
parent 5e94d76127
commit e7ad22ff69
2 changed files with 8 additions and 7 deletions
@@ -455,7 +455,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
                for pin in pin_list:
                    self.add_power_pin(name=pin_name,
                                       loc=pin.center(),
-                                       directions=("V", "V"),
                                       start_layer=pin.layer)

            for inst in self.replica_col_insts: