From e553f3db417620c003a9273880e112b25cb1c2be Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 7 Sep 2023 12:24:39 -0700 Subject: [PATCH] fix sram.sp spare_wen --- compiler/modules/sram_1bank.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index 48e6cf89..97494ea5 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -662,7 +662,10 @@ class sram_1bank(design, verilog, lef): inputs = [] outputs = [] for bit in range(self.num_spare_cols): - inputs.append("spare_wen{}[{}]".format(port, bit)) + if self.num_spare_cols == 1: + inputs.append("spare_wen{}".format(port)) + else: + inputs.append("spare_wen{}[{}]".format(port, bit)) outputs.append("bank_spare_wen{}_{}".format(port, bit)) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)