diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py
index 48e6cf89..97494ea5 100644
--- a/compiler/modules/sram_1bank.py
+++ b/compiler/modules/sram_1bank.py
@@ -662,7 +662,10 @@ class sram_1bank(design, verilog, lef):
             inputs = []
             outputs = []
             for bit in range(self.num_spare_cols):
-                inputs.append("spare_wen{}[{}]".format(port, bit))
+                if self.num_spare_cols == 1:
+                    inputs.append("spare_wen{}".format(port))
+                else:
+                    inputs.append("spare_wen{}[{}]".format(port, bit))
                 outputs.append("bank_spare_wen{}_{}".format(port, bit))
 
             self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)