From 935cc5109bc3488c3f290c9be2745827980dce66 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 16 Nov 2018 08:37:54 -0800 Subject: [PATCH 001/521] Set theme jekyll-theme-hacker --- _config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/_config.yml b/_config.yml index 2f7efbea..fc24e7a6 100644 --- a/_config.yml +++ b/_config.yml @@ -1 +1 @@ -theme: jekyll-theme-minimal \ No newline at end of file +theme: jekyll-theme-hacker \ No newline at end of file From a1526c03944c1cb29f1b8d8b697eaee04d564c4a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 16 Nov 2018 08:54:45 -0800 Subject: [PATCH 002/521] Set theme jekyll-theme-midnight --- _config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/_config.yml b/_config.yml index fc24e7a6..18854876 100644 --- a/_config.yml +++ b/_config.yml @@ -1 +1 @@ -theme: jekyll-theme-hacker \ No newline at end of file +theme: jekyll-theme-midnight \ No newline at end of file From 82a5fbd4d42f46148fe6d7efc83592fc8f9381b4 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 16 Nov 2018 08:56:44 -0800 Subject: [PATCH 003/521] Set theme jekyll-theme-dinky --- _config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/_config.yml b/_config.yml index 18854876..9da9a029 100644 --- a/_config.yml +++ b/_config.yml @@ -1 +1 @@ -theme: jekyll-theme-midnight \ No newline at end of file +theme: jekyll-theme-dinky \ No newline at end of file From 764d4da1bdbc5519fa5902007ae68253817b4d40 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 23 Oct 2019 10:48:18 -0700 Subject: [PATCH 004/521] Clean up config file organization. Improve gdsMill debug output. --- compiler/characterizer/setup_hold.py | 1 + compiler/gdsMill/gdsMill/vlsiLayout.py | 26 +++++++++++-------- compiler/tests/01_library_drc_test.py | 2 +- compiler/tests/02_library_lvs_test.py | 2 +- compiler/tests/03_contact_test.py | 2 +- compiler/tests/03_path_test.py | 2 +- compiler/tests/03_ptx_1finger_nmos_test.py | 2 +- compiler/tests/03_ptx_1finger_pmos_test.py | 2 +- compiler/tests/03_ptx_3finger_nmos_test.py | 2 +- compiler/tests/03_ptx_3finger_pmos_test.py | 2 +- compiler/tests/03_ptx_4finger_nmos_test.py | 2 +- compiler/tests/03_ptx_4finger_pmos_test.py | 2 +- compiler/tests/03_wire_test.py | 2 +- compiler/tests/04_dummy_pbitcell_test.py | 2 +- compiler/tests/04_pand2_test.py | 2 +- compiler/tests/04_pand3_test.py | 2 +- compiler/tests/04_pbitcell_test.py | 2 +- compiler/tests/04_pbuf_test.py | 2 +- compiler/tests/04_pdriver_test.py | 2 +- compiler/tests/04_pinv_10x_test.py | 2 +- compiler/tests/04_pinv_1x_beta_test.py | 2 +- compiler/tests/04_pinv_1x_test.py | 2 +- compiler/tests/04_pinv_2x_test.py | 2 +- compiler/tests/04_pinvbuf_test.py | 2 +- compiler/tests/04_pnand2_test.py | 2 +- compiler/tests/04_pnand3_test.py | 2 +- compiler/tests/04_pnor2_test.py | 2 +- compiler/tests/04_precharge_test.py | 2 +- compiler/tests/04_replica_pbitcell_test.py | 2 +- .../tests/04_single_level_column_mux_test.py | 2 +- .../tests/05_bitcell_1rw_1r_array_test.py | 2 +- compiler/tests/05_bitcell_array_test.py | 2 +- compiler/tests/05_dummy_array_test.py | 2 +- compiler/tests/05_pbitcell_array_test.py | 2 +- .../tests/05_replica_pbitcell_array_test.py | 2 +- .../tests/06_hierarchical_decoder_test.py | 2 +- .../06_hierarchical_predecode2x4_test.py | 2 +- .../06_hierarchical_predecode3x8_test.py | 2 +- .../07_single_level_column_mux_array_test.py | 2 +- compiler/tests/08_precharge_array_test.py | 2 +- compiler/tests/08_wordline_driver_test.py | 2 +- compiler/tests/09_sense_amp_array_test.py | 2 +- compiler/tests/10_write_driver_array_test.py | 2 +- .../tests/10_write_driver_array_wmask_test.py | 2 +- .../tests/10_write_mask_and_array_test.py | 2 +- compiler/tests/11_dff_array_test.py | 2 +- compiler/tests/11_dff_buf_array_test.py | 2 +- compiler/tests/11_dff_buf_test.py | 2 +- compiler/tests/12_tri_gate_array_test.py | 2 +- compiler/tests/13_delay_chain_test.py | 2 +- .../14_replica_bitcell_1rw_1r_array_test.py | 2 +- .../tests/14_replica_bitcell_array_test.py | 2 +- compiler/tests/14_replica_column_test.py | 2 +- .../tests/16_control_logic_multiport_test.py | 2 +- compiler/tests/16_control_logic_test.py | 2 +- compiler/tests/18_port_address_test.py | 2 +- compiler/tests/18_port_data_test.py | 2 +- compiler/tests/18_port_data_wmask_test.py | 2 +- compiler/tests/19_bank_select_test.py | 2 +- compiler/tests/19_multi_bank_test.py | 2 +- compiler/tests/19_pmulti_bank_test.py | 2 +- compiler/tests/19_psingle_bank_test.py | 2 +- compiler/tests/19_single_bank_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_1w_1r_test.py | 2 +- compiler/tests/19_single_bank_test.py | 2 +- compiler/tests/19_single_bank_wmask_test.py | 2 +- .../tests/20_psram_1bank_2mux_1rw_1w_test.py | 2 +- .../20_psram_1bank_2mux_1rw_1w_wmask_test.py | 2 +- .../tests/20_psram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_test.py | 2 +- .../tests/20_psram_1bank_4mux_1rw_1r_test.py | 2 +- .../tests/20_sram_1bank_2mux_1rw_1r_test.py | 2 +- .../tests/20_sram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_test.py | 2 +- .../tests/20_sram_1bank_2mux_wmask_test.py | 2 +- .../20_sram_1bank_32b_1024_wmask_test.py | 2 +- compiler/tests/20_sram_1bank_4mux_test.py | 2 +- .../tests/20_sram_1bank_8mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_8mux_test.py | 2 +- .../tests/20_sram_1bank_nomux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_test.py | 2 +- .../tests/20_sram_1bank_nomux_wmask_test.py | 2 +- compiler/tests/20_sram_2bank_test.py | 2 +- compiler/tests/21_hspice_delay_test.py | 2 +- compiler/tests/21_hspice_setuphold_test.py | 2 +- compiler/tests/21_model_delay_test.py | 2 +- compiler/tests/21_ngspice_delay_test.py | 2 +- compiler/tests/21_ngspice_setuphold_test.py | 2 +- .../tests/22_psram_1bank_2mux_func_test.py | 2 +- .../tests/22_psram_1bank_4mux_func_test.py | 2 +- .../tests/22_psram_1bank_8mux_func_test.py | 2 +- .../tests/22_psram_1bank_nomux_func_test.py | 2 +- .../tests/22_sram_1bank_2mux_func_test.py | 2 +- .../tests/22_sram_1bank_4mux_func_test.py | 2 +- .../tests/22_sram_1bank_8mux_func_test.py | 2 +- .../tests/22_sram_1bank_nomux_func_test.py | 2 +- .../22_sram_1rw_1r_1bank_nomux_func_test.py | 2 +- .../tests/22_sram_wmask_1w_1r_func_test.py | 2 +- compiler/tests/22_sram_wmask_func_test.py | 2 +- .../tests/23_lib_sram_model_corners_test.py | 2 +- compiler/tests/23_lib_sram_model_test.py | 2 +- compiler/tests/23_lib_sram_prune_test.py | 2 +- compiler/tests/23_lib_sram_test.py | 2 +- compiler/tests/24_lef_sram_test.py | 2 +- compiler/tests/25_verilog_sram_test.py | 2 +- compiler/tests/26_hspice_pex_pinv_test.py | 2 +- compiler/tests/26_ngspice_pex_pinv_test.py | 2 +- compiler/tests/26_pex_test.py | 2 +- compiler/tests/30_openram_back_end_test.py | 4 +-- compiler/tests/30_openram_front_end_test.py | 5 ++-- .../config.py} | 0 .../config_back_end.py} | 0 .../config_front_end.py} | 0 .../config.py} | 0 .../config_back_end.py} | 0 .../config_front_end.py} | 0 .../config.py} | 0 .../config_back_end.py} | 0 .../config_front_end.py} | 0 119 files changed, 126 insertions(+), 122 deletions(-) rename compiler/tests/{config_freepdk45.py => freepdk45/config.py} (100%) rename compiler/tests/{config_freepdk45_back_end.py => freepdk45/config_back_end.py} (100%) rename compiler/tests/{config_freepdk45_front_end.py => freepdk45/config_front_end.py} (100%) rename compiler/tests/{config_scn3me_subm.py => scn3me_subm/config.py} (100%) rename compiler/tests/{config_scn3me_subm_back_end.py => scn3me_subm/config_back_end.py} (100%) rename compiler/tests/{config_scn3me_subm_front_end.py => scn3me_subm/config_front_end.py} (100%) rename compiler/tests/{config_scn4m_subm.py => scn4m_subm/config.py} (100%) rename compiler/tests/{config_scn4m_subm_back_end.py => scn4m_subm/config_back_end.py} (100%) rename compiler/tests/{config_scn4m_subm_front_end.py => scn4m_subm/config_front_end.py} (100%) diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index 8def076d..3739326a 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -24,6 +24,7 @@ class setup_hold(): # This must match the spice model order self.pins = ["data", "dout", "clk", "vdd", "gnd"] self.model_name = "dff" + print(OPTS.openram_tech) self.model_location = OPTS.openram_tech + "sp_lib/dff.sp" self.period = tech.spice["feasible_period"] diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index f4248ebd..671802ae 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -193,17 +193,21 @@ class VlsiLayout: delegateFunction(startingStructureName, transformPath) #starting with a particular structure, we will recursively traverse the tree #********might have to set the recursion level deeper for big layouts! - if(len(self.structures[startingStructureName].srefs)>0): #does this structure reference any others? - #if so, go through each and call this function again - #if not, return back to the caller (caller can be this function) - for sref in self.structures[startingStructureName].srefs: - #here, we are going to modify the sref coordinates based on the parent objects rotation - self.traverseTheHierarchy(startingStructureName = sref.sName, - delegateFunction = delegateFunction, - transformPath = transformPath, - rotateAngle = sref.rotateAngle, - transFlags = sref.transFlags, - coordinates = sref.coordinates) + try: + if(len(self.structures[startingStructureName].srefs)>0): #does this structure reference any others? + #if so, go through each and call this function again + #if not, return back to the caller (caller can be this function) + for sref in self.structures[startingStructureName].srefs: + #here, we are going to modify the sref coordinates based on the parent objects rotation + self.traverseTheHierarchy(startingStructureName = sref.sName, + delegateFunction = delegateFunction, + transformPath = transformPath, + rotateAngle = sref.rotateAngle, + transFlags = sref.transFlags, + coordinates = sref.coordinates) + except KeyError: + debug.error("Could not find structure {} in GDS file.".format(startingStructureName),-1) + #MUST HANDLE AREFs HERE AS WELL #when we return, drop the last transform from the transformPath del transformPath[-1] diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index f8da685b..b5578d1b 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -17,7 +17,7 @@ import debug class library_drc_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import verify (gds_dir, gds_files) = setup_files() diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index ad150a2b..2bb4aa32 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -17,7 +17,7 @@ import debug class library_lvs_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import verify (gds_dir, sp_dir, allnames) = setup_files() diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 3d7254c3..84e18d80 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -18,7 +18,7 @@ import debug class contact_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]: stack_name = ":".join(map(str, layer_stack)) diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index 21001718..a753e609 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -17,7 +17,7 @@ import debug class path_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import wire_path import tech import design diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index f436d7d0..a174ff54 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_1finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking min size NMOS with 1 finger") diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index ae8078e7..50725055 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_1finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking min size PMOS with 1 finger") diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index c010a948..0f55bd23 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_3finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 85cca9e2..484ae403 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_3finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index 4a410d51..d4b122c6 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_4finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index 34fbaf9f..f4c5bfe1 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 4ee360ce..9c7f6c3d 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -17,7 +17,7 @@ import debug class wire_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import wire import tech import design diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py index e8e3cc1c..64964067 100755 --- a/compiler/tests/04_dummy_pbitcell_test.py +++ b/compiler/tests/04_dummy_pbitcell_test.py @@ -18,7 +18,7 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import dummy_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index 42045b43..b2ee471e 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -18,7 +18,7 @@ import debug class pand2_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) global verify import verify diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index 4408f6e8..4a778b20 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -18,7 +18,7 @@ import debug class pand3_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) global verify import verify diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 0f14c4c5..16497ca9 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -19,7 +19,7 @@ from sram_factory import factory class pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.num_rw_ports=1 OPTS.num_w_ports=1 diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 35db8ccf..e2990beb 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -18,7 +18,7 @@ import debug class pbuf_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pbuf", size=8) diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index abaab4a0..bbb790ea 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -18,7 +18,7 @@ import debug class pdriver_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") # a tests the error message for specifying conflicting conditions diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index 2ccce34a..e3c3b6a7 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 8x inverter") tx = factory.create(module_type="pinv", size=8) diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index 2f96020c..124c31dd 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 1x beta=3 size inverter") tx = factory.create(module_type="pinv", size=1, beta=3) diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index 9b0f1bc6..cc240f22 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 1x size inverter") tx = factory.create(module_type="pinv", size=1) diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index d8a7598f..430af7f7 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 2x size inverter") tx = factory.create(module_type="pinv", size=2) diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index 86af0708..fefb157f 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -18,7 +18,7 @@ import debug class pinvbuf_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pinvbuf", size=8) diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index bc066cfc..1873a38e 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -18,7 +18,7 @@ import debug class pnand2_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 2-input nand gate") tx = factory.create(module_type="pnand2", size=1) diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index 8bf5098f..c8ea4174 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -18,7 +18,7 @@ import debug class pnand3_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 3-input nand gate") tx = factory.create(module_type="pnand3", size=1) diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index 0e524506..db93c64f 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -18,7 +18,7 @@ import debug class pnor2_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 2-input nor gate") tx = factory.create(module_type="pnor2", size=1) diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 9b2addd5..a9027ee7 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -18,7 +18,7 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 65ce5ecf..1308ac56 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -18,7 +18,7 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import replica_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 3ecbbe9d..77c8a01c 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -20,7 +20,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check single level column mux in single port debug.info(2, "Checking column mux") diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 972fb8e6..1f96c469 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -21,7 +21,7 @@ class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 6a561019..2c23d40f 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -20,7 +20,7 @@ import debug class array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="bitcell_array", cols=4, rows=4) diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index de379a97..40b0436c 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -16,7 +16,7 @@ import debug class dummy_row_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing dummy row for 6t_cell") a = factory.create(module_type="dummy_array", rows=1, cols=4) diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index 91bf7522..cc9ee573 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -19,7 +19,7 @@ import debug class pbitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell") OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/05_replica_pbitcell_array_test.py b/compiler/tests/05_replica_pbitcell_array_test.py index 2bc4a0d2..1f66fe11 100755 --- a/compiler/tests/05_replica_pbitcell_array_test.py +++ b/compiler/tests/05_replica_pbitcell_array_test.py @@ -16,7 +16,7 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index c349e889..3a407dc1 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -18,7 +18,7 @@ import debug class hierarchical_decoder_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 0a5363ab..cd730563 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -18,7 +18,7 @@ import debug class hierarchical_predecode2x4_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # checking hierarchical precode 2x4 for single port debug.info(1, "Testing sample for hierarchy_predecode2x4") diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index b2a8d438..b595cec8 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -18,7 +18,7 @@ import debug class hierarchical_predecode3x8_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # checking hierarchical precode 3x8 for single port debug.info(1, "Testing sample for hierarchy_predecode3x8") diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index c6cd7ed2..cdf2aa47 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -17,7 +17,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import single_level_column_mux_array # check single level column mux array in single port diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index ee29211b..e03e0308 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -18,7 +18,7 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check precharge array in single port debug.info(2, "Checking 3 column precharge") diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index 31415a6c..f39148d9 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -20,7 +20,7 @@ import debug class wordline_driver_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check wordline driver for single port debug.info(2, "Checking driver") diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index e35ea3c3..52131505 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -18,7 +18,7 @@ import debug class sense_amp_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 20dacca6..e2fffd04 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -18,7 +18,7 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py index d09286b5..8acce579 100755 --- a/compiler/tests/10_write_driver_array_wmask_test.py +++ b/compiler/tests/10_write_driver_array_wmask_test.py @@ -20,7 +20,7 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4") diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py index 91155467..5c40b146 100755 --- a/compiler/tests/10_write_mask_and_array_test.py +++ b/compiler/tests/10_write_mask_and_array_test.py @@ -20,7 +20,7 @@ import debug class write_mask_and_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check write driver array for single port debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4") diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index b843a6bb..0aed8737 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -18,7 +18,7 @@ import debug class dff_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing dff_array for 3x3") a = factory.create(module_type="dff_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index ec0e7742..ad0ab517 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -18,7 +18,7 @@ import debug class dff_buf_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing dff_buf_array for 3x3") a = factory.create(module_type="dff_buf_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index 161deaa2..e8b4a2d9 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -18,7 +18,7 @@ import debug class dff_buf_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing dff_buf 4x 8x") a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8) diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index 0bd5f60c..c297f399 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -18,7 +18,7 @@ import debug class tri_gate_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(1, "Testing tri_gate_array for columns=8, word_size=8") a = factory.create(module_type="tri_gate_array", columns=8, word_size=8) diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index 9dc8faeb..2483010b 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -18,7 +18,7 @@ import debug class delay_chain_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing delay_chain") a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4]) diff --git a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py index bae7edde..f4fb5587 100755 --- a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py @@ -16,7 +16,7 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index 2b446758..4e4d115b 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -16,7 +16,7 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index c0db4d17..0146695d 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -16,7 +16,7 @@ import debug class replica_column_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing replica column for 6t_cell") a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1) diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index 66c34d24..7418f2e8 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -22,7 +22,7 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import control_logic import tech diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 92d5c94b..7fcbffd8 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -18,7 +18,7 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import control_logic import tech diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py index c8db6ec2..7e38c916 100755 --- a/compiler/tests/18_port_address_test.py +++ b/compiler/tests/18_port_address_test.py @@ -16,7 +16,7 @@ import debug class port_address_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(1, "Port address 16 rows") a = factory.create("port_address", cols=16, rows=16) diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py index e5f94329..dcaacb0b 100755 --- a/compiler/tests/18_port_data_test.py +++ b/compiler/tests/18_port_data_test.py @@ -16,7 +16,7 @@ import debug class port_data_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index e9b70337..bfaf4ae3 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -18,7 +18,7 @@ import debug class port_data_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=16, diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index e2f5a9a8..a4530bf1 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -18,7 +18,7 @@ import debug class bank_select_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(1, "No column mux, rw control logic") a = factory.create(module_type="bank_select", port="rw") diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index 1816cd61..d8f64a37 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -19,7 +19,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 749460fa..9a14f741 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -19,7 +19,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 90e886f4..3708940d 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -19,7 +19,7 @@ import debug class psingle_bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index ab5ce041..e4d53de6 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class single_bank_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index 12b9f3a0..0d874605 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -18,7 +18,7 @@ import debug class single_bank_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index 1d010db5..ad1d2a52 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -18,7 +18,7 @@ import debug class single_bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index 439ffeba..644678d5 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -18,7 +18,7 @@ import debug class single_bank_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index fdeae56f..c6621219 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index 20fbd8e6..705e6d93 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -21,7 +21,7 @@ import debug class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index a5c01d8f..a619c48e 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 64fa72ca..c932a95a 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 7779b794..e012ce30 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index 60192759..b506b87d 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 2e1e848f..18c031c9 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 7e5a4f3a..3d43bb04 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py index 65f025a7..55fe2d0b 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py @@ -21,7 +21,7 @@ import debug class sram_1bank_2mux_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=8, write_size=4, diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py index a5232267..4df085e0 100755 --- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py +++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py @@ -21,7 +21,7 @@ import debug class sram_1bank_32b_1024_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=32, write_size=8, diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 34af86a1..d849135f 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_4mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=64, diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index 48a42106..bf8ee8f0 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index c5eaea75..e056732a 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_8mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=2, num_words=128, diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index f6bccc13..cb7dbd9f 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 650d2ac2..b9bc14a4 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_nomux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=16, diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py index e0292e95..26d75d82 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py @@ -21,7 +21,7 @@ import debug class sram_1bank_nomux_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=8, write_size=4, diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index c5d9d3d0..61b909ec 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -19,7 +19,7 @@ import debug class sram_2bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=16, num_words=32, diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index ebb424aa..a1ad05a7 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -18,7 +18,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 83bd5509..c309b10a 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -18,7 +18,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index a4de4c2a..1b611808 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -20,7 +20,7 @@ class model_delay_test(openram_test): """ Compare the accuracy of the analytical model with a spice simulation. """ def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index a5eb67fa..63ad6022 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -18,7 +18,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 0d160943..c0db881a 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -18,7 +18,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index f986c3e7..63d65993 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -18,7 +18,7 @@ import debug class psram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index c5fd8945..d688d4a0 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index acb168c0..6938732c 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index a2a2b41c..a1d1051c 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 2037169e..048ee372 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index 178f955b..c8bd2657 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index d531163a..b8d7fc07 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index eb6d2412..7133fc71 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index 169e34d0..a24610a2 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_wmask_1w_1r_func_test.py b/compiler/tests/22_sram_wmask_1w_1r_func_test.py index 2ee79750..afd8310a 100755 --- a/compiler/tests/22_sram_wmask_1w_1r_func_test.py +++ b/compiler/tests/22_sram_wmask_1w_1r_func_test.py @@ -21,7 +21,7 @@ import debug class sram_wmask_1w_1r_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index c390f030..8b3fa90d 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -19,7 +19,7 @@ import debug class sram_wmask_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 5840c05d..5020a5c9 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -18,7 +18,7 @@ import debug class lib_model_corners_lib_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 75e73f71..399daf7e 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -18,7 +18,7 @@ import debug class lib_sram_model_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 1fc5a66b..cd10fb10 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -18,7 +18,7 @@ import debug class lib_sram_prune_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.trim_netlist = True diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 0ababf32..5a60e9ad 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -17,7 +17,7 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.trim_netlist = False diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 5f7fdc60..3390c2e2 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -18,7 +18,7 @@ import debug class lef_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index da6a2682..e44f081a 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -17,7 +17,7 @@ import debug class verilog_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py index f0cccba3..7d99120c 100755 --- a/compiler/tests/26_hspice_pex_pinv_test.py +++ b/compiler/tests/26_hspice_pex_pinv_test.py @@ -20,7 +20,7 @@ import debug class hspice_pex_pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import pinv # load the hspice diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py index 2eb95948..96cc72aa 100755 --- a/compiler/tests/26_ngspice_pex_pinv_test.py +++ b/compiler/tests/26_ngspice_pex_pinv_test.py @@ -19,7 +19,7 @@ import debug class ngspice_pex_pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import pinv # load the ngspice diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index 78409249..3fd63117 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -19,7 +19,7 @@ import debug class sram_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.use_pex = True diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index de1bec05..16ffbbef 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -20,7 +20,7 @@ class openram_back_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/config_{1}".format(OPENRAM_HOME,OPTS.tech_name)) + globals.init_openram("{0}/tests/{1}/config".format(OPENRAM_HOME,OPTS.tech_name)) debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" @@ -51,7 +51,7 @@ class openram_back_end_test(openram_test): exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) - config_name = "{0}config_{1}_back_end.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name) + config_name = "{0}/tests/{1}/config_back_end.py".format(OPENRAM_HOME,OPTS.tech_name) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, out_path, diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index dbe7fcb9..58b70574 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -16,12 +16,11 @@ from sram_factory import factory import debug import getpass -#@unittest.skip("SKIPPING 30_openram_front_end_test") class openram_front_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/config_{1}".format(OPENRAM_HOME,OPTS.tech_name)) + globals.init_openram("{0}/tests/{1}/config".format(OPENRAM_HOME,OPTS.tech_name)) debug.info(1, "Testing top-level front-end openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" @@ -52,7 +51,7 @@ class openram_front_end_test(openram_test): exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) - config_name = "{0}config_{1}_front_end.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name) + config_name = "{0}/tests/{1}/config_front_end.py".format(OPENRAM_HOME,OPTS.tech_name) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, out_path, diff --git a/compiler/tests/config_freepdk45.py b/compiler/tests/freepdk45/config.py similarity index 100% rename from compiler/tests/config_freepdk45.py rename to compiler/tests/freepdk45/config.py diff --git a/compiler/tests/config_freepdk45_back_end.py b/compiler/tests/freepdk45/config_back_end.py similarity index 100% rename from compiler/tests/config_freepdk45_back_end.py rename to compiler/tests/freepdk45/config_back_end.py diff --git a/compiler/tests/config_freepdk45_front_end.py b/compiler/tests/freepdk45/config_front_end.py similarity index 100% rename from compiler/tests/config_freepdk45_front_end.py rename to compiler/tests/freepdk45/config_front_end.py diff --git a/compiler/tests/config_scn3me_subm.py b/compiler/tests/scn3me_subm/config.py similarity index 100% rename from compiler/tests/config_scn3me_subm.py rename to compiler/tests/scn3me_subm/config.py diff --git a/compiler/tests/config_scn3me_subm_back_end.py b/compiler/tests/scn3me_subm/config_back_end.py similarity index 100% rename from compiler/tests/config_scn3me_subm_back_end.py rename to compiler/tests/scn3me_subm/config_back_end.py diff --git a/compiler/tests/config_scn3me_subm_front_end.py b/compiler/tests/scn3me_subm/config_front_end.py similarity index 100% rename from compiler/tests/config_scn3me_subm_front_end.py rename to compiler/tests/scn3me_subm/config_front_end.py diff --git a/compiler/tests/config_scn4m_subm.py b/compiler/tests/scn4m_subm/config.py similarity index 100% rename from compiler/tests/config_scn4m_subm.py rename to compiler/tests/scn4m_subm/config.py diff --git a/compiler/tests/config_scn4m_subm_back_end.py b/compiler/tests/scn4m_subm/config_back_end.py similarity index 100% rename from compiler/tests/config_scn4m_subm_back_end.py rename to compiler/tests/scn4m_subm/config_back_end.py diff --git a/compiler/tests/config_scn4m_subm_front_end.py b/compiler/tests/scn4m_subm/config_front_end.py similarity index 100% rename from compiler/tests/config_scn4m_subm_front_end.py rename to compiler/tests/scn4m_subm/config_front_end.py From 31825d9d77e049b56182ad0eeae50537047195c3 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 24 Oct 2019 13:17:33 -0700 Subject: [PATCH 005/521] Fix magicrc for multiple openram tech paths --- technology/scn4m_subm/mag_lib/.magicrc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/technology/scn4m_subm/mag_lib/.magicrc b/technology/scn4m_subm/mag_lib/.magicrc index 0dfe42ef..c85bb879 100644 --- a/technology/scn4m_subm/mag_lib/.magicrc +++ b/technology/scn4m_subm/mag_lib/.magicrc @@ -1,4 +1,7 @@ -path sys +$::env(OPENRAM_TECH)/scn4m_subm/tech +set openram_paths [split $::env(OPENRAM_TECH) ":"] +foreach p $openram_paths { + path sys +$p/scn4m_subm/tech +} tech load SCN4M_SUBM.20 -noprompt scalegrid 1 4 set GND gnd From 38213d998fcdb5d973ba5d7447fed7704dd203e4 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 25 Oct 2019 10:03:25 -0700 Subject: [PATCH 006/521] Add separate layer and purpose pairs to tech layers. --- compiler/base/geometry.py | 21 ++++---- compiler/base/hierarchy_layout.py | 26 +++++----- compiler/base/pin_layout.py | 28 ++++++---- compiler/base/utils.py | 18 +++---- compiler/gdsMill/gdsMill/gds2reader.py | 8 --- compiler/gdsMill/gdsMill/vlsiLayout.py | 71 ++++++++++++++------------ compiler/globals.py | 1 - technology/freepdk45/tech/tech.py | 66 ++++++++++++------------ technology/scn3me_subm/tech/tech.py | 36 ++++++------- technology/scn4m_subm/tech/tech.py | 40 +++++++-------- 10 files changed, 160 insertions(+), 155 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 74b02f5f..f8eb03ab 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -266,11 +266,12 @@ class instance(geometry): class path(geometry): """Represents a Path""" - def __init__(self, layerNumber, coordinates, path_width): + def __init__(self, lpp, coordinates, path_width): """Initializes a path for the specified layer""" geometry.__init__(self) self.name = "path" - self.layerNumber = layerNumber + self.layerNumber = lpp[0] + self.layerPurpose = lpp[1] self.coordinates = map(lambda x: [x[0], x[1]], coordinates) self.coordinates = vector(self.coordinates).snap_to_grid() self.path_width = path_width @@ -283,7 +284,7 @@ class path(geometry): """Writes the path to GDS""" debug.info(4, "writing path (" + str(self.layerNumber) + "): " + self.coordinates) new_layout.addPath(layerNumber=self.layerNumber, - purposeNumber=0, + purposeNumber=self.layerPurpose, coordinates=self.coordinates, width=self.path_width) @@ -303,12 +304,13 @@ class path(geometry): class label(geometry): """Represents a text label""" - def __init__(self, text, layerNumber, offset, zoom=-1): + def __init__(self, text, lpp, offset, zoom=-1): """Initializes a text label for specified layer""" geometry.__init__(self) self.name = "label" self.text = text - self.layerNumber = layerNumber + self.layerNumber = lpp[0] + self.layerPurpose = lpp[1] self.offset = vector(offset).snap_to_grid() if zoom<0: @@ -325,7 +327,7 @@ class label(geometry): debug.info(4, "writing label (" + str(self.layerNumber) + "): " + self.text) new_layout.addText(text=self.text, layerNumber=self.layerNumber, - purposeNumber=0, + purposeNumber=self.layerPurpose, offsetInMicrons=self.offset, magnification=self.zoom, rotate=None) @@ -346,11 +348,12 @@ class label(geometry): class rectangle(geometry): """Represents a rectangular shape""" - def __init__(self, layerNumber, offset, width, height): + def __init__(self, lpp, offset, width, height): """Initializes a rectangular shape for specified layer""" geometry.__init__(self) self.name = "rect" - self.layerNumber = layerNumber + self.layerNumber = lpp[0] + self.layerPurpose = lpp[1] self.offset = vector(offset).snap_to_grid() self.size = vector(width, height).snap_to_grid() self.width = round_to_grid(self.size.x) @@ -374,7 +377,7 @@ class rectangle(geometry): debug.info(4, "writing rectangle (" + str(self.layerNumber) + "):" + str(self.width) + "x" + str(self.height) + " @ " + str(self.offset)) new_layout.addBox(layerNumber=self.layerNumber, - purposeNumber=0, + purposeNumber=self.layerPurpose, offsetInMicrons=self.offset, width=self.width, height=self.height, diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 2fea5c61..503bd1d5 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -150,9 +150,9 @@ class layout(): if not height: height=drc["minwidth_{}".format(layer)] # negative layers indicate "unused" layers in a given technology - layer_num = techlayer[layer] - if layer_num >= 0: - self.objs.append(geometry.rectangle(layer_num, offset, width, height)) + lpp = techlayer[layer] + if lpp[0] >= 0: + self.objs.append(geometry.rectangle(lpp, offset, width, height)) return self.objs[-1] return None @@ -165,10 +165,10 @@ class layout(): if not height: height=drc["minwidth_{}".format(layer)] # negative layers indicate "unused" layers in a given technology - layer_num = techlayer[layer] + lpp = techlayer[layer] corrected_offset = offset - vector(0.5*width,0.5*height) - if layer_num >= 0: - self.objs.append(geometry.rectangle(layer_num, corrected_offset, width, height)) + if lpp[0] >= 0: + self.objs.append(geometry.rectangle(lpp, corrected_offset, width, height)) return self.objs[-1] return None @@ -334,9 +334,9 @@ class layout(): """Adds a text label on the given layer,offset, and zoom level""" # negative layers indicate "unused" layers in a given technology debug.info(5,"add label " + str(text) + " " + layer + " " + str(offset)) - layer_num = techlayer[layer] - if layer_num >= 0: - self.objs.append(geometry.label(text, layer_num, offset, zoom)) + lpp = techlayer[layer] + if lpp[0] >= 0: + self.objs.append(geometry.label(text, lpp, offset, zoom)) return self.objs[-1] return None @@ -347,9 +347,9 @@ class layout(): import wire_path # NOTE: (UNTESTED) add_path(...) is currently not used # negative layers indicate "unused" layers in a given technology - #layer_num = techlayer[layer] - #if layer_num >= 0: - # self.objs.append(geometry.path(layer_num, coordinates, width)) + #lpp = techlayer[layer] + #if lpp[0] >= 0: + # self.objs.append(geometry.path(lpp, coordinates, width)) wire_path.wire_path(obj=self, layer=layer, @@ -539,7 +539,7 @@ class layout(): Do not write the pins since they aren't obstructions. """ if type(layer)==str: - layer_num = techlayer[layer] + layer_num = techlayer[layer][0] else: layer_num = layer diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index 2d389119..10d10774 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -17,7 +17,7 @@ class pin_layout: single shape. """ - def __init__(self, name, rect, layer_name_num): + def __init__(self, name, rect, layer_name_pp): self.name = name # repack the rect as a vector, just in case if type(rect[0])==vector: @@ -30,12 +30,19 @@ class pin_layout: debug.check(self.width()>0,"Zero width pin.") debug.check(self.height()>0,"Zero height pin.") - # if it's a layer number look up the layer name. this assumes a unique layer number. - if type(layer_name_num)==int: - self.layer = list(layer.keys())[list(layer.values()).index(layer_name_num)] + # if it's a string, use the name + if type(layer_name_pp)==str: + self.layer=layer_name_pp + # else it is required to be a lpp else: - self.layer=layer_name_num - self.layer_num = layer[self.layer] + for (layer_name, lpp) in layer.items(): + if layer_name_pp[0]==lpp[0] and (layer_name_pp[1]==None or layer_name_pp[1]==lpp[1]): + self.layer=layer_name + break + else: + debug.error("Couldn't find layer {}".format(layer_name_pp),-1) + + self.lpp = layer[self.layer] def __str__(self): """ override print function output """ @@ -310,8 +317,9 @@ class pin_layout: """Writes the pin shape and label to GDS""" debug.info(4, "writing pin (" + str(self.layer) + "):" + str(self.width()) + "x" + str(self.height()) + " @ " + str(self.ll())) - newLayout.addBox(layerNumber=layer[self.layer], - purposeNumber=0, + (layer_num,purpose) = layer[self.layer] + newLayout.addBox(layerNumber=layer_num, + purposeNumber=purpose, offsetInMicrons=self.ll(), width=self.width(), height=self.height(), @@ -319,8 +327,8 @@ class pin_layout: # Add the tet in the middle of the pin. # This fixes some pin label offsetting when GDS gets imported into Magic. newLayout.addText(text=self.name, - layerNumber=layer[self.layer], - purposeNumber=0, + layerNumber=layer_num, + purposeNumber=purpose, offsetInMicrons=self.center(), magnification=GDS["zoom"], rotate=None) diff --git a/compiler/base/utils.py b/compiler/base/utils.py index 61e12096..1816a508 100644 --- a/compiler/base/utils.py +++ b/compiler/base/utils.py @@ -45,7 +45,7 @@ def pin_center(boundary): """ return [0.5 * (boundary[0] + boundary[2]), 0.5 * (boundary[1] + boundary[3])] -def auto_measure_libcell(pin_list, name, units, layer): +def auto_measure_libcell(pin_list, name, units, lpp): """ Open a GDS file and find the pins in pin_list as text on a given layer. Return these as a set of properties including the cell width/height too. @@ -56,19 +56,19 @@ def auto_measure_libcell(pin_list, name, units, layer): reader.loadFromFile(cell_gds) cell = {} - measure_result = cell_vlsi.getLayoutBorder(layer) + measure_result = cell_vlsi.getLayoutBorder(lpp[0]) if measure_result == None: measure_result = cell_vlsi.measureSize(name) [cell["width"], cell["height"]] = measure_result for pin in pin_list: - (name,layer,boundary)=cell_vlsi.getPinShapeByLabel(str(pin)) + (name,lpp,boundary)=cell_vlsi.getPinShapeByLabel(str(pin)) cell[str(pin)] = pin_center(boundary) return cell -def get_gds_size(name, gds_filename, units, layer): +def get_gds_size(name, gds_filename, units, lpp): """ Open a GDS file and return the size from either the bounding box or a border layer. @@ -79,20 +79,20 @@ def get_gds_size(name, gds_filename, units, layer): reader.loadFromFile(gds_filename) cell = {} - measure_result = cell_vlsi.getLayoutBorder(layer) + measure_result = cell_vlsi.getLayoutBorder(lpp) if measure_result == None: debug.info(2,"Layout border failed. Trying to measure size for {}".format(name)) measure_result = cell_vlsi.measureSize(name) # returns width,height return measure_result -def get_libcell_size(name, units, layer): +def get_libcell_size(name, units, lpp): """ Open a GDS file and return the library cell size from either the bounding box or a border layer. """ cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" - return(get_gds_size(name, cell_gds, units, layer)) + return(get_gds_size(name, cell_gds, units, lpp)) def get_gds_pins(pin_names, name, gds_filename, units): @@ -109,10 +109,10 @@ def get_gds_pins(pin_names, name, gds_filename, units): cell[str(pin_name)]=[] pin_list=cell_vlsi.getPinShape(str(pin_name)) for pin_shape in pin_list: - (layer,boundary)=pin_shape + (lpp,boundary)=pin_shape rect=[vector(boundary[0],boundary[1]),vector(boundary[2],boundary[3])] # this is a list because other cells/designs may have must-connect pins - cell[str(pin_name)].append(pin_layout(pin_name, rect, layer)) + cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp)) return cell def get_libcell_pins(pin_list, name, units): diff --git a/compiler/gdsMill/gdsMill/gds2reader.py b/compiler/gdsMill/gdsMill/gds2reader.py index 85fc0c66..7e519c36 100644 --- a/compiler/gdsMill/gdsMill/gds2reader.py +++ b/compiler/gdsMill/gdsMill/gds2reader.py @@ -686,10 +686,6 @@ class Gds2reader: if idBits==('\x07','\x00'): break; #we've reached the end of the structure elif(idBits==('\x06','\x06')): structName = self.stripNonASCII(record[2::]) #(record[2:1] + record[1::]).rstrip() -# print(''.[x for x in structName if ord(x) < 128]) -# stripped = (c for c in structName if 0 < ord(c) < 127) -# structName = "".join(stripped) -# print(self.stripNonASCII(structName)) ##FIXME: trimming by Tom g. ##could be an issue here with string trimming! thisStructure.name = structName if(findStructName==thisStructure.name): wantedStruct=1 @@ -767,10 +763,6 @@ class Gds2reader: if idBits==('\x07','\x00'): break; #we've reached the end of the structure elif(idBits==('\x06','\x06')): structName = self.stripNonASCII(record[2::]) #(record[2:1] + record[1::]).rstrip() -# print(''.[x for x in structName if ord(x) < 128]) -# stripped = (c for c in structName if 0 < ord(c) < 127) -# structName = "".join(stripped) -# print(self.stripNonASCIIx(structName)) ##FIXME: trimming by Tom g. ##could be an issue here with string trimming! thisStructure.name = structName if(self.debugToTerminal==1): print("\tStructure Name: "+structName) diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index 671802ae..8d071e9f 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -19,7 +19,8 @@ class VlsiLayout: self.layerNumbersInUse = [] self.debug = False if name: - self.rootStructureName=name + #take the root structure and copy it to a new structure with the new name + self.rootStructureName=self.padText(name) #create the ROOT structure self.structures[self.rootStructureName] = GdsStructure() self.structures[self.rootStructureName].name = name @@ -82,13 +83,9 @@ class VlsiLayout: return coordinatesRotate def rename(self,newName): - #make sure the newName is a multiple of 2 characters - if(len(newName)%2 == 1): - #pad with a zero - newName = newName + '\x00' #take the root structure and copy it to a new structure with the new name self.structures[newName] = self.structures[self.rootStructureName] - self.structures[newName].name = newName + self.structures[newName].name = self.padText(newName) #and delete the old root del self.structures[self.rootStructureName] self.rootStructureName = newName @@ -159,13 +156,14 @@ class VlsiLayout: debug.check(len(structureNames)==1,"Multiple possible root structures in the layout: {}".format(str(structureNames))) self.rootStructureName = structureNames[0] + def traverseTheHierarchy(self, startingStructureName=None, delegateFunction = None, transformPath = [], rotateAngle = 0, transFlags = [0,0,0], coordinates = (0,0)): #since this is a recursive function, must deal with the default #parameters explicitly if startingStructureName == None: startingStructureName = self.rootStructureName - + #set up the rotation matrix if(rotateAngle == None or rotateAngle == ""): angle = 0 @@ -219,7 +217,7 @@ class VlsiLayout: self.populateCoordinateMap() for layerNumber in self.layerNumbersInUse: - self.processLabelPins(layerNumber) + self.processLabelPins((layerNumber,None)) def populateCoordinateMap(self): @@ -400,10 +398,10 @@ class VlsiLayout: cY = self.userUnits(coordinate[1]) layoutUnitCoordinates.append((cX,cY)) pathToAdd = GdsPath() - pathToAdd.drawingLayer=layerNumber + pathToAdd.drawingLayer = layerNumber pathToAdd.purposeLayer = purposeNumber - pathToAdd.pathWidth=widthInLayoutUnits - pathToAdd.coordinates=layoutUnitCoordinates + pathToAdd.pathWidth = widthInLayoutUnits + pathToAdd.coordinates = layoutUnitCoordinates #add the sref to the root structure self.structures[self.rootStructureName].paths.append(pathToAdd) @@ -414,10 +412,8 @@ class VlsiLayout: textToAdd.purposeLayer = purposeNumber textToAdd.dataType = 0 textToAdd.coordinates = [offsetInLayoutUnits] - textToAdd.transFlags = [0,0,0] - if(len(text)%2 == 1): - text = text + '\x00' - textToAdd.textString = text + textToAdd.transFlags = [0,0,0] + textToAdd.textString = self.padText(text) #textToAdd.transFlags[1] = 1 textToAdd.magFactor = magnification if rotate: @@ -425,7 +421,13 @@ class VlsiLayout: textToAdd.rotateAngle = rotate #add the sref to the root structure self.structures[self.rootStructureName].texts.append(textToAdd) - + + def padText(self, text): + if(len(text)%2 == 1): + return text + '\x00' + else: + return text + def isBounded(self,testPoint,startPoint,endPoint): #these arguments are touples of (x,y) coordinates if testPoint == None: @@ -591,22 +593,23 @@ class VlsiLayout: passFailIndex += 1 print("Done\n\n") - def getLayoutBorder(self,borderlayer): + def getLayoutBorder(self,lpp): cellSizeMicron=None for boundary in self.structures[self.rootStructureName].boundaries: - if boundary.drawingLayer==borderlayer: + if boundary.drawingLayer==lpp[0] and \ + (lpp[1]==None or boundary.purposeLayer==None or boundary.purposeLayer==lpp[1]): if self.debug: debug.info(1,"Find border "+str(boundary.coordinates)) left_bottom=boundary.coordinates[0] right_top=boundary.coordinates[2] cellSize=[right_top[0]-left_bottom[0],right_top[1]-left_bottom[1]] cellSizeMicron=[cellSize[0]*self.units[0],cellSize[1]*self.units[0]] - if not(cellSizeMicron): - print("Error: "+str(self.rootStructureName)+".cell_size information not found yet") + debug.check(cellSizeMicron, + "Error: "+str(self.rootStructureName)+".cell_size information not found yet") return cellSizeMicron def measureSize(self,startStructure): - self.rootStructureName=startStructure + self.rootStructureName=self.padText(startStructure) self.populateCoordinateMap() cellBoundary = [None, None, None, None] for TreeUnit in self.xyTree: @@ -616,7 +619,7 @@ class VlsiLayout: return cellSizeMicron def measureBoundary(self,startStructure): - self.rootStructureName=startStructure + self.rootStructureName=self.padText(startStructure) self.populateCoordinateMap() cellBoundary = [None, None, None, None] for TreeUnit in self.xyTree: @@ -653,13 +656,13 @@ class VlsiLayout: return cellBoundary - def getTexts(self, layer): + def getTexts(self, lpp): """ Get all of the labels on a given layer only at the root level. """ text_list = [] for Text in self.structures[self.rootStructureName].texts: - if Text.drawingLayer == layer: + if Text.drawingLayer==lpp[0] and (lpp[1]==None or Text.purposeLayer==lpp[1]): text_list.append(Text) return text_list @@ -700,16 +703,16 @@ class VlsiLayout: return shape_list - def processLabelPins(self, layer): + def processLabelPins(self, lpp): """ Find all text labels and create a map to a list of shapes that they enclose on the given layer. """ # Get the labels on a layer in the root level - labels = self.getTexts(layer) + labels = self.getTexts(lpp) # Get all of the shapes on the layer at all levels # and transform them to the current level - shapes = self.getAllShapes(layer) + shapes = self.getAllShapes(lpp) for label in labels: label_coordinate = label.coordinates[0] @@ -717,7 +720,7 @@ class VlsiLayout: pin_shapes = [] for boundary in shapes: if self.labelInRectangle(user_coordinate,boundary): - pin_shapes.append((layer, boundary)) + pin_shapes.append((lpp, boundary)) label_text = label.textString # Remove the padding if it exists @@ -731,14 +734,14 @@ class VlsiLayout: self.pins[label_text].append(pin_shapes) - def getBlockages(self,layer): + def getBlockages(self, lpp): """ Return all blockages on a given layer in [coordinate 1, coordinate 2,...] format and user units. """ blockages = [] - shapes = self.getAllShapes(layer) + shapes = self.getAllShapes(lpp) for boundary in shapes: vectors = [] for i in range(0,len(boundary),2): @@ -746,7 +749,7 @@ class VlsiLayout: blockages.append(vectors) return blockages - def getAllShapes(self,layer): + def getAllShapes(self, lpp): """ Return all shapes on a given layer in [llx, lly, urx, ury] format and user units for rectangles and [coordinate 1, coordinate 2,...] format and user units for polygons. @@ -754,7 +757,7 @@ class VlsiLayout: boundaries = set() for TreeUnit in self.xyTree: #print(TreeUnit[0]) - boundaries.update(self.getShapesInStructure(layer,TreeUnit)) + boundaries.update(self.getShapesInStructure(lpp,TreeUnit)) # Convert to user units user_boundaries = [] @@ -766,7 +769,7 @@ class VlsiLayout: return user_boundaries - def getShapesInStructure(self,layer,structure): + def getShapesInStructure(self, lpp, structure): """ Go through all the shapes in a structure and return the list of shapes in the form [llx, lly, urx, ury] for rectangles and [coordinate 1, coordinate 2,...] for polygons. @@ -775,7 +778,7 @@ class VlsiLayout: #print(structureName,"u",structureuVector.transpose(),"v",structurevVector.transpose(),"o",structureOrigin.transpose()) boundaries = [] for boundary in self.structures[str(structureName)].boundaries: - if layer==boundary.drawingLayer: + if boundary.drawingLayer==lpp[0] and (lpp[1]==None or boundary.purposeLayer==lpp[1]): if len(boundary.coordinates)!=5: # if shape is a polygon (used in DFF) boundaryPolygon = [] diff --git a/compiler/globals.py b/compiler/globals.py index ab489242..0bdd486d 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -438,7 +438,6 @@ def import_tech(): OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/" - # Add the tech directory tech_path = OPTS.openram_tech sys.path.append(tech_path) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index caa3c748..07748390 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -35,39 +35,39 @@ GDS["zoom"] = 0.05 # create the GDS layer map # FIXME: parse the gds layer map from the cadence map? layer = {} -layer["active"] = 1 -layer["pwell"] = 2 -layer["nwell"] = 3 -layer["nimplant"]= 4 -layer["pimplant"]= 5 -layer["vtg"] = 6 -layer["vth"] = 7 -layer["thkox"] = 8 -layer["poly"] = 9 -layer["contact"] = 10 -layer["active_contact"] = 10 -layer["metal1"] = 11 -layer["via1"] = 12 -layer["metal2"] = 13 -layer["via2"] = 14 -layer["metal3"] = 15 -layer["via3"] = 16 -layer["metal4"] = 17 -layer["via4"] = 18 -layer["metal5"] = 19 -layer["via5"] = 20 -layer["metal6"] = 21 -layer["via6"] = 22 -layer["metal7"] = 23 -layer["via7"] = 24 -layer["metal8"] = 25 -layer["via8"] = 26 -layer["metal9"] = 27 -layer["via9"] = 28 -layer["metal10"] = 29 -layer["text"] = 239 -layer["boundary"]= 239 -layer["blockage"]= 239 +layer["active"] = (1, 0) +layer["pwell"] = (2, 0) +layer["nwell"] = (3, 0) +layer["nimplant"]= (4, 0) +layer["pimplant"]= (5, 0) +layer["vtg"] = (6, 0) +layer["vth"] = (7, 0) +layer["thkox"] = (8, 0) +layer["poly"] = (9, 0) +layer["contact"] = (10, 0) +layer["active_contact"] = (10, 0) +layer["metal1"] = (11, 0) +layer["via1"] = (12, 0) +layer["metal2"] = (13, 0) +layer["via2"] = (14, 0) +layer["metal3"] = (15, 0) +layer["via3"] = (16, 0) +layer["metal4"] = (17, 0) +layer["via4"] = (18, 0) +layer["metal5"] = (19, 0) +layer["via5"] = (20, 0) +layer["metal6"] = (21, 0) +layer["via6"] = (22, 0) +layer["metal7"] = (23, 0) +layer["via7"] = (24, 0) +layer["metal8"] = (25, 0) +layer["via8"] = (26, 0) +layer["metal9"] = (27, 0) +layer["via9"] = (28, 0) +layer["metal10"] = (29, 0) +layer["text"] = (239, 0) +layer["boundary"]= (239, 0) +layer["blockage"]= (239, 0) ################################################### ##END GDS Layer Map diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 074009f2..cc405c21 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -29,24 +29,24 @@ GDS["zoom"] = 0.5 # create the GDS layer map layer={} -layer["vtg"] = -1 -layer["vth"] = -1 -layer["contact"] = 47 -layer["pwell"] = 41 -layer["nwell"] = 42 -layer["active"] = 43 -layer["pimplant"] = 44 -layer["nimplant"] = 45 -layer["poly"] = 46 -layer["active_contact"] = 48 -layer["metal1"] = 49 -layer["via1"] = 50 -layer["metal2"] = 51 -layer["via2"] = 61 -layer["metal3"] = 62 -layer["text"] = 63 -layer["boundary"] = 63 -layer["blockage"] = 83 +layer["vtg"] = (-1, 0) +layer["vth"] = (-1, 0) +layer["contact"] = (47, 0) +layer["pwell"] = (41, 0) +layer["nwell"] = (42, 0) +layer["active"] = (43, 0) +layer["pimplant"] = (44, 0) +layer["nimplant"] = (45, 0) +layer["poly"] = (46, 0) +layer["active_contact"] = (48, 0) +layer["metal1"] = (49, 0) +layer["via1"] = (50, 0) +layer["metal2"] = (51, 0) +layer["via2"] = (61, 0) +layer["metal3"] = (62, 0) +layer["text"] = (63, 0) +layer["boundary"] = (63, 0) +layer["blockage"] = (83, 0) ################################################### ##END GDS Layer Map diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 37e55e21..3964a088 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -35,26 +35,26 @@ GDS["zoom"] = 0.5 # create the GDS layer map layer={} -layer["vtg"] = -1 -layer["vth"] = -1 -layer["contact"] = 47 -layer["pwell"] = 41 -layer["nwell"] = 42 -layer["active"] = 43 -layer["pimplant"] = 44 -layer["nimplant"] = 45 -layer["poly"] = 46 -layer["active_contact"] = 48 -layer["metal1"] = 49 -layer["via1"] = 50 -layer["metal2"] = 51 -layer["via2"] = 61 -layer["metal3"] = 62 -layer["via3"] = 30 -layer["metal4"] = 31 -layer["text"] = 63 -layer["boundary"] = 63 -layer["blockage"] = 83 +layer["vtg"] = (-1, 0) +layer["vth"] = (-1, 0) +layer["contact"] = (47, 0) +layer["pwell"] = (41, 0) +layer["nwell"] = (42, 0) +layer["active"] = (43, 0) +layer["pimplant"] = (44, 0) +layer["nimplant"] = (45, 0) +layer["poly"] = (46, 0) +layer["active_contact"] = (48, 0) +layer["metal1"] = (49, 0) +layer["via1"] = (50, 0) +layer["metal2"] = (51, 0) +layer["via2"] = (61, 0) +layer["metal3"] = (62, 0) +layer["via3"] = (30, 0) +layer["metal4"] = (31, 0) +layer["text"] = (63, 0) +layer["boundary"] = (63, 0) +layer["blockage"] = (83, 0) ################################################### ##END GDS Layer Map From ecbed870c00f60e9d43d1760872bab55f24e6489 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 30 Oct 2019 06:54:11 -0700 Subject: [PATCH 007/521] Remove blockage layer. --- technology/freepdk45/tech/tech.py | 2 +- technology/scn4m_subm/tech/tech.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 07748390..8406fa53 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -67,7 +67,7 @@ layer["via9"] = (28, 0) layer["metal10"] = (29, 0) layer["text"] = (239, 0) layer["boundary"]= (239, 0) -layer["blockage"]= (239, 0) +#layer["blockage"]= (239, 0) ################################################### ##END GDS Layer Map diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 3964a088..c74d7ee5 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -54,7 +54,7 @@ layer["via3"] = (30, 0) layer["metal4"] = (31, 0) layer["text"] = (63, 0) layer["boundary"] = (63, 0) -layer["blockage"] = (83, 0) +#layer["blockage"] = (83, 0) ################################################### ##END GDS Layer Map From 35e65fc6f294c473cb277750b845db1af790356b Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Wed, 6 Nov 2019 21:19:36 +0000 Subject: [PATCH 008/521] PEP8 wordline driver --- compiler/modules/wordline_driver.py | 81 ++++++++++++++--------------- 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index b1292560..a0a92b35 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -5,17 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from tech import drc, parameter import debug import design import contact -from math import log -from math import sqrt -import math from vector import vector from sram_factory import factory from globals import OPTS + class wordline_driver(design.design): """ Creates a Wordline Driver @@ -58,26 +55,20 @@ class wordline_driver(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - def add_modules(self): - # This is just used for measurements, - # so don't add the module - self.inv = factory.create(module_type="pdriver", fanout=self.cols, neg_polarity=True) self.add_mod(self.inv) - self.inv_no_output = factory.create(module_type="pinv", - route_output=False) - self.add_mod(self.inv_no_output) - self.nand2 = factory.create(module_type="pnand2") self.add_mod(self.nand2) - def route_vdd_gnd(self): - """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ + """ + Add a pin for each row of vdd/gnd which + are must-connects next level up. + """ # Find the x offsets for where the vias/pins should be placed a_xoffset = self.nand_inst[0].rx() @@ -86,7 +77,9 @@ class wordline_driver(design.design): # this will result in duplicate polygons for rails, but who cares # use the inverter offset even though it will be the nand's too - (gate_offset, y_dir) = self.get_gate_offset(0, self.inv.height, num) + (gate_offset, y_dir) = self.get_gate_offset(0, + self.inv.height, + num) # Route both supplies for name in ["vdd", "gnd"]: @@ -97,8 +90,6 @@ class wordline_driver(design.design): pin_pos = vector(xoffset, supply_pin.cy()) self.add_power_pin(name, pin_pos) - - def create_drivers(self): self.nand_inst = [] self.inv2_inst = [] @@ -119,8 +110,7 @@ class wordline_driver(design.design): self.connect_inst(["wl_bar_{0}".format(row), "wl_{0}".format(row), "vdd", "gnd"]) - - + def place_drivers(self): nand2_xoffset = 2*self.m1_width + 5*self.m1_space inv2_xoffset = nand2_xoffset + self.nand2.width @@ -136,8 +126,8 @@ class wordline_driver(design.design): y_offset = self.inv.height*row inst_mirror = "R0" - nand2_offset=[nand2_xoffset, y_offset] - inv2_offset=[inv2_xoffset, y_offset] + nand2_offset = [nand2_xoffset, y_offset] + inv2_offset = [inv2_xoffset, y_offset] # add nand 2 self.nand_inst[row].place(offset=nand2_offset, @@ -146,17 +136,16 @@ class wordline_driver(design.design): self.inv2_inst[row].place(offset=inv2_offset, mirror=inst_mirror) - def route_layout(self): """ Route all of the signals """ # Wordline enable connection - en_pin=self.add_layout_pin(text="en", - layer="metal2", - offset=[self.m1_width + 2*self.m1_space,0], - width=self.m2_width, - height=self.height) - + en_offset = [self.m1_width + 2 * self.m1_space, 0] + en_pin = self.add_layout_pin(text="en", + layer="metal2", + offset=en_offset, + width=self.m2_width, + height=self.height) for row in range(self.rows): nand_inst = self.nand_inst[row] @@ -165,7 +154,7 @@ class wordline_driver(design.design): # en connection a_pin = nand_inst.get_pin("A") a_pos = a_pin.lc() - clk_offset = vector(en_pin.bc().x,a_pos.y) + clk_offset = vector(en_pin.bc().x, a_pos.y) self.add_segment_center(layer="metal1", start=clk_offset, end=a_pos) @@ -183,10 +172,14 @@ class wordline_driver(design.design): # connect the decoder input pin to nand2 B b_pin = nand_inst.get_pin("B") b_pos = b_pin.lc() - # needs to move down since B nand input is nearly aligned with A inv input - up_or_down = self.m2_space if row%2 else -self.m2_space - input_offset = vector(0,b_pos.y + up_or_down) - mid_via_offset = vector(clk_offset.x,input_offset.y) + vector(0.5*self.m2_width+self.m2_space+0.5*contact.m1m2.width,0) + # needs to move down since B nand input is + # nearly aligned with A inv input + up_or_down = self.m2_space if row % 2 else -self.m2_space + input_offset = vector(0, b_pos.y + up_or_down) + base_offset = vector(clk_offset.x, input_offset.y) + contact_offset = vector(0.5 * self.m2_width + self.m2_space + 0.5 * contact.m1m2.width, 0) + mid_via_offset = base_offset + contact_offset + # must under the clk line in M1 self.add_layout_pin_segment_center(text="in_{0}".format(row), layer="metal1", @@ -194,24 +187,27 @@ class wordline_driver(design.design): end=mid_via_offset) self.add_via_center(layers=("metal1", "via1", "metal2"), offset=mid_via_offset, - directions=("V","V")) + directions=("V", "V")) # now connect to the nand2 B self.add_path("metal2", [mid_via_offset, b_pos]) + contact_offset = b_pos - vector(0.5 * contact.m1m2.height, 0) self.add_via_center(layers=("metal1", "via1", "metal2"), - offset=b_pos - vector(0.5*contact.m1m2.height,0), - directions=("H","H")) - + offset=contact_offset, + directions=("H", "H")) # output each WL on the right wl_offset = inv2_inst.get_pin("Z").rc() self.add_layout_pin_segment_center(text="wl_{0}".format(row), layer="metal1", start=wl_offset, - end=wl_offset-vector(self.m1_width,0)) + end=wl_offset - vector(self.m1_width, 0)) def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): - """Follows the clk_buf to a wordline signal adding each stages stage effort to a list""" + """ + Follows the clk_buf to a wordline signal adding + each stages stage effort to a list. + """ stage_effort_list = [] stage1_cout = self.inv.get_cin() @@ -225,7 +221,10 @@ class wordline_driver(design.design): return stage_effort_list def get_wl_en_cin(self): - """Get the relative capacitance of all the enable connections in the bank""" - #The enable is connected to a nand2 for every row. + """ + Get the relative capacitance of all + the enable connections in the bank + """ + # The enable is connected to a nand2 for every row. total_cin = self.nand2.get_cin() * self.rows return total_cin From a2422cc8d4bc1f74ba42f62763f4b720861b3737 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Wed, 6 Nov 2019 21:51:21 +0000 Subject: [PATCH 009/521] Sometimes round down pdriver to fix polarity --- compiler/modules/wordline_driver.py | 12 +++---- compiler/pgates/pdriver.py | 53 +++++++++++++++++++++-------- 2 files changed, 44 insertions(+), 21 deletions(-) diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index a0a92b35..fbd800b2 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -65,9 +65,9 @@ class wordline_driver(design.design): self.add_mod(self.nand2) def route_vdd_gnd(self): - """ - Add a pin for each row of vdd/gnd which - are must-connects next level up. + """ + Add a pin for each row of vdd/gnd which + are must-connects next level up. """ # Find the x offsets for where the vias/pins should be placed @@ -91,8 +91,8 @@ class wordline_driver(design.design): self.add_power_pin(name, pin_pos) def create_drivers(self): - self.nand_inst = [] - self.inv2_inst = [] + self.nand_inst = [] + self.inv2_inst = [] for row in range(self.rows): name_nand = "wl_driver_nand{}".format(row) name_inv2 = "wl_driver_inv{}".format(row) @@ -164,7 +164,7 @@ class wordline_driver(design.design): # Nand2 out to 2nd inv zr_pos = nand_inst.get_pin("Z").rc() al_pos = inv2_inst.get_pin("A").lc() - # ensure the bend is in the middle + # ensure the bend is in the middle mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y) mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y) self.add_path("metal1", [zr_pos, mid1_pos, mid2_pos, al_pos]) diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index bb7739b7..2e778220 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -27,12 +27,12 @@ class pdriver(pgate.pgate): self.size_list = size_list self.fanout = fanout - if not size_list and self.fanout == 0: - debug.error("Either fanout or size list must be specified.", -1) - if self.size_list and self.fanout != 0: - debug.error("Cannot specify both size_list and fanout.", -1) - if self.size_list and self.neg_polarity: - debug.error("Cannot specify both size_list and neg_polarity.", -1) + debug.check(self.size_list or self.fanout > 0, + "Either fanout or size list must be specified.") + debug.check(not (self.size_list and self.fanout > 0), + "Cannot specify both size_list and fanout.") + debug.check(not (self.size_list and self.neg_polarity), + "Cannot specify both size_list and neg_polarity.") # Creates the netlist and layout pgate.pgate.__init__(self, name, height) @@ -43,21 +43,44 @@ class pdriver(pgate.pgate): self.num_stages = len(self.size_list) else: # Find the optimal number of stages for the given effort - self.num_stages = max(1, - int(round(self.fanout ** (1 / self.stage_effort)))) + optimal_stages = self.fanout ** (1 / self.stage_effort) + rounded_stages = int(round(optimal_stages)) + difference = optimal_stages - rounded_stages - # Increase the number of stages if we need to fix polarity - if self.neg_polarity and (self.num_stages % 2 == 0): - self.num_stages += 1 - elif not self.neg_polarity and (self.num_stages % 2): - self.num_stages += 1 + + # Determine if we need to fix the polarity + if self.neg_polarity and (rounded_stages % 2 == 0): + wrong_polarity = True + elif not self.neg_polarity and (optimal_stages % 2): + wrong_polarity = True + else: + wrong_polarity = False + + # Depending on the difference, round up or down. + if wrong_polarity: + # If we rounded up and can round down, do it. + if difference < 0 and rounded_stages > 1: + rounded_stages -= 1 + else: + # Otherwise, we must round up + rounded_stages += 1 + + if self.neg_polarity: + # Need at least one stage for negative + self.num_stages = max(1, rounded_stages) + else: + # Need at least two stages for positive + self.num_stages = max(2, rounded_stages) + # Use the actual stage effort + actual_stage_effort = self.fanout / self.num_stages + self.size_list = [] # compute sizes backwards from the fanout fanout_prev = self.fanout for x in range(self.num_stages): - fanout_prev = max(round(fanout_prev / self.stage_effort), 1) - self.size_list.append(fanout_prev) + fanout_prev = fanout_prev / actual_stage_effort + self.size_list.append(max(round(fanout_prev), 1)) # reverse the sizes to be from input to output self.size_list.reverse() From 0dea153919e6c3ab5d5fb4b4da58be7ff847cefe Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Thu, 7 Nov 2019 16:33:13 +0000 Subject: [PATCH 010/521] PEP8 formatting --- compiler/router/pin_group.py | 231 ++++++------ compiler/router/router.py | 656 ++++++++++++++++++----------------- 2 files changed, 468 insertions(+), 419 deletions(-) diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index 99986e76..df97bf9b 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -7,17 +7,15 @@ # from direction import direction from pin_layout import pin_layout -from vector3d import vector3d from vector import vector -import grid_utils -from tech import drc import debug + class pin_group: """ - A class to represent a group of rectangular design pin. - It requires a router to define the track widths and blockages which - determine how pin shapes get mapped to tracks. + A class to represent a group of rectangular design pin. + It requires a router to define the track widths and blockages which + determine how pin shapes get mapped to tracks. It is initially constructed with a single set of (touching) pins. """ def __init__(self, name, pin_set, router): @@ -30,19 +28,22 @@ class pin_group: # Remove any redundant pins (i.e. contained in other pins) irredundant_pin_set = self.remove_redundant_shapes(list(pin_set)) - # This is a list because we can have a pin group of disconnected sets of pins + # This is a list because we can have a pin + # group of disconnected sets of pins # and these are represented by separate lists self.pins = set(irredundant_pin_set) self.router = router # These are the corresponding pin grids for each pin group. self.grids = set() - # These are the secondary grids that could or could not be part of the pin + # These are the secondary grids that could + # or could not be part of the pin self.secondary_grids = set() # The corresponding set of partially blocked grids for each pin group. - # These are blockages for other nets but unblocked for routing this group. - # These are also blockages if we used a simple enclosure to route to a rail. + # These are blockages for other nets but unblocked + # for routing this group. These are also blockages if we + # used a simple enclosure to route to a rail. self.blockages = set() # This is a set of pin_layout shapes to cover the grids @@ -88,22 +89,23 @@ class pin_group: """ local_debug = False if local_debug: - debug.info(0,"INITIAL: {}".format(pin_list)) + debug.info(0, "INITIAL: {}".format(pin_list)) # Make a copy of the list to start new_pin_list = pin_list.copy() remove_indices = set() # This is n^2, but the number is small - for index1,pin1 in enumerate(pin_list): + for index1, pin1 in enumerate(pin_list): # If we remove this pin, it can't contain other pins if index1 in remove_indices: continue - for index2,pin2 in enumerate(pin_list): - # Can't contain yourself, but compare the indices and not the pins + for index2, pin2 in enumerate(pin_list): + # Can't contain yourself, + # but compare the indices and not the pins # so you can remove duplicate copies. - if index1==index2: + if index1 == index2: continue # If we already removed it, can't remove it again... if index2 in remove_indices: @@ -111,7 +113,7 @@ class pin_group: if pin1.contains(pin2): if local_debug: - debug.info(0,"{0} contains {1}".format(pin1,pin2)) + debug.info(0, "{0} contains {1}".format(pin1, pin2)) remove_indices.add(index2) # Remove them in decreasing order to not invalidate the indices @@ -119,7 +121,7 @@ class pin_group: del new_pin_list[i] if local_debug: - debug.info(0,"FINAL : {}".format(new_pin_list)) + debug.info(0, "FINAL : {}".format(new_pin_list)) return new_pin_list @@ -130,23 +132,26 @@ class pin_group: # Enumerate every possible enclosure pin_list = [] for seed in self.grids: - (ll, ur) = self.enclose_pin_grids(seed, direction.NORTH, direction.EAST) + (ll, ur) = self.enclose_pin_grids(seed, + direction.NORTH, + direction.EAST) enclosure = self.router.compute_pin_enclosure(ll, ur, ll.z) pin_list.append(enclosure) - (ll, ur) = self.enclose_pin_grids(seed, direction.EAST, direction.NORTH) + (ll, ur) = self.enclose_pin_grids(seed, + direction.EAST, + direction.NORTH) enclosure = self.router.compute_pin_enclosure(ll, ur, ll.z) pin_list.append(enclosure) - # Now simplify the enclosure list new_pin_list = self.remove_redundant_shapes(pin_list) return new_pin_list def compute_connector(self, pin, enclosure): - """ - Compute a shape to connect the pin to the enclosure shape. + """ + Compute a shape to connect the pin to the enclosure shape. This assumes the shape will be the dimension of the pin. """ if pin.xoverlaps(enclosure): @@ -154,9 +159,9 @@ class pin_group: plc = pin.lc() prc = pin.rc() elc = enclosure.lc() - erc = enclosure.rc() - ymin = min(plc.y,elc.y) - ymax = max(plc.y,elc.y) + # erc = enclosure.rc() + ymin = min(plc.y, elc.y) + ymax = max(plc.y, elc.y) ll = vector(plc.x, ymin) ur = vector(prc.x, ymax) elif pin.yoverlaps(enclosure): @@ -164,9 +169,9 @@ class pin_group: pbc = pin.bc() puc = pin.uc() ebc = enclosure.bc() - euc = enclosure.uc() - xmin = min(pbc.x,ebc.x) - xmax = max(pbc.x,ebc.x) + # euc = enclosure.uc() + xmin = min(pbc.x, ebc.x) + xmax = max(pbc.x, ebc.x) ll = vector(xmin, pbc.y) ur = vector(xmax, puc.y) else: @@ -180,7 +185,7 @@ class pin_group: ll = vector(xmin, ymin) ur = vector(xmax, ymax) - if ll.x==ur.x or ll.y==ur.y: + if ll.x == ur.x or ll.y == ur.y: return None p = pin_layout(pin.name, [ll, ur], pin.layer) return p @@ -202,13 +207,13 @@ class pin_group: # Find the bottom edge that is next to the pin's top edge above_item = None for item in edge_list: - if item.by()>=pin.uy(): + if item.by() >= pin.uy(): above_item = item else: break - # There was nothing - if above_item==None: + # There was nothing + if not above_item: return None # If it already overlaps, no connector needed if above_item.overlaps(pin): @@ -219,7 +224,7 @@ class pin_group: return p def find_below_connector(self, pin, enclosures): - """ + """ Find the enclosure that is below the pin and make a connector to it's upper edge. """ @@ -235,13 +240,13 @@ class pin_group: # Find the upper edge that is next to the pin's bottom edge bottom_item = None for item in edge_list: - if item.uy()<=pin.by(): + if item.uy() <= pin.by(): bottom_item = item else: break # There was nothing to the left - if bottom_item==None: + if not bottom_item: return None # If it already overlaps, no connector needed if bottom_item.overlaps(pin): @@ -274,7 +279,7 @@ class pin_group: break # There was nothing to the left - if left_item==None: + if not left_item: return None # If it already overlaps, no connector needed if left_item.overlaps(pin): @@ -301,13 +306,13 @@ class pin_group: # Find the left edge that is next to the pin's right edge right_item = None for item in edge_list: - if item.lx()>=pin.rx(): + if item.lx() >= pin.rx(): right_item = item else: break # There was nothing to the right - if right_item==None: + if not right_item: return None # If it already overlaps, no connector needed if right_item.overlaps(pin): @@ -319,50 +324,50 @@ class pin_group: def find_smallest_connector(self, pin_list, shape_list): """ - Compute all of the connectors between the overlapping pins and enclosure shape list.. + Compute all of the connectors between the overlapping + pins and enclosure shape list. Return the smallest. """ smallest = None for pin in pin_list: for enclosure in shape_list: new_enclosure = self.compute_connector(pin, enclosure) - if smallest == None or new_enclosure.area() min_width: - if smallest_shape == None or other.area()0): + connector_list = [left_connector, + right_connector, + above_connector, + below_connector] + filtered_list = list(filter(lambda x: not x, connector_list)) + if (len(filtered_list) > 0): import copy - bbox_connector = copy.copy(pin) + bbox_connector = copy.copy(pin) bbox_connector.bbox(filtered_list) self.enclosures.append(bbox_connector) - # Now, make sure each pin touches an enclosure. If not, add another (diagonal) connector. - # This could only happen when there was no enclosure in any cardinal direction from a pin + # Now, make sure each pin touches an enclosure. + # If not, add another (diagonal) connector. + # This could only happen when there was no enclosure + # in any cardinal direction from a pin if not self.overlap_any_shape(self.pins, self.enclosures): - connector = self.find_smallest_connector(self.pins, self.enclosures) - if connector==None: - debug.error("Could not find a connector for {} with {}".format(self.pins, self.enclosures)) + connector = self.find_smallest_connector(self.pins, + self.enclosures) + if not connector: + debug.error("Could not find a connector for {} with {}".format(self.pins, + self.enclosures)) self.router.write_debug_gds("no_connector.gds") self.enclosures.append(connector) - # At this point, the pins are overlapping, but there might be more than one! + # At this point, the pins are overlapping, + # but there might be more than one! overlap_set = set() for pin in self.pins: overlap_set.update(self.transitive_overlap(pin, self.enclosures)) - # Use the new enclosures and recompute the grids that correspond to them - if len(overlap_set)0: - debug.info(2,"Removing pins {}".format(shared_set)) + if len(shared_set) > 0: + debug.info(2, "Removing pins {}".format(shared_set)) pin_set.difference_update(shared_set) shared_set = partial_set & self.router.blocked_grids - if len(shared_set)>0: - debug.info(2,"Removing pins {}".format(shared_set)) + if len(shared_set) > 0: + debug.info(2, "Removing pins {}".format(shared_set)) partial_set.difference_update(shared_set) shared_set = blockage_set & self.router.blocked_grids - if len(shared_set)>0: - debug.info(2,"Removing blocks {}".format(shared_set)) + if len(shared_set) > 0: + debug.info(2, "Removing blocks {}".format(shared_set)) blockage_set.difference_update(shared_set) # At least one of the groups must have some valid tracks - if (len(pin_set)==0 and len(partial_set)==0 and len(blockage_set)==0): - #debug.warning("Pin is very close to metal blockage.\nAttempting to expand blocked pin {}".format(self.pins)) + if (len(pin_set) == 0 and len(partial_set) == 0 and len(blockage_set) == 0): + # debug.warning("Pin is very close to metal blockage.\nAttempting to expand blocked pin {}".format(self.pins)) for pin in self.pins: debug.warning(" Expanding conversion {0}".format(pin)) - # Determine which tracks the pin overlaps - (sufficient,insufficient)=self.router.convert_pin_to_tracks(self.name, pin, expansion=1) + # Determine which tracks the pin overlaps + (sufficient,insufficient)=self.router.convert_pin_to_tracks(self.name, + pin, + expansion=1) pin_set.update(sufficient) partial_set.update(insufficient) - if len(pin_set)==0 and len(partial_set)==0: - debug.error("Unable to find unblocked pin {} {}".format(self.name, self.pins)) + if len(pin_set) == 0 and len(partial_set) == 0: + debug.error("Unable to find unblocked pin {} {}".format(self.name, + self.pins)) self.router.write_debug_gds("blocked_pin.gds") # Consider all the grids that would be blocked - self.grids = pin_set | partial_set - # Remember the secondary grids for removing adjacent pins - self.secondary_grids = partial_set + self.grids = pin_set | partial_set + # Remember the secondary grids for removing adjacent pins + self.secondary_grids = partial_set - debug.info(2," pins {}".format(self.grids)) - debug.info(2," secondary {}".format(self.secondary_grids)) + debug.info(2, " pins {}".format(self.grids)) + debug.info(2, " secondary {}".format(self.secondary_grids)) diff --git a/compiler/router/router.py b/compiler/router/router.py index fd95def6..15f6f6b3 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -5,9 +5,9 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import sys + import gdsMill -from tech import drc,GDS +from tech import drc, GDS from tech import layer as techlayer import math import debug @@ -15,12 +15,12 @@ from router_tech import router_tech from pin_layout import pin_layout from pin_group import pin_group from vector import vector -from vector3d import vector3d -from globals import OPTS,print_time -from pprint import pformat +from vector3d import vector3d +from globals import OPTS, print_time import grid_utils from datetime import datetime + class router(router_tech): """ A router class to read an obstruction map from a gds and plan a @@ -31,7 +31,8 @@ class router(router_tech): def __init__(self, layers, design, gds_filename=None, rail_track_width=1): """ This will instantiate a copy of the gds file or the module at (0,0) and - route on top of this. The blockages from the gds/module will be considered. + route on top of this. The blockages from the gds/module will be + considered. """ router_tech.__init__(self, layers, rail_track_width) @@ -39,7 +40,7 @@ class router(router_tech): # If didn't specify a gds blockage file, write it out to read the gds # This isn't efficient, but easy for now - #start_time = datetime.now() + # start_time = datetime.now() if not gds_filename: gds_filename = OPTS.openram_temp+"temp.gds" self.cell.gds_write(gds_filename) @@ -49,32 +50,37 @@ class router(router_tech): self.reader = gdsMill.Gds2reader(self.layout) self.reader.loadFromFile(gds_filename) self.top_name = self.layout.rootStructureName - #print_time("GDS read",datetime.now(), start_time) + # print_time("GDS read",datetime.now(), start_time) - ### The pin data structures + # The pin data structures # A map of pin names to a set of pin_layout structures # (i.e. pins with a given label) self.pins = {} - # This is a set of all pins (ignoring names) so that can quickly not create blockages for pins - # (They will be blocked when we are routing other nets based on their name.) + # This is a set of all pins (ignoring names) so that can quickly + # not create blockages for pins + # (They will be blocked when we are routing other + # nets based on their name.) self.all_pins = set() - # The labeled pins above categorized into pin groups that are touching/connected. + # The labeled pins above categorized into pin groups + # that are touching/connected. self.pin_groups = {} - ### The blockage data structures - # A list of metal shapes (using the same pin_layout structure) that are not pins but blockages. - self.blockages=[] + # The blockage data structures + # A list of metal shapes (using the same pin_layout structure) + # that are not pins but blockages. + self.blockages = [] # The corresponding set of blocked grids for above pin shapes self.blocked_grids = set() - ### The routed data structures + # The routed data structures # A list of paths that have been "routed" self.paths = [] # A list of path blockages (they might be expanded for wide metal DRC) self.path_blockages = [] - # The boundary will determine the limits to the size of the routing grid + # The boundary will determine the limits to the size + # of the routing grid self.boundary = self.layout.measureBoundary(self.top_name) # These must be un-indexed to get rid of the matrix type self.ll = vector(self.boundary[0][0], self.boundary[0][1]) @@ -90,90 +96,90 @@ class router(router_tech): self.pin_groups = {} # DO NOT clear the blockages as these don't change self.rg.reinit() - - def set_top(self,top_name): + def set_top(self, top_name): """ If we want to route something besides the top-level cell.""" self.top_name = top_name - - def is_wave(self,path): + def is_wave(self, path): """ - Determines if this is a multi-track width wave (True) or a normal route (False) + Determines if this is a multi-track width wave (True) + # or a normal route (False) """ - return len(path[0])>1 + return len(path[0]) > 1 - - def retrieve_pins(self,pin_name): + def retrieve_pins(self, pin_name): """ Retrieve the pin shapes on metal 3 from the layout. """ - debug.info(2,"Retrieving pins for {}.".format(pin_name)) - shape_list=self.layout.getAllPinShapes(str(pin_name)) + debug.info(2, "Retrieving pins for {}.".format(pin_name)) + shape_list = self.layout.getAllPinShapes(str(pin_name)) pin_set = set() for shape in shape_list: - (layer,boundary)=shape + (layer, boundary) = shape # GDSMill boundaries are in (left, bottom, right, top) order # so repack and snap to the grid - ll = vector(boundary[0],boundary[1]).snap_to_grid() - ur = vector(boundary[2],boundary[3]).snap_to_grid() - rect = [ll,ur] + ll = vector(boundary[0], boundary[1]).snap_to_grid() + ur = vector(boundary[2], boundary[3]).snap_to_grid() + rect = [ll, ur] pin = pin_layout(pin_name, rect, layer) pin_set.add(pin) - debug.check(len(pin_set)>0,"Did not find any pin shapes for {0}.".format(str(pin_name))) + debug.check(len(pin_set) > 0, + "Did not find any pin shapes for {0}.".format(str(pin_name))) self.pins[pin_name] = pin_set self.all_pins.update(pin_set) for pin in self.pins[pin_name]: - debug.info(3,"Retrieved pin {}".format(str(pin))) - + debug.info(3, "Retrieved pin {}".format(str(pin))) def find_blockages(self): """ Iterate through all the layers and write the obstacles to the routing grid. - This doesn't consider whether the obstacles will be pins or not. They get reset later - if they are not actually a blockage. + This doesn't consider whether the obstacles will be pins or not. + They get reset later if they are not actually a blockage. """ - debug.info(1,"Finding blockages.") - for layer in [self.vert_layer_number,self.horiz_layer_number]: + debug.info(1, "Finding blockages.") + for layer in [self.vert_layer_number, self.horiz_layer_number]: self.retrieve_blockages(layer) def find_pins_and_blockages(self, pin_list): """ Find the pins and blockages in the design """ - # This finds the pin shapes and sorts them into "groups" that are connected - # This must come before the blockages, so we can not count the pins themselves + # This finds the pin shapes and sorts them into "groups" that + # are connected. This must come before the blockages, so we + # can not count the pins themselves # as blockages. start_time = datetime.now() for pin_name in pin_list: self.retrieve_pins(pin_name) - print_time("Retrieving pins",datetime.now(), start_time, 4) + print_time("Retrieving pins", datetime.now(), start_time, 4) start_time = datetime.now() for pin_name in pin_list: self.analyze_pins(pin_name) - print_time("Analyzing pins",datetime.now(), start_time, 4) + print_time("Analyzing pins", datetime.now(), start_time, 4) # This will get all shapes as blockages and convert to grid units # This ignores shapes that were pins start_time = datetime.now() self.find_blockages() - print_time("Finding blockages",datetime.now(), start_time, 4) + print_time("Finding blockages", datetime.now(), start_time, 4) # Convert the blockages to grid units start_time = datetime.now() self.convert_blockages() - print_time("Converting blockages",datetime.now(), start_time, 4) + print_time("Converting blockages", datetime.now(), start_time, 4) # This will convert the pins to grid units - # It must be done after blockages to ensure no DRCs between expanded pins and blocked grids + # It must be done after blockages to ensure no DRCs + # between expanded pins and blocked grids start_time = datetime.now() for pin in pin_list: self.convert_pins(pin) - print_time("Converting pins",datetime.now(), start_time, 4) + print_time("Converting pins", datetime.now(), start_time, 4) # Combine adjacent pins into pin groups to reduce run-time # by reducing the number of maze routes. @@ -184,17 +190,18 @@ class router(router_tech): # print_time("Combining adjacent pins",datetime.now(), start_time, 4) - # Separate any adjacent grids of differing net names that overlap + # Separate any adjacent grids of differing net names + # that overlap # Must be done before enclosing pins start_time = datetime.now() self.separate_adjacent_pins(0) - print_time("Separating adjacent pins",datetime.now(), start_time, 4) + print_time("Separating adjacent pins", datetime.now(), start_time, 4) - # Enclose the continguous grid units in a metal rectangle to fix some DRCs + # Enclose the continguous grid units in a metal + # rectangle to fix some DRCs start_time = datetime.now() self.enclose_pins() - print_time("Enclosing pins",datetime.now(), start_time, 4) - + print_time("Enclosing pins", datetime.now(), start_time, 4) # MRG: Removing this code for now. The later compute enclosure code # assumes that all pins are touching and this may produce sets of pins @@ -249,57 +256,63 @@ class router(router_tech): # # Use the new pin group! # self.pin_groups[pin_name] = new_pin_groups # removed_pairs = old_size - len(new_pin_groups) - # debug.info(1, "Combined {0} pin groups for {1}".format(removed_pairs,pin_name)) + # debug.info(1, + # "Combined {0} pin groups for {1}".format(removed_pairs,pin_name)) # return removed_pairs - def separate_adjacent_pins(self, separation): """ - This will try to separate all grid pins by the supplied number of separation - tracks (default is to prevent adjacency). + This will try to separate all grid pins by the supplied + number of separation tracks (default is to prevent adjacency). """ # Commented out to debug with SCMOS - #if separation==0: - # return + # if separation==0: + # return pin_names = self.pin_groups.keys() - for i,pin_name1 in enumerate(pin_names): - for j,pin_name2 in enumerate(pin_names): - if i==j: + for i, pin_name1 in enumerate(pin_names): + for j, pin_name2 in enumerate(pin_names): + if i == j: continue - if i>j: + if i > j: return self.separate_adjacent_pin(pin_name1, pin_name2, separation) def separate_adjacent_pin(self, pin_name1, pin_name2, separation): """ - Go through all of the pin groups and check if any other pin group is + Go through all of the pin groups and check if any other pin group is within a separation of it. If so, reduce the pin group grid to not include the adjacent grid. Try to do this intelligently to keep th pins enclosed. """ - debug.info(1,"Comparing {0} and {1} adjacency".format(pin_name1, pin_name2)) + debug.info(1, + "Comparing {0} and {1} adjacency".format(pin_name1, + pin_name2)) removed_grids = 0 - for index1,pg1 in enumerate(self.pin_groups[pin_name1]): - for index2,pg2 in enumerate(self.pin_groups[pin_name2]): + for index1, pg1 in enumerate(self.pin_groups[pin_name1]): + for index2, pg2 in enumerate(self.pin_groups[pin_name2]): adj_grids = pg1.adjacent_grids(pg2, separation) removed_grids += len(adj_grids) # These should have the same length, so... - if len(adj_grids)>0: - debug.info(3,"Adjacent grids {0} {1} adj={2}".format(index1,index2,adj_grids)) + if len(adj_grids) > 0: + debug.info(3, + "Adjacent grids {0} {1} adj={2}".format(index1, + index2, + adj_grids)) self.remove_adjacent_grid(pg1, pg2, adj_grids) - debug.info(1,"Removed {} adjacent grids.".format(removed_grids)) + debug.info(1, "Removed {} adjacent grids.".format(removed_grids)) def remove_adjacent_grid(self, pg1, pg2, adj_grids): """ Remove one of the adjacent grids in a heuristic manner. - This will try to keep the groups similar sized by removing from the bigger group. + This will try to keep the groups similar sized by + removing from the bigger group. """ - if pg1.size()>pg2.size(): + if pg1.size() > pg2.size(): bigger = pg1 smaller = pg2 else: @@ -309,54 +322,58 @@ class router(router_tech): for adj in adj_grids: - # If the adjacent grids are a subset of the secondary grids (i.e. not necessary) - # remove them from each + # If the adjacent grids are a subset of the secondary + # grids (i.e. not necessary) remove them from each if adj in bigger.secondary_grids: - debug.info(3,"Removing {} from bigger secondary {}".format(adj, bigger)) + debug.info(3,"Removing {} from bigger secondary {}".format(adj, + bigger)) bigger.grids.remove(adj) bigger.secondary_grids.remove(adj) self.blocked_grids.add(adj) elif adj in smaller.secondary_grids: - debug.info(3,"Removing {} from smaller secondary {}".format(adj, smaller)) + debug.info(3,"Removing {} from smaller secondary {}".format(adj, + smaller)) smaller.grids.remove(adj) smaller.secondary_grids.remove(adj) self.blocked_grids.add(adj) else: - # If we couldn't remove from a secondary grid, we must remove from the primary + # If we couldn't remove from a secondary grid, + # we must remove from the primary # grid of at least one pin if adj in bigger.grids: - debug.info(3,"Removing {} from bigger primary {}".format(adj, bigger)) + debug.info(3,"Removing {} from bigger primary {}".format(adj, + bigger)) bigger.grids.remove(adj) elif adj in smaller.grids: - debug.info(3,"Removing {} from smaller primary {}".format(adj, smaller)) + debug.info(3,"Removing {} from smaller primary {}".format(adj, + smaller)) smaller.grids.remove(adj) - - - def prepare_blockages(self, pin_name): """ Reset and add all of the blockages in the design. Names is a list of pins to add as a blockage. """ - debug.info(3,"Preparing blockages.") + debug.info(3, "Preparing blockages.") # Start fresh. Not the best for run-time, but simpler. self.clear_blockages() # This adds the initial blockges of the design - #print("BLOCKING:",self.blocked_grids) - self.set_blockages(self.blocked_grids,True) + #print("BLOCKING:", self.blocked_grids) + self.set_blockages(self.blocked_grids, True) - # Block all of the supply rails (some will be unblocked if they're a target) + # Block all of the supply rails + # (some will be unblocked if they're a target) self.set_supply_rail_blocked(True) - # Block all of the pin components (some will be unblocked if they're a source/target) + # Block all of the pin components + # (some will be unblocked if they're a source/target) # Also block the previous routes for name in self.pin_groups: blockage_grids = {y for x in self.pin_groups[name] for y in x.grids} - self.set_blockages(blockage_grids,True) + self.set_blockages(blockage_grids, True) blockage_grids = {y for x in self.pin_groups[name] for y in x.blockages} - self.set_blockages(blockage_grids,True) + self.set_blockages(blockage_grids, True) # FIXME: These duplicate a bit of work # These are the paths that have already been routed. @@ -366,22 +383,20 @@ class router(router_tech): # directly to a rail, but unblock all the source components so we can # route over them blockage_grids = {y for x in self.pin_groups[pin_name] for y in x.grids} - self.set_blockages(blockage_grids,False) - + self.set_blockages(blockage_grids, False) def convert_shape_to_units(self, shape): - """ - Scale a shape (two vector list) to user units + """ + Scale a shape (two vector list) to user units """ unit_factor = [GDS["unit"][0]] * 2 - ll=shape[0].scale(unit_factor) - ur=shape[1].scale(unit_factor) - return [ll,ur] - + ll = shape[0].scale(unit_factor) + ur = shape[1].scale(unit_factor) + return [ll, ur] def min_max_coord(self, coord): - """ - Find the lowest and highest corner of a Rectangle + """ + Find the lowest and highest corner of a Rectangle """ coordinate = [] minx = min(coord[0][0], coord[1][0], coord[2][0], coord[3][0]) @@ -392,24 +407,24 @@ class router(router_tech): coordinate += [vector(maxx, maxy)] return coordinate - def get_inertia(self,p0,p1): - """ - Sets the direction based on the previous direction we came from. + def get_inertia(self, p0, p1): + """ + Sets the direction based on the previous direction we came from. """ # direction (index) of movement - if p0.x!=p1.x: + if p0.x != p1.x: return 0 - elif p0.y!=p1.y: + elif p0.y != p1.y: return 1 else: # z direction return 2 def clear_blockages(self): - """ + """ Clear all blockages on the grid. """ - debug.info(3,"Clearing all blockages") + debug.info(3, "Clearing all blockages") self.rg.clear_blockages() def set_blockages(self, blockages, value=True): @@ -417,137 +432,142 @@ class router(router_tech): self.rg.set_blocked(blockages, value) def get_blockage_tracks(self, ll, ur, z): - debug.info(3,"Converting blockage ll={0} ur={1} z={2}".format(str(ll),str(ur),z)) + debug.info(3, "Converting blockage ll={0} ur={1} z={2}".format(str(ll),str(ur),z)) block_list = [] - for x in range(int(ll[0]),int(ur[0])+1): - for y in range(int(ll[1]),int(ur[1])+1): - block_list.append(vector3d(x,y,z)) + for x in range(int(ll[0]), int(ur[0])+1): + for y in range(int(ll[1]), int(ur[1])+1): + block_list.append(vector3d(x, y, z)) return set(block_list) def convert_blockage(self, blockage): - """ - Convert a pin layout blockage shape to routing grid tracks. + """ + Convert a pin layout blockage shape to routing grid tracks. """ # Inflate the blockage by half a spacing rule - [ll,ur]=self.convert_blockage_to_tracks(blockage.inflate()) + [ll, ur] = self.convert_blockage_to_tracks(blockage.inflate()) zlayer = self.get_zindex(blockage.layer_num) blockage_tracks = self.get_blockage_tracks(ll, ur, zlayer) return blockage_tracks def convert_blockages(self): """ Convert blockages to grid tracks. """ - debug.info(1,"Converting blockages.") + debug.info(1, "Converting blockages.") for blockage in self.blockages: - debug.info(3,"Converting blockage {}".format(str(blockage))) + debug.info(3, "Converting blockage {}".format(str(blockage))) blockage_list = self.convert_blockage(blockage) self.blocked_grids.update(blockage_list) - - def retrieve_blockages(self, layer_num): + def retrieve_blockages(self, layer_num): """ Recursive find boundaries as blockages to the routing grid. """ shapes = self.layout.getAllShapes(layer_num) for boundary in shapes: - ll = vector(boundary[0],boundary[1]) - ur = vector(boundary[2],boundary[3]) - rect = [ll,ur] - new_pin = pin_layout("blockage{}".format(len(self.blockages)),rect,layer_num) + ll = vector(boundary[0], boundary[1]) + ur = vector(boundary[2], boundary[3]) + rect = [ll, ur] + new_pin = pin_layout("blockage{}".format(len(self.blockages)), + rect, + layer_num) - # If there is a rectangle that is the same in the pins, it isn't a blockage! + # If there is a rectangle that is the same in the pins, + # it isn't a blockage! if new_pin not in self.all_pins: self.blockages.append(new_pin) - def convert_point_to_units(self, p): """ Convert a path set of tracks to center line path. """ pt = vector3d(p) - pt = pt.scale(self.track_widths[0],self.track_widths[1],1) + pt = pt.scale(self.track_widths[0], self.track_widths[1], 1) return pt def convert_wave_to_units(self, wave): - """ - Convert a wave to a set of center points + """ + Convert a wave to a set of center points """ return [self.convert_point_to_units(i) for i in wave] - def convert_blockage_to_tracks(self, shape): - """ + """ Convert a rectangular blockage shape into track units. """ - (ll,ur) = shape + (ll, ur) = shape ll = snap_to_grid(ll) ur = snap_to_grid(ur) # to scale coordinates to tracks - debug.info(3,"Converting [ {0} , {1} ]".format(ll,ur)) - old_ll = ll - old_ur = ur - ll=ll.scale(self.track_factor) - ur=ur.scale(self.track_factor) + debug.info(3, "Converting [ {0} , {1} ]".format(ll, ur)) + ll = ll.scale(self.track_factor) + ur = ur.scale(self.track_factor) # We can round since we are using inflated shapes # and the track points are at the center ll = ll.round() ur = ur.round() - return [ll,ur] + return [ll, ur] def convert_pin_to_tracks(self, pin_name, pin, expansion=0): - """ - Convert a rectangular pin shape into a list of track locations,layers. - If no pins are "on-grid" (i.e. sufficient overlap) it makes the one with most overlap if it is not blocked. - If expansion>0, expamine areas beyond the current pin when it is blocked. """ - (ll,ur) = pin.rect - debug.info(3,"Converting pin [ {0} , {1} ]".format(ll,ur)) + Convert a rectangular pin shape into a list of track locations,layers. + If no pins are "on-grid" (i.e. sufficient overlap) + it makes the one with most overlap if it is not blocked. + If expansion>0, expamine areas beyond the current pin + when it is blocked. + """ + (ll, ur) = pin.rect + debug.info(3, "Converting pin [ {0} , {1} ]".format(ll, ur)) # scale the size bigger to include neaby tracks - ll=ll.scale(self.track_factor).floor() - ur=ur.scale(self.track_factor).ceil() + ll = ll.scale(self.track_factor).floor() + ur = ur.scale(self.track_factor).ceil() # Keep tabs on tracks with sufficient and insufficient overlap sufficient_list = set() insufficient_list = set() - zindex=self.get_zindex(pin.layer_num) - for x in range(int(ll[0])+expansion,int(ur[0])+1+expansion): - for y in range(int(ll[1]+expansion),int(ur[1])+1+expansion): - (full_overlap, partial_overlap) = self.convert_pin_coord_to_tracks(pin, vector3d(x,y,zindex)) + zindex = self.get_zindex(pin.layer_num) + for x in range(int(ll[0]) + expansion, int(ur[0]) + 1 + expansion): + for y in range(int(ll[1] + expansion), int(ur[1]) + 1 + expansion): + (full_overlap, partial_overlap) = self.convert_pin_coord_to_tracks(pin, + vector3d(x, + y, + zindex)) if full_overlap: sufficient_list.update([full_overlap]) if partial_overlap: insufficient_list.update([partial_overlap]) - debug.info(2,"Converting [ {0} , {1} ] full={2}".format(x,y, full_overlap)) + debug.info(2, + "Converting [ {0} , {1} ] full={2}".format(x, + y, + full_overlap)) # Return all grids with any potential overlap (sufficient or not) - return (sufficient_list,insufficient_list) - + return (sufficient_list, insufficient_list) def get_all_offgrid_pin(self, pin, insufficient_list): - """ + """ Find a list of all pins with some overlap. """ - #print("INSUFFICIENT LIST",insufficient_list) + # print("INSUFFICIENT LIST",insufficient_list) # Find the coordinate with the most overlap any_overlap = set() for coord in insufficient_list: full_pin = self.convert_track_to_pin(coord) # Compute the overlap with that rectangle - overlap_rect=pin.compute_overlap(full_pin) + overlap_rect = pin.compute_overlap(full_pin) # Determine the max x or y overlap max_overlap = max(overlap_rect) - if max_overlap>0: + if max_overlap > 0: any_overlap.update([coord]) return any_overlap def get_best_offgrid_pin(self, pin, insufficient_list): - """ + """ Find a list of the single pin with the most overlap. """ # Find the coordinate with the most overlap @@ -556,17 +576,17 @@ class router(router_tech): for coord in insufficient_list: full_pin = self.convert_track_to_pin(coord) # Compute the overlap with that rectangle - overlap_rect=pin.compute_overlap(full_pin) + overlap_rect = pin.compute_overlap(full_pin) # Determine the min x or y overlap min_overlap = min(overlap_rect) - if min_overlap>best_overlap: - best_overlap=min_overlap - best_coord=coord + if min_overlap > best_overlap: + best_overlap = min_overlap + best_coord = coord return set([best_coord]) def get_furthest_offgrid_pin(self, pin, insufficient_list): - """ + """ Get a grid cell that is the furthest from the blocked grids. """ @@ -575,14 +595,14 @@ class router(router_tech): best_dist = math.inf for coord in insufficient_list: min_dist = grid_utils.distance_set(coord, self.blocked_grids) - if min_dist 0: - debug.info(2," Overlap: {0} >? {1}".format(overlap_length,0)) - return (coord,None) + if overlap_length == math.inf or overlap_length > 0: + debug.info(2," Overlap: {0} >? {1}".format(overlap_length, 0)) + return (coord, None) # If it overlaps with the inflated pin, it is partial - elif inflated_overlap_length==math.inf or inflated_overlap_length > 0: - debug.info(2," Partial overlap: {0} >? {1}".format(inflated_overlap_length,0)) - return (None,coord) + elif inflated_overlap_length == math.inf or inflated_overlap_length > 0: + debug.info(2," Partial overlap: {0} >? {1}".format(inflated_overlap_length, 0)) + return (None, coord) else: - debug.info(2," No overlap: {0} {1}".format(overlap_length,0)) - return (None,None) - + debug.info(2, " No overlap: {0} {1}".format(overlap_length, 0)) + return (None, None) def convert_track_to_pin(self, track): - """ + """ Convert a grid point into a rectangle shape that is centered track in the track and leaves half a DRC space in each direction. """ - # calculate lower left - x = track.x*self.track_width - 0.5*self.track_width + 0.5*self.track_space - y = track.y*self.track_width - 0.5*self.track_width + 0.5*self.track_space + # calculate lower left + x = track.x * self.track_width - 0.5 * self.track_width + 0.5 * self.track_space + y = track.y * self.track_width - 0.5 * self.track_width + 0.5 * self.track_space ll = snap_to_grid(vector(x,y)) # calculate upper right - x = track.x*self.track_width + 0.5*self.track_width - 0.5*self.track_space - y = track.y*self.track_width + 0.5*self.track_width - 0.5*self.track_space - ur = snap_to_grid(vector(x,y)) + x = track.x * self.track_width + 0.5 * self.track_width - 0.5 * self.track_space + y = track.y * self.track_width + 0.5 * self.track_width - 0.5 * self.track_space + ur = snap_to_grid(vector(x, y)) p = pin_layout("", [ll, ur], self.get_layer(track[2])) return p def convert_track_to_shape_pin(self, track): - """ - Convert a grid point into a rectangle shape that occupies the entire centered - track. + """ + Convert a grid point into a rectangle shape + that occupies the entire centered track. """ # to scale coordinates to tracks x = track[0]*self.track_width - 0.5*self.track_width y = track[1]*self.track_width - 0.5*self.track_width # offset lowest corner object to to (-track halo,-track halo) - ll = snap_to_grid(vector(x,y)) - ur = snap_to_grid(ll + vector(self.track_width,self.track_width)) + ll = snap_to_grid(vector(x, y)) + ur = snap_to_grid(ll + vector(self.track_width, self.track_width)) p = pin_layout("", [ll, ur], self.get_layer(track[2])) return p def convert_track_to_shape(self, track): - """ - Convert a grid point into a rectangle shape that occupies the entire centered - track. + """ + Convert a grid point into a rectangle shape + that occupies the entire centered track. """ # to scale coordinates to tracks try: x = track[0]*self.track_width - 0.5*self.track_width except TypeError: - print(track[0],type(track[0]),self.track_width,type(self.track_width)) + print(track[0], type(track[0]), self.track_width, type(self.track_width)) y = track[1]*self.track_width - 0.5*self.track_width # offset lowest corner object to to (-track halo,-track halo) - ll = snap_to_grid(vector(x,y)) - ur = snap_to_grid(ll + vector(self.track_width,self.track_width)) + ll = snap_to_grid(vector(x, y)) + ur = snap_to_grid(ll + vector(self.track_width, self.track_width)) - return [ll,ur] + return [ll, ur] def convert_track_to_inflated_pin(self, track): - """ - Convert a grid point into a rectangle shape that is inflated by a half DRC space. """ - # calculate lower left + Convert a grid point into a rectangle shape + that is inflated by a half DRC space. + """ + # calculate lower left x = track.x*self.track_width - 0.5*self.track_width - 0.5*self.track_space y = track.y*self.track_width - 0.5*self.track_width - 0.5*self.track_space ll = snap_to_grid(vector(x,y)) @@ -691,16 +719,17 @@ class router(router_tech): # calculate upper right x = track.x*self.track_width + 0.5*self.track_width + 0.5*self.track_space y = track.y*self.track_width + 0.5*self.track_width + 0.5*self.track_space - ur = snap_to_grid(vector(x,y)) + ur = snap_to_grid(vector(x, y)) p = pin_layout("", [ll, ur], self.get_layer(track[2])) return p def analyze_pins(self, pin_name): - """ - Analyze the shapes of a pin and combine them into pin_groups which are connected. """ - debug.info(2,"Analyzing pin groups for {}.".format(pin_name)) + Analyze the shapes of a pin and combine + them into pin_groups which are connected. + """ + debug.info(2, "Analyzing pin groups for {}.".format(pin_name)) pin_set = self.pins[pin_name] # This will be a list of pin tuples that overlap @@ -713,8 +742,8 @@ class router(router_tech): y_coordinates.sort(key=lambda x: x[0]) # Map the pins to the lower indices - bottom_index_map = {x[1]:i for i,x in enumerate(y_coordinates) if x[2]=="bottom"} - top_index_map = {x[1]:i for i,x in enumerate(y_coordinates) if x[2]=="bottom"} + bottom_index_map = {x[1]: i for i, x in enumerate(y_coordinates) if x[2] == "bottom"} + # top_index_map = {x[1]: i for i, x in enumerate(y_coordinates) if x[2] == "bottom"} # Sort the pin list by x coordinate pin_list = list(pin_set) @@ -725,10 +754,10 @@ class router(router_tech): # start at pin's lower y coordinate bottom_index = bottom_index_map[pin] compared_pins = set() - for i in range(bottom_index,len(y_coordinates)): + for i in range(bottom_index, len(y_coordinates)): compare_pin = y_coordinates[i][1] # Don't overlap yourself - if pin==compare_pin: + if pin == compare_pin: continue # Done when we encounter any shape above the pin if compare_pin.by() > pin.uy(): @@ -739,7 +768,7 @@ class router(router_tech): compared_pins.add(compare_pin) # If we overlap, add them to the list if pin.overlaps(compare_pin): - overlap_list.append((pin,compare_pin)) + overlap_list.append((pin, compare_pin)) # Initial unique group assignments group_id = {} @@ -749,33 +778,31 @@ class router(router_tech): gid += 1 for p in overlap_list: - (p1,p2) = p + (p1, p2) = p for pin in pin_list: if group_id[pin] == group_id[p2]: group_id[pin] = group_id[p1] - # For each pin add it to it's group group_map = {} for pin in pin_list: gid = group_id[pin] if gid not in group_map: - group_map[gid] = pin_group(name=pin_name, pin_set=[], router=self) + group_map[gid] = pin_group(name=pin_name, + pin_set=[], + router=self) # We always add it to the first set since they are touching group_map[gid].pins.add(pin) self.pin_groups[pin_name] = list(group_map.values()) - def convert_pins(self, pin_name): - """ + """ Convert the pin groups into pin tracks and blockage tracks. """ - debug.info(1,"Converting pins for {}.".format(pin_name)) + debug.info(1, "Converting pins for {}.".format(pin_name)) for pg in self.pin_groups[pin_name]: pg.convert_pin() - - def enclose_pins(self): """ @@ -784,13 +811,13 @@ class router(router_tech): by other shapes. """ for pin_name in self.pin_groups: - debug.info(1,"Enclosing pins for {}".format(pin_name)) + debug.info(1, "Enclosing pins for {}".format(pin_name)) for pg in self.pin_groups[pin_name]: pg.enclose_pin() pg.add_enclosure(self.cell) def add_source(self, pin_name): - """ + """ This will mark the grids for all pin components as a source. Marking as source or target also clears blockage status. """ @@ -798,7 +825,7 @@ class router(router_tech): self.add_pin_component_source(pin_name, i) def add_target(self, pin_name): - """ + """ This will mark the grids for all pin components as a target. Marking as source or target also clears blockage status. """ @@ -806,44 +833,46 @@ class router(router_tech): self.add_pin_component_target(pin_name, i) def num_pin_components(self, pin_name): - """ + """ This returns how many disconnected pin components there are. """ return len(self.pin_groups[pin_name]) def add_pin_component_source(self, pin_name, index): - """ - This will mark only the pin tracks from the indexed pin component as a source. + """ + This will mark only the pin tracks + from the indexed pin component as a source. It also unsets it as a blockage. """ - debug.check(index1: + if len(self.layers) > 1: self.cell.add_route(layers=self.layers, coordinates=abs_path, layer_widths=self.layer_widths) @@ -908,83 +936,81 @@ class router(router_tech): def add_single_enclosure(self, track): """ - Add a metal enclosure that is the size of the routing grid minus a spacing on each side. + Add a metal enclosure that is the size of + the routing grid minus a spacing on each side. """ pin = self.convert_track_to_pin(track) - (ll,ur) = pin.rect + (ll, ur) = pin.rect self.cell.add_rect(layer=self.get_layer(track.z), offset=ll, width=ur.x-ll.x, height=ur.y-ll.y) - - - def add_via(self,loc,size=1): - """ + def add_via(self, loc, size=1): + """ Add a via centered at the current location """ - loc = self.convert_point_to_units(vector3d(loc[0],loc[1],0)) + loc = self.convert_point_to_units(vector3d(loc[0], loc[1], 0)) self.cell.add_via_center(layers=self.layers, - offset=vector(loc.x,loc.y), - size=(size,size)) + offset=vector(loc.x, loc.y), + size=(size, size)) def compute_pin_enclosure(self, ll, ur, zindex, name=""): """ Enclose the tracks from ll to ur in a single rectangle that meets - the track DRC rules. + the track DRC rules. """ layer = self.get_layer(zindex) - # This finds the pin shape enclosed by the track with DRC spacing on the sides + # This finds the pin shape enclosed by the + # track with DRC spacing on the sides pin = self.convert_track_to_pin(ll) - (abs_ll,unused) = pin.rect + (abs_ll, unused) = pin.rect pin = self.convert_track_to_pin(ur) - (unused,abs_ur) = pin.rect + (unused, abs_ur) = pin.rect pin = pin_layout(name, [abs_ll, abs_ur], layer) return pin - def contract_path(self,path): - """ + def contract_path(self, path): + """ Remove intermediate points in a rectilinear path or a wave. """ # Waves are always linear, so just return the first and last. if self.is_wave(path): - return [path[0],path[-1]] + return [path[0], path[-1]] # Make a list only of points that change inertia of the path newpath = [path[0]] - for i in range(1,len(path)-1): - prev_inertia=self.get_inertia(path[i-1][0],path[i][0]) - next_inertia=self.get_inertia(path[i][0],path[i+1][0]) + for i in range(1, len(path) - 1): + prev_inertia = self.get_inertia(path[i-1][0], path[i][0]) + next_inertia = self.get_inertia(path[i][0], path[i+1][0]) # if we switch directions, add the point, otherwise don't - if prev_inertia!=next_inertia: + if prev_inertia != next_inertia: newpath.append(path[i]) # always add the last path unless it was a single point - if len(path)>1: + if len(path) > 1: newpath.append(path[-1]) return newpath - - def run_router(self, detour_scale): """ - This assumes the blockages, source, and target are all set up. + This assumes the blockages, source, and target are all set up. """ # Double check source and taget are not same node, if so, we are done! - for k,v in self.rg.map.items(): + for k, v in self.rg.map.items(): if v.source and v.target: debug.error("Grid cell is source and target! {}".format(k)) return False # returns the path in tracks - (path,cost) = self.rg.route(detour_scale) + (path, cost) = self.rg.route(detour_scale) if path: - debug.info(1,"Found path: cost={0} ".format(cost)) - debug.info(1,str(path)) + debug.info(1, "Found path: cost={0} ".format(cost)) + debug.info(1, str(path)) self.paths.append(path) self.add_route(path) @@ -998,34 +1024,34 @@ class router(router_tech): return False return True - def annotate_pin_and_tracks(self, pin, tracks): """" Annotate some shapes for debug purposes """ - debug.info(0,"Annotating\n pin {0}\n tracks {1}".format(pin,tracks)) + debug.info(0, "Annotating\n pin {0}\n tracks {1}".format(pin, tracks)) for coord in tracks: - (ll,ur) = self.convert_track_to_shape(coord) + (ll, ur) = self.convert_track_to_shape(coord) self.cell.add_rect(layer="text", offset=ll, width=ur[0]-ll[0], height=ur[1]-ll[1]) - (ll,ur) = self.convert_track_to_pin(coord).rect + (ll, ur) = self.convert_track_to_pin(coord).rect self.cell.add_rect(layer="boundary", offset=ll, width=ur[0]-ll[0], height=ur[1]-ll[1]) - (ll,ur) = pin.rect + (ll, ur) = pin.rect self.cell.add_rect(layer="text", offset=ll, width=ur[0]-ll[0], height=ur[1]-ll[1]) def write_debug_gds(self, gds_name="debug_route.gds", stop_program=True): - """ - Write out a GDS file with the routing grid and search information annotated on it. """ - debug.info(0,"Writing annotated router gds file to {}".format(gds_name)) + Write out a GDS file with the routing grid and + search information annotated on it. + """ + debug.info(0, "Writing annotated router gds file to {}".format(gds_name)) self.del_router_info() self.add_router_info() self.cell.gds_write(gds_name) @@ -1039,41 +1065,41 @@ class router(router_tech): Display grid information in the GDS file for a single grid cell. """ shape = self.convert_track_to_shape(g) - partial_track=vector(0,self.track_width/6.0) + partial_track = vector(0,self.track_width/6.0) self.cell.add_rect(layer="text", offset=shape[0], width=shape[1].x-shape[0].x, height=shape[1].y-shape[0].y) - t=self.rg.map[g].get_type() + t = self.rg.map[g].get_type() # midpoint offset - off=vector((shape[1].x+shape[0].x)/2, + off = vector((shape[1].x+shape[0].x)/2, (shape[1].y+shape[0].y)/2) - if t!=None: - if g[2]==1: + if t != None: + if g[2] == 1: # Upper layer is upper right label - type_off=off+partial_track + type_off = off + partial_track else: # Lower layer is lower left label - type_off=off-partial_track + type_off = off - partial_track self.cell.add_label(text=str(t), layer="text", offset=type_off) - t=self.rg.map[g].get_cost() - partial_track=vector(self.track_width/6.0,0) - if t!=None: - if g[2]==1: + t = self.rg.map[g].get_cost() + partial_track = vector(self.track_width/6.0, 0) + if t: + if g[2] == 1: # Upper layer is right label - type_off=off+partial_track + type_off = off + partial_track else: # Lower layer is left label - type_off=off-partial_track + type_off = off - partial_track self.cell.add_label(text=str(t), layer="text", offset=type_off) - self.cell.add_label(text="{0},{1}".format(g[0],g[1]), + self.cell.add_label(text="{0},{1}".format(g[0], g[1]), layer="text", offset=shape[0], zoom=0.05) @@ -1082,18 +1108,17 @@ class router(router_tech): """ Erase all of the comments on the current level. """ - debug.info(0,"Erasing router info") + debug.info(0, "Erasing router info") layer_num = techlayer["text"] self.cell.objs = [x for x in self.cell.objs if x.layerNumber != layer_num] - def add_router_info(self): """ - Write the routing grid and router cost, blockage, pins on - the boundary layer for debugging purposes. This can only be + Write the routing grid and router cost, blockage, pins on + the boundary layer for debugging purposes. This can only be called once or the labels will overlap. """ - debug.info(0,"Adding router info") + debug.info(0, "Adding router info") show_blockages = False show_blockage_grids = False @@ -1108,14 +1133,14 @@ class router(router_tech): if show_blockages: # Display the inflated blockage for blockage in self.blockages: - debug.info(1,"Adding {}".format(blockage)) - (ll,ur) = blockage.inflate() + debug.info(1, "Adding {}".format(blockage)) + (ll, ur) = blockage.inflate() self.cell.add_rect(layer="text", offset=ll, width=ur.x-ll.x, height=ur.y-ll.y) if show_blockage_grids: - self.set_blockages(self.blocked_grids,True) + self.set_blockages(self.blocked_grids, True) for g in self.rg.map: self.annotate_grid(g) @@ -1125,22 +1150,27 @@ class router(router_tech): if not pg.enclosed: continue for pin in pg.enclosures: - #print("enclosure: ",pin.name,pin.ll(),pin.width(),pin.height()) + # print("enclosure: ", + # pin.name, + # pin.ll(), + # pin.width(), + # pin.height()) self.cell.add_rect(layer="text", offset=pin.ll(), width=pin.width(), height=pin.height()) - -# FIXME: This should be replaced with vector.snap_to_grid at some point + +# FIXME: This should be replaced with vector.snap_to_grid at some point def snap_to_grid(offset): """ Changes the coodrinate to match the grid settings """ xoff = snap_val_to_grid(offset[0]) - yoff = snap_val_to_grid(offset[1]) + yoff = snap_val_to_grid(offset[1]) return vector(xoff, yoff) + def snap_val_to_grid(x): grid = drc("grid") xgrid = int(round(round((x / grid), 2), 0)) From 32f1cde897532e790358074f21000c50548c2337 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Thu, 7 Nov 2019 16:48:37 +0000 Subject: [PATCH 011/521] PEP8 formatting --- compiler/base/pin_layout.py | 227 +++++++++++++++++++----------------- 1 file changed, 120 insertions(+), 107 deletions(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index 10d10774..ae431bc6 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -11,6 +11,7 @@ from vector import vector from tech import layer import math + class pin_layout: """ A class to represent a rectangular design pin. It is limited to a @@ -20,40 +21,45 @@ class pin_layout: def __init__(self, name, rect, layer_name_pp): self.name = name # repack the rect as a vector, just in case - if type(rect[0])==vector: + if type(rect[0]) == vector: self.rect = rect else: - self.rect = [vector(rect[0]),vector(rect[1])] + self.rect = [vector(rect[0]), vector(rect[1])] # snap the rect to the grid self.rect = [x.snap_to_grid() for x in self.rect] - debug.check(self.width()>0,"Zero width pin.") - debug.check(self.height()>0,"Zero height pin.") + debug.check(self.width() > 0,"Zero width pin.") + debug.check(self.height() > 0,"Zero height pin.") # if it's a string, use the name - if type(layer_name_pp)==str: - self.layer=layer_name_pp + if type(layer_name_pp) == str: + self.layer = layer_name_pp # else it is required to be a lpp else: for (layer_name, lpp) in layer.items(): - if layer_name_pp[0]==lpp[0] and (layer_name_pp[1]==None or layer_name_pp[1]==lpp[1]): - self.layer=layer_name + if layer_name_pp[0] == lpp[0] and (not layer_name_pp[1] or layer_name_pp[1]==lpp[1]): + self.layer = layer_name break else: - debug.error("Couldn't find layer {}".format(layer_name_pp),-1) + debug.error("Couldn't find layer {}".format(layer_name_pp), -1) self.lpp = layer[self.layer] def __str__(self): """ override print function output """ - return "({} layer={} ll={} ur={})".format(self.name,self.layer,self.rect[0],self.rect[1]) + return "({} layer={} ll={} ur={})".format(self.name, + self.layer, + self.rect[0], + self.rect[1]) def __repr__(self): - """ - override repr function output (don't include + """ + override repr function output (don't include name since pin shapes could have same shape but diff name e.g. blockage vs A) """ - return "(layer={} ll={} ur={})".format(self.layer,self.rect[0],self.rect[1]) + return "(layer={} ll={} ur={})".format(self.layer, + self.rect[0], + self.rect[1]) def __hash__(self): """ Implement the hash function for sets etc. """ @@ -72,15 +78,15 @@ class pin_layout: def __eq__(self, other): """ Check if these are the same pins for duplicate checks """ if isinstance(other, self.__class__): - return (self.layer==other.layer and self.rect == other.rect) + return (self.layer == other.layer and self.rect == other.rect) else: - return False + return False def bbox(self, pin_list): """ Given a list of layout pins, create a bounding box layout. """ - (ll, ur) = self.rect + (ll, ur) = self.rect min_x = ll.x max_x = ur.x min_y = ll.y @@ -92,17 +98,17 @@ class pin_layout: min_y = min(min_y, pin.ll().y) max_y = max(max_y, pin.ur().y) - self.rect = [vector(min_x,min_y),vector(max_x,max_y)] + self.rect = [vector(min_x, min_y), vector(max_x, max_y)] def inflate(self, spacing=None): - """ - Inflate the rectangle by the spacing (or other rule) - and return the new rectangle. + """ + Inflate the rectangle by the spacing (or other rule) + and return the new rectangle. """ if not spacing: spacing = 0.5*drc("{0}_to_{0}".format(self.layer)) - (ll,ur) = self.rect + (ll, ur) = self.rect spacing = vector(spacing, spacing) newll = ll - spacing newur = ur + spacing @@ -111,20 +117,20 @@ class pin_layout: def intersection(self, other): """ Check if a shape overlaps with a rectangle """ - (ll,ur) = self.rect - (oll,our) = other.rect + (ll, ur) = self.rect + (oll, our) = other.rect min_x = max(ll.x, oll.x) max_x = min(ll.x, oll.x) min_y = max(ll.y, oll.y) max_y = min(ll.y, oll.y) - return [vector(min_x,min_y),vector(max_x,max_y)] + return [vector(min_x, min_y), vector(max_x, max_y)] def xoverlaps(self, other): """ Check if shape has x overlap """ - (ll,ur) = self.rect - (oll,our) = other.rect + (ll, ur) = self.rect + (oll, our) = other.rect x_overlaps = False # check if self is within other x range if (ll.x >= oll.x and ll.x <= our.x) or (ur.x >= oll.x and ur.x <= our.x): @@ -137,8 +143,8 @@ class pin_layout: def yoverlaps(self, other): """ Check if shape has x overlap """ - (ll,ur) = self.rect - (oll,our) = other.rect + (ll, ur) = self.rect + (oll, our) = other.rect y_overlaps = False # check if self is within other y range @@ -152,15 +158,15 @@ class pin_layout: def xcontains(self, other): """ Check if shape contains the x overlap """ - (ll,ur) = self.rect - (oll,our) = other.rect + (ll, ur) = self.rect + (oll, our) = other.rect return (oll.x >= ll.x and our.x <= ur.x) def ycontains(self, other): """ Check if shape contains the y overlap """ - (ll,ur) = self.rect - (oll,our) = other.rect + (ll, ur) = self.rect + (oll, our) = other.rect return (oll.y >= ll.y and our.y <= ur.y) @@ -189,7 +195,6 @@ class pin_layout: return True return False - def overlaps(self, other): """ Check if a shape overlaps with a rectangle """ # Can only overlap on the same layer @@ -215,40 +220,45 @@ class pin_layout: def normalize(self): """ Re-find the LL and UR points after a transform """ - (first,second)=self.rect - ll = vector(min(first[0],second[0]),min(first[1],second[1])) - ur = vector(max(first[0],second[0]),max(first[1],second[1])) - self.rect=[ll,ur] + (first, second) = self.rect + ll = vector(min(first[0], second[0]), min(first[1], second[1])) + ur = vector(max(first[0], second[0]), max(first[1], second[1])) + self.rect=[ll, ur] - def transform(self,offset,mirror,rotate): - """ Transform with offset, mirror and rotation to get the absolute pin location. - We must then re-find the ll and ur. The master is the cell instance. """ - (ll,ur) = self.rect - if mirror=="MX": - ll=ll.scale(1,-1) - ur=ur.scale(1,-1) - elif mirror=="MY": - ll=ll.scale(-1,1) - ur=ur.scale(-1,1) - elif mirror=="XY": - ll=ll.scale(-1,-1) - ur=ur.scale(-1,-1) + def transform(self, offset, mirror, rotate): + """ + Transform with offset, mirror and rotation + to get the absolute pin location. + We must then re-find the ll and ur. + The master is the cell instance. + """ + (ll, ur) = self.rect + if mirror == "MX": + ll = ll.scale(1, -1) + ur = ur.scale(1, -1) + elif mirror == "MY": + ll = ll.scale(-1, 1) + ur = ur.scale(-1, 1) + elif mirror == "XY": + ll = ll.scale(-1, -1) + ur = ur.scale(-1, -1) - if rotate==90: - ll=ll.rotate_scale(-1,1) - ur=ur.rotate_scale(-1,1) - elif rotate==180: - ll=ll.scale(-1,-1) - ur=ur.scale(-1,-1) - elif rotate==270: - ll=ll.rotate_scale(1,-1) - ur=ur.rotate_scale(1,-1) + if rotate == 90: + ll = ll.rotate_scale(-1, 1) + ur = ur.rotate_scale(-1, 1) + elif rotate == 180: + ll = ll.scale(-1, -1) + ur = ur.scale(-1, -1) + elif rotate == 270: + ll = ll.rotate_scale(1, -1) + ur = ur.rotate_scale(1, -1) - self.rect=[offset+ll,offset+ur] + self.rect = [offset + ll, offset + ur] self.normalize() def center(self): - return vector(0.5*(self.rect[0].x+self.rect[1].x),0.5*(self.rect[0].y+self.rect[1].y)) + return vector(0.5*(self.rect[0].x+self.rect[1].x), + 0.5*(self.rect[0].y+self.rect[1].y)) def cx(self): """ Center x """ @@ -265,17 +275,17 @@ class pin_layout: def ul(self): """ Upper left point """ - return vector(self.rect[0].x,self.rect[1].y) + return vector(self.rect[0].x, self.rect[1].y) def lr(self): """ Lower right point """ - return vector(self.rect[1].x,self.rect[0].y) + return vector(self.rect[1].x, self.rect[0].y) def ur(self): """ Upper right point """ return self.rect[1] - # The possible y edge values + # The possible y edge values def uy(self): """ Upper y value """ return self.rect[1].y @@ -294,30 +304,33 @@ class pin_layout: """ Right x value """ return self.rect[1].x - # The edge centers def rc(self): """ Right center point """ - return vector(self.rect[1].x,0.5*(self.rect[0].y+self.rect[1].y)) + return vector(self.rect[1].x, + 0.5*(self.rect[0].y+self.rect[1].y)) def lc(self): """ Left center point """ - return vector(self.rect[0].x,0.5*(self.rect[0].y+self.rect[1].y)) + return vector(self.rect[0].x, + 0.5*(self.rect[0].y+self.rect[1].y)) def uc(self): """ Upper center point """ - return vector(0.5*(self.rect[0].x+self.rect[1].x),self.rect[1].y) + return vector(0.5*(self.rect[0].x+self.rect[1].x), + self.rect[1].y) def bc(self): """ Bottom center point """ - return vector(0.5*(self.rect[0].x+self.rect[1].x),self.rect[0].y) - + return vector(0.5*(self.rect[0].x+self.rect[1].x), + self.rect[0].y) def gds_write_file(self, newLayout): """Writes the pin shape and label to GDS""" - debug.info(4, "writing pin (" + str(self.layer) + "):" - + str(self.width()) + "x" + str(self.height()) + " @ " + str(self.ll())) - (layer_num,purpose) = layer[self.layer] + debug.info(4, "writing pin (" + str(self.layer) + "):" + + str(self.width()) + "x" + + str(self.height()) + " @ " + str(self.ll())) + (layer_num, purpose) = layer[self.layer] newLayout.addBox(layerNumber=layer_num, purposeNumber=purpose, offsetInMicrons=self.ll(), @@ -325,37 +338,37 @@ class pin_layout: height=self.height(), center=False) # Add the tet in the middle of the pin. - # This fixes some pin label offsetting when GDS gets imported into Magic. + # This fixes some pin label offsetting when GDS gets + # imported into Magic. newLayout.addText(text=self.name, layerNumber=layer_num, purposeNumber=purpose, offsetInMicrons=self.center(), magnification=GDS["zoom"], rotate=None) - def compute_overlap(self, other): """ Calculate the rectangular overlap of two rectangles. """ - (r1_ll,r1_ur) = self.rect - (r2_ll,r2_ur) = other.rect + (r1_ll, r1_ur) = self.rect + (r2_ll, r2_ur) = other.rect - #ov_ur = vector(min(r1_ur.x,r2_ur.x),min(r1_ur.y,r2_ur.y)) - #ov_ll = vector(max(r1_ll.x,r2_ll.x),max(r1_ll.y,r2_ll.y)) + # ov_ur = vector(min(r1_ur.x,r2_ur.x),min(r1_ur.y,r2_ur.y)) + # ov_ll = vector(max(r1_ll.x,r2_ll.x),max(r1_ll.y,r2_ll.y)) - dy = min(r1_ur.y,r2_ur.y)-max(r1_ll.y,r2_ll.y) - dx = min(r1_ur.x,r2_ur.x)-max(r1_ll.x,r2_ll.x) + dy = min(r1_ur.y, r2_ur.y) - max(r1_ll.y, r2_ll.y) + dx = min(r1_ur.x, r2_ur.x) - max(r1_ll.x, r2_ll.x) - if dx>=0 and dy>=0: - return [dx,dy] + if dx >= 0 and dy >= 0: + return [dx, dy] else: - return [0,0] + return [0, 0] def distance(self, other): - """ + """ Calculate the distance to another pin layout. """ - (r1_ll,r1_ur) = self.rect - (r2_ll,r2_ur) = other.rect + (r1_ll, r1_ur) = self.rect + (r2_ll, r2_ur) = other.rect def dist(x1, y1, x2, y2): return math.sqrt((x2-x1)**2 + (y2-y1)**2) @@ -376,7 +389,7 @@ class pin_layout: elif left: return r1_ll.x - r2_ur.x elif right: - return r2_ll.x - r1.ur.x + return r2_ll.x - r1_ur.x elif bottom: return r1_ll.y - r2_ur.y elif top: @@ -385,9 +398,8 @@ class pin_layout: # rectangles intersect return 0 - def overlap_length(self, other): - """ + """ Calculate the intersection segment and determine its length """ @@ -399,21 +411,21 @@ class pin_layout: intersections = self.compute_overlap_segment(other) # This is the common case where two pairs of edges overlap # at two points, so just find the distance between those two points - if len(intersections)==2: - (p1,p2) = intersections - return math.sqrt(pow(p1[0]-p2[0],2) + pow(p1[1]-p2[1],2)) + if len(intersections) == 2: + (p1, p2) = intersections + return math.sqrt(pow(p1[0]-p2[0], 2) + pow(p1[1]-p2[1], 2)) else: # This is where we had a corner intersection or none return 0 def compute_overlap_segment(self, other): - """ - Calculate the intersection segment of two rectangles + """ + Calculate the intersection segment of two rectangles (if any) """ - (r1_ll,r1_ur) = self.rect - (r2_ll,r2_ur) = other.rect + (r1_ll, r1_ur) = self.rect + (r2_ll, r2_ur) = other.rect # The other corners besides ll and ur r1_ul = vector(r1_ll.x, r1_ur.y) @@ -422,6 +434,7 @@ class pin_layout: r2_lr = vector(r2_ur.x, r2_ll.y) from itertools import tee + def pairwise(iterable): "s -> (s0,s1), (s1,s2), (s2, s3), ..." a, b = tee(iterable) @@ -431,14 +444,14 @@ class pin_layout: # R1 edges CW r1_cw_points = [r1_ll, r1_ul, r1_ur, r1_lr, r1_ll] r1_edges = [] - for (p,q) in pairwise(r1_cw_points): - r1_edges.append([p,q]) + for (p, q) in pairwise(r1_cw_points): + r1_edges.append([p, q]) # R2 edges CW r2_cw_points = [r2_ll, r2_ul, r2_ur, r2_lr, r2_ll] r2_edges = [] - for (p,q) in pairwise(r2_cw_points): - r2_edges.append([p,q]) + for (p, q) in pairwise(r2_cw_points): + r2_edges.append([p, q]) # There are 4 edges on each rectangle # so just brute force check intersection of each @@ -460,18 +473,18 @@ class pin_layout: q.x >= min(p.x, r.x) and \ q.y <= max(p.y, r.y) and \ q.y >= min(p.y, r.y): - return True + return True return False def segment_intersection(self, s1, s2): - """ + """ Determine the intersection point of two segments Return the a segment if they overlap. Return None if they don't. """ - (a,b) = s1 - (c,d) = s2 + (a, b) = s1 + (c, d) = s2 # Line AB represented as a1x + b1y = c1 a1 = b.y - a.y b1 = a.x - b.x @@ -484,11 +497,11 @@ class pin_layout: determinant = a1*b2 - a2*b1 - if determinant!=0: + if determinant != 0: x = (b2*c1 - b1*c2)/determinant y = (a1*c2 - a2*c1)/determinant - r = vector(x,y).snap_to_grid() + r = vector(x, y).snap_to_grid() if self.on_segment(a, r, b) and self.on_segment(c, r, d): return r From 8d158e9eb5ed19b4b7eb203a72d9bfb13199f0b5 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Fri, 8 Nov 2019 15:45:25 +0000 Subject: [PATCH 012/521] Fix lpp change --- compiler/router/pin_group.py | 4 ++-- compiler/router/router.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index df97bf9b..4fff2ae5 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -360,7 +360,7 @@ class pin_group: """ smallest_shape = None - zindex = self.router.get_zindex(pin.layer_num) + zindex = self.router.get_zindex(pin.lpp[0]) (min_width, min_space) = self.router.get_layer_width_space(zindex) # Now compare it with every other shape to check how much they overlap @@ -469,7 +469,7 @@ class pin_group: right_connector, above_connector, below_connector] - filtered_list = list(filter(lambda x: not x, connector_list)) + filtered_list = list(filter(lambda x: x!=None, connector_list)) if (len(filtered_list) > 0): import copy bbox_connector = copy.copy(pin) diff --git a/compiler/router/router.py b/compiler/router/router.py index 15f6f6b3..7be3a4c0 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -447,7 +447,7 @@ class router(router_tech): """ # Inflate the blockage by half a spacing rule [ll, ur] = self.convert_blockage_to_tracks(blockage.inflate()) - zlayer = self.get_zindex(blockage.layer_num) + zlayer = self.get_zindex(blockage.lpp[0]) blockage_tracks = self.get_blockage_tracks(ll, ur, zlayer) return blockage_tracks @@ -529,7 +529,7 @@ class router(router_tech): sufficient_list = set() insufficient_list = set() - zindex = self.get_zindex(pin.layer_num) + zindex = self.get_zindex(pin.lpp[0]) for x in range(int(ll[0]) + expansion, int(ur[0]) + 1 + expansion): for y in range(int(ll[1] + expansion), int(ur[1]) + 1 + expansion): (full_overlap, partial_overlap) = self.convert_pin_coord_to_tracks(pin, From bba6995653b08da770bd411aee90cea97f9af603 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Fri, 8 Nov 2019 19:42:09 +0000 Subject: [PATCH 013/521] Call debugger if debug_level more than 0 and an error. --- compiler/debug.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/compiler/debug.py b/compiler/debug.py index 15876f22..228193a5 100644 --- a/compiler/debug.py +++ b/compiler/debug.py @@ -26,7 +26,10 @@ def check(check, str): log("ERROR: file {0}: line {1}: {2}\n".format( os.path.basename(filename), line_number, str)) - assert 0 + if globals.OPTS.debug_level > 0: + import pdb; pdb.set_trace() + else: + assert 0 def error(str, return_value=0): @@ -37,7 +40,10 @@ def error(str, return_value=0): log("ERROR: file {0}: line {1}: {2}\n".format( os.path.basename(filename), line_number, str)) - assert return_value == 0 + if globals.OPTS.debug_level > 0: + import pdb; pdb.set_trace() + else: + assert return_value == 0 def warning(str): From 131f4bda4a75b5b74169cb7d15cb767806741ed5 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Thu, 14 Nov 2019 18:17:20 +0000 Subject: [PATCH 014/521] Add layer-purpose GDS support. Various PEP8 fixes. --- compiler/base/pin_layout.py | 22 ++- compiler/base/utils.py | 40 +++--- compiler/debug.py | 12 +- compiler/gdsMill/gdsMill/vlsiLayout.py | 177 +++++++++++++++---------- compiler/modules/dff.py | 10 +- compiler/router/pin_group.py | 141 ++++++++++---------- compiler/router/router.py | 32 +++-- compiler/router/router_tech.py | 26 ++-- compiler/router/supply_grid_router.py | 3 +- technology/freepdk45/tech/tech.py | 1 - technology/scn4m_subm/tech/tech.py | 1 - 11 files changed, 267 insertions(+), 198 deletions(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index ae431bc6..f5d25263 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -28,8 +28,8 @@ class pin_layout: # snap the rect to the grid self.rect = [x.snap_to_grid() for x in self.rect] - debug.check(self.width() > 0,"Zero width pin.") - debug.check(self.height() > 0,"Zero height pin.") + debug.check(self.width() > 0, "Zero width pin.") + debug.check(self.height() > 0, "Zero height pin.") # if it's a string, use the name if type(layer_name_pp) == str: @@ -37,7 +37,7 @@ class pin_layout: # else it is required to be a lpp else: for (layer_name, lpp) in layer.items(): - if layer_name_pp[0] == lpp[0] and (not layer_name_pp[1] or layer_name_pp[1]==lpp[1]): + if self.same_lpp(layer_name_pp, lpp): self.layer = layer_name break else: @@ -78,7 +78,7 @@ class pin_layout: def __eq__(self, other): """ Check if these are the same pins for duplicate checks """ if isinstance(other, self.__class__): - return (self.layer == other.layer and self.rect == other.rect) + return (self.lpp == other.lpp and self.rect == other.rect) else: return False @@ -177,7 +177,7 @@ class pin_layout: return True # Can only overlap on the same layer - if self.layer != other.layer: + if not self.same_lpp(self.lpp, other.lpp): return False if not self.xcontains(other): @@ -198,7 +198,7 @@ class pin_layout: def overlaps(self, other): """ Check if a shape overlaps with a rectangle """ # Can only overlap on the same layer - if self.layer != other.layer: + if not self.same_lpp(self.lpp, other.lpp): return False x_overlaps = self.xoverlaps(other) @@ -506,3 +506,13 @@ class pin_layout: return r return None + + def same_lpp(self, lpp1, lpp2): + """ + Check if the layers and purposes are the same. + Ignore if purpose is a None. + """ + if lpp1[1] == None or lpp2[1] == None: + return lpp1[0] == lpp2[0] + + return lpp1[0] == lpp2[0] and lpp1[1] == lpp2[1] diff --git a/compiler/base/utils.py b/compiler/base/utils.py index 1816a508..f02b2b85 100644 --- a/compiler/base/utils.py +++ b/compiler/base/utils.py @@ -5,7 +5,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import os import gdsMill import tech import math @@ -16,6 +15,7 @@ from pin_layout import pin_layout OPTS = globals.OPTS + def ceil(decimal): """ Performs a ceiling function on the decimal place specified by the DRC grid. @@ -23,27 +23,33 @@ def ceil(decimal): grid = tech.drc["grid"] return math.ceil(decimal * 1 / grid) / (1 / grid) + def round_to_grid(number): """ Rounds an arbitrary number to the grid. """ - grid = tech.drc["grid"] + grid = tech.drc["grid"] # this gets the nearest integer value number_grid = int(round(round((number / grid), 2), 0)) number_off = number_grid * grid return number_off + def snap_to_grid(offset): """ Changes the coodrinate to match the grid settings """ - return [round_to_grid(offset[0]),round_to_grid(offset[1])] + return [round_to_grid(offset[0]), + round_to_grid(offset[1])] + def pin_center(boundary): """ This returns the center of a pin shape in the vlsiLayout border format. """ - return [0.5 * (boundary[0] + boundary[2]), 0.5 * (boundary[1] + boundary[3])] + return [0.5 * (boundary[0] + boundary[2]), + 0.5 * (boundary[1] + boundary[3])] + def auto_measure_libcell(pin_list, name, units, lpp): """ @@ -57,35 +63,34 @@ def auto_measure_libcell(pin_list, name, units, lpp): cell = {} measure_result = cell_vlsi.getLayoutBorder(lpp[0]) - if measure_result == None: + if measure_result: measure_result = cell_vlsi.measureSize(name) [cell["width"], cell["height"]] = measure_result for pin in pin_list: - (name,lpp,boundary)=cell_vlsi.getPinShapeByLabel(str(pin)) + (name, lpp, boundary) = cell_vlsi.getPinShapeByLabel(str(pin)) cell[str(pin)] = pin_center(boundary) return cell - def get_gds_size(name, gds_filename, units, lpp): """ Open a GDS file and return the size from either the bounding box or a border layer. """ - debug.info(4,"Creating VLSI layout for {}".format(name)) + debug.info(4, "Creating VLSI layout for {}".format(name)) cell_vlsi = gdsMill.VlsiLayout(units=units) reader = gdsMill.Gds2reader(cell_vlsi) reader.loadFromFile(gds_filename) - cell = {} measure_result = cell_vlsi.getLayoutBorder(lpp) - if measure_result == None: - debug.info(2,"Layout border failed. Trying to measure size for {}".format(name)) + if not measure_result: + debug.info(2, "Layout border failed. Trying to measure size for {}".format(name)) measure_result = cell_vlsi.measureSize(name) # returns width,height return measure_result + def get_libcell_size(name, units, lpp): """ Open a GDS file and return the library cell size from either the @@ -106,15 +111,18 @@ def get_gds_pins(pin_names, name, gds_filename, units): cell = {} for pin_name in pin_names: - cell[str(pin_name)]=[] - pin_list=cell_vlsi.getPinShape(str(pin_name)) + cell[str(pin_name)] = [] + pin_list = cell_vlsi.getPinShape(str(pin_name)) for pin_shape in pin_list: - (lpp,boundary)=pin_shape - rect=[vector(boundary[0],boundary[1]),vector(boundary[2],boundary[3])] - # this is a list because other cells/designs may have must-connect pins + (lpp, boundary) = pin_shape + rect = [vector(boundary[0], boundary[1]), + vector(boundary[2], boundary[3])] + # this is a list because other cells/designs + # may have must-connect pins cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp)) return cell + def get_libcell_pins(pin_list, name, units): """ Open a GDS file and find the pins in pin_list as text on a given layer. diff --git a/compiler/debug.py b/compiler/debug.py index 228193a5..a902bca0 100644 --- a/compiler/debug.py +++ b/compiler/debug.py @@ -27,9 +27,9 @@ def check(check, str): os.path.basename(filename), line_number, str)) if globals.OPTS.debug_level > 0: - import pdb; pdb.set_trace() - else: - assert 0 + import pdb + pdb.set_trace() + assert 0 def error(str, return_value=0): @@ -41,9 +41,9 @@ def error(str, return_value=0): os.path.basename(filename), line_number, str)) if globals.OPTS.debug_level > 0: - import pdb; pdb.set_trace() - else: - assert return_value == 0 + import pdb + pdb.set_trace() + assert return_value == 0 def warning(str): diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index 8d071e9f..eec1870c 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -213,11 +213,11 @@ class VlsiLayout: def initialize(self): self.deduceHierarchy() - #self.traverseTheHierarchy() + # self.traverseTheHierarchy() self.populateCoordinateMap() for layerNumber in self.layerNumbersInUse: - self.processLabelPins((layerNumber,None)) + self.processLabelPins((layerNumber, None)) def populateCoordinateMap(self): @@ -245,21 +245,24 @@ class VlsiLayout: self.xyTree.append((startingStructureName,origin,uVector,vVector)) self.traverseTheHierarchy(delegateFunction = addToXyTree) - def microns(self,userUnits): + def microns(self, userUnits): """Utility function to convert user units to microns""" userUnit = self.units[1]/self.units[0] - userUnitsPerMicron = userUnit / (userunit) + userUnitsPerMicron = userUnit / userunit layoutUnitsPerMicron = userUnitsPerMicron / self.units[0] return userUnits / layoutUnitsPerMicron - def userUnits(self,microns): + def userUnits(self, microns): """Utility function to convert microns to user units""" userUnit = self.units[1]/self.units[0] - #userUnitsPerMicron = userUnit / 1e-6 + # userUnitsPerMicron = userUnit / 1e-6 userUnitsPerMicron = userUnit / (userUnit) layoutUnitsPerMicron = userUnitsPerMicron / self.units[0] - #print("userUnit:",userUnit,"userUnitsPerMicron",userUnitsPerMicron,"layoutUnitsPerMicron",layoutUnitsPerMicron,[microns,microns*layoutUnitsPerMicron]) - return round(microns*layoutUnitsPerMicron,0) + # print("userUnit:",userUnit, + # "userUnitsPerMicron",userUnitsPerMicron, + # "layoutUnitsPerMicron",layoutUnitsPerMicron, + # [microns,microns*layoutUnitsPerMicron]) + return round(microns*layoutUnitsPerMicron, 0) def changeRoot(self,newRoot, create=False): """ @@ -386,7 +389,7 @@ class VlsiLayout: #add the sref to the root structure self.structures[self.rootStructureName].boundaries.append(boundaryToAdd) - def addPath(self, layerNumber=0, purposeNumber = None, coordinates=[(0,0)], width=1.0): + def addPath(self, layerNumber=0, purposeNumber=None, coordinates=[(0,0)], width=1.0): """ Method to add a path to a layout """ @@ -405,7 +408,7 @@ class VlsiLayout: #add the sref to the root structure self.structures[self.rootStructureName].paths.append(pathToAdd) - def addText(self, text, layerNumber=0, purposeNumber = None, offsetInMicrons=(0,0), magnification=0.1, rotate = None): + def addText(self, text, layerNumber=0, purposeNumber=None, offsetInMicrons=(0,0), magnification=0.1, rotate = None): offsetInLayoutUnits = (self.userUnits(offsetInMicrons[0]),self.userUnits(offsetInMicrons[1])) textToAdd = GdsText() textToAdd.drawingLayer = layerNumber @@ -593,42 +596,50 @@ class VlsiLayout: passFailIndex += 1 print("Done\n\n") - def getLayoutBorder(self,lpp): - cellSizeMicron=None + def getLayoutBorder(self, lpp): + cellSizeMicron = None for boundary in self.structures[self.rootStructureName].boundaries: - if boundary.drawingLayer==lpp[0] and \ - (lpp[1]==None or boundary.purposeLayer==None or boundary.purposeLayer==lpp[1]): + if sameLPP((boundary.drawingLayer, boundary.purposeLayer), + lpp): if self.debug: - debug.info(1,"Find border "+str(boundary.coordinates)) - left_bottom=boundary.coordinates[0] - right_top=boundary.coordinates[2] - cellSize=[right_top[0]-left_bottom[0],right_top[1]-left_bottom[1]] - cellSizeMicron=[cellSize[0]*self.units[0],cellSize[1]*self.units[0]] + debug.info(1, "Find border "+str(boundary.coordinates)) + left_bottom = boundary.coordinates[0] + right_top = boundary.coordinates[2] + cellSize = [right_top[0]-left_bottom[0], + right_top[1]-left_bottom[1]] + cellSizeMicron = [cellSize[0]*self.units[0], + cellSize[1]*self.units[0]] debug.check(cellSizeMicron, "Error: "+str(self.rootStructureName)+".cell_size information not found yet") + return cellSizeMicron - def measureSize(self,startStructure): - self.rootStructureName=self.padText(startStructure) + def measureSize(self, startStructure): + self.rootStructureName = self.padText(startStructure) self.populateCoordinateMap() cellBoundary = [None, None, None, None] for TreeUnit in self.xyTree: - cellBoundary=self.measureSizeInStructure(TreeUnit,cellBoundary) - cellSize=[cellBoundary[2]-cellBoundary[0],cellBoundary[3]-cellBoundary[1]] - cellSizeMicron=[cellSize[0]*self.units[0],cellSize[1]*self.units[0]] + cellBoundary = self.measureSizeInStructure(TreeUnit, cellBoundary) + cellSize = [cellBoundary[2]-cellBoundary[0], + cellBoundary[3]-cellBoundary[1]] + cellSizeMicron = [cellSize[0]*self.units[0], + cellSize[1]*self.units[0]] return cellSizeMicron - def measureBoundary(self,startStructure): - self.rootStructureName=self.padText(startStructure) + def measureBoundary(self, startStructure): + self.rootStructureName = self.padText(startStructure) self.populateCoordinateMap() cellBoundary = [None, None, None, None] for TreeUnit in self.xyTree: - cellBoundary=self.measureSizeInStructure(TreeUnit,cellBoundary) - return [[self.units[0]*cellBoundary[0],self.units[0]*cellBoundary[1]], - [self.units[0]*cellBoundary[2],self.units[0]*cellBoundary[3]]] + cellBoundary = self.measureSizeInStructure(TreeUnit, cellBoundary) + return [[self.units[0]*cellBoundary[0], + self.units[0]*cellBoundary[1]], + [self.units[0]*cellBoundary[2], + self.units[0]*cellBoundary[3]]] - def measureSizeInStructure(self,structure,cellBoundary): - (structureName,structureOrigin,structureuVector,structurevVector)=structure + def measureSizeInStructure(self, structure, cellBoundary): + (structureName, structureOrigin, + structureuVector, structurevVector) = structure for boundary in self.structures[str(structureName)].boundaries: left_bottom=boundary.coordinates[0] right_top=boundary.coordinates[2] @@ -655,14 +666,14 @@ class VlsiLayout: cellBoundary[3]=right_top_Y return cellBoundary - def getTexts(self, lpp): """ Get all of the labels on a given layer only at the root level. """ text_list = [] for Text in self.structures[self.rootStructureName].texts: - if Text.drawingLayer==lpp[0] and (lpp[1]==None or Text.purposeLayer==lpp[1]): + if sameLPP((Text.drawingLayer, Text.purposeLayer), + lpp): text_list.append(Text) return text_list @@ -678,9 +689,9 @@ class VlsiLayout: max_pin = None max_area = 0 for pin in pin_list: - (layer,boundary) = pin + (layer, boundary) = pin new_area = boundaryArea(boundary) - if max_pin == None or new_area>max_area: + if not max_pin or new_area > max_area: max_pin = pin max_area = new_area max_pins.append(max_pin) @@ -697,11 +708,10 @@ class VlsiLayout: pin_map = self.pins[pin_name] for pin_list in pin_map: for pin in pin_list: - (pin_layer, boundary) = pin + (pin_layer, boundary) = pin shape_list.append(pin) return shape_list - def processLabelPins(self, lpp): """ @@ -710,19 +720,21 @@ class VlsiLayout: """ # Get the labels on a layer in the root level labels = self.getTexts(lpp) + # Get all of the shapes on the layer at all levels # and transform them to the current level - shapes = self.getAllShapes(lpp) + shapes = self.getAllShapes(lpp) for label in labels: label_coordinate = label.coordinates[0] user_coordinate = [x*self.units[0] for x in label_coordinate] pin_shapes = [] for boundary in shapes: - if self.labelInRectangle(user_coordinate,boundary): + if self.labelInRectangle(user_coordinate, boundary): pin_shapes.append((lpp, boundary)) label_text = label.textString + # Remove the padding if it exists if label_text[-1] == "\x00": label_text = label_text[0:-1] @@ -732,11 +744,11 @@ class VlsiLayout: except KeyError: self.pins[label_text] = [] self.pins[label_text].append(pin_shapes) - def getBlockages(self, lpp): """ - Return all blockages on a given layer in [coordinate 1, coordinate 2,...] format and + Return all blockages on a given layer in + [coordinate 1, coordinate 2,...] format and user units. """ blockages = [] @@ -744,69 +756,85 @@ class VlsiLayout: shapes = self.getAllShapes(lpp) for boundary in shapes: vectors = [] - for i in range(0,len(boundary),2): - vectors.append(vector(boundary[i],boundary[i+1])) + for i in range(0, len(boundary), 2): + vectors.append(vector(boundary[i], boundary[i+1])) blockages.append(vectors) - return blockages + + return blockages def getAllShapes(self, lpp): """ - Return all shapes on a given layer in [llx, lly, urx, ury] format and user units for rectangles - and [coordinate 1, coordinate 2,...] format and user units for polygons. + Return all shapes on a given layer in [llx, lly, urx, ury] + format and user units for rectangles + and [coordinate 1, coordinate 2,...] format and user + units for polygons. """ boundaries = set() for TreeUnit in self.xyTree: - #print(TreeUnit[0]) - boundaries.update(self.getShapesInStructure(lpp,TreeUnit)) + # print(TreeUnit[0]) + boundaries.update(self.getShapesInStructure(lpp, TreeUnit)) # Convert to user units user_boundaries = [] for boundary in boundaries: boundaries_list = [] - for i in range(0,len(boundary)): + for i in range(0, len(boundary)): boundaries_list.append(boundary[i]*self.units[0]) user_boundaries.append(boundaries_list) return user_boundaries - def getShapesInStructure(self, lpp, structure): - """ - Go through all the shapes in a structure and return the list of shapes in - the form [llx, lly, urx, ury] for rectangles and [coordinate 1, coordinate 2,...] for polygons. """ - (structureName,structureOrigin,structureuVector,structurevVector)=structure - #print(structureName,"u",structureuVector.transpose(),"v",structurevVector.transpose(),"o",structureOrigin.transpose()) + Go through all the shapes in a structure and + return the list of shapes in + the form [llx, lly, urx, ury] for rectangles + and [coordinate 1, coordinate 2,...] for polygons. + """ + (structureName, structureOrigin, + structureuVector, structurevVector) = structure + # print(structureName, + # "u", structureuVector.transpose(), + # "v",structurevVector.transpose(), + # "o",structureOrigin.transpose()) boundaries = [] for boundary in self.structures[str(structureName)].boundaries: - if boundary.drawingLayer==lpp[0] and (lpp[1]==None or boundary.purposeLayer==lpp[1]): - if len(boundary.coordinates)!=5: + if sameLPP((boundary.drawingLayer, boundary.purposeLayer), + lpp): + if len(boundary.coordinates) != 5: # if shape is a polygon (used in DFF) boundaryPolygon = [] # Polygon is a list of coordinates going ccw - for coord in range(0,len(boundary.coordinates)): + for coord in range(0, len(boundary.coordinates)): boundaryPolygon.append(boundary.coordinates[coord][0]) boundaryPolygon.append(boundary.coordinates[coord][1]) # perform the rotation - boundaryPolygon=self.transformPolygon(boundaryPolygon,structureuVector,structurevVector) - # add the offset + boundaryPolygon = self.transformPolygon(boundaryPolygon, + structureuVector, + structurevVector) + # add the offset polygon = [] - for i in range(0,len(boundaryPolygon),2): - polygon.append(boundaryPolygon[i]+structureOrigin[0].item()) - polygon.append(boundaryPolygon[i+1]+structureOrigin[1].item()) + for i in range(0, len(boundaryPolygon), 2): + polygon.append(boundaryPolygon[i] + structureOrigin[0].item()) + polygon.append(boundaryPolygon[i+1] + structureOrigin[1].item()) # make it a tuple polygon = tuple(polygon) boundaries.append(polygon) else: # else shape is a rectangle - left_bottom=boundary.coordinates[0] - right_top=boundary.coordinates[2] + left_bottom = boundary.coordinates[0] + right_top = boundary.coordinates[2] # Rectangle is [leftx, bottomy, rightx, topy]. - boundaryRect=[left_bottom[0],left_bottom[1],right_top[0],right_top[1]] + boundaryRect = [left_bottom[0], left_bottom[1], + right_top[0], right_top[1]] # perform the rotation - boundaryRect=self.transformRectangle(boundaryRect,structureuVector,structurevVector) + boundaryRect = self.transformRectangle(boundaryRect, + structureuVector, + structurevVector) # add the offset and make it a tuple - boundaryRect=(boundaryRect[0]+structureOrigin[0].item(),boundaryRect[1]+structureOrigin[1].item(), - boundaryRect[2]+structureOrigin[0].item(),boundaryRect[3]+structureOrigin[1].item()) + boundaryRect = (boundaryRect[0]+structureOrigin[0].item(), + boundaryRect[1]+structureOrigin[1].item(), + boundaryRect[2]+structureOrigin[0].item(), + boundaryRect[3]+structureOrigin[1].item()) boundaries.append(boundaryRect) return boundaries @@ -868,6 +896,17 @@ class VlsiLayout: else: return False + +def sameLPP(lpp1, lpp2): + """ + Check if the layers and purposes are the same. + Ignore if purpose is a None. + """ + if lpp1[1] == None or lpp2[1] == None: + return lpp1[0] == lpp2[0] + + return lpp1[0] == lpp2[0] and lpp1[1] == lpp2[1] + def boundaryArea(A): """ diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 3cb1bcf1..8871872d 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -5,13 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import globals import design -from math import log -import design -from tech import GDS,layer,spice,parameter +from tech import GDS, layer, spice, parameter import utils + class dff(design.design): """ Memory address flip-flop @@ -19,7 +17,9 @@ class dff(design.design): pin_names = ["D", "Q", "clk", "vdd", "gnd"] type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] - (width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"]) + (width, height) = utils.get_libcell_size("dff", + GDS["unit"], + layer["boundary"]) pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"]) def __init__(self, name="dff"): diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index 4fff2ae5..8a1362c2 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -18,16 +18,17 @@ class pin_group: determine how pin shapes get mapped to tracks. It is initially constructed with a single set of (touching) pins. """ + def __init__(self, name, pin_set, router): self.name = name # Flag for when it is routed self.routed = False # Flag for when it is enclosed self.enclosed = False - + # Remove any redundant pins (i.e. contained in other pins) irredundant_pin_set = self.remove_redundant_shapes(list(pin_set)) - + # This is a list because we can have a pin # group of disconnected sets of pins # and these are represented by separate lists @@ -39,7 +40,7 @@ class pin_group: # These are the secondary grids that could # or could not be part of the pin self.secondary_grids = set() - + # The corresponding set of partially blocked grids for each pin group. # These are blockages for other nets but unblocked # for routing this group. These are also blockages if we @@ -52,16 +53,16 @@ class pin_group: def __str__(self): """ override print function output """ total_string = "(pg {} ".format(self.name) - + pin_string = "\n pins={}".format(self.pins) total_string += pin_string - + grids_string = "\n grids={}".format(self.grids) total_string += grids_string grids_string = "\n secondary={}".format(self.secondary_grids) total_string += grids_string - + if self.enclosed: enclosure_string = "\n enclose={}".format(self.enclosures) total_string += enclosure_string @@ -72,7 +73,7 @@ class pin_group: def __repr__(self): """ override repr function output """ return str(self) - + def size(self): return len(self.grids) @@ -81,7 +82,7 @@ class pin_group: def is_routed(self): return self.routed - + def remove_redundant_shapes(self, pin_list): """ Remove any pin layout that is contained within another. @@ -90,7 +91,7 @@ class pin_group: local_debug = False if local_debug: debug.info(0, "INITIAL: {}".format(pin_list)) - + # Make a copy of the list to start new_pin_list = pin_list.copy() @@ -100,7 +101,7 @@ class pin_group: # If we remove this pin, it can't contain other pins if index1 in remove_indices: continue - + for index2, pin2 in enumerate(pin_list): # Can't contain yourself, # but compare the indices and not the pins @@ -110,7 +111,7 @@ class pin_group: # If we already removed it, can't remove it again... if index2 in remove_indices: continue - + if pin1.contains(pin2): if local_debug: debug.info(0, "{0} contains {1}".format(pin1, pin2)) @@ -119,10 +120,10 @@ class pin_group: # Remove them in decreasing order to not invalidate the indices for i in sorted(remove_indices, reverse=True): del new_pin_list[i] - + if local_debug: debug.info(0, "FINAL : {}".format(new_pin_list)) - + return new_pin_list def compute_enclosures(self): @@ -144,11 +145,17 @@ class pin_group: enclosure = self.router.compute_pin_enclosure(ll, ur, ll.z) pin_list.append(enclosure) - # Now simplify the enclosure list + debug.check(len(pin_list) > 0, + "Did not find any enclosures.") + + # Now simplify the enclosure list new_pin_list = self.remove_redundant_shapes(pin_list) - - return new_pin_list + + debug.check(len(new_pin_list) > 0, + "Did not find any enclosures.") + return new_pin_list + def compute_connector(self, pin, enclosure): """ Compute a shape to connect the pin to the enclosure shape. @@ -200,7 +207,7 @@ class pin_group: for shape in enclosures: if shape.xcontains(pin): edge_list.append(shape) - + # Sort them by their bottom edge edge_list.sort(key=lambda x: x.by(), reverse=True) @@ -233,7 +240,7 @@ class pin_group: for shape in enclosures: if shape.xcontains(pin): edge_list.append(shape) - + # Sort them by their upper edge edge_list.sort(key=lambda x: x.uy()) @@ -251,13 +258,13 @@ class pin_group: # If it already overlaps, no connector needed if bottom_item.overlaps(pin): return None - + # Otherwise, make a connector to the item p = self.compute_connector(pin, bottom_item) return p - + def find_left_connector(self, pin, enclosures): - """ + """ Find the enclosure that is to the left of the pin and make a connector to it's right edge. """ @@ -266,14 +273,14 @@ class pin_group: for shape in enclosures: if shape.ycontains(pin): edge_list.append(shape) - + # Sort them by their right edge edge_list.sort(key=lambda x: x.rx()) # Find the right edge that is to the pin's left edge left_item = None for item in edge_list: - if item.rx()<=pin.lx(): + if item.rx() <= pin.lx(): left_item = item else: break @@ -284,13 +291,13 @@ class pin_group: # If it already overlaps, no connector needed if left_item.overlaps(pin): return None - + # Otherwise, make a connector to the item p = self.compute_connector(pin, left_item) return p - + def find_right_connector(self, pin, enclosures): - """ + """ Find the enclosure that is to the right of the pin and make a connector to it's left edge. """ @@ -299,7 +306,7 @@ class pin_group: for shape in enclosures: if shape.ycontains(pin): edge_list.append(shape) - + # Sort them by their right edge edge_list.sort(key=lambda x: x.lx(), reverse=True) @@ -317,11 +324,11 @@ class pin_group: # If it already overlaps, no connector needed if right_item.overlaps(pin): return None - + # Otherwise, make a connector to the item p = self.compute_connector(pin, right_item) return p - + def find_smallest_connector(self, pin_list, shape_list): """ Compute all of the connectors between the overlapping @@ -334,7 +341,7 @@ class pin_group: new_enclosure = self.compute_connector(pin, enclosure) if not smallest or new_enclosure.area() < smallest.area(): smallest = new_enclosure - + return smallest def find_smallest_overlapping(self, pin_list, shape_list): @@ -350,7 +357,7 @@ class pin_group: # overlap_length = pin.overlap_length(overlap_shape) if not smallest_shape or overlap_shape.area() < smallest_shape.area(): smallest_shape = overlap_shape - + return smallest_shape def find_smallest_overlapping_pin(self, pin, shape_list): @@ -369,9 +376,9 @@ class pin_group: if overlap_length > min_width: if not smallest_shape or other.area() < smallest_shape.area(): smallest_shape = other - + return smallest_shape - + def overlap_any_shape(self, pin_list, shape_list): """ Does the given pin overlap any of the shapes in the pin list. @@ -391,7 +398,7 @@ class pin_group: for pin in pin_list: if pin.area() > biggest.area(): biggest = pin - + return pin def enclose_pin_grids(self, ll, dir1=direction.NORTH, dir2=direction.EAST): @@ -406,8 +413,7 @@ class pin_group: offset2 = direction.get_offset(dir2) # We may have started with an empty set - if not self.grids: - return None + debug.check(len(self.grids) > 0, "Cannot seed an grid empty set.") # Start with the ll and make the widest row row = [ll] @@ -436,7 +442,7 @@ class pin_group: # Add a shape from ll to ur ur = row[-1] return (ll, ur) - + def enclose_pin(self): """ If there is one set of connected pin shapes, @@ -445,13 +451,13 @@ class pin_group: If there is not, it simply returns all the enclosures. """ self.enclosed = True - + # Compute the enclosure pin_layout list of the set of tracks self.enclosures = self.compute_enclosures() # Find a connector to every pin and add it to the enclosures for pin in self.pins: - + # If it is contained, it won't need a connector if pin.contained_by_any(self.enclosures): continue @@ -469,7 +475,7 @@ class pin_group: right_connector, above_connector, below_connector] - filtered_list = list(filter(lambda x: x!=None, connector_list)) + filtered_list = list(filter(lambda x: x != None, connector_list)) if (len(filtered_list) > 0): import copy bbox_connector = copy.copy(pin) @@ -487,8 +493,9 @@ class pin_group: debug.error("Could not find a connector for {} with {}".format(self.pins, self.enclosures)) self.router.write_debug_gds("no_connector.gds") + import pdb; pdb.set_trace() self.enclosures.append(connector) - + # At this point, the pins are overlapping, # but there might be more than one! overlap_set = set() @@ -505,12 +512,11 @@ class pin_group: (sufficient, insufficient) = self.router.convert_pin_to_tracks(self.name, enclosure) self.grids.update(sufficient) - - - debug.info(3,"Computed enclosure(s) {0}\n {1}\n {2}\n {3}".format(self.name, - self.pins, - self.grids, - self.enclosures)) + + debug.info(3, "Computed enclosure(s) {0}\n {1}\n {2}\n {3}".format(self.name, + self.pins, + self.grids, + self.enclosures)) def transitive_overlap(self, shape, shape_list): """ @@ -532,22 +538,22 @@ class pin_group: # Remove the original shape connected_set.remove(shape) - + # if len(connected_set) 0: debug.info(2, "Removing blocks {}".format(shared_set)) blockage_set.difference_update(shared_set) - + # At least one of the groups must have some valid tracks if (len(pin_set) == 0 and len(partial_set) == 0 and len(blockage_set) == 0): # debug.warning("Pin is very close to metal blockage.\nAttempting to expand blocked pin {}".format(self.pins)) - + for pin in self.pins: debug.warning(" Expanding conversion {0}".format(pin)) # Determine which tracks the pin overlaps - (sufficient,insufficient)=self.router.convert_pin_to_tracks(self.name, - pin, - expansion=1) + (sufficient, insufficient) = self.router.convert_pin_to_tracks(self.name, + pin, + expansion=1) pin_set.update(sufficient) partial_set.update(insufficient) - + if len(pin_set) == 0 and len(partial_set) == 0: debug.error("Unable to find unblocked pin {} {}".format(self.name, self.pins)) @@ -653,11 +659,12 @@ class pin_group: # Consider all the grids that would be blocked self.grids = pin_set | partial_set + if len(self.grids) < 0: + debug.error("Did not find any unblocked grids: {}".format(str(self.pins))) + self.router.write_debug_gds("blocked_pin.gds") + # Remember the secondary grids for removing adjacent pins self.secondary_grids = partial_set debug.info(2, " pins {}".format(self.grids)) debug.info(2, " secondary {}".format(self.secondary_grids)) - - - diff --git a/compiler/router/router.py b/compiler/router/router.py index 7be3a4c0..cacd5117 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -27,11 +27,10 @@ class router(router_tech): route on a given layer. This is limited to two layer routes. It populates blockages on a grid class. """ - def __init__(self, layers, design, gds_filename=None, rail_track_width=1): """ This will instantiate a copy of the gds file or the module at (0,0) and - route on top of this. The blockages from the gds/module will be + route on top of this. The blockages from the gds/module will be considered. """ router_tech.__init__(self, layers, rail_track_width) @@ -84,7 +83,7 @@ class router(router_tech): self.boundary = self.layout.measureBoundary(self.top_name) # These must be un-indexed to get rid of the matrix type self.ll = vector(self.boundary[0][0], self.boundary[0][1]) - self.ur = vector(self.boundary[1][0], self.boundary[1][1]) + self.ur = vector(self.boundary[1][0], self.boundary[1][1]) def clear_pins(self): """ @@ -93,7 +92,7 @@ class router(router_tech): """ self.pins = {} self.all_pins = set() - self.pin_groups = {} + self.pin_groups = {} # DO NOT clear the blockages as these don't change self.rg.reinit() @@ -112,7 +111,7 @@ class router(router_tech): """ Retrieve the pin shapes on metal 3 from the layout. """ - debug.info(2, "Retrieving pins for {}.".format(pin_name)) + debug.info(2, "Retrieving pins for {}.".format(pin_name)) shape_list = self.layout.getAllPinShapes(str(pin_name)) pin_set = set() for shape in shape_list: @@ -140,13 +139,13 @@ class router(router_tech): This doesn't consider whether the obstacles will be pins or not. They get reset later if they are not actually a blockage. """ - debug.info(1, "Finding blockages.") - for layer in [self.vert_layer_number, self.horiz_layer_number]: - self.retrieve_blockages(layer) + debug.info(1, "Finding blockages.") + for lpp in [self.vert_lpp, self.horiz_lpp]: + self.retrieve_blockages(lpp) def find_pins_and_blockages(self, pin_list): """ - Find the pins and blockages in the design + Find the pins and blockages in the design """ # This finds the pin shapes and sorts them into "groups" that # are connected. This must come before the blockages, so we @@ -447,7 +446,7 @@ class router(router_tech): """ # Inflate the blockage by half a spacing rule [ll, ur] = self.convert_blockage_to_tracks(blockage.inflate()) - zlayer = self.get_zindex(blockage.lpp[0]) + zlayer = self.get_zindex(blockage.lpp) blockage_tracks = self.get_blockage_tracks(ll, ur, zlayer) return blockage_tracks @@ -459,19 +458,19 @@ class router(router_tech): blockage_list = self.convert_blockage(blockage) self.blocked_grids.update(blockage_list) - def retrieve_blockages(self, layer_num): + def retrieve_blockages(self, lpp): """ Recursive find boundaries as blockages to the routing grid. """ - shapes = self.layout.getAllShapes(layer_num) + shapes = self.layout.getAllShapes(lpp) for boundary in shapes: ll = vector(boundary[0], boundary[1]) ur = vector(boundary[2], boundary[3]) rect = [ll, ur] new_pin = pin_layout("blockage{}".format(len(self.blockages)), rect, - layer_num) + lpp) # If there is a rectangle that is the same in the pins, # it isn't a blockage! @@ -529,7 +528,7 @@ class router(router_tech): sufficient_list = set() insufficient_list = set() - zindex = self.get_zindex(pin.lpp[0]) + zindex = self.get_zindex(pin.lpp) for x in range(int(ll[0]) + expansion, int(ur[0]) + 1 + expansion): for y in range(int(ll[1] + expansion), int(ur[1]) + 1 + expansion): (full_overlap, partial_overlap) = self.convert_pin_coord_to_tracks(pin, @@ -622,7 +621,6 @@ class router(router_tech): """ Return all tracks that an inflated pin overlaps """ - # This is using the full track shape rather # than a single track pin shape # because we will later patch a connector if there isn't overlap. @@ -807,8 +805,8 @@ class router(router_tech): def enclose_pins(self): """ This will find the biggest rectangle enclosing some grid squares and - put a rectangle over it. It does not enclose grid squares that are blocked - by other shapes. + put a rectangle over it. It does not enclose grid squares + that are blocked by other shapes. """ for pin_name in self.pin_groups: debug.info(1, "Enclosing pins for {}".format(pin_name)) diff --git a/compiler/router/router_tech.py b/compiler/router/router_tech.py index 49df06fd..efae2708 100644 --- a/compiler/router/router_tech.py +++ b/compiler/router/router_tech.py @@ -5,13 +5,13 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from tech import drc,layer +from tech import drc, layer from contact import contact -from pin_group import pin_group from vector import vector import debug import math + class router_tech: """ This is a class to hold the router tech constants. @@ -25,9 +25,9 @@ class router_tech: self.layers = layers self.rail_track_width = rail_track_width - if len(self.layers)==1: + if len(self.layers) == 1: self.horiz_layer_name = self.vert_layer_name = self.layers[0] - self.horiz_layer_number = self.vert_layer_number = layer[self.layers[0]] + self.horiz_lpp = self.vert_lpp = layer[self.layers[0]] (self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_supply_layer_width_space(1) (self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_supply_layer_width_space(0) @@ -40,8 +40,8 @@ class router_tech: via_connect = contact(self.layers, (1, 1)) max_via_size = max(via_connect.width,via_connect.height) - self.horiz_layer_number = layer[self.horiz_layer_name] - self.vert_layer_number = layer[self.vert_layer_name] + self.horiz_lpp = layer[self.horiz_layer_name] + self.vert_lpp = layer[self.vert_layer_name] (self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_supply_layer_width_space(1) (self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_supply_layer_width_space(0) @@ -68,8 +68,18 @@ class router_tech: # When we actually create the routes, make them the width of the track (minus 1/2 spacing on each side) self.layer_widths = [self.track_wire, 1, self.track_wire] - def get_zindex(self,layer_num): - if layer_num==self.horiz_layer_number: + def same_lpp(self, lpp1, lpp2): + """ + Check if the layers and purposes are the same. + Ignore if purpose is a None. + """ + if lpp1[1] == None or lpp2[1] == None: + return lpp1[0] == lpp2[0] + + return lpp1[0] == lpp2[0] and lpp1[1] == lpp2[1] + + def get_zindex(self, lpp): + if self.same_lpp(lpp, self.horiz_lpp): return 0 else: return 1 diff --git a/compiler/router/supply_grid_router.py b/compiler/router/supply_grid_router.py index 5ddabc98..881e87b2 100644 --- a/compiler/router/supply_grid_router.py +++ b/compiler/router/supply_grid_router.py @@ -55,7 +55,7 @@ class supply_grid_router(router): self.rg = supply_grid.supply_grid(self.ll, self.ur, self.track_width) def route(self, vdd_name="vdd", gnd_name="gnd"): - """ + """ Add power supply rails and connect all pins to these rails. """ debug.info(1,"Running supply router on {0} and {1}...".format(vdd_name, gnd_name)) @@ -75,7 +75,6 @@ class supply_grid_router(router): start_time = datetime.now() self.find_pins_and_blockages([self.vdd_name, self.gnd_name]) print_time("Finding pins and blockages",datetime.now(), start_time, 3) - # Add the supply rails in a mesh network and connect H/V with vias start_time = datetime.now() # Block everything diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 8406fa53..4ffeb4fe 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -67,7 +67,6 @@ layer["via9"] = (28, 0) layer["metal10"] = (29, 0) layer["text"] = (239, 0) layer["boundary"]= (239, 0) -#layer["blockage"]= (239, 0) ################################################### ##END GDS Layer Map diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index c74d7ee5..6edaf7aa 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -54,7 +54,6 @@ layer["via3"] = (30, 0) layer["metal4"] = (31, 0) layer["text"] = (63, 0) layer["boundary"] = (63, 0) -#layer["blockage"] = (83, 0) ################################################### ##END GDS Layer Map From 7e9d08206c015c06db367b41779dc01217a98f7b Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Thu, 14 Nov 2019 20:18:18 +0000 Subject: [PATCH 015/521] Fix config import to be location independent --- compiler/globals.py | 245 +++++++++++++++++++++++++++----------------- 1 file changed, 150 insertions(+), 95 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index 0bdd486d..eae61ba7 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -6,8 +6,8 @@ # All rights reserved. # """ -This is called globals.py, but it actually parses all the arguments and performs -the global OpenRAM setup as well. +This is called globals.py, but it actually parses all the arguments +and performs the global OpenRAM setup as well. """ import os import debug @@ -24,7 +24,8 @@ NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" OPTS = options.options() -CHECKPOINT_OPTS=None +CHECKPOINT_OPTS = None + def parse_args(): """ Parse the optional arguments for OpenRAM """ @@ -32,27 +33,55 @@ def parse_args(): global OPTS option_list = { - optparse.make_option("-b", "--backannotated", action="store_true", dest="use_pex", + optparse.make_option("-b", + "--backannotated", + action="store_true", + dest="use_pex", help="Back annotate simulation"), - optparse.make_option("-o", "--output", dest="output_name", - help="Base output file name(s) prefix", metavar="FILE"), - optparse.make_option("-p", "--outpath", dest="output_path", + optparse.make_option("-o", + "--output", + dest="output_name", + help="Base output file name(s) prefix", + metavar="FILE"), + optparse.make_option("-p", "--outpath", + dest="output_path", help="Output file(s) location"), - optparse.make_option("-i", "--inlinecheck", action="store_true", - help="Enable inline LVS/DRC checks", dest="inline_lvsdrc"), - optparse.make_option("-n", "--nocheck", action="store_false", - help="Disable all LVS/DRC checks", dest="check_lvsdrc"), - optparse.make_option("-v", "--verbose", action="count", dest="debug_level", + optparse.make_option("-i", + "--inlinecheck", + action="store_true", + help="Enable inline LVS/DRC checks", + dest="inline_lvsdrc"), + optparse.make_option("-n", "--nocheck", + action="store_false", + help="Disable all LVS/DRC checks", + dest="check_lvsdrc"), + optparse.make_option("-v", + "--verbose", + action="count", + dest="debug_level", help="Increase the verbosity level"), - optparse.make_option("-t", "--tech", dest="tech_name", + optparse.make_option("-t", + "--tech", + dest="tech_name", help="Technology name"), - optparse.make_option("-s", "--spice", dest="spice_name", + optparse.make_option("-s", + "--spice", + dest="spice_name", help="Spice simulator executable name"), - optparse.make_option("-r", "--remove_netlist_trimming", action="store_false", dest="trim_netlist", + optparse.make_option("-r", + "--remove_netlist_trimming", + action="store_false", + dest="trim_netlist", help="Disable removal of noncritical memory cells during characterization"), - optparse.make_option("-c", "--characterize", action="store_false", dest="analytical_delay", + optparse.make_option("-c", + "--characterize", + action="store_false", + dest="analytical_delay", help="Perform characterization to calculate delays (default is analytical models)"), - optparse.make_option("-d", "--dontpurge", action="store_false", dest="purge_temp", + optparse.make_option("-d", + "--dontpurge", + action="store_false", + dest="purge_temp", help="Don't purge the contents of the temp directory after a successful run") # -h --help is implicit. } @@ -73,6 +102,7 @@ def parse_args(): return (options, args) + def print_banner(): """ Conditionally print the banner to stdout """ global OPTS @@ -117,13 +147,13 @@ def check_versions(): except: OPTS.coverage = 0 + def init_openram(config_file, is_unit_test=True): - """Initialize the technology, paths, simulators, etc.""" + """ Initialize the technology, paths, simulators, etc. """ - check_versions() - debug.info(1,"Initializing OpenRAM...") + debug.info(1, "Initializing OpenRAM...") setup_paths() @@ -146,10 +176,11 @@ def init_openram(config_file, is_unit_test=True): # This is a hack. If we are running a unit test and have checkpointed # the options, load them rather than reading the config file. # This way, the configuration is reloaded at the start of every unit test. - # If a unit test fails, we don't have to worry about restoring the old config values + # If a unit test fails, + # we don't have to worry about restoring the old config values # that may have been tested. if is_unit_test and CHECKPOINT_OPTS: - OPTS.__dict__ = CHECKPOINT_OPTS.__dict__.copy() + OPTS.__dict__ = CHECKPOINT_OPTS.__dict__.copy() return # Import these to find the executables for checkpointing @@ -159,7 +190,8 @@ def init_openram(config_file, is_unit_test=True): # after each unit test if not CHECKPOINT_OPTS: CHECKPOINT_OPTS = copy.copy(OPTS) - + + def setup_bitcell(): """ Determine the correct custom or parameterized bitcell for the design. @@ -169,30 +201,29 @@ def setup_bitcell(): # If we have non-1rw ports, # and the user didn't over-ride the bitcell manually, # figure out the right bitcell to use - if (OPTS.bitcell=="bitcell"): + if (OPTS.bitcell == "bitcell"): - if (OPTS.num_rw_ports==1 and OPTS.num_w_ports==0 and OPTS.num_r_ports==0): + if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0): OPTS.bitcell = "bitcell" OPTS.replica_bitcell = "replica_bitcell" OPTS.dummy_bitcell = "dummy_bitcell" else: ports = "" - if OPTS.num_rw_ports>0: + if OPTS.num_rw_ports > 0: ports += "{}rw_".format(OPTS.num_rw_ports) - if OPTS.num_w_ports>0: + if OPTS.num_w_ports > 0: ports += "{}w_".format(OPTS.num_w_ports) - if OPTS.num_r_ports>0: + if OPTS.num_r_ports > 0: ports += "{}r".format(OPTS.num_r_ports) OPTS.bitcell = "bitcell_"+ports OPTS.replica_bitcell = "replica_bitcell_"+ports OPTS.dummy_bitcell = "dummy_bitcell_"+ports else: - OPTS.replica_bitcell = "replica_" + OPTS.bitcell - OPTS.replica_bitcell = "dummy_" + OPTS.bitcell + OPTS.replica_bitcell = "replica_" + OPTS.bitcell + OPTS.replica_bitcell = "dummy_" + OPTS.bitcell # See if bitcell exists - from importlib import find_loader try: __import__(OPTS.bitcell) __import__(OPTS.replica_bitcell) @@ -206,7 +237,7 @@ def setup_bitcell(): OPTS.replica_bitcell = "dummy_pbitcell" if not OPTS.is_unit_test: debug.warning("Using the parameterized bitcell which may have suboptimal density.") - debug.info(1,"Using bitcell: {}".format(OPTS.bitcell)) + debug.info(1, "Using bitcell: {}".format(OPTS.bitcell)) def get_tool(tool_type, preferences, default_name=None): @@ -215,63 +246,77 @@ def get_tool(tool_type, preferences, default_name=None): one selected and its full path. If default is specified, find that one only and error otherwise. """ - debug.info(2,"Finding {} tool...".format(tool_type)) + debug.info(2, "Finding {} tool...".format(tool_type)) if default_name: - exe_name=find_exe(default_name) + exe_name = find_exe(default_name) if exe_name == None: - debug.error("{0} not found. Cannot find {1} tool.".format(default_name,tool_type),2) + debug.error("{0} not found. Cannot find {1} tool.".format(default_name, + tool_type), + 2) else: - debug.info(1, "Using {0}: {1}".format(tool_type,exe_name)) - return(default_name,exe_name) + debug.info(1, "Using {0}: {1}".format(tool_type, exe_name)) + return(default_name, exe_name) else: for name in preferences: exe_name = find_exe(name) if exe_name != None: - debug.info(1, "Using {0}: {1}".format(tool_type,exe_name)) - return(name,exe_name) + debug.info(1, "Using {0}: {1}".format(tool_type, exe_name)) + return(name, exe_name) else: - debug.info(1, "Could not find {0}, trying next {1} tool.".format(name,tool_type)) + debug.info(1, + "Could not find {0}, trying next {1} tool.".format(name, + tool_type)) else: - return(None,"") + return(None, "") def read_config(config_file, is_unit_test=True): - """ + """ Read the configuration file that defines a few parameters. The config file is just a Python file that defines some config options. This will only actually get read the first time. Subsequent reads will just restore the previous copy (ask mrg) """ global OPTS - - # Create a full path relative to current dir unless it is already an abs path + + # it is already not an abs path, make it one if not os.path.isabs(config_file): - config_file = os.getcwd() + "/" + config_file - # Make it a python file if the base name was only given - config_file = re.sub(r'\.py$', "", config_file) + try: + OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) + except: + debug.error("$OPENRAM_HOME is not properly defined.", 1) + config_file = OPENRAM_HOME + "/tests/" + config_file + ".py" + debug.check(os.path.isfile(config_file), + "{} is not a valid config file".format(config_file)) + + # Expand the user if it is used config_file = os.path.expanduser(config_file) OPTS.config_file = config_file - # Add the path to the system path so we can import things in the other directory + # Add the path to the system path + # so we can import things in the other directory dir_name = os.path.dirname(config_file) file_name = os.path.basename(config_file) + # Remove the py from the module name + file_name = re.sub(r'\.py$', "", file_name) + # Prepend the path to avoid if we are using the example config - sys.path.insert(0,dir_name) + sys.path.insert(0, dir_name) # Import the configuration file of which modules to use debug.info(1, "Configuration file is " + config_file + ".py") try: - config = importlib.import_module(file_name) + config = importlib.import_module(file_name) except: debug.error("Unable to read configuration file: {0}".format(config_file),2) - for k,v in config.__dict__.items(): + for k, v in config.__dict__.items(): # The command line will over-ride the config file # except in the case of the tech name! This is because the tech name # is sometimes used to specify the config file itself (e.g. unit tests) # Note that if we re-read a config file, nothing will get read again! - if not k in OPTS.__dict__ or k=="tech_name": - OPTS.__dict__[k]=v + if not k in OPTS.__dict__ or k == "tech_name": + OPTS.__dict__[k] = v # Massage the output path to be an absolute one if not OPTS.output_path.endswith('/'): @@ -281,20 +326,20 @@ def read_config(config_file, is_unit_test=True): debug.info(1, "Output saved in " + OPTS.output_path) # Remember if we are running unit tests to reduce output - OPTS.is_unit_test=is_unit_test + OPTS.is_unit_test = is_unit_test # If we are only generating a netlist, we can't do DRC/LVS if OPTS.netlist_only: - OPTS.check_lvsdrc=False + OPTS.check_lvsdrc = False # If config didn't set output name, make a reasonable default. if (OPTS.output_name == ""): ports = "" - if OPTS.num_rw_ports>0: + if OPTS.num_rw_ports > 0: ports += "{}rw_".format(OPTS.num_rw_ports) - if OPTS.num_w_ports>0: + if OPTS.num_w_ports > 0: ports += "{}w_".format(OPTS.num_w_ports) - if OPTS.num_r_ports>0: + if OPTS.num_r_ports > 0: ports += "{}r_".format(OPTS.num_r_ports) OPTS.output_name = "sram_{0}b_{1}_{2}{3}".format(OPTS.word_size, OPTS.num_words, @@ -302,8 +347,6 @@ def read_config(config_file, is_unit_test=True): OPTS.tech_name) - - def end_openram(): """ Clean up openram for a proper exit """ cleanup_paths() @@ -312,9 +355,7 @@ def end_openram(): import verify verify.print_drc_stats() verify.print_lvs_stats() - verify.print_pex_stats() - - + verify.print_pex_stats() def cleanup_paths(): @@ -323,40 +364,44 @@ def cleanup_paths(): """ global OPTS if not OPTS.purge_temp: - debug.info(0,"Preserving temp directory: {}".format(OPTS.openram_temp)) + debug.info(0, + "Preserving temp directory: {}".format(OPTS.openram_temp)) return elif os.path.exists(OPTS.openram_temp): - debug.info(1,"Purging temp directory: {}".format(OPTS.openram_temp)) - # This annoyingly means you have to re-cd into the directory each debug iteration - #shutil.rmtree(OPTS.openram_temp, ignore_errors=True) + debug.info(1, + "Purging temp directory: {}".format(OPTS.openram_temp)) + # This annoyingly means you have to re-cd into + # the directory each debug iteration + # shutil.rmtree(OPTS.openram_temp, ignore_errors=True) contents = [os.path.join(OPTS.openram_temp, i) for i in os.listdir(OPTS.openram_temp)] for i in contents: if os.path.isfile(i) or os.path.islink(i): os.remove(i) else: shutil.rmtree(i) - def setup_paths(): """ Set up the non-tech related paths. """ - debug.info(2,"Setting up paths...") + debug.info(2, "Setting up paths...") global OPTS try: OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) except: - debug.error("$OPENRAM_HOME is not properly defined.",1) - debug.check(os.path.isdir(OPENRAM_HOME),"$OPENRAM_HOME does not exist: {0}".format(OPENRAM_HOME)) + debug.error("$OPENRAM_HOME is not properly defined.", 1) + debug.check(os.path.isdir(OPENRAM_HOME), + "$OPENRAM_HOME does not exist: {0}".format(OPENRAM_HOME)) # Add all of the subdirs to the python path - # These subdirs are modules and don't need to be added: characterizer, verify + # These subdirs are modules and don't need + # to be added: characterizer, verify subdirlist = [ item for item in os.listdir(OPENRAM_HOME) if os.path.isdir(os.path.join(OPENRAM_HOME, item)) ] for subdir in subdirlist: - full_path = "{0}/{1}".format(OPENRAM_HOME,subdir) + full_path = "{0}/{1}".format(OPENRAM_HOME, subdir) debug.check(os.path.isdir(full_path), - "$OPENRAM_HOME/{0} does not exist: {1}".format(subdir,full_path)) + "$OPENRAM_HOME/{0} does not exist: {1}".format(subdir, full_path)) sys.path.append("{0}".format(full_path)) if not OPTS.openram_temp.endswith('/'): @@ -364,13 +409,16 @@ def setup_paths(): debug.info(1, "Temporary files saved in " + OPTS.openram_temp) - def is_exe(fpath): """ Return true if the given is an executable file that exists. """ return os.path.exists(fpath) and os.access(fpath, os.X_OK) + def find_exe(check_exe): - """ Check if the binary exists in any path dir and return the full path. """ + """ + Check if the binary exists in any path dir + and return the full path. + """ # Check if the preferred spice option exists in the path for path in os.environ["PATH"].split(os.pathsep): exe = os.path.join(path, check_exe) @@ -379,12 +427,14 @@ def find_exe(check_exe): return exe return None + def init_paths(): """ Create the temp and output directory if it doesn't exist """ # make the directory if it doesn't exist try: - debug.info(1,"Creating temp directory: {}".format(OPTS.openram_temp)) + debug.info(1, + "Creating temp directory: {}".format(OPTS.openram_temp)) os.makedirs(OPTS.openram_temp, 0o750) except OSError as e: if e.errno == 17: # errno.EEXIST @@ -398,8 +448,9 @@ def init_paths(): if e.errno == 17: # errno.EEXIST os.chmod(OPTS.output_path, 0o750) except: - debug.error("Unable to make output directory.",-1) + debug.error("Unable to make output directory.", -1) + def set_default_corner(): """ Set the default corner. """ @@ -416,17 +467,19 @@ def import_tech(): """ Dynamically adds the tech directory to the path and imports it. """ global OPTS - debug.info(2,"Importing technology: " + OPTS.tech_name) + debug.info(2, + "Importing technology: " + OPTS.tech_name) # environment variable should point to the technology dir try: OPENRAM_TECH = os.path.abspath(os.environ.get("OPENRAM_TECH")) except: - debug.error("$OPENRAM_TECH environment variable is not defined.",1) + debug.error("$OPENRAM_TECH environment variable is not defined.", 1) # Add all of the paths for tech_path in OPENRAM_TECH.split(":"): - debug.check(os.path.isdir(tech_path),"$OPENRAM_TECH does not exist: {0}".format(tech_path)) + debug.check(os.path.isdir(tech_path), + "$OPENRAM_TECH does not exist: {0}".format(tech_path)) sys.path.append(tech_path) debug.info(1, "Adding technology path: {}".format(tech_path)) @@ -452,22 +505,25 @@ def print_time(name, now_time, last_time=None, indentation=2): global OPTS # Don't print during testing - if not OPTS.is_unit_test or OPTS.debug_level>0: + if not OPTS.is_unit_test or OPTS.debug_level > 0: if last_time: time = str(round((now_time-last_time).total_seconds(),1)) + " seconds" else: time = now_time.strftime('%m/%d/%Y %H:%M:%S') - debug.print_raw("{0} {1}: {2}".format("*"*indentation,name,time)) + debug.print_raw("{0} {1}: {2}".format("*"*indentation, name, time)) def report_status(): - """ Check for valid arguments and report the info about the SRAM being generated """ + """ + Check for valid arguments and report the + info about the SRAM being generated + """ global OPTS # Check if all arguments are integers for bits, size, banks - if type(OPTS.word_size)!=int: + if type(OPTS.word_size) != int: debug.error("{0} is not an integer in config file.".format(OPTS.word_size)) - if type(OPTS.num_words)!=int: + if type(OPTS.num_words) != int: debug.error("{0} is not an integer in config file.".format(OPTS.sram_size)) if type(OPTS.write_size) is not int and OPTS.write_size is not None: debug.error("{0} is not an integer in config file.".format(OPTS.write_size)) @@ -477,30 +533,29 @@ def report_status(): if OPTS.write_size is not None: if (OPTS.word_size % OPTS.write_size != 0): debug.error("Write size needs to be an integer multiple of word size.") - # If write size is more than half of the word size, then it doesn't need a write mask. It would be writing + # If write size is more than half of the word size, + # then it doesn't need a write mask. It would be writing # the whole word. if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size/2): debug.error("Write size needs to be between 1 bit and {0} bits/2.".format(OPTS.word_size)) - - if not OPTS.tech_name: debug.error("Tech name must be specified in config file.") debug.print_raw("Technology: {0}".format(OPTS.tech_name)) total_size = OPTS.word_size*OPTS.num_words*OPTS.num_banks debug.print_raw("Total size: {} bits".format(total_size)) - if total_size>=2**14: + if total_size >= 2**14: debug.warning("Requesting such a large memory size ({0}) will have a large run-time. ".format(total_size) + "Consider using multiple smaller banks.") debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size, - OPTS.num_words, - OPTS.num_banks)) + OPTS.num_words, + OPTS.num_banks)) if (OPTS.write_size != OPTS.word_size): debug.print_raw("Write size: {}".format(OPTS.write_size)) debug.print_raw("RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports)) + OPTS.num_r_ports, + OPTS.num_w_ports)) if OPTS.netlist_only: debug.print_raw("Netlist only mode (no physical design is being done, netlist_only=False to disable).") @@ -517,7 +572,7 @@ def report_status(): if OPTS.analytical_delay: debug.print_raw("Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).") else: - if OPTS.spice_name!="": + if OPTS.spice_name != "": debug.print_raw("Performing simulation-based characterization with {}".format(OPTS.spice_name)) if OPTS.trim_netlist: debug.print_raw("Trimming netlist to speed up characterization (trim_netlist=False to disable).") From 2c7aa5d0dae1720faa1cd2e8c1e6c9d0bfee5f32 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Fri, 15 Nov 2019 03:59:57 +0000 Subject: [PATCH 016/521] Non-power of 2 address decode tentative --- compiler/modules/hierarchical_decoder.py | 61 ++++++++++--------- .../tests/06_hierarchical_decoder_test.py | 36 +++++++++++ 2 files changed, 69 insertions(+), 28 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 0e70db55..4648519a 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -10,6 +10,7 @@ import debug import design from math import log from math import sqrt +from math import ceil import math import contact from sram_factory import factory @@ -31,7 +32,7 @@ class hierarchical_decoder(design.design): self.cell_height = height self.rows = rows - self.num_inputs = int(math.log(self.rows, 2)) + self.num_inputs = math.ceil(math.log(self.rows, 2)) (self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) self.create_netlist() @@ -338,14 +339,15 @@ class hierarchical_decoder(design.design): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): row = len(self.predec_groups[0])*j + i - name = self.NAND_FORMAT.format(row) - self.nand_inst.append(self.add_inst(name=name, - mod=self.nand2)) - pins =["out_{0}".format(i), - "out_{0}".format(j + len(self.predec_groups[0])), - "Z_{0}".format(row), - "vdd", "gnd"] - self.connect_inst(pins) + if (row < self.rows): + name = self.NAND_FORMAT.format(row) + self.nand_inst.append(self.add_inst(name=name, + mod=self.nand2)) + pins =["out_{0}".format(i), + "out_{0}".format(j + len(self.predec_groups[0])), + "Z_{0}".format(row), + "vdd", "gnd"] + self.connect_inst(pins) # Row Decoder NAND GATE array for address inputs >5. @@ -356,16 +358,17 @@ class hierarchical_decoder(design.design): row = (len(self.predec_groups[0])*len(self.predec_groups[1])) * k \ + len(self.predec_groups[0])*j + i - name = self.NAND_FORMAT.format(row) - self.nand_inst.append(self.add_inst(name=name, - mod=self.nand3)) + if (row < self.rows): + name = self.NAND_FORMAT.format(row) + self.nand_inst.append(self.add_inst(name=name, + mod=self.nand3)) - pins = ["out_{0}".format(i), - "out_{0}".format(j + len(self.predec_groups[0])), - "out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])), - "Z_{0}".format(row), - "vdd", "gnd"] - self.connect_inst(pins) + pins = ["out_{0}".format(i), + "out_{0}".format(j + len(self.predec_groups[0])), + "out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])), + "Z_{0}".format(row), + "vdd", "gnd"] + self.connect_inst(pins) def create_decoder_inv_array(self): @@ -527,10 +530,11 @@ class hierarchical_decoder(design.design): for index_B in self.predec_groups[1]: for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? - predecode_name = "predecode_{}".format(index_A) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A")) - predecode_name = "predecode_{}".format(index_B) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B")) + if (row_index < self.rows): + predecode_name = "predecode_{}".format(index_A) + self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A")) + predecode_name = "predecode_{}".format(index_B) + self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B")) row_index = row_index + 1 elif (self.num_inputs > 5): @@ -538,12 +542,13 @@ class hierarchical_decoder(design.design): for index_B in self.predec_groups[1]: for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? - predecode_name = "predecode_{}".format(index_A) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A")) - predecode_name = "predecode_{}".format(index_B) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B")) - predecode_name = "predecode_{}".format(index_C) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("C")) + if (row_index < self.rows): + predecode_name = "predecode_{}".format(index_A) + self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A")) + predecode_name = "predecode_{}".format(index_B) + self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B")) + predecode_name = "predecode_{}".format(index_C) + self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("C")) row_index = row_index + 1 def route_vdd_gnd(self): diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index c349e889..5b901e0c 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -34,14 +34,30 @@ class hierarchical_decoder_test(openram_test): a = factory.create(module_type="hierarchical_decoder", rows=16) self.local_check(a) + debug.info(1, "Testing 17 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", rows=17) + self.local_check(a) + + debug.info(1, "Testing 23 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", rows=23) + self.local_check(a) + debug.info(1, "Testing 32 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", rows=32) self.local_check(a) + debug.info(1, "Testing 65 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", rows=65) + self.local_check(a) + debug.info(1, "Testing 128 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", rows=128) self.local_check(a) + debug.info(1, "Testing 341 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", rows=341) + self.local_check(a) + debug.info(1, "Testing 512 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", rows=512) self.local_check(a) @@ -57,14 +73,34 @@ class hierarchical_decoder_test(openram_test): a = factory.create(module_type="hierarchical_decoder", rows=16) self.local_check(a) + factory.reset() + debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=17) + self.local_check(a) + + factory.reset() + debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=23) + self.local_check(a) + debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", rows=32) self.local_check(a) + factory.reset() + debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=65) + self.local_check(a) + debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", rows=128) self.local_check(a) + factory.reset() + debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=341) + self.local_check(a) + debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", rows=512) self.local_check(a) From c4cf8134fe2e2cae14cc3db0111e2c959a07b2de Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Fri, 15 Nov 2019 18:47:59 +0000 Subject: [PATCH 017/521] Undo changes for config expansion. Change unit tests to use OPENRAM_HOME. --- compiler/base/geometry.py | 6 +-- compiler/base/hierarchy_layout.py | 50 ++++++++++++++----- compiler/globals.py | 18 +++---- compiler/tests/01_library_drc_test.py | 3 +- compiler/tests/02_library_lvs_test.py | 3 +- compiler/tests/03_contact_test.py | 3 +- compiler/tests/03_path_test.py | 3 +- compiler/tests/03_ptx_1finger_nmos_test.py | 3 +- compiler/tests/03_ptx_1finger_pmos_test.py | 3 +- compiler/tests/03_ptx_3finger_nmos_test.py | 3 +- compiler/tests/03_ptx_3finger_pmos_test.py | 3 +- compiler/tests/03_ptx_4finger_nmos_test.py | 3 +- compiler/tests/03_ptx_4finger_pmos_test.py | 3 +- compiler/tests/03_wire_test.py | 3 +- compiler/tests/04_dummy_pbitcell_test.py | 3 +- compiler/tests/04_pand2_test.py | 3 +- compiler/tests/04_pand3_test.py | 3 +- compiler/tests/04_pbitcell_test.py | 3 +- compiler/tests/04_pbuf_test.py | 3 +- compiler/tests/04_pdriver_test.py | 3 +- compiler/tests/04_pinv_10x_test.py | 3 +- compiler/tests/04_pinv_1x_beta_test.py | 3 +- compiler/tests/04_pinv_1x_test.py | 3 +- compiler/tests/04_pinv_2x_test.py | 3 +- compiler/tests/04_pinvbuf_test.py | 3 +- compiler/tests/04_pnand2_test.py | 3 +- compiler/tests/04_pnand3_test.py | 3 +- compiler/tests/04_pnor2_test.py | 3 +- compiler/tests/04_precharge_test.py | 3 +- compiler/tests/04_replica_pbitcell_test.py | 3 +- .../tests/04_single_level_column_mux_test.py | 3 +- .../tests/05_bitcell_1rw_1r_array_test.py | 4 +- compiler/tests/05_bitcell_array_test.py | 3 +- compiler/tests/05_dummy_array_test.py | 3 +- compiler/tests/05_pbitcell_array_test.py | 3 +- .../tests/05_replica_pbitcell_array_test.py | 3 +- .../tests/06_hierarchical_decoder_test.py | 3 +- .../06_hierarchical_predecode2x4_test.py | 3 +- .../06_hierarchical_predecode3x8_test.py | 3 +- .../07_single_level_column_mux_array_test.py | 3 +- compiler/tests/08_precharge_array_test.py | 3 +- compiler/tests/08_wordline_driver_test.py | 3 +- compiler/tests/09_sense_amp_array_test.py | 3 +- compiler/tests/10_write_driver_array_test.py | 3 +- .../tests/10_write_driver_array_wmask_test.py | 5 +- .../tests/10_write_mask_and_array_test.py | 3 +- compiler/tests/11_dff_array_test.py | 3 +- compiler/tests/11_dff_buf_array_test.py | 3 +- compiler/tests/11_dff_buf_test.py | 3 +- compiler/tests/12_tri_gate_array_test.py | 3 +- compiler/tests/13_delay_chain_test.py | 3 +- .../14_replica_bitcell_1rw_1r_array_test.py | 3 +- .../tests/14_replica_bitcell_array_test.py | 3 +- compiler/tests/14_replica_column_test.py | 3 +- .../tests/16_control_logic_multiport_test.py | 3 +- compiler/tests/16_control_logic_test.py | 3 +- compiler/tests/18_port_address_test.py | 3 +- compiler/tests/18_port_data_test.py | 3 +- compiler/tests/18_port_data_wmask_test.py | 3 +- compiler/tests/19_bank_select_test.py | 3 +- compiler/tests/19_multi_bank_test.py | 3 +- compiler/tests/19_pmulti_bank_test.py | 3 +- compiler/tests/19_psingle_bank_test.py | 3 +- compiler/tests/19_single_bank_1rw_1r_test.py | 3 +- compiler/tests/19_single_bank_1w_1r_test.py | 3 +- compiler/tests/19_single_bank_test.py | 3 +- compiler/tests/19_single_bank_wmask_test.py | 3 +- .../tests/20_psram_1bank_2mux_1rw_1w_test.py | 5 +- .../20_psram_1bank_2mux_1rw_1w_wmask_test.py | 5 +- .../tests/20_psram_1bank_2mux_1w_1r_test.py | 5 +- compiler/tests/20_psram_1bank_2mux_test.py | 5 +- .../tests/20_psram_1bank_4mux_1rw_1r_test.py | 5 +- .../tests/20_sram_1bank_2mux_1rw_1r_test.py | 3 +- .../tests/20_sram_1bank_2mux_1w_1r_test.py | 5 +- compiler/tests/20_sram_1bank_2mux_test.py | 3 +- .../tests/20_sram_1bank_2mux_wmask_test.py | 5 +- .../20_sram_1bank_32b_1024_wmask_test.py | 5 +- compiler/tests/20_sram_1bank_4mux_test.py | 3 +- .../tests/20_sram_1bank_8mux_1rw_1r_test.py | 3 +- compiler/tests/20_sram_1bank_8mux_test.py | 3 +- .../tests/20_sram_1bank_nomux_1rw_1r_test.py | 3 +- compiler/tests/20_sram_1bank_nomux_test.py | 3 +- .../tests/20_sram_1bank_nomux_wmask_test.py | 5 +- compiler/tests/20_sram_2bank_test.py | 3 +- compiler/tests/21_hspice_delay_test.py | 3 +- compiler/tests/21_hspice_setuphold_test.py | 3 +- compiler/tests/21_model_delay_test.py | 3 +- compiler/tests/21_ngspice_delay_test.py | 3 +- compiler/tests/21_ngspice_setuphold_test.py | 3 +- .../tests/22_psram_1bank_2mux_func_test.py | 3 +- .../tests/22_psram_1bank_4mux_func_test.py | 3 +- .../tests/22_psram_1bank_8mux_func_test.py | 3 +- .../tests/22_psram_1bank_nomux_func_test.py | 3 +- .../tests/22_sram_1bank_2mux_func_test.py | 3 +- .../tests/22_sram_1bank_4mux_func_test.py | 3 +- .../tests/22_sram_1bank_8mux_func_test.py | 3 +- .../tests/22_sram_1bank_nomux_func_test.py | 3 +- .../22_sram_1rw_1r_1bank_nomux_func_test.py | 3 +- .../tests/22_sram_wmask_1w_1r_func_test.py | 3 +- compiler/tests/22_sram_wmask_func_test.py | 3 +- .../tests/23_lib_sram_model_corners_test.py | 3 +- compiler/tests/23_lib_sram_model_test.py | 3 +- compiler/tests/23_lib_sram_prune_test.py | 3 +- compiler/tests/23_lib_sram_test.py | 3 +- compiler/tests/24_lef_sram_test.py | 3 +- compiler/tests/25_verilog_sram_test.py | 3 +- compiler/tests/26_hspice_pex_pinv_test.py | 3 +- compiler/tests/26_ngspice_pex_pinv_test.py | 3 +- compiler/tests/26_pex_test.py | 3 +- compiler/tests/30_openram_back_end_test.py | 3 +- compiler/tests/30_openram_front_end_test.py | 3 +- 111 files changed, 272 insertions(+), 147 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index f8eb03ab..cbc1d268 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -167,7 +167,7 @@ class instance(geometry): debug.info(4, "creating instance: " + self.name) - def get_blockages(self, layer, top=False): + def get_blockages(self, lpp, top=False): """ Retrieve blockages of all modules in this instance. Apply the transform of the instance placement to give absolute blockages.""" angle = math.radians(float(self.rotate)) @@ -191,11 +191,11 @@ class instance(geometry): if self.mod.is_library_cell: # Writes library cell blockages as shapes instead of a large metal blockage blockages = [] - blockages = self.mod.gds.getBlockages(layer) + blockages = self.mod.gds.getBlockages(lpp) for b in blockages: new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) else: - blockages = self.mod.get_blockages(layer) + blockages = self.mod.get_blockages(lpp) for b in blockages: new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) return new_blockages diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 503bd1d5..000e16ee 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -539,21 +539,21 @@ class layout(): Do not write the pins since they aren't obstructions. """ if type(layer)==str: - layer_num = techlayer[layer][0] + lpp = techlayer[layer] else: - layer_num = layer + lpp = layer blockages = [] for i in self.objs: - blockages += i.get_blockages(layer_num) + blockages += i.get_blockages(lpp) for i in self.insts: - blockages += i.get_blockages(layer_num) + blockages += i.get_blockages(lpp) # Must add pin blockages to non-top cells if not top_level: - blockages += self.get_pin_blockages(layer_num) + blockages += self.get_pin_blockages(lpp) return blockages - def get_pin_blockages(self, layer_num): + def get_pin_blockages(self, lpp): """ Return the pin shapes as blockages for non-top-level blocks. """ # FIXME: We don't have a body contact in ptx, so just ignore it for now import copy @@ -565,33 +565,57 @@ class layout(): for pin_name in pin_names: pin_list = self.get_pins(pin_name) for pin in pin_list: - if pin.layer_num==layer_num: + if pin.same_lpp(pin.lpp, lpp): blockages += [pin.rect] return blockages def create_horizontal_pin_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus of pins. """ - return self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=True) + return self.create_bus(layer, + pitch, + offset, + names, + length, + vertical=False, + make_pins=True) def create_vertical_pin_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus of pins. """ - return self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=True) + return self.create_bus(layer, + pitch, + offset, + names, + length, + vertical=True, + make_pins=True) def create_vertical_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus. """ - return self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=False) + return self.create_bus(layer, + pitch, + offset, + names, + length, + vertical=True, + make_pins=False) def create_horizontal_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus. """ - return self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=False) + return self.create_bus(layer, + pitch, + offset, + names, + length, + vertical=False, + make_pins=False) def create_bus(self, layer, pitch, offset, names, length, vertical, make_pins): - """ + """ Create a horizontal or vertical bus. It can be either just rectangles, or actual layout pins. It returns an map of line center line positions indexed by name. - The other coordinate is a 0 since the bus provides a range. + The other coordinate is a 0 since the bus provides a range. TODO: combine with channel router. """ diff --git a/compiler/globals.py b/compiler/globals.py index eae61ba7..08ae4d96 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -282,13 +282,9 @@ def read_config(config_file, is_unit_test=True): # it is already not an abs path, make it one if not os.path.isabs(config_file): - try: - OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - except: - debug.error("$OPENRAM_HOME is not properly defined.", 1) - config_file = OPENRAM_HOME + "/tests/" + config_file + ".py" - debug.check(os.path.isfile(config_file), - "{} is not a valid config file".format(config_file)) + config_file = os.getcwd() + "/" + config_file + # Make it a python file if the base name was only given + config_file = re.sub(r'\.py$', "", config_file) # Expand the user if it is used @@ -297,16 +293,14 @@ def read_config(config_file, is_unit_test=True): # Add the path to the system path # so we can import things in the other directory dir_name = os.path.dirname(config_file) - file_name = os.path.basename(config_file) - # Remove the py from the module name - file_name = re.sub(r'\.py$', "", file_name) + module_name = os.path.basename(config_file) # Prepend the path to avoid if we are using the example config sys.path.insert(0, dir_name) # Import the configuration file of which modules to use debug.info(1, "Configuration file is " + config_file + ".py") try: - config = importlib.import_module(file_name) + config = importlib.import_module(module_name) except: debug.error("Unable to read configuration file: {0}".format(config_file),2) @@ -315,7 +309,7 @@ def read_config(config_file, is_unit_test=True): # except in the case of the tech name! This is because the tech name # is sometimes used to specify the config file itself (e.g. unit tests) # Note that if we re-read a config file, nothing will get read again! - if not k in OPTS.__dict__ or k == "tech_name": + if k not in OPTS.__dict__ or k == "tech_name": OPTS.__dict__[k] = v # Massage the output path to be an absolute one diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index b5578d1b..94e7b396 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -17,7 +17,8 @@ import debug class library_drc_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import verify (gds_dir, gds_files) = setup_files() diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 2bb4aa32..2916a3da 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -17,7 +17,8 @@ import debug class library_lvs_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import verify (gds_dir, sp_dir, allnames) = setup_files() diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 84e18d80..e43eeee3 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -18,7 +18,8 @@ import debug class contact_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]: stack_name = ":".join(map(str, layer_stack)) diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index a753e609..4cc1f942 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -17,7 +17,8 @@ import debug class path_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import wire_path import tech import design diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index a174ff54..81977458 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_1finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking min size NMOS with 1 finger") diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 50725055..bb995099 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_1finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking min size PMOS with 1 finger") diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index 0f55bd23..bbfea153 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_3finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 484ae403..88b80321 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_3finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index d4b122c6..52d8f2f2 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_4finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index f4c5bfe1..3cdcc492 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 9c7f6c3d..0cd977f6 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -17,7 +17,8 @@ import debug class wire_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import wire import tech import design diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py index 64964067..a19145f5 100755 --- a/compiler/tests/04_dummy_pbitcell_test.py +++ b/compiler/tests/04_dummy_pbitcell_test.py @@ -18,7 +18,8 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import dummy_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index b2ee471e..7cb21615 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -18,7 +18,8 @@ import debug class pand2_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) global verify import verify diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index 4a778b20..2efbdacf 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -18,7 +18,8 @@ import debug class pand3_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) global verify import verify diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 16497ca9..e6b093b9 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -19,7 +19,8 @@ from sram_factory import factory class pbitcell_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.num_rw_ports=1 OPTS.num_w_ports=1 diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index e2990beb..847a2139 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -18,7 +18,8 @@ import debug class pbuf_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pbuf", size=8) diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index bbb790ea..95865f84 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -18,7 +18,8 @@ import debug class pdriver_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing inverter/buffer 4x 8x") # a tests the error message for specifying conflicting conditions diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index e3c3b6a7..22da05db 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -18,7 +18,8 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 8x inverter") tx = factory.create(module_type="pinv", size=8) diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index 124c31dd..fe91d339 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -18,7 +18,8 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 1x beta=3 size inverter") tx = factory.create(module_type="pinv", size=1, beta=3) diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index cc240f22..d25192f5 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -18,7 +18,8 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 1x size inverter") tx = factory.create(module_type="pinv", size=1) diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index 430af7f7..b4419bc5 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -18,7 +18,8 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 2x size inverter") tx = factory.create(module_type="pinv", size=2) diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index fefb157f..0a32c7c4 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -18,7 +18,8 @@ import debug class pinvbuf_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pinvbuf", size=8) diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index 1873a38e..0f0f2a5d 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -18,7 +18,8 @@ import debug class pnand2_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 2-input nand gate") tx = factory.create(module_type="pnand2", size=1) diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index c8ea4174..be1ac294 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -18,7 +18,8 @@ import debug class pnand3_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 3-input nand gate") tx = factory.create(module_type="pnand3", size=1) diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index db93c64f..046fc6ab 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -18,7 +18,8 @@ import debug class pnor2_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 2-input nor gate") tx = factory.create(module_type="pnor2", size=1) diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index a9027ee7..3b0d2e0c 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -18,7 +18,8 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 1308ac56..1e075629 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -18,7 +18,8 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import replica_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 77c8a01c..07dada90 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -20,7 +20,8 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check single level column mux in single port debug.info(2, "Checking column mux") diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 1f96c469..6e757067 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -20,8 +20,8 @@ import debug class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 2c23d40f..f9bebaef 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -20,7 +20,8 @@ import debug class array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="bitcell_array", cols=4, rows=4) diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index 40b0436c..a10ee83d 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -16,7 +16,8 @@ import debug class dummy_row_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing dummy row for 6t_cell") a = factory.create(module_type="dummy_array", rows=1, cols=4) diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index cc9ee573..0e58da3a 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -19,7 +19,8 @@ import debug class pbitcell_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell") OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/05_replica_pbitcell_array_test.py b/compiler/tests/05_replica_pbitcell_array_test.py index 1f66fe11..13204f0a 100755 --- a/compiler/tests/05_replica_pbitcell_array_test.py +++ b/compiler/tests/05_replica_pbitcell_array_test.py @@ -16,7 +16,8 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index 3a407dc1..d4d68017 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -18,7 +18,8 @@ import debug class hierarchical_decoder_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index cd730563..ddc9cec2 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -18,7 +18,8 @@ import debug class hierarchical_predecode2x4_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # checking hierarchical precode 2x4 for single port debug.info(1, "Testing sample for hierarchy_predecode2x4") diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index b595cec8..4e4c5b9a 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -18,7 +18,8 @@ import debug class hierarchical_predecode3x8_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # checking hierarchical precode 3x8 for single port debug.info(1, "Testing sample for hierarchy_predecode3x8") diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index cdf2aa47..09eeb98c 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -17,7 +17,8 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import single_level_column_mux_array # check single level column mux array in single port diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index e03e0308..5340404b 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -18,7 +18,8 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check precharge array in single port debug.info(2, "Checking 3 column precharge") diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index f39148d9..873833bd 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -20,7 +20,8 @@ import debug class wordline_driver_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check wordline driver for single port debug.info(2, "Checking driver") diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index 52131505..ad9cfeb2 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -18,7 +18,8 @@ import debug class sense_amp_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index e2fffd04..ad3826a2 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -18,7 +18,8 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py index 8acce579..f61aa144 100755 --- a/compiler/tests/10_write_driver_array_wmask_test.py +++ b/compiler/tests/10_write_driver_array_wmask_test.py @@ -20,7 +20,8 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4") @@ -58,4 +59,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py index 5c40b146..eb7e3ad9 100755 --- a/compiler/tests/10_write_mask_and_array_test.py +++ b/compiler/tests/10_write_mask_and_array_test.py @@ -20,7 +20,8 @@ import debug class write_mask_and_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check write driver array for single port debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4") diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index 0aed8737..eff032a4 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -18,7 +18,8 @@ import debug class dff_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing dff_array for 3x3") a = factory.create(module_type="dff_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index ad0ab517..18344676 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -18,7 +18,8 @@ import debug class dff_buf_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing dff_buf_array for 3x3") a = factory.create(module_type="dff_buf_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index e8b4a2d9..1183a4ea 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -18,7 +18,8 @@ import debug class dff_buf_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing dff_buf 4x 8x") a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8) diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index c297f399..7ff58be4 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -18,7 +18,8 @@ import debug class tri_gate_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "Testing tri_gate_array for columns=8, word_size=8") a = factory.create(module_type="tri_gate_array", columns=8, word_size=8) diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index 2483010b..989fab48 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -18,7 +18,8 @@ import debug class delay_chain_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing delay_chain") a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4]) diff --git a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py index f4fb5587..579b2805 100755 --- a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py @@ -16,7 +16,8 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index 4e4d115b..0514d0ce 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -16,7 +16,8 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index 0146695d..9deadc41 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -16,7 +16,8 @@ import debug class replica_column_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing replica column for 6t_cell") a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1) diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index 7418f2e8..e81391f2 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -22,7 +22,8 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import control_logic import tech diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 7fcbffd8..677cd271 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -18,7 +18,8 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import control_logic import tech diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py index 7e38c916..0ebb3508 100755 --- a/compiler/tests/18_port_address_test.py +++ b/compiler/tests/18_port_address_test.py @@ -16,7 +16,8 @@ import debug class port_address_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "Port address 16 rows") a = factory.create("port_address", cols=16, rows=16) diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py index dcaacb0b..4939ad33 100755 --- a/compiler/tests/18_port_data_test.py +++ b/compiler/tests/18_port_data_test.py @@ -16,7 +16,8 @@ import debug class port_data_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index bfaf4ae3..d486a7fd 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -18,7 +18,8 @@ import debug class port_data_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=16, diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index a4530bf1..27a9a279 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -18,7 +18,8 @@ import debug class bank_select_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "No column mux, rw control logic") a = factory.create(module_type="bank_select", port="rw") diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index d8f64a37..c7293126 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -19,7 +19,8 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 9a14f741..aa7c5992 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -19,7 +19,8 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 3708940d..d64a5edd 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -19,7 +19,8 @@ import debug class psingle_bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index e4d53de6..bc9f8ff0 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -18,7 +18,8 @@ import debug class single_bank_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index 0d874605..4170e66a 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -18,7 +18,8 @@ import debug class single_bank_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index ad1d2a52..53e32b65 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -18,7 +18,8 @@ import debug class single_bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index 644678d5..0d70c43e 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -18,7 +18,8 @@ import debug class single_bank_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index c6621219..eb885f0b 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -18,8 +18,9 @@ import debug #@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") class psram_1bank_2mux_1rw_1w_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index 705e6d93..ab475aaf 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -21,7 +21,8 @@ import debug class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" @@ -58,4 +59,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index a619c48e..154fda4e 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -18,8 +18,9 @@ import debug #@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") class psram_1bank_2mux_1w_1r_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index c932a95a..b0dec84b 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -18,8 +18,9 @@ import debug #@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error") class psram_1bank_2mux_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index e012ce30..8d4d048f 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -17,8 +17,9 @@ import debug class psram_1bank_4mux_1rw_1r_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index b506b87d..5824c60a 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -18,7 +18,8 @@ import debug class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 18c031c9..6cfac474 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -18,8 +18,9 @@ import debug #@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") class psram_1bank_2mux_1w_1r_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 3d43bb04..e2d431bf 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py index 55fe2d0b..dba51753 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py @@ -21,7 +21,8 @@ import debug class sram_1bank_2mux_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=8, write_size=4, @@ -51,4 +52,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py index 4df085e0..823b841a 100755 --- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py +++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py @@ -21,7 +21,8 @@ import debug class sram_1bank_32b_1024_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=32, write_size=8, @@ -50,4 +51,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index d849135f..7a77650e 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_4mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, num_words=64, diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index bf8ee8f0..ae75618f 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -18,7 +18,8 @@ import debug class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index e056732a..d7ae16a8 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_8mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=2, num_words=128, diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index cb7dbd9f..ecc44117 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -18,7 +18,8 @@ import debug class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index b9bc14a4..c21e6694 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_nomux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, num_words=16, diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py index 26d75d82..71d97db2 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py @@ -21,7 +21,8 @@ import debug class sram_1bank_nomux_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=8, write_size=4, @@ -51,4 +52,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index 61b909ec..b1d54460 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -19,7 +19,8 @@ import debug class sram_2bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=16, num_words=32, diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index a1ad05a7..c27ab122 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -18,7 +18,8 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index c309b10a..fb81d137 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -18,7 +18,8 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index 1b611808..289af76e 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -20,7 +20,8 @@ class model_delay_test(openram_test): """ Compare the accuracy of the analytical model with a spice simulation. """ def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 63ad6022..86cbc518 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -18,7 +18,8 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index c0db881a..37fb56c0 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -18,7 +18,8 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index 63d65993..ae9de4f6 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -18,7 +18,8 @@ import debug class psram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index d688d4a0..7d945951 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -19,7 +19,8 @@ import debug class psram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 6938732c..3173210d 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -19,7 +19,8 @@ import debug class psram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index a1d1051c..ed7f17fc 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -19,7 +19,8 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 048ee372..04856d3a 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index c8bd2657..a92ef19e 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index b8d7fc07..538c72e6 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index 7133fc71..5a8e5697 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index a24610a2..370a4de8 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -19,7 +19,8 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_wmask_1w_1r_func_test.py b/compiler/tests/22_sram_wmask_1w_1r_func_test.py index afd8310a..7111299f 100755 --- a/compiler/tests/22_sram_wmask_1w_1r_func_test.py +++ b/compiler/tests/22_sram_wmask_1w_1r_func_test.py @@ -21,7 +21,8 @@ import debug class sram_wmask_1w_1r_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index 8b3fa90d..22c4b29b 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -19,7 +19,8 @@ import debug class sram_wmask_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 5020a5c9..7527fd2b 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -18,7 +18,8 @@ import debug class lib_model_corners_lib_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 399daf7e..dab05941 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -18,7 +18,8 @@ import debug class lib_sram_model_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index cd10fb10..4c9b17ba 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -18,7 +18,8 @@ import debug class lib_sram_prune_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.trim_netlist = True diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 5a60e9ad..4c5d4ed8 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -17,7 +17,8 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.trim_netlist = False diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 3390c2e2..bb0a5116 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -18,7 +18,8 @@ import debug class lef_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index e44f081a..ce058f4a 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -17,7 +17,8 @@ import debug class verilog_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py index 7d99120c..da52e8c3 100755 --- a/compiler/tests/26_hspice_pex_pinv_test.py +++ b/compiler/tests/26_hspice_pex_pinv_test.py @@ -20,7 +20,8 @@ import debug class hspice_pex_pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import pinv # load the hspice diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py index 96cc72aa..c1cf97bd 100755 --- a/compiler/tests/26_ngspice_pex_pinv_test.py +++ b/compiler/tests/26_ngspice_pex_pinv_test.py @@ -19,7 +19,8 @@ import debug class ngspice_pex_pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import pinv # load the ngspice diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index 3fd63117..bc445a68 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -19,7 +19,8 @@ import debug class sram_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.use_pex = True diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index 16ffbbef..a947ac30 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -20,7 +20,8 @@ class openram_back_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/{1}/config".format(OPENRAM_HOME,OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 58b70574..54e2b443 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -20,7 +20,8 @@ class openram_front_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/{1}/config".format(OPENRAM_HOME,OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "Testing top-level front-end openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" From 0b3d2fe9de44466eabdb2d14d16ce151f25f88bc Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Sat, 16 Nov 2019 19:54:39 +0000 Subject: [PATCH 018/521] Undo pdriver size change for now. --- compiler/pgates/pdriver.py | 53 +++++++++++--------------------------- 1 file changed, 15 insertions(+), 38 deletions(-) diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 2e778220..bb7739b7 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -27,12 +27,12 @@ class pdriver(pgate.pgate): self.size_list = size_list self.fanout = fanout - debug.check(self.size_list or self.fanout > 0, - "Either fanout or size list must be specified.") - debug.check(not (self.size_list and self.fanout > 0), - "Cannot specify both size_list and fanout.") - debug.check(not (self.size_list and self.neg_polarity), - "Cannot specify both size_list and neg_polarity.") + if not size_list and self.fanout == 0: + debug.error("Either fanout or size list must be specified.", -1) + if self.size_list and self.fanout != 0: + debug.error("Cannot specify both size_list and fanout.", -1) + if self.size_list and self.neg_polarity: + debug.error("Cannot specify both size_list and neg_polarity.", -1) # Creates the netlist and layout pgate.pgate.__init__(self, name, height) @@ -43,44 +43,21 @@ class pdriver(pgate.pgate): self.num_stages = len(self.size_list) else: # Find the optimal number of stages for the given effort - optimal_stages = self.fanout ** (1 / self.stage_effort) - rounded_stages = int(round(optimal_stages)) - difference = optimal_stages - rounded_stages + self.num_stages = max(1, + int(round(self.fanout ** (1 / self.stage_effort)))) - - # Determine if we need to fix the polarity - if self.neg_polarity and (rounded_stages % 2 == 0): - wrong_polarity = True - elif not self.neg_polarity and (optimal_stages % 2): - wrong_polarity = True - else: - wrong_polarity = False - - # Depending on the difference, round up or down. - if wrong_polarity: - # If we rounded up and can round down, do it. - if difference < 0 and rounded_stages > 1: - rounded_stages -= 1 - else: - # Otherwise, we must round up - rounded_stages += 1 - - if self.neg_polarity: - # Need at least one stage for negative - self.num_stages = max(1, rounded_stages) - else: - # Need at least two stages for positive - self.num_stages = max(2, rounded_stages) + # Increase the number of stages if we need to fix polarity + if self.neg_polarity and (self.num_stages % 2 == 0): + self.num_stages += 1 + elif not self.neg_polarity and (self.num_stages % 2): + self.num_stages += 1 - # Use the actual stage effort - actual_stage_effort = self.fanout / self.num_stages - self.size_list = [] # compute sizes backwards from the fanout fanout_prev = self.fanout for x in range(self.num_stages): - fanout_prev = fanout_prev / actual_stage_effort - self.size_list.append(max(round(fanout_prev), 1)) + fanout_prev = max(round(fanout_prev / self.stage_effort), 1) + self.size_list.append(fanout_prev) # reverse the sizes to be from input to output self.size_list.reverse() From aca99b87bc45025f38bae399c6231973eb9c1246 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Sat, 16 Nov 2019 22:22:30 +0000 Subject: [PATCH 019/521] Fix config for tests 30 --- compiler/globals.py | 8 +++++--- compiler/sram/sram.py | 2 +- compiler/tests/30_openram_back_end_test.py | 2 +- compiler/tests/30_openram_front_end_test.py | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index 08ae4d96..a0f04de1 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -283,13 +283,15 @@ def read_config(config_file, is_unit_test=True): # it is already not an abs path, make it one if not os.path.isabs(config_file): config_file = os.getcwd() + "/" + config_file - # Make it a python file if the base name was only given - config_file = re.sub(r'\.py$', "", config_file) + + # Make it a python file if the base name was only given + config_file = re.sub(r'\.py$', "", config_file) # Expand the user if it is used config_file = os.path.expanduser(config_file) - OPTS.config_file = config_file + + OPTS.config_file = config_file + ".py" # Add the path to the system path # so we can import things in the other directory dir_name = os.path.dirname(config_file) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index c4f41f77..dfde78f7 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -112,7 +112,7 @@ class sram(): # Write the config file start_time = datetime.datetime.now() from shutil import copyfile - copyfile(OPTS.config_file + '.py', OPTS.output_path + OPTS.output_name + '.py') + copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py') debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py')) print_time("Config", datetime.datetime.now(), start_time) diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index a947ac30..0c7d5e17 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -20,7 +20,7 @@ class openram_back_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/{}/config_back_end".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) globals.init_openram(config_file) debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.") diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 54e2b443..79b19dc6 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -20,7 +20,7 @@ class openram_front_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/{}/config_front_end".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) globals.init_openram(config_file) debug.info(1, "Testing top-level front-end openram.py with 2-bit, 16 word SRAM.") From b3fb4e31833ac71dbeb00a742b1afe74da6acc3a Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Sun, 17 Nov 2019 00:44:31 +0000 Subject: [PATCH 020/521] Make unit test configs generic to tech_name --- compiler/tests/01_library_drc_test.py | 2 +- compiler/tests/02_library_lvs_test.py | 2 +- compiler/tests/03_contact_test.py | 2 +- compiler/tests/03_path_test.py | 2 +- compiler/tests/03_ptx_1finger_nmos_test.py | 2 +- compiler/tests/03_ptx_1finger_pmos_test.py | 2 +- compiler/tests/03_ptx_3finger_nmos_test.py | 2 +- compiler/tests/03_ptx_3finger_pmos_test.py | 2 +- compiler/tests/03_ptx_4finger_nmos_test.py | 2 +- compiler/tests/03_ptx_4finger_pmos_test.py | 2 +- compiler/tests/03_wire_test.py | 2 +- compiler/tests/04_dummy_pbitcell_test.py | 2 +- compiler/tests/04_pand2_test.py | 2 +- compiler/tests/04_pand3_test.py | 2 +- compiler/tests/04_pbitcell_test.py | 2 +- compiler/tests/04_pbuf_test.py | 2 +- compiler/tests/04_pdriver_test.py | 2 +- compiler/tests/04_pinv_10x_test.py | 2 +- compiler/tests/04_pinv_1x_beta_test.py | 2 +- compiler/tests/04_pinv_1x_test.py | 2 +- compiler/tests/04_pinv_2x_test.py | 2 +- compiler/tests/04_pinvbuf_test.py | 2 +- compiler/tests/04_pnand2_test.py | 2 +- compiler/tests/04_pnand3_test.py | 2 +- compiler/tests/04_pnor2_test.py | 2 +- compiler/tests/04_precharge_test.py | 2 +- compiler/tests/04_replica_pbitcell_test.py | 2 +- .../tests/04_single_level_column_mux_test.py | 2 +- .../tests/05_bitcell_1rw_1r_array_test.py | 2 +- compiler/tests/05_bitcell_array_test.py | 2 +- compiler/tests/05_dummy_array_test.py | 2 +- compiler/tests/05_pbitcell_array_test.py | 2 +- .../tests/05_replica_pbitcell_array_test.py | 2 +- .../tests/06_hierarchical_decoder_test.py | 2 +- .../06_hierarchical_predecode2x4_test.py | 2 +- .../06_hierarchical_predecode3x8_test.py | 2 +- .../07_single_level_column_mux_array_test.py | 2 +- compiler/tests/08_precharge_array_test.py | 2 +- compiler/tests/08_wordline_driver_test.py | 2 +- compiler/tests/09_sense_amp_array_test.py | 2 +- compiler/tests/10_write_driver_array_test.py | 2 +- .../tests/10_write_driver_array_wmask_test.py | 2 +- .../tests/10_write_mask_and_array_test.py | 2 +- compiler/tests/11_dff_array_test.py | 2 +- compiler/tests/11_dff_buf_array_test.py | 2 +- compiler/tests/11_dff_buf_test.py | 2 +- compiler/tests/12_tri_gate_array_test.py | 2 +- compiler/tests/13_delay_chain_test.py | 2 +- .../14_replica_bitcell_1rw_1r_array_test.py | 2 +- .../tests/14_replica_bitcell_array_test.py | 2 +- compiler/tests/14_replica_column_test.py | 2 +- .../tests/16_control_logic_multiport_test.py | 2 +- compiler/tests/16_control_logic_test.py | 2 +- compiler/tests/18_port_address_test.py | 2 +- compiler/tests/18_port_data_test.py | 2 +- compiler/tests/18_port_data_wmask_test.py | 2 +- compiler/tests/19_bank_select_test.py | 2 +- compiler/tests/19_multi_bank_test.py | 2 +- compiler/tests/19_pmulti_bank_test.py | 2 +- compiler/tests/19_psingle_bank_test.py | 2 +- compiler/tests/19_single_bank_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_1w_1r_test.py | 2 +- compiler/tests/19_single_bank_test.py | 2 +- compiler/tests/19_single_bank_wmask_test.py | 2 +- .../tests/20_psram_1bank_2mux_1rw_1w_test.py | 2 +- .../20_psram_1bank_2mux_1rw_1w_wmask_test.py | 2 +- .../tests/20_psram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_test.py | 2 +- .../tests/20_psram_1bank_4mux_1rw_1r_test.py | 2 +- .../tests/20_sram_1bank_2mux_1rw_1r_test.py | 2 +- .../tests/20_sram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_test.py | 2 +- .../tests/20_sram_1bank_2mux_wmask_test.py | 2 +- .../20_sram_1bank_32b_1024_wmask_test.py | 2 +- compiler/tests/20_sram_1bank_4mux_test.py | 2 +- .../tests/20_sram_1bank_8mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_8mux_test.py | 2 +- .../tests/20_sram_1bank_nomux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_test.py | 2 +- .../tests/20_sram_1bank_nomux_wmask_test.py | 2 +- compiler/tests/20_sram_2bank_test.py | 2 +- compiler/tests/21_hspice_delay_test.py | 2 +- compiler/tests/21_hspice_setuphold_test.py | 2 +- compiler/tests/21_model_delay_test.py | 2 +- compiler/tests/21_ngspice_delay_test.py | 2 +- compiler/tests/21_ngspice_setuphold_test.py | 2 +- .../tests/22_psram_1bank_2mux_func_test.py | 2 +- .../tests/22_psram_1bank_4mux_func_test.py | 2 +- .../tests/22_psram_1bank_8mux_func_test.py | 2 +- .../tests/22_psram_1bank_nomux_func_test.py | 2 +- .../tests/22_sram_1bank_2mux_func_test.py | 2 +- .../tests/22_sram_1bank_4mux_func_test.py | 2 +- .../tests/22_sram_1bank_8mux_func_test.py | 2 +- .../tests/22_sram_1bank_nomux_func_test.py | 2 +- .../22_sram_1rw_1r_1bank_nomux_func_test.py | 2 +- .../tests/22_sram_wmask_1w_1r_func_test.py | 2 +- compiler/tests/22_sram_wmask_func_test.py | 2 +- .../tests/23_lib_sram_model_corners_test.py | 2 +- compiler/tests/23_lib_sram_model_test.py | 2 +- compiler/tests/23_lib_sram_prune_test.py | 2 +- compiler/tests/23_lib_sram_test.py | 2 +- compiler/tests/24_lef_sram_test.py | 2 +- compiler/tests/25_verilog_sram_test.py | 2 +- compiler/tests/26_hspice_pex_pinv_test.py | 2 +- compiler/tests/26_ngspice_pex_pinv_test.py | 2 +- compiler/tests/26_pex_test.py | 2 +- compiler/tests/30_openram_back_end_test.py | 2 +- compiler/tests/30_openram_front_end_test.py | 2 +- .../tests/{scn4m_subm => configs}/config.py | 3 ++- .../config_back_end.py | 3 ++- .../config_front_end.py | 3 ++- compiler/tests/freepdk45/config.py | 18 ----------------- compiler/tests/freepdk45/config_back_end.py | 20 ------------------- compiler/tests/freepdk45/config_front_end.py | 18 ----------------- 114 files changed, 114 insertions(+), 167 deletions(-) rename compiler/tests/{scn4m_subm => configs}/config.py (90%) rename compiler/tests/{scn4m_subm => configs}/config_back_end.py (90%) rename compiler/tests/{scn4m_subm => configs}/config_front_end.py (89%) delete mode 100644 compiler/tests/freepdk45/config.py delete mode 100644 compiler/tests/freepdk45/config_back_end.py delete mode 100644 compiler/tests/freepdk45/config_front_end.py diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index 94e7b396..cfeb4ab2 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -17,7 +17,7 @@ import debug class library_drc_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import verify diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 2916a3da..5f53753b 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -17,7 +17,7 @@ import debug class library_lvs_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import verify diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index e43eeee3..2e3f4f0f 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -18,7 +18,7 @@ import debug class contact_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]: diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index 4cc1f942..be210c8f 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -17,7 +17,7 @@ import debug class path_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import wire_path import tech diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index 81977458..ae323d90 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_1finger_nmos_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import tech diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index bb995099..3bf3e293 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_1finger_pmos_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import tech diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index bbfea153..95700e8f 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_3finger_nmos_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import tech diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 88b80321..8c09cf9b 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_3finger_pmos_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import tech diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index 52d8f2f2..da9e438d 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_4finger_nmos_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import tech diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index 3cdcc492..4fc60d5c 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import tech diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 0cd977f6..2e2db319 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -17,7 +17,7 @@ import debug class wire_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import wire import tech diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py index a19145f5..b39e48ea 100755 --- a/compiler/tests/04_dummy_pbitcell_test.py +++ b/compiler/tests/04_dummy_pbitcell_test.py @@ -18,7 +18,7 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import dummy_pbitcell diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index 7cb21615..f7e5f304 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -18,7 +18,7 @@ import debug class pand2_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) global verify import verify diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index 2efbdacf..e58f1ee9 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -18,7 +18,7 @@ import debug class pand3_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) global verify import verify diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index e6b093b9..450c0263 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -19,7 +19,7 @@ from sram_factory import factory class pbitcell_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.num_rw_ports=1 diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 847a2139..ffd06962 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -18,7 +18,7 @@ import debug class pbuf_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing inverter/buffer 4x 8x") diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index 95865f84..e65b6fad 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -18,7 +18,7 @@ import debug class pdriver_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing inverter/buffer 4x 8x") diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index 22da05db..ae3f480b 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Checking 8x inverter") diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index fe91d339..0b8c055a 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Checking 1x beta=3 size inverter") diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index d25192f5..e6c0bff2 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Checking 1x size inverter") diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index b4419bc5..0a0e63ec 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Checking 2x size inverter") diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index 0a32c7c4..df7645d1 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -18,7 +18,7 @@ import debug class pinvbuf_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing inverter/buffer 4x 8x") diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index 0f0f2a5d..f939738a 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -18,7 +18,7 @@ import debug class pnand2_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Checking 2-input nand gate") diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index be1ac294..f1af19ac 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -18,7 +18,7 @@ import debug class pnand3_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Checking 3-input nand gate") diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index 046fc6ab..ea0d6dbc 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -18,7 +18,7 @@ import debug class pnor2_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Checking 2-input nor gate") diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 3b0d2e0c..1c12ad8b 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -18,7 +18,7 @@ import debug class precharge_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check precharge in single port diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 1e075629..77336c61 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -18,7 +18,7 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import replica_pbitcell diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 07dada90..de5870fc 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -20,7 +20,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check single level column mux in single port diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 6e757067..3426f0c5 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -20,7 +20,7 @@ import debug class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index f9bebaef..256ad526 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -20,7 +20,7 @@ import debug class array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing 4x4 array for 6t_cell") diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index a10ee83d..97ec8db5 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -16,7 +16,7 @@ import debug class dummy_row_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing dummy row for 6t_cell") diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index 0e58da3a..6c5e4729 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -19,7 +19,7 @@ import debug class pbitcell_array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell") diff --git a/compiler/tests/05_replica_pbitcell_array_test.py b/compiler/tests/05_replica_pbitcell_array_test.py index 13204f0a..34bdbee7 100755 --- a/compiler/tests/05_replica_pbitcell_array_test.py +++ b/compiler/tests/05_replica_pbitcell_array_test.py @@ -16,7 +16,7 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index 01d9c0e7..9d8353f3 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -18,7 +18,7 @@ import debug class hierarchical_decoder_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index ddc9cec2..2e55f5e9 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -18,7 +18,7 @@ import debug class hierarchical_predecode2x4_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # checking hierarchical precode 2x4 for single port diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index 4e4c5b9a..da7573e1 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -18,7 +18,7 @@ import debug class hierarchical_predecode3x8_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # checking hierarchical precode 3x8 for single port diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index 09eeb98c..ff6c51eb 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -17,7 +17,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import single_level_column_mux_array diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index 5340404b..d4f5591b 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -18,7 +18,7 @@ import debug class precharge_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check precharge array in single port diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index 873833bd..f64503f8 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -20,7 +20,7 @@ import debug class wordline_driver_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check wordline driver for single port diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index ad9cfeb2..3baf51f0 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -18,7 +18,7 @@ import debug class sense_amp_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check sense amp array for single port diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index ad3826a2..16e280ed 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -18,7 +18,7 @@ import debug class write_driver_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check write driver array for single port diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py index f61aa144..743d331a 100755 --- a/compiler/tests/10_write_driver_array_wmask_test.py +++ b/compiler/tests/10_write_driver_array_wmask_test.py @@ -20,7 +20,7 @@ import debug class write_driver_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check write driver array for single port diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py index eb7e3ad9..303ce2f4 100755 --- a/compiler/tests/10_write_mask_and_array_test.py +++ b/compiler/tests/10_write_mask_and_array_test.py @@ -20,7 +20,7 @@ import debug class write_mask_and_array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check write driver array for single port diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index eff032a4..9d8798c5 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -18,7 +18,7 @@ import debug class dff_array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing dff_array for 3x3") diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index 18344676..6eb338a5 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -18,7 +18,7 @@ import debug class dff_buf_array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing dff_buf_array for 3x3") diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index 1183a4ea..070cdb56 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -18,7 +18,7 @@ import debug class dff_buf_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing dff_buf 4x 8x") diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index 7ff58be4..813feda0 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -18,7 +18,7 @@ import debug class tri_gate_array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(1, "Testing tri_gate_array for columns=8, word_size=8") diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index 989fab48..4b893a8a 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -18,7 +18,7 @@ import debug class delay_chain_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing delay_chain") diff --git a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py index 579b2805..9fbdf497 100755 --- a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py @@ -16,7 +16,7 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index 0514d0ce..19413cd5 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -16,7 +16,7 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing 4x4 array for 6t_cell") diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index 9deadc41..57c92e84 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -16,7 +16,7 @@ import debug class replica_column_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(2, "Testing replica column for 6t_cell") diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index e81391f2..919e2335 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -22,7 +22,7 @@ import debug class control_logic_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import control_logic import tech diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 677cd271..ecc6008a 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -18,7 +18,7 @@ import debug class control_logic_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import control_logic import tech diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py index 0ebb3508..23f35540 100755 --- a/compiler/tests/18_port_address_test.py +++ b/compiler/tests/18_port_address_test.py @@ -16,7 +16,7 @@ import debug class port_address_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(1, "Port address 16 rows") diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py index 4939ad33..71681056 100755 --- a/compiler/tests/18_port_data_test.py +++ b/compiler/tests/18_port_data_test.py @@ -16,7 +16,7 @@ import debug class port_data_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index d486a7fd..f670990e 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -18,7 +18,7 @@ import debug class port_data_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index 27a9a279..adb2523e 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -18,7 +18,7 @@ import debug class bank_select_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(1, "No column mux, rw control logic") diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index c7293126..f4c622c7 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -19,7 +19,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index aa7c5992..7c3da444 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -19,7 +19,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index d64a5edd..8c6ddb12 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -19,7 +19,7 @@ import debug class psingle_bank_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index bc9f8ff0..b3e18407 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class single_bank_1rw_1r_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index 4170e66a..c1228e5a 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -18,7 +18,7 @@ import debug class single_bank_1w_1r_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index 53e32b65..6cff481b 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -18,7 +18,7 @@ import debug class single_bank_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index 0d70c43e..50567ebb 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -18,7 +18,7 @@ import debug class single_bank_wmask_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index eb885f0b..599cb2ce 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index ab475aaf..0d236bc2 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -21,7 +21,7 @@ import debug class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 154fda4e..30b951fb 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index b0dec84b..44272b2d 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 8d4d048f..472a60a6 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index 5824c60a..a8d635ba 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 6cfac474..bf572700 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index e2d431bf..582f5217 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_2mux_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py index dba51753..50bd41dc 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py @@ -21,7 +21,7 @@ import debug class sram_1bank_2mux_wmask_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=8, diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py index 823b841a..05cb7c0d 100755 --- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py +++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py @@ -21,7 +21,7 @@ import debug class sram_1bank_32b_1024_wmask_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=32, diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 7a77650e..e38ef7c4 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_4mux_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index ae75618f..69a623d2 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index d7ae16a8..dfdcd5b7 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_8mux_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=2, diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index ecc44117..f9b96b84 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index c21e6694..c79d8552 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_nomux_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py index 71d97db2..24d7c97d 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py @@ -21,7 +21,7 @@ import debug class sram_1bank_nomux_wmask_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=8, diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index b1d54460..5fd4bf29 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -19,7 +19,7 @@ import debug class sram_2bank_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=16, diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index c27ab122..832a6308 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -18,7 +18,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.spice_name="hspice" OPTS.analytical_delay = False diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index fb81d137..1844fd39 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -18,7 +18,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.spice_name="hspice" OPTS.analytical_delay = False diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index 289af76e..e21d658e 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -20,7 +20,7 @@ class model_delay_test(openram_test): """ Compare the accuracy of the analytical model with a spice simulation. """ def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 86cbc518..fb72a57d 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -18,7 +18,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.spice_name="ngspice" OPTS.analytical_delay = False diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 37fb56c0..246bdff9 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -18,7 +18,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.spice_name="ngspice" OPTS.analytical_delay = False diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index ae9de4f6..7a6da149 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -18,7 +18,7 @@ import debug class psram_1bank_2mux_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index 7d945951..facd3874 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_4mux_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 3173210d..acf0c3a4 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_8mux_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index ed7f17fc..b7d6cf78 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 04856d3a..10d19c1c 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_2mux_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index a92ef19e..d2bf7886 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_4mux_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index 538c72e6..3f6ff55f 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_8mux_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index 5a8e5697..2aa20e99 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_nomux_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index 370a4de8..d271d1e5 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_wmask_1w_1r_func_test.py b/compiler/tests/22_sram_wmask_1w_1r_func_test.py index 7111299f..50acd5bf 100755 --- a/compiler/tests/22_sram_wmask_1w_1r_func_test.py +++ b/compiler/tests/22_sram_wmask_1w_1r_func_test.py @@ -21,7 +21,7 @@ import debug class sram_wmask_1w_1r_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index 22c4b29b..d29795a9 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -19,7 +19,7 @@ import debug class sram_wmask_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 7527fd2b..1e853fae 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -18,7 +18,7 @@ import debug class lib_model_corners_lib_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.netlist_only = True diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index dab05941..6043d83f 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -18,7 +18,7 @@ import debug class lib_sram_model_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.netlist_only = True diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 4c9b17ba..9df647ce 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -18,7 +18,7 @@ import debug class lib_sram_prune_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.trim_netlist = True diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 4c5d4ed8..08bb5565 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -17,7 +17,7 @@ import debug class lib_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.trim_netlist = False diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index bb0a5116..14ad551f 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -18,7 +18,7 @@ import debug class lef_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram import sram diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index ce058f4a..c385e455 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -17,7 +17,7 @@ import debug class verilog_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram import sram diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py index da52e8c3..b4b55cdb 100755 --- a/compiler/tests/26_hspice_pex_pinv_test.py +++ b/compiler/tests/26_hspice_pex_pinv_test.py @@ -20,7 +20,7 @@ import debug class hspice_pex_pinv_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import pinv diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py index c1cf97bd..e6e0cfb2 100755 --- a/compiler/tests/26_ngspice_pex_pinv_test.py +++ b/compiler/tests/26_ngspice_pex_pinv_test.py @@ -19,7 +19,7 @@ import debug class ngspice_pex_pinv_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import pinv diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index bc445a68..4eff7db5 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -19,7 +19,7 @@ import debug class sram_func_test(openram_test): def runTest(self): - config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.use_pex = True diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index 0c7d5e17..b3c35010 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -20,7 +20,7 @@ class openram_back_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - config_file = "{}/tests/{}/config_back_end".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config_back_end".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.") diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 79b19dc6..8ed76627 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -20,7 +20,7 @@ class openram_front_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - config_file = "{}/tests/{}/config_front_end".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + config_file = "{}/tests/configs/config_front_end".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(1, "Testing top-level front-end openram.py with 2-bit, 16 word SRAM.") diff --git a/compiler/tests/scn4m_subm/config.py b/compiler/tests/configs/config.py similarity index 90% rename from compiler/tests/scn4m_subm/config.py rename to compiler/tests/configs/config.py index abb31435..b43d2707 100644 --- a/compiler/tests/scn4m_subm/config.py +++ b/compiler/tests/configs/config.py @@ -5,10 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from globals import OPTS word_size = 1 num_words = 16 -tech_name = "scn4m_subm" +tech_name = OPTS.tech_name process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] diff --git a/compiler/tests/scn4m_subm/config_back_end.py b/compiler/tests/configs/config_back_end.py similarity index 90% rename from compiler/tests/scn4m_subm/config_back_end.py rename to compiler/tests/configs/config_back_end.py index 35e4cd91..3ef6fae1 100644 --- a/compiler/tests/scn4m_subm/config_back_end.py +++ b/compiler/tests/configs/config_back_end.py @@ -5,10 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from globals import OPTS word_size = 1 num_words = 16 -tech_name = "scn4m_subm" +tech_name = OPTS.tech_name process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] diff --git a/compiler/tests/scn4m_subm/config_front_end.py b/compiler/tests/configs/config_front_end.py similarity index 89% rename from compiler/tests/scn4m_subm/config_front_end.py rename to compiler/tests/configs/config_front_end.py index 142191a0..18bb1b3e 100644 --- a/compiler/tests/scn4m_subm/config_front_end.py +++ b/compiler/tests/configs/config_front_end.py @@ -5,10 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from globals import OPTS word_size = 1 num_words = 16 -tech_name = "scn4m_subm" +tech_name = OPTS.tech_name process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] diff --git a/compiler/tests/freepdk45/config.py b/compiler/tests/freepdk45/config.py deleted file mode 100644 index 3103217f..00000000 --- a/compiler/tests/freepdk45/config.py +++ /dev/null @@ -1,18 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -word_size = 1 -num_words = 16 - -tech_name = "freepdk45" -process_corners = ["TT"] -supply_voltages = [1.0] -temperatures = [25] - -route_supplies = True -check_lvsdrc = True - diff --git a/compiler/tests/freepdk45/config_back_end.py b/compiler/tests/freepdk45/config_back_end.py deleted file mode 100644 index 68417a3b..00000000 --- a/compiler/tests/freepdk45/config_back_end.py +++ /dev/null @@ -1,20 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -word_size = 1 -num_words = 16 - -tech_name = "freepdk45" -process_corners = ["TT"] -supply_voltages = [1.0] -temperatures = [25] - -inline_lvsdrc = True -route_supplies = True -check_lvsdrc = True -analytical_delay = False - diff --git a/compiler/tests/freepdk45/config_front_end.py b/compiler/tests/freepdk45/config_front_end.py deleted file mode 100644 index 1886d808..00000000 --- a/compiler/tests/freepdk45/config_front_end.py +++ /dev/null @@ -1,18 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -word_size = 1 -num_words = 16 - -tech_name = "freepdk45" -process_corners = ["TT"] -supply_voltages = [1.0] -temperatures = [25] - -analytical_delay = False - - From cdf01c6c239708ed5a5fefd7c3213bbfdb76c364 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Sun, 17 Nov 2019 00:49:38 +0000 Subject: [PATCH 021/521] Fix test 30 for generic configs --- compiler/tests/30_openram_back_end_test.py | 2 +- compiler/tests/30_openram_front_end_test.py | 2 +- compiler/tests/configs/config.py | 11 ++++++++--- compiler/tests/configs/config_back_end.py | 12 +++++++++--- compiler/tests/configs/config_front_end.py | 12 +++++++++--- 5 files changed, 28 insertions(+), 11 deletions(-) diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index b3c35010..73d201b1 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -52,7 +52,7 @@ class openram_back_end_test(openram_test): exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) - config_name = "{0}/tests/{1}/config_back_end.py".format(OPENRAM_HOME,OPTS.tech_name) + config_name = "{0}/tests/configs/config_back_end.py".format(OPENRAM_HOME) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, out_path, diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 8ed76627..3aec10f9 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -52,7 +52,7 @@ class openram_front_end_test(openram_test): exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) - config_name = "{0}/tests/{1}/config_front_end.py".format(OPENRAM_HOME,OPTS.tech_name) + config_name = "{0}/tests/configs/config_front_end.py".format(OPENRAM_HOME) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, out_path, diff --git a/compiler/tests/configs/config.py b/compiler/tests/configs/config.py index b43d2707..c420da33 100644 --- a/compiler/tests/configs/config.py +++ b/compiler/tests/configs/config.py @@ -17,7 +17,12 @@ temperatures = [25] route_supplies = True check_lvsdrc = True -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" +if tech_name == "freepdk45": + drc_name = "calibre" + lvs_name = "calibre" + pex_name = "calibre" +else: + drc_name = "magic" + lvs_name = "netgen" + pex_name = "magic" diff --git a/compiler/tests/configs/config_back_end.py b/compiler/tests/configs/config_back_end.py index 3ef6fae1..cc0a3e1e 100644 --- a/compiler/tests/configs/config_back_end.py +++ b/compiler/tests/configs/config_back_end.py @@ -19,6 +19,12 @@ check_lvsdrc = True inline_lvsdrc = True analytical_delay = False -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" +if tech_name == "freepdk45": + drc_name = "calibre" + lvs_name = "calibre" + pex_name = "calibre" +else: + drc_name = "magic" + lvs_name = "netgen" + pex_name = "magic" + diff --git a/compiler/tests/configs/config_front_end.py b/compiler/tests/configs/config_front_end.py index 18bb1b3e..2b0f7e08 100644 --- a/compiler/tests/configs/config_front_end.py +++ b/compiler/tests/configs/config_front_end.py @@ -14,7 +14,13 @@ process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" +if tech_name == "freepdk45": + drc_name = "calibre" + lvs_name = "calibre" + pex_name = "calibre" +else: + drc_name = "magic" + lvs_name = "netgen" + pex_name = "magic" + From 240c416100657359bf0cad4bddb71ca674691cc8 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Sun, 17 Nov 2019 10:40:01 -0800 Subject: [PATCH 022/521] Remove extra print --- compiler/characterizer/setup_hold.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index 3739326a..8def076d 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -24,7 +24,6 @@ class setup_hold(): # This must match the spice model order self.pins = ["data", "dout", "clk", "vdd", "gnd"] self.model_name = "dff" - print(OPTS.openram_tech) self.model_location = OPTS.openram_tech + "sp_lib/dff.sp" self.period = tech.spice["feasible_period"] From 3364f47e565b25a33ec360377f9bbb82fbf01da4 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 20 Nov 2019 09:50:27 -0800 Subject: [PATCH 023/521] Fix wrong supply voltage in config files. --- compiler/tests/configs/config.py | 2 ++ compiler/tests/configs/config_back_end.py | 1 + compiler/tests/configs/config_front_end.py | 1 + 3 files changed, 4 insertions(+) diff --git a/compiler/tests/configs/config.py b/compiler/tests/configs/config.py index c420da33..4711214b 100644 --- a/compiler/tests/configs/config.py +++ b/compiler/tests/configs/config.py @@ -10,6 +10,7 @@ word_size = 1 num_words = 16 tech_name = OPTS.tech_name + process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] @@ -18,6 +19,7 @@ route_supplies = True check_lvsdrc = True if tech_name == "freepdk45": + supply_voltages = [1.0] drc_name = "calibre" lvs_name = "calibre" pex_name = "calibre" diff --git a/compiler/tests/configs/config_back_end.py b/compiler/tests/configs/config_back_end.py index cc0a3e1e..57288031 100644 --- a/compiler/tests/configs/config_back_end.py +++ b/compiler/tests/configs/config_back_end.py @@ -20,6 +20,7 @@ inline_lvsdrc = True analytical_delay = False if tech_name == "freepdk45": + supply_voltages = [1.0] drc_name = "calibre" lvs_name = "calibre" pex_name = "calibre" diff --git a/compiler/tests/configs/config_front_end.py b/compiler/tests/configs/config_front_end.py index 2b0f7e08..4a4faf37 100644 --- a/compiler/tests/configs/config_front_end.py +++ b/compiler/tests/configs/config_front_end.py @@ -15,6 +15,7 @@ supply_voltages = [5.0] temperatures = [25] if tech_name == "freepdk45": + supply_voltages = [1.0] drc_name = "calibre" lvs_name = "calibre" pex_name = "calibre" From 190c5a078ee258343a8c5a3ca04a486382df565a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 20 Nov 2019 11:49:39 -0800 Subject: [PATCH 024/521] Fix permissions on pwrite_driver test --- compiler/tests/04_pwrite_driver_test.py | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 compiler/tests/04_pwrite_driver_test.py diff --git a/compiler/tests/04_pwrite_driver_test.py b/compiler/tests/04_pwrite_driver_test.py old mode 100644 new mode 100755 From 807923cbf1bbc22a6a56e126a6febacd84c594ac Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 21 Nov 2019 10:11:19 -0800 Subject: [PATCH 025/521] Ignore pycache dirs. Fix output error message. --- compiler/globals.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index a0f04de1..90160512 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -398,7 +398,8 @@ def setup_paths(): full_path = "{0}/{1}".format(OPENRAM_HOME, subdir) debug.check(os.path.isdir(full_path), "$OPENRAM_HOME/{0} does not exist: {1}".format(subdir, full_path)) - sys.path.append("{0}".format(full_path)) + if "__pycache__" not in full_path: + sys.path.append("{0}".format(full_path)) if not OPTS.openram_temp.endswith('/'): OPTS.openram_temp += "/" @@ -483,7 +484,7 @@ def import_tech(): try: tech_mod = __import__(OPTS.tech_name) except ImportError: - debug.error("Nonexistent technology_setup_file: {0}.py".format(filename), -1) + debug.error("Nonexistent technology module: {0}".format(OPTS.tech_name), -1) OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/" From 982e12be5e29269368eb63ec747dd2013722c9cf Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 21 Nov 2019 11:00:22 -0800 Subject: [PATCH 026/521] Increment minor version --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index a0f04de1..59d34999 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.2" +VERSION = "1.1.3" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From 909321326d47de73d31cc95611b48c45c6566016 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 26 Nov 2019 13:21:29 -0800 Subject: [PATCH 027/521] Ignore unused layers --- compiler/base/pin_layout.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index f5d25263..f7427a9c 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -37,6 +37,8 @@ class pin_layout: # else it is required to be a lpp else: for (layer_name, lpp) in layer.items(): + if not lpp: + continue if self.same_lpp(layer_name_pp, lpp): self.layer = layer_name break From 102758881a4abf349d314b8b2dbad14c6a7aef1a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 26 Nov 2019 13:22:52 -0800 Subject: [PATCH 028/521] Use layer instead of special flags for wells --- compiler/pgates/pgate.py | 6 +++--- compiler/pgates/ptx.py | 3 ++- technology/freepdk45/tech/tech.py | 5 +---- technology/scn4m_subm/tech/tech.py | 7 ++----- 4 files changed, 8 insertions(+), 13 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 9113146b..a7974cd2 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -8,7 +8,7 @@ import contact import design import debug -from tech import drc +from tech import layers from vector import vector from globals import OPTS from sram_factory import factory @@ -141,7 +141,7 @@ class pgate(design.design): max_y_offset = self.height + 0.5 * self.m1_width self.nwell_position = middle_position nwell_height = max_y_offset - middle_position.y - if drc("has_nwell"): + if layers["nwell"]: self.add_rect(layer="nwell", offset=middle_position, width=self.well_width, @@ -153,7 +153,7 @@ class pgate(design.design): pwell_position = vector(0, -0.5 * self.m1_width) pwell_height = middle_position.y - pwell_position.y - if drc("has_pwell"): + if layers["pwell"]: self.add_rect(layer="pwell", offset=pwell_position, width=self.well_width, diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 3cc767d7..3cdf1a7c 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -152,7 +152,8 @@ class ptx(design.design): self.active_offset = vector([self.well_enclose_active] * 2) # Well enclosure of active, ensure minwidth as well - if drc("has_{}well".format(self.well_type)): + well_name = "{}well".format(self.well_type) + if layer[well_name]): self.cell_well_width = max(self.active_width + 2 * self.well_enclose_active, self.well_width) self.cell_well_height = max(self.tx_width + 2 * self.well_enclose_active, diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 4ffeb4fe..ff55bcc7 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -46,6 +46,7 @@ layer["thkox"] = (8, 0) layer["poly"] = (9, 0) layer["contact"] = (10, 0) layer["active_contact"] = (10, 0) +layer["poly_contact"] = None layer["metal1"] = (11, 0) layer["via1"] = (12, 0) layer["metal2"] = (13, 0) @@ -89,10 +90,6 @@ drclvs_home=os.environ.get("DRCLVS_HOME") drc = design_rules("freepdk45") -drc["body_tie_down"] = 0 -drc["has_pwell"] = True -drc["has_nwell"] = True - #grid size drc["grid"] = 0.0025 diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 6edaf7aa..60dc8421 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -37,13 +37,14 @@ GDS["zoom"] = 0.5 layer={} layer["vtg"] = (-1, 0) layer["vth"] = (-1, 0) -layer["contact"] = (47, 0) layer["pwell"] = (41, 0) layer["nwell"] = (42, 0) layer["active"] = (43, 0) layer["pimplant"] = (44, 0) layer["nimplant"] = (45, 0) layer["poly"] = (46, 0) +layer["poly_contact"] = None +layer["contact"] = (47, 0) layer["active_contact"] = (48, 0) layer["metal1"] = (49, 0) layer["via1"] = (50, 0) @@ -78,10 +79,6 @@ drclvs_home=os.environ.get("DRCLVS_HOME") drc = design_rules("scn4me_sub") -drc["body_tie_down"] = 0 -drc["has_pwell"] = True -drc["has_nwell"] = True - #grid size is 1/2 a lambda drc["grid"]=0.5*_lambda_ From f4599b7121fddf7dd9e326074d196cde27eba171 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 26 Nov 2019 13:23:18 -0800 Subject: [PATCH 029/521] Default tools are calibre except for SCMOS --- compiler/tests/configs/config.py | 10 +++++----- compiler/tests/configs/config_back_end.py | 10 +++++----- compiler/tests/configs/config_front_end.py | 10 +++++----- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/compiler/tests/configs/config.py b/compiler/tests/configs/config.py index 4711214b..52344e41 100644 --- a/compiler/tests/configs/config.py +++ b/compiler/tests/configs/config.py @@ -18,13 +18,13 @@ temperatures = [25] route_supplies = True check_lvsdrc = True -if tech_name == "freepdk45": +if tech_name.startswith("scn"): + drc_name = "magic" + lvs_name = "netgen" + pex_name = "magic" +else: supply_voltages = [1.0] drc_name = "calibre" lvs_name = "calibre" pex_name = "calibre" -else: - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" diff --git a/compiler/tests/configs/config_back_end.py b/compiler/tests/configs/config_back_end.py index 57288031..2a7223f5 100644 --- a/compiler/tests/configs/config_back_end.py +++ b/compiler/tests/configs/config_back_end.py @@ -19,13 +19,13 @@ check_lvsdrc = True inline_lvsdrc = True analytical_delay = False -if tech_name == "freepdk45": +if tech_name.startswith("scn"): + drc_name = "magic" + lvs_name = "netgen" + pex_name = "magic" +else: supply_voltages = [1.0] drc_name = "calibre" lvs_name = "calibre" pex_name = "calibre" -else: - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" diff --git a/compiler/tests/configs/config_front_end.py b/compiler/tests/configs/config_front_end.py index 4a4faf37..0a9bda4e 100644 --- a/compiler/tests/configs/config_front_end.py +++ b/compiler/tests/configs/config_front_end.py @@ -14,14 +14,14 @@ process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] -if tech_name == "freepdk45": +if tech_name.startswith("scn"): + drc_name = "magic" + lvs_name = "netgen" + pex_name = "magic" +else: supply_voltages = [1.0] drc_name = "calibre" lvs_name = "calibre" pex_name = "calibre" -else: - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" From 04045cf67250a117531af5159c16d594c893e3c6 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 26 Nov 2019 13:24:19 -0800 Subject: [PATCH 030/521] Fix syntax error --- compiler/pgates/ptx.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 3cdf1a7c..64e6a893 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -153,7 +153,7 @@ class ptx(design.design): # Well enclosure of active, ensure minwidth as well well_name = "{}well".format(self.well_type) - if layer[well_name]): + if layer[well_name]: self.cell_well_width = max(self.active_width + 2 * self.well_enclose_active, self.well_width) self.cell_well_height = max(self.tx_width + 2 * self.well_enclose_active, From b71d630643bf2767048a23c53224b6d4b071f1bc Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 26 Nov 2019 13:34:39 -0800 Subject: [PATCH 031/521] None for layer means unused. --- compiler/pgates/pgate.py | 24 +++++++++++++----------- compiler/pgates/ptx.py | 8 +++++--- technology/scn4m_subm/tech/tech.py | 4 ++-- 3 files changed, 20 insertions(+), 16 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index a7974cd2..0c1c0b52 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -8,7 +8,7 @@ import contact import design import debug -from tech import layers +from tech import layer, drc from vector import vector from globals import OPTS from sram_factory import factory @@ -141,27 +141,29 @@ class pgate(design.design): max_y_offset = self.height + 0.5 * self.m1_width self.nwell_position = middle_position nwell_height = max_y_offset - middle_position.y - if layers["nwell"]: + if layer["nwell"]: self.add_rect(layer="nwell", offset=middle_position, width=self.well_width, height=nwell_height) - self.add_rect(layer="vtg", - offset=self.nwell_position, - width=self.well_width, - height=nwell_height) + if layer["vtg"]: + self.add_rect(layer="vtg", + offset=self.nwell_position, + width=self.well_width, + height=nwell_height) pwell_position = vector(0, -0.5 * self.m1_width) pwell_height = middle_position.y - pwell_position.y - if layers["pwell"]: + if layer["pwell"]: self.add_rect(layer="pwell", offset=pwell_position, width=self.well_width, height=pwell_height) - self.add_rect(layer="vtg", - offset=pwell_position, - width=self.well_width, - height=pwell_height) + if layer["vtg"]: + self.add_rect(layer="vtg", + offset=pwell_position, + width=self.well_width, + height=pwell_height) def add_nwell_contact(self, pmos, pmos_pos): """ Add an nwell contact next to the given pmos device. """ diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 64e6a893..f3180840 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -7,7 +7,7 @@ # import design import debug -from tech import drc, spice +from tech import layer, drc, spice from vector import vector from sram_factory import factory @@ -319,11 +319,13 @@ class ptx(design.design): """ Add an (optional) well and implant for the type of transistor. """ - if drc("has_{}well".format(self.well_type)): - self.add_rect(layer="{}well".format(self.well_type), + well_name = "{}well".format(self.well_type) + if layer[well_name]: + self.add_rect(layer=well_name, offset=(0,0), width=self.cell_well_width, height=self.cell_well_height) + if layer["vtg"]: self.add_rect(layer="vtg", offset=(0,0), width=self.cell_well_width, diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 60dc8421..8d466023 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -35,8 +35,8 @@ GDS["zoom"] = 0.5 # create the GDS layer map layer={} -layer["vtg"] = (-1, 0) -layer["vth"] = (-1, 0) +layer["vtg"] = None +layer["vth"] = None layer["pwell"] = (41, 0) layer["nwell"] = (42, 0) layer["active"] = (43, 0) From abd8b0a23ad029eaf33e0b3c7f0f3db8cbc09f08 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 26 Nov 2019 13:54:37 -0800 Subject: [PATCH 032/521] Only setup bitcell when running top-level OpenRAM --- compiler/globals.py | 2 -- compiler/openram.py | 4 ++++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index 3865a759..464bafd0 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -168,8 +168,6 @@ def init_openram(config_file, is_unit_test=True): from sram_factory import factory factory.reset() - setup_bitcell() - global OPTS global CHECKPOINT_OPTS diff --git a/compiler/openram.py b/compiler/openram.py index 5fec7102..63a8cfd6 100755 --- a/compiler/openram.py +++ b/compiler/openram.py @@ -31,8 +31,12 @@ if len(args) != 1: # These depend on arguments, so don't load them until now. import debug +# Parse config file and set up all the options g.init_openram(config_file=args[0], is_unit_test=False) +# Ensure that the right bitcell exists or use the parameterised one +g.setup_bitcell() + # Only print banner here so it's not in unit tests g.print_banner() From d511f648c65e24004a2daf90f6c8ef92b5cfe159 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 29 Nov 2019 12:01:33 -0800 Subject: [PATCH 033/521] Move DRC/LVS/PEX tools to tech file. --- compiler/globals.py | 18 +++++++++++--- compiler/options.py | 6 +++-- compiler/tests/configs/config.py | 14 ----------- compiler/tests/configs/config_back_end.py | 12 --------- compiler/tests/configs/config_front_end.py | 13 ---------- compiler/verify/__init__.py | 29 +++++++++++++--------- technology/freepdk45/config.py | 7 ++++++ technology/freepdk45/tech/tech.py | 11 ++++++++ technology/scn3me_subm/__init__.py | 6 +---- technology/scn3me_subm/tech/tech.py | 12 +++++++++ technology/scn4m_subm/__init__.py | 6 +---- technology/scn4m_subm/config.py | 7 ++++++ technology/scn4m_subm/tech/tech.py | 12 +++++++++ 13 files changed, 86 insertions(+), 67 deletions(-) create mode 100644 technology/freepdk45/config.py create mode 100644 technology/scn4m_subm/config.py diff --git a/compiler/globals.py b/compiler/globals.py index 464bafd0..3a8153bd 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -448,14 +448,24 @@ def init_paths(): def set_default_corner(): """ Set the default corner. """ - + + import tech # Set some default options now based on the technology... if (OPTS.process_corners == ""): - OPTS.process_corners = tech.spice["fet_models"].keys() + if OPTS.nominal_corner_only: + OPTS.process_corners = ["TT"] + else: + OPTS.process_corners = tech.spice["fet_models"].keys() if (OPTS.supply_voltages == ""): - OPTS.supply_voltages = tech.spice["supply_voltages"] + if OPTS.nominal_corner_only: + OPTS.supply_voltages = [tech.spice["supply_voltages"][1]] + else: + OPTS.supply_voltages = tech.spice["supply_voltages"] if (OPTS.temperatures == ""): - OPTS.temperatures = tech.spice["temperatures"] + if OPTS.nominal_corner_only: + OPTS.temperatures = [tech.spice["temperatures"][1]] + else: + OPTS.temperatures = tech.spice["temperatures"] def import_tech(): diff --git a/compiler/options.py b/compiler/options.py index 56bd1757..444730c1 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -34,6 +34,7 @@ class options(optparse.Values): write_size = None # These will get initialized by the user or the tech file + nominal_corner_only = True supply_voltages = "" temperatures = "" process_corners = "" @@ -85,6 +86,8 @@ class options(optparse.Values): check_lvsdrc = False # This determines whether LVS and DRC is checked for every submodule. inline_lvsdrc = False + # Treat the bitcell as a black box (no DRC, LVS, or extraction) + blackbox_bitcell = False # Remove noncritical memory cells for characterization speed-up trim_netlist = False # Run with extracted parasitics @@ -110,8 +113,7 @@ class options(optparse.Values): # Should we print out the banner at startup print_banner = True - # Use detailed LEF blockages - detailed_blockages = True + # Define the output file paths output_path = "." # Define the output file base name diff --git a/compiler/tests/configs/config.py b/compiler/tests/configs/config.py index 52344e41..b876c07d 100644 --- a/compiler/tests/configs/config.py +++ b/compiler/tests/configs/config.py @@ -11,20 +11,6 @@ num_words = 16 tech_name = OPTS.tech_name -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] - route_supplies = True check_lvsdrc = True -if tech_name.startswith("scn"): - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" -else: - supply_voltages = [1.0] - drc_name = "calibre" - lvs_name = "calibre" - pex_name = "calibre" - diff --git a/compiler/tests/configs/config_back_end.py b/compiler/tests/configs/config_back_end.py index 2a7223f5..8f195e7a 100644 --- a/compiler/tests/configs/config_back_end.py +++ b/compiler/tests/configs/config_back_end.py @@ -10,22 +10,10 @@ word_size = 1 num_words = 16 tech_name = OPTS.tech_name -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] route_supplies = True check_lvsdrc = True inline_lvsdrc = True analytical_delay = False -if tech_name.startswith("scn"): - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" -else: - supply_voltages = [1.0] - drc_name = "calibre" - lvs_name = "calibre" - pex_name = "calibre" diff --git a/compiler/tests/configs/config_front_end.py b/compiler/tests/configs/config_front_end.py index 0a9bda4e..1ea88cd4 100644 --- a/compiler/tests/configs/config_front_end.py +++ b/compiler/tests/configs/config_front_end.py @@ -10,18 +10,5 @@ word_size = 1 num_words = 16 tech_name = OPTS.tech_name -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] - -if tech_name.startswith("scn"): - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" -else: - supply_voltages = [1.0] - drc_name = "calibre" - lvs_name = "calibre" - pex_name = "calibre" diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index 042fecff..59df42db 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -17,7 +17,12 @@ If not, OpenRAM will continue as if nothing happened! import os import debug -from globals import OPTS,find_exe,get_tool +from globals import OPTS +from globals import find_exe +from globals import get_tool +from tech import drc_name +from tech import lvs_name +from tech import pex_name import sys debug.info(1,"Initializing verify...") @@ -29,29 +34,29 @@ if not OPTS.check_lvsdrc: OPTS.pex_exe = None else: debug.info(1, "Finding DRC/LVS/PEX tools.") - OPTS.drc_exe = get_tool("DRC", ["calibre","assura","magic"], OPTS.drc_name) - OPTS.lvs_exe = get_tool("LVS", ["calibre","assura","netgen"], OPTS.lvs_name) - OPTS.pex_exe = get_tool("PEX", ["calibre","magic"], OPTS.pex_name) + OPTS.drc_exe = get_tool("DRC", ["calibre","assura","magic"], drc_name) + OPTS.lvs_exe = get_tool("LVS", ["calibre","assura","netgen"], lvs_name) + OPTS.pex_exe = get_tool("PEX", ["calibre","magic"], pex_name) if OPTS.drc_exe == None: - from .none import run_drc,print_drc_stats + from .none import run_drc, print_drc_stats elif "calibre"==OPTS.drc_exe[0]: - from .calibre import run_drc,print_drc_stats + from .calibre import run_drc, print_drc_stats elif "assura"==OPTS.drc_exe[0]: - from .assura import run_drc,print_drc_stats + from .assura import run_drc, print_drc_stats elif "magic"==OPTS.drc_exe[0]: - from .magic import run_drc,print_drc_stats + from .magic import run_drc, print_drc_stats else: debug.warning("Did not find a supported DRC tool.") if OPTS.lvs_exe == None: - from .none import run_lvs,print_lvs_stats + from .none import run_lvs, print_lvs_stats elif "calibre"==OPTS.lvs_exe[0]: - from .calibre import run_lvs,print_lvs_stats + from .calibre import run_lvs, print_lvs_stats elif "assura"==OPTS.lvs_exe[0]: - from .assura import run_lvs,print_lvs_stats + from .assura import run_lvs, print_lvs_stats elif "netgen"==OPTS.lvs_exe[0]: - from .magic import run_lvs,print_lvs_stats + from .magic import run_lvs, print_lvs_stats else: debug.warning("Did not find a supported LVS tool.") diff --git a/technology/freepdk45/config.py b/technology/freepdk45/config.py new file mode 100644 index 00000000..6058bb64 --- /dev/null +++ b/technology/freepdk45/config.py @@ -0,0 +1,7 @@ +process_corners = ["TT"] +supply_voltages = [1.0] +temperatures = [25] + +drc_name = "calibre" +lvs_name = "calibre" +pex_name = "calibre" diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index ff55bcc7..14db2ea4 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -336,3 +336,14 @@ parameter["bitcell_drain_cap"] = 0.1 #In Femto-Farad, approximation of dr ##END Spice Simulation Parameters ################################################### +################################################### +##BEGIN Technology Tool Preferences +################################################### + +drc_name = "calibre" +lvs_name = "calibre" +pex_name = "calibre" + +################################################### +##END Technology Tool Preferences +################################################### diff --git a/technology/scn3me_subm/__init__.py b/technology/scn3me_subm/__init__.py index 87b26056..6b08d0b9 100644 --- a/technology/scn3me_subm/__init__.py +++ b/technology/scn3me_subm/__init__.py @@ -35,9 +35,5 @@ except: DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech" os.environ["DRCLVS_HOME"] = DRCLVS_HOME -# try: -# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR")) -# except: -OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) -os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) +os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__)) diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index cc405c21..6fc68686 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -277,3 +277,15 @@ parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of dr ################################################### ##END Spice Simulation Parameters ################################################### + +################################################### +##BEGIN Technology Tool Preferences +################################################### + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" + +################################################### +##END Technology Tool Preferences +################################################### diff --git a/technology/scn4m_subm/__init__.py b/technology/scn4m_subm/__init__.py index c7a863f0..5fbd8c08 100644 --- a/technology/scn4m_subm/__init__.py +++ b/technology/scn4m_subm/__init__.py @@ -35,9 +35,5 @@ except: DRCLVS_HOME=OPENRAM_TECH+"/scn4m_subm/tech" os.environ["DRCLVS_HOME"] = DRCLVS_HOME -# try: -# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR")) -# except: -OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) -os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) +os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__)) diff --git a/technology/scn4m_subm/config.py b/technology/scn4m_subm/config.py new file mode 100644 index 00000000..ed604578 --- /dev/null +++ b/technology/scn4m_subm/config.py @@ -0,0 +1,7 @@ +process_corners = ["TT"] +supply_voltages = [5.0] +temperatures = [25] + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 8d466023..be3ab83c 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -301,3 +301,15 @@ parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of dr ################################################### ##END Spice Simulation Parameters ################################################### + +################################################### +##BEGIN Technology Tool Preferences +################################################### + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" + +################################################### +##END Technology Tool Preferences +################################################### From 0cdd3af1aa0c61db2ff750b035997ef59c640dad Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 29 Nov 2019 12:08:53 -0800 Subject: [PATCH 034/521] Change default nominal corners to false and enable in test config. --- compiler/example_configs/big_config_scn4m_subm.py | 4 +--- .../example_configs/example_config_1rw_1r_scn4m_subm.py | 5 +---- compiler/example_configs/example_config_1w_1r_scn4m_subm.py | 1 + compiler/example_configs/example_config_freepdk45.py | 1 + compiler/example_configs/example_config_scn4m_subm.py | 4 +--- compiler/example_configs/giant_config_scn4m_subm.py | 5 +---- compiler/example_configs/medium_config_scn4m_subm.py | 6 ++---- compiler/options.py | 2 +- compiler/tests/configs/config.py | 1 + compiler/tests/configs/config_back_end.py | 1 + compiler/tests/configs/config_front_end.py | 1 - 11 files changed, 11 insertions(+), 20 deletions(-) diff --git a/compiler/example_configs/big_config_scn4m_subm.py b/compiler/example_configs/big_config_scn4m_subm.py index 279fa04a..b90a9b1a 100644 --- a/compiler/example_configs/big_config_scn4m_subm.py +++ b/compiler/example_configs/big_config_scn4m_subm.py @@ -2,6 +2,7 @@ word_size = 32 num_words = 128 tech_name = "scn4m_subm" +nominal_corners_only = False process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] @@ -9,6 +10,3 @@ temperatures = [25] output_path = "temp" output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name) -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" diff --git a/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py b/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py index ecb03395..7f2e6059 100644 --- a/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py +++ b/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py @@ -6,6 +6,7 @@ num_r_ports = 1 num_w_ports = 0 tech_name = "scn4m_subm" +nominal_corners_only = False process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] @@ -17,7 +18,3 @@ output_path = "temp" output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size, num_words, tech_name) - -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" diff --git a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py index 4b6584d4..330d8d46 100644 --- a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py +++ b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py @@ -6,6 +6,7 @@ num_r_ports = 1 num_w_ports = 0 tech_name = "scn4m_subm" +nominal_corners_only = False process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] diff --git a/compiler/example_configs/example_config_freepdk45.py b/compiler/example_configs/example_config_freepdk45.py index eb5f6af3..f0d71d6d 100644 --- a/compiler/example_configs/example_config_freepdk45.py +++ b/compiler/example_configs/example_config_freepdk45.py @@ -2,6 +2,7 @@ word_size = 2 num_words = 16 tech_name = "freepdk45" +nominal_corners_only = False process_corners = ["TT"] supply_voltages = [1.0] temperatures = [25] diff --git a/compiler/example_configs/example_config_scn4m_subm.py b/compiler/example_configs/example_config_scn4m_subm.py index 500b4beb..71ef328b 100644 --- a/compiler/example_configs/example_config_scn4m_subm.py +++ b/compiler/example_configs/example_config_scn4m_subm.py @@ -2,6 +2,7 @@ word_size = 2 num_words = 16 tech_name = "scn4m_subm" +nominal_corners_only = False process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] @@ -14,6 +15,3 @@ output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name) -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" diff --git a/compiler/example_configs/giant_config_scn4m_subm.py b/compiler/example_configs/giant_config_scn4m_subm.py index e91455da..56751a9c 100644 --- a/compiler/example_configs/giant_config_scn4m_subm.py +++ b/compiler/example_configs/giant_config_scn4m_subm.py @@ -2,6 +2,7 @@ word_size = 64 num_words = 1024 tech_name = "scn4m_subm" +nominal_corners_only = False process_corners = ["TT"] supply_voltages = [ 5.0 ] temperatures = [ 25 ] @@ -10,7 +11,3 @@ output_path = "temp" output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name) - -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" diff --git a/compiler/example_configs/medium_config_scn4m_subm.py b/compiler/example_configs/medium_config_scn4m_subm.py index 7c063c97..ac4af8b4 100644 --- a/compiler/example_configs/medium_config_scn4m_subm.py +++ b/compiler/example_configs/medium_config_scn4m_subm.py @@ -2,8 +2,9 @@ word_size = 16 num_words = 256 tech_name = "scn4m_subm" +nominal_corners_only = False process_corners = ["TT"] -supply_voltages = [3.3] +supply_voltages = [5.0] temperatures = [25] output_path = "temp" @@ -11,6 +12,3 @@ output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name) -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" diff --git a/compiler/options.py b/compiler/options.py index 444730c1..fb8aab35 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -34,7 +34,7 @@ class options(optparse.Values): write_size = None # These will get initialized by the user or the tech file - nominal_corner_only = True + nominal_corner_only = False supply_voltages = "" temperatures = "" process_corners = "" diff --git a/compiler/tests/configs/config.py b/compiler/tests/configs/config.py index b876c07d..d19ae02e 100644 --- a/compiler/tests/configs/config.py +++ b/compiler/tests/configs/config.py @@ -11,6 +11,7 @@ num_words = 16 tech_name = OPTS.tech_name +nominal_corner_only = True route_supplies = True check_lvsdrc = True diff --git a/compiler/tests/configs/config_back_end.py b/compiler/tests/configs/config_back_end.py index 8f195e7a..3ba6492e 100644 --- a/compiler/tests/configs/config_back_end.py +++ b/compiler/tests/configs/config_back_end.py @@ -11,6 +11,7 @@ num_words = 16 tech_name = OPTS.tech_name +nominal_corner_only = True route_supplies = True check_lvsdrc = True inline_lvsdrc = True diff --git a/compiler/tests/configs/config_front_end.py b/compiler/tests/configs/config_front_end.py index 1ea88cd4..cf872ce6 100644 --- a/compiler/tests/configs/config_front_end.py +++ b/compiler/tests/configs/config_front_end.py @@ -11,4 +11,3 @@ num_words = 16 tech_name = OPTS.tech_name - From 2a912dab7a3debf2cc4666430e11b68057003dbd Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 29 Nov 2019 12:35:35 -0800 Subject: [PATCH 035/521] Remove unused config files --- compiler/tests/scn3me_subm/config.py | 22 ------------------ compiler/tests/scn3me_subm/config_back_end.py | 23 ------------------- .../tests/scn3me_subm/config_front_end.py | 21 ----------------- technology/freepdk45/config.py | 7 ------ technology/scn4m_subm/config.py | 7 ------ 5 files changed, 80 deletions(-) delete mode 100644 compiler/tests/scn3me_subm/config.py delete mode 100644 compiler/tests/scn3me_subm/config_back_end.py delete mode 100644 compiler/tests/scn3me_subm/config_front_end.py delete mode 100644 technology/freepdk45/config.py delete mode 100644 technology/scn4m_subm/config.py diff --git a/compiler/tests/scn3me_subm/config.py b/compiler/tests/scn3me_subm/config.py deleted file mode 100644 index 7b5b5e15..00000000 --- a/compiler/tests/scn3me_subm/config.py +++ /dev/null @@ -1,22 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -word_size = 1 -num_words = 16 - -tech_name = "scn3me_subm" -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] - -route_supplies = True -check_lvsdrc = True - -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" - diff --git a/compiler/tests/scn3me_subm/config_back_end.py b/compiler/tests/scn3me_subm/config_back_end.py deleted file mode 100644 index f9c23417..00000000 --- a/compiler/tests/scn3me_subm/config_back_end.py +++ /dev/null @@ -1,23 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -word_size = 1 -num_words = 16 - -tech_name = "scn3me_subm" -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] - -route_supplies = True -check_lvsdrc = True -inline_lvsdrc = True -analytical_delay = False - -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" diff --git a/compiler/tests/scn3me_subm/config_front_end.py b/compiler/tests/scn3me_subm/config_front_end.py deleted file mode 100644 index 40504a18..00000000 --- a/compiler/tests/scn3me_subm/config_front_end.py +++ /dev/null @@ -1,21 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -word_size = 1 -num_words = 16 - -tech_name = "scn3me_subm" -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] - -analytical_delay = False - -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" - diff --git a/technology/freepdk45/config.py b/technology/freepdk45/config.py deleted file mode 100644 index 6058bb64..00000000 --- a/technology/freepdk45/config.py +++ /dev/null @@ -1,7 +0,0 @@ -process_corners = ["TT"] -supply_voltages = [1.0] -temperatures = [25] - -drc_name = "calibre" -lvs_name = "calibre" -pex_name = "calibre" diff --git a/technology/scn4m_subm/config.py b/technology/scn4m_subm/config.py deleted file mode 100644 index ed604578..00000000 --- a/technology/scn4m_subm/config.py +++ /dev/null @@ -1,7 +0,0 @@ -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] - -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" From bedae873158d254bb4739aef9a583bb85686eea7 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 29 Nov 2019 13:31:44 -0800 Subject: [PATCH 036/521] Only use max/min and typical corner --- compiler/characterizer/lib.py | 48 +++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 07a753a7..3e50fe8f 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -66,22 +66,44 @@ class lib: self.supply_voltages = OPTS.supply_voltages self.process_corners = OPTS.process_corners - # Enumerate all possible corners + # Corner values + min_temperature = min(self.temperatures) + nom_temperature = tech.spice["nom_temperature"] + max_temperature = max(self.temperatures) + min_supply = min(self.supply_voltages) + nom_supply = tech.spice["nom_supply_voltage"] + max_supply = max(self.supply_voltages) + min_process = "FF" + nom_process = "TT" + max_process = "SS" + self.corners = [] self.lib_files = [] - for proc in self.process_corners: - for temp in self.temperatures: - for volt in self.supply_voltages: - self.corner_name = "{0}_{1}_{2}V_{3}C".format(self.sram.name, - proc, - volt, - temp) - self.corner_name = self.corner_name.replace(".","p") # Remove decimals - lib_name = self.out_dir+"{}.lib".format(self.corner_name) + + # Nominal corner + self.add_corner(nom_process, nom_supply, nom_temperature) + # Temperature corners + self.add_corner(nom_process, nom_supply, min_temperature) + self.add_corner(nom_process, nom_supply, max_temperature) + # Supply corners + self.add_corner(nom_process, min_supply, nom_temperature) + self.add_corner(nom_process, max_supply, nom_temperature) + # Process corners + self.add_corner(min_process, nom_supply, nom_temperature) + self.add_corner(max_process, nom_supply, nom_temperature) + + def add_corner(self, proc, volt, temp): + self.corner_name = "{0}_{1}_{2}V_{3}C".format(self.sram.name, + proc, + volt, + temp) + self.corner_name = self.corner_name.replace(".","p") # Remove decimals + lib_name = self.out_dir+"{}.lib".format(self.corner_name) + + # A corner is a tuple of PVT + self.corners.append((proc, volt, temp)) + self.lib_files.append(lib_name) - # A corner is a tuple of PVT - self.corners.append((proc, volt, temp)) - self.lib_files.append(lib_name) def characterize_corners(self): """ Characterize the list of corners. """ From 46c2cbd2d99749ae06f7a752fd53757e0211d5b3 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 29 Nov 2019 14:47:02 -0800 Subject: [PATCH 037/521] Check nominal_corner_only in new corner creation routine --- compiler/characterizer/lib.py | 20 +++++++++++--------- compiler/globals.py | 4 ++-- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 3e50fe8f..6baff201 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -82,15 +82,16 @@ class lib: # Nominal corner self.add_corner(nom_process, nom_supply, nom_temperature) - # Temperature corners - self.add_corner(nom_process, nom_supply, min_temperature) - self.add_corner(nom_process, nom_supply, max_temperature) - # Supply corners - self.add_corner(nom_process, min_supply, nom_temperature) - self.add_corner(nom_process, max_supply, nom_temperature) - # Process corners - self.add_corner(min_process, nom_supply, nom_temperature) - self.add_corner(max_process, nom_supply, nom_temperature) + if not OPTS.nominal_corner_only: + # Temperature corners + self.add_corner(nom_process, nom_supply, min_temperature) + self.add_corner(nom_process, nom_supply, max_temperature) + # Supply corners + self.add_corner(nom_process, min_supply, nom_temperature) + self.add_corner(nom_process, max_supply, nom_temperature) + # Process corners + self.add_corner(min_process, nom_supply, nom_temperature) + self.add_corner(max_process, nom_supply, nom_temperature) def add_corner(self, proc, volt, temp): self.corner_name = "{0}_{1}_{2}V_{3}C".format(self.sram.name, @@ -107,6 +108,7 @@ class lib: def characterize_corners(self): """ Characterize the list of corners. """ + debug.info(1,"Characterizing corners: " + str(self.corners)) for (self.corner,lib_name) in zip(self.corners,self.lib_files): debug.info(1,"Corner: " + str(self.corner)) (self.process, self.voltage, self.temperature) = self.corner diff --git a/compiler/globals.py b/compiler/globals.py index 3a8153bd..e9b77d66 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -581,5 +581,5 @@ def report_status(): debug.print_raw("Performing simulation-based characterization with {}".format(OPTS.spice_name)) if OPTS.trim_netlist: debug.print_raw("Trimming netlist to speed up characterization (trim_netlist=False to disable).") - - + if OPTS.nominal_corner_only: + debug.print_raw("Only characterizing nominal corner.") From 6ef1b6a4ec499db1d7da8af017aa4c36f8d2f771 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 29 Nov 2019 15:50:32 -0800 Subject: [PATCH 038/521] Blackbox option for DRC waivers --- compiler/options.py | 2 -- compiler/tests/01_library_drc_test.py | 5 +++++ technology/freepdk45/tech/tech.py | 2 ++ technology/scn4m_subm/tech/tech.py | 2 ++ 4 files changed, 9 insertions(+), 2 deletions(-) diff --git a/compiler/options.py b/compiler/options.py index fb8aab35..d891ebd9 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -86,8 +86,6 @@ class options(optparse.Values): check_lvsdrc = False # This determines whether LVS and DRC is checked for every submodule. inline_lvsdrc = False - # Treat the bitcell as a black box (no DRC, LVS, or extraction) - blackbox_bitcell = False # Remove noncritical memory cells for characterization speed-up trim_netlist = False # Run with extracted parasitics diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index cfeb4ab2..ad8671d2 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -42,6 +42,11 @@ def setup_files(): files = os.listdir(gds_dir) nametest = re.compile("\.gds$", re.IGNORECASE) gds_files = list(filter(nametest.search, files)) + import tech + if tech.blackbox_bitcell: + # Ignore DRC of all bitcells + nametest = re.compile("cell", re.IGNORECASE) + gds_files = list(filter(lambda v: not nametest.search(v), gds_files)) return (gds_dir, gds_files) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 14db2ea4..13e7ccff 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -344,6 +344,8 @@ drc_name = "calibre" lvs_name = "calibre" pex_name = "calibre" +blackbox_bitcell = False + ################################################### ##END Technology Tool Preferences ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index be3ab83c..2d1d5e15 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -310,6 +310,8 @@ drc_name = "magic" lvs_name = "netgen" pex_name = "magic" +blackbox_bitcell = False + ################################################### ##END Technology Tool Preferences ################################################### From 7b9e7ff35bdd89ad094419338b2c9c34d8a939f0 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Sat, 30 Nov 2019 12:48:25 -0800 Subject: [PATCH 039/521] Nominal corner only for sim tests. Netlist only for speed. --- compiler/tests/23_lib_sram_model_corners_test.py | 1 + compiler/tests/23_lib_sram_model_test.py | 1 + compiler/tests/23_lib_sram_prune_test.py | 1 + compiler/tests/23_lib_sram_test.py | 1 + 4 files changed, 4 insertions(+) diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 1e853fae..84de2b3f 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -20,6 +20,7 @@ class lib_model_corners_lib_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) + OPTS.nominal_corner_only = False OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 6043d83f..1ea8fc9e 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -20,6 +20,7 @@ class lib_sram_model_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) + OPTS.nominal_corner_only = False OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 9df647ce..e9c727c6 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -21,6 +21,7 @@ class lib_sram_prune_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False + OPTS.netlist_only = True OPTS.trim_netlist = True # This is a hack to reload the characterizer __init__ with the spice version diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 08bb5565..91f410c3 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -20,6 +20,7 @@ class lib_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.analytical_delay = False + OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version From 2ed34160172e77bd4c5a660508158f0e484fafa6 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Tue, 3 Dec 2019 18:29:38 +0000 Subject: [PATCH 040/521] Smalle dits to README and HINTS --- HINTS.md | 23 +++++++++++++++-------- README.md | 26 +++++++++++++++++--------- 2 files changed, 32 insertions(+), 17 deletions(-) diff --git a/HINTS.md b/HINTS.md index b12704e5..6f29c16b 100644 --- a/HINTS.md +++ b/HINTS.md @@ -37,7 +37,15 @@ to run Calibre or Magic+Netgen. To debug, you will need a layout viewer. I prefer to use Glade on my Mac, but you can also use Calibre, Magic, etc. -1. Calibre +1. Klayout + + You can view the designs in [Klayout](https://www.klayout.de/) with the configuration + file provided in the tech directories. For example, +``` + klayout temp.gds -l /home/vagrant/openram/technology/freepdk45/tf/FreePDK45.lyp +``` + +2. Calibre Start the Calibre DESIGNrev viewer in the temp directory and load your GDS file: ``` @@ -52,10 +60,9 @@ on my Mac, but you can also use Calibre, Magic, etc. In the viewer ">" opens the layout down a level. -2. Glade +3. Glade - You can view errors in Glade as well. I like this because it is on my laptop. - You can get it from: http://www.peardrop.co.uk/glade/ + You can view errors in [Glade](http://www.peardrop.co.uk/glade/) as well. To remote display over X windows, you need to disable OpenGL acceleration or use vnc or something. You can disable by adding this to your .bashrc in bash: @@ -82,16 +89,16 @@ ui().importCds("default", To load the errors, you simply do Verify->Import Calibre Errors select the .results file from Calibre. -3. Magic +4. Magic Magic is only supported in SCMOS. You will need to install the MOSIS SCMOS rules - and Magic from: http://opencircuitdesign.com/ + and [Magic](http://opencircuitdesign.com/) When running DRC or extraction, OpenRAM will load the GDS file, save the .ext/.mag files, and export an extracted netlist (.spice). -4. It is possible to use other viewers as well, such as: - * LayoutEditor http://www.layouteditor.net/ +5. It is possible to use other viewers as well, such as: + * [LayoutEditor](http://www.layouteditor.net/) # Example to output/input .gds layout files from/to Cadence diff --git a/README.md b/README.md index 05bb7772..f141b317 100644 --- a/README.md +++ b/README.md @@ -33,15 +33,6 @@ things that need to be fixed. # Basic Setup -## Docker Image - -We have a pre-configured Ubuntu [Docker](https://www.docker.com/) image -available that has all tools installed for the [SCMOS] process. It is -available at [docker hub](https://hub.docker.com/r/vlsida/openram-ubuntu). -Please see -[our README.md](https://github.com/VLSIDA/openram-docker-images/blob/master/README.md) -for information on how to use this docker image. - ## Dependencies The OpenRAM compiler has very few dependencies: @@ -88,6 +79,23 @@ You may get the entire [FreePDK45 PDK here][FreePDK45]. If you are using [SCMOS], you should install [Magic] and [Netgen]. We have included the most recent SCN4M_SUBM design rules from [Qflow]. +## Docker Image + +We have a pre-configured Ubuntu [Docker](https://www.docker.com/) image +available that has all tools installed for the [SCMOS] process. It is +available at [docker hub](https://hub.docker.com/r/vlsida/openram-ubuntu). +Please see +[our README.md](https://github.com/VLSIDA/openram-docker-images/blob/master/README.md) +for information on how to use this docker image. + +## Vagrant Image + +We have a pre-configured Ubuntu [Vagrant](https://www.vagrantup.com/) image +available that has all tools installed for the [SCMOS] process. +Please see +[our README.md](https://github.com/VLSIDA/openram-vagrant-image/blob/master/README.md) +for information on how to use this image. + # Basic Usage Once you have defined the environment, you can run OpenRAM from the command line From 0d359412410c5f2fd6c1fb33dd27a45a220fa2eb Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 3 Dec 2019 12:06:58 -0800 Subject: [PATCH 041/521] Fix missing dbUnit conversion in gdsMill --- compiler/gdsMill/gdsMill/gds2reader.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/gdsMill/gdsMill/gds2reader.py b/compiler/gdsMill/gdsMill/gds2reader.py index 7e519c36..f660fe3c 100644 --- a/compiler/gdsMill/gdsMill/gds2reader.py +++ b/compiler/gdsMill/gdsMill/gds2reader.py @@ -164,7 +164,7 @@ class Gds2reader: print("Mask: "+mask) elif(idBits==b'\x03\x05'): #this is also wrong b/c python doesn't natively have an 8 byte float userUnits=self.ieeeDoubleFromIbmData(record[2:10]) - dbUnits=self.ieeeDoubleFromIbmData + dbUnits=self.ieeeDoubleFromIbmData(record[10:18]) self.layoutObject.info["units"] = (userUnits,dbUnits) if(self.debugToTerminal==1): print("Units: 1 user unit="+str(userUnits)+" database units, 1 database unit="+str(dbUnits)+" meters.") From 69bb245f28eb5571889cd6a021fb24facd357b93 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 4 Dec 2019 16:12:53 -0800 Subject: [PATCH 042/521] Updates to gdsMill/tech layers Create active and poly contact types. Define standard cell boundary option. DataType and PurposeLayer are the same. Text must have type 0. Remove vector from vlsiLayout. More debug in reader. --- compiler/base/contact.py | 16 ++++---- compiler/base/design.py | 6 +-- compiler/base/geometry.py | 3 +- compiler/base/hierarchy_layout.py | 6 ++- compiler/base/pin_layout.py | 1 - compiler/bitcells/pbitcell.py | 8 ++-- compiler/gdsMill/gdsMill/gds2reader.py | 45 ++++++++++++++++++--- compiler/gdsMill/gdsMill/gds2writer.py | 24 ++++++------ compiler/gdsMill/gdsMill/gdsPrimitives.py | 9 ++--- compiler/gdsMill/gdsMill/vlsiLayout.py | 12 ++---- compiler/pgates/ptx.py | 8 ++-- technology/freepdk45/tech/tech.py | 44 +++++++++++++++------ technology/scn4m_subm/tech/tech.py | 48 ++++++++++++++++------- 13 files changed, 148 insertions(+), 82 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 30f6870b..fb8ea0e8 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -48,7 +48,8 @@ class contact(hierarchy_design.hierarchy_design): # Module does not have pins, but has empty pin list. self.pins = [] self.create_layout() - + self.add_boundary() + def create_layout(self): self.setup_layers() @@ -71,14 +72,11 @@ class contact(hierarchy_design.hierarchy_design): (first_layer, via_layer, second_layer) = self.layer_stack self.first_layer_name = first_layer - self.via_layer_name = via_layer - # Some technologies have a separate active - # contact from the poly contact - # We will use contact for DRC, but active_contact for output - if first_layer == "active" or second_layer == "active": - self.via_layer_name_expanded = "active_" + via_layer + # Contacts will have unique per first layer + if via_layer == "contact": + self.via_layer_name = first_layer + "_" + via_layer else: - self.via_layer_name_expanded = via_layer + self.via_layer_name = via_layer self.second_layer_name = second_layer def setup_layout_constants(self): @@ -144,7 +142,7 @@ class contact(hierarchy_design.hierarchy_design): for i in range(self.dimensions[1]): offset = self.via_layer_position + vector(0, self.contact_pitch * i) for j in range(self.dimensions[0]): - self.add_rect(layer=self.via_layer_name_expanded, + self.add_rect(layer=self.via_layer_name, offset=offset, width=self.contact_width, height=self.contact_width) diff --git a/compiler/base/design.py b/compiler/base/design.py index 33914358..c6385243 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -48,12 +48,12 @@ class design(hierarchy_design): self.m4_space = drc("metal4_to_metal4") self.active_width = drc("minwidth_active") self.active_space = drc("active_to_body_active") - self.contact_width = drc("minwidth_contact") + self.contact_width = drc("minwidth_active_contact") self.poly_to_active = drc("poly_to_active") self.poly_extend_active = drc("poly_extend_active") - self.poly_to_polycontact = drc("poly_to_polycontact") - self.contact_to_gate = drc("contact_to_gate") + self.poly_to_poly_contact = drc("poly_to_poly_contact") + self.active_contact_to_gate = drc("active_contact_to_gate") self.well_enclose_active = drc("well_enclosure_active") self.implant_enclose_active = drc("implant_enclosure_active") self.implant_space = drc("implant_to_implant") diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index cbc1d268..e5c86546 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -193,7 +193,7 @@ class instance(geometry): blockages = [] blockages = self.mod.gds.getBlockages(lpp) for b in blockages: - new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) + new_blockages.append(self.transform_coords(vector(b),self.offset, mirr, angle)) else: blockages = self.mod.get_blockages(lpp) for b in blockages: @@ -327,7 +327,6 @@ class label(geometry): debug.info(4, "writing label (" + str(self.layerNumber) + "): " + self.text) new_layout.addText(text=self.text, layerNumber=self.layerNumber, - purposeNumber=self.layerPurpose, offsetInMicrons=self.offset, magnification=self.zoom, rotate=None) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 000e16ee..b6ca8f33 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -939,7 +939,11 @@ class layout(): def add_boundary(self, offset=vector(0,0)): """ Add boundary for debugging dimensions """ - self.add_rect(layer="boundary", + if "stdc" in techlayer.keys(): + boundary_layer = "stdc" + else: + boundary_layer = "boundary" + self.add_rect(layer=boundary_layer, offset=offset, height=self.height, width=self.width) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index f7427a9c..ea114ac6 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -344,7 +344,6 @@ class pin_layout: # imported into Magic. newLayout.addText(text=self.name, layerNumber=layer_num, - purposeNumber=purpose, offsetInMicrons=self.center(), magnification=GDS["zoom"], rotate=None) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index bbfdf942..0e0e1bf7 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -243,7 +243,7 @@ class pbitcell(bitcell_base.bitcell_base): (self.inverter_nmos.active_contact.height - self.inverter_nmos.active_height) self.inverter_gap = max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + self.poly_to_polycontact + 2 * contact.poly.width \ + + self.poly_to_poly_contact + 2 * contact.poly.width \ + self.m1_space + inverter_pmos_contact_extension self.cross_couple_lower_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ @@ -254,7 +254,7 @@ class pbitcell(bitcell_base.bitcell_base): + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + self.poly_to_polycontact \ + + self.poly_to_poly_contact \ + 1.5 * contact.poly.width # spacing between wordlines (and gnd) @@ -926,14 +926,14 @@ class pbitcell(bitcell_base.bitcell_base): """ # add poly to metal1 contacts for gates of the inverters left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x \ - - self.poly_to_polycontact - 0.5*contact.poly.width, + - self.poly_to_poly_contact - 0.5*contact.poly.width, self.cross_couple_upper_ypos) self.add_via_center(layers=("poly", "contact", "metal1"), offset=left_storage_contact, directions=("H", "H")) right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \ - + self.poly_to_polycontact + 0.5*contact.poly.width, + + self.poly_to_poly_contact + 0.5*contact.poly.width, self.cross_couple_upper_ypos) self.add_via_center(layers=("poly", "contact", "metal1"), offset=right_storage_contact, diff --git a/compiler/gdsMill/gdsMill/gds2reader.py b/compiler/gdsMill/gdsMill/gds2reader.py index f660fe3c..351df6a4 100644 --- a/compiler/gdsMill/gdsMill/gds2reader.py +++ b/compiler/gdsMill/gdsMill/gds2reader.py @@ -175,6 +175,8 @@ class Gds2reader: def readBoundary(self): ##reads in a boundary type structure = a filled polygon + if(self.debugToTerminal==1): + print("\t\t\tBeginBoundary") thisBoundary=GdsBoundary() while 1: record = self.readNextRecord() @@ -201,11 +203,6 @@ class Gds2reader: thisBoundary.purposeLayer=purposeLayer if(self.debugToTerminal==1): print("\t\tPurpose Layer: "+str(purposeLayer)) - elif(idBits==b'\x0E\x02'): #DataType - dataType = struct.unpack(">h",record[2:4])[0] - thisBoundary.dataType=dataType - if(self.debugToTerminal==1): - print("\t\t\tData Type: "+str(dataType)) elif(idBits==b'\x10\x03'): #XY Data Points numDataPoints = len(record)-2 #packed as XY coordinates 4 bytes each thisBoundary.coordinates=[] @@ -216,10 +213,15 @@ class Gds2reader: if(self.debugToTerminal==1): print("\t\t\tXY Point: "+str(x)+","+str(y)) elif(idBits==b'\x11\x00'): #End Of Element + if(self.debugToTerminal==1): + print("\t\t\tEndBoundary") break; return thisBoundary def readPath(self): #reads in a path structure + if(self.debugToTerminal==1): + print("\t\t\tBeginPath") + thisPath=GdsPath() while 1: record = self.readNextRecord() @@ -266,10 +268,15 @@ class Gds2reader: if(self.debugToTerminal==1): print("\t\t\tXY Point: "+str(x)+","+str(y)) elif(idBits==b'\x11\x00'): #End Of Element + if(self.debugToTerminal==1): + print("\t\t\tEndPath") break; return thisPath def readSref(self): #reads in a reference to another structure + if(self.debugToTerminal==1): + print("\t\t\tBeginSref") + thisSref=GdsSref() while 1: record = self.readNextRecord() @@ -317,10 +324,15 @@ class Gds2reader: if(self.debugToTerminal==1): print("\t\t\tXY Point: "+str(x)+","+str(y)) elif(idBits==b'\x11\x00'): #End Of Element + if(self.debugToTerminal==1): + print("\t\t\tEndSref") break; return thisSref def readAref(self): #an array of references + if(self.debugToTerminal==1): + print("\t\t\tBeginAref") + thisAref = GdsAref() while 1: record = self.readNextRecord() @@ -372,11 +384,15 @@ class Gds2reader: print("\t\t\t\tArray Width: "+str(rightMostX-topLeftX)) print("\t\t\t\tArray Height: "+str(topLeftY-bottomMostY)) elif(idBits==b'\x11\x00'): #End Of Element + if(self.debugToTerminal==1): + print("\t\t\tEndAref") break; return thisAref def readText(self): - ##reads in a text structure + if(self.debugToTerminal==1): + print("\t\t\tBeginText") + thisText=GdsText() while 1: record = self.readNextRecord() @@ -472,10 +488,15 @@ class Gds2reader: if(self.debugToTerminal==1): print("\t\t\tText String: "+textString) elif(idBits==b'\x11\x00'): #End Of Element + if(self.debugToTerminal==1): + print("\t\t\tEndText") break; return thisText def readNode(self): + if(self.debugToTerminal==1): + print("\t\t\tBeginNode") + ##reads in a node type structure = an electrical net thisNode = GdsNode() while 1: @@ -513,10 +534,15 @@ class Gds2reader: if(self.debugToTerminal==1): print("\t\t\tXY Point: "+str(x)+","+str(y)) elif(idBits==b'\x11\x00'): #End Of Element + if(self.debugToTerminal==1): + print("\t\t\tEndNode") break; return thisNode def readBox(self): + if(self.debugToTerminal==1): + print("\t\t\tBeginBox") + ##reads in a gds BOX structure thisBox = GdsBox() while 1: @@ -559,6 +585,8 @@ class Gds2reader: if(self.debugToTerminal==1): print("\t\t\tXY Point: "+str(x)+","+str(y)) elif(idBits==b'\x11\x00'): #End Of Element + if(self.debugToTerminal==1): + print("\t\t\tEndBox") break; return thisBox @@ -566,6 +594,7 @@ class Gds2reader: thisStructure = GdsStructure() record = self.readNextRecord() idBits = record[0:2] + # Begin structure if(idBits==b'\x05\x02' and len(record)==26): createYear = struct.unpack(">h",record[2:4])[0] createMonth = struct.unpack(">h",record[4:6])[0] @@ -581,6 +610,10 @@ class Gds2reader: modSecond = struct.unpack(">h",record[24:26])[0] thisStructure.createDate=(createYear,createMonth,createDay,createHour,createMinute,createSecond) thisStructure.modDate=(modYear,modMonth,modDay,modHour,modMinute,modSecond) + if(self.debugToTerminal==1): + print("Date Created:"+str(createYear)+","+str(createMonth)+","+str(createDay)+\ + ","+str(createHour)+","+str(createMinute)+","+str(createSecond)) + print("Date Modified:"+str(modYear)+","+str(modMonth)+","+str(modDay)+","+str(modHour)+","+str(modMinute)+","+str(modSecond)) else: #means we have hit the last structure, so return the record #to whoever called us to do something with it diff --git a/compiler/gdsMill/gdsMill/gds2writer.py b/compiler/gdsMill/gdsMill/gds2writer.py index 402416cd..3a319324 100644 --- a/compiler/gdsMill/gdsMill/gds2writer.py +++ b/compiler/gdsMill/gdsMill/gds2writer.py @@ -187,27 +187,25 @@ class Gds2writer: idBits=b'\x08\x00' #record Type self.writeRecord(idBits) if(thisBoundary.elementFlags!=""): - idBits=b'\x26\x01' #ELFLAGS + idBits=b'\x26\x01' # ELFLAGS elementFlags = struct.pack(">h",thisBoundary.elementFlags) self.writeRecord(idBits+elementFlags) if(thisBoundary.plex!=""): - idBits=b'\x2F\x03' #PLEX + idBits=b'\x2F\x03' # PLEX plex = struct.pack(">i",thisBoundary.plex) self.writeRecord(idBits+plex) if(thisBoundary.drawingLayer!=""): - idBits=b'\x0D\x02' #drawig layer + idBits=b'\x0D\x02' # drawing layer drawingLayer = struct.pack(">h",thisBoundary.drawingLayer) self.writeRecord(idBits+drawingLayer) - if(thisBoundary.purposeLayer): - idBits=b'\x16\x02' #purpose layer - purposeLayer = struct.pack(">h",thisBoundary.purposeLayer) - self.writeRecord(idBits+purposeLayer) - if(thisBoundary.dataType!=""): - idBits=b'\x0E\x02'#DataType - dataType = struct.pack(">h",thisBoundary.dataType) + if(thisBoundary.purposeLayer!=""): + idBits=b'\x0E\x02' # DataType + if type(thisBoundary.purposeLayer)!=int: + import pdb; pdb.set_trace() + dataType = struct.pack(">h",thisBoundary.purposeLayer) self.writeRecord(idBits+dataType) if(thisBoundary.coordinates!=""): - idBits=b'\x10\x03' #XY Data Points + idBits=b'\x10\x03' # XY Data Points coordinateRecord = idBits for coordinate in thisBoundary.coordinates: x=struct.pack(">i",int(coordinate[0])) @@ -377,9 +375,9 @@ class Gds2writer: idBits=b'\x0D\x02' #drawing layer drawingLayer = struct.pack(">h",thisText.drawingLayer) self.writeRecord(idBits+drawingLayer) - #if(thisText.purposeLayer): + # TextType is always a 0 per GDS specification idBits=b'\x16\x02' #purpose layer - purposeLayer = struct.pack(">h",thisText.purposeLayer) + purposeLayer = struct.pack(">h",0) self.writeRecord(idBits+purposeLayer) if(thisText.transFlags != ""): idBits=b'\x1A\x01' diff --git a/compiler/gdsMill/gdsMill/gdsPrimitives.py b/compiler/gdsMill/gdsMill/gdsPrimitives.py index dc43fea6..09bd85b4 100644 --- a/compiler/gdsMill/gdsMill/gdsPrimitives.py +++ b/compiler/gdsMill/gdsMill/gdsPrimitives.py @@ -21,8 +21,7 @@ class GdsBoundary: self.elementFlags="" self.plex="" self.drawingLayer="" - self.purposeLayer = None - self.dataType="" + self.purposeLayer=0 self.coordinates="" class GdsPath: @@ -31,7 +30,7 @@ class GdsPath: self.elementFlags="" self.plex="" self.drawingLayer="" - self.purposeLayer = None + self.purposeLayer=0 self.pathType="" self.pathWidth="" self.coordinates="" @@ -140,7 +139,7 @@ class GdsText: self.elementFlags="" self.plex="" self.drawingLayer="" - self.purposeLayer = None + self.purposeLayer=0 self.transFlags=[0,0,0] self.magFactor="" self.rotateAngle="" @@ -165,6 +164,6 @@ class GdsBox: self.elementFlags="" self.plex="" self.drawingLayer="" - self.purposeLayer = None + self.purposeLayer=0 self.boxValue="" self.coordinates="" diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index eec1870c..412a430c 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -2,7 +2,6 @@ from .gdsPrimitives import * from datetime import * #from mpmath import matrix #from numpy import matrix -from vector import vector import numpy as np #import gdsPrimitives import debug @@ -358,7 +357,7 @@ class VlsiLayout: #add the sref to the root structure self.structures[self.rootStructureName].srefs.append(layoutToAddSref) - def addBox(self,layerNumber=0, purposeNumber=None, offsetInMicrons=(0,0), width=1.0, height=1.0,center=False): + def addBox(self,layerNumber=0, purposeNumber=0, offsetInMicrons=(0,0), width=1.0, height=1.0,center=False): """ Method to add a box to a layout """ @@ -383,13 +382,12 @@ class VlsiLayout: boundaryToAdd = GdsBoundary() boundaryToAdd.drawingLayer = layerNumber - boundaryToAdd.dataType = 0 boundaryToAdd.coordinates = coordinates boundaryToAdd.purposeLayer = purposeNumber #add the sref to the root structure self.structures[self.rootStructureName].boundaries.append(boundaryToAdd) - def addPath(self, layerNumber=0, purposeNumber=None, coordinates=[(0,0)], width=1.0): + def addPath(self, layerNumber=0, purposeNumber=0, coordinates=[(0,0)], width=1.0): """ Method to add a path to a layout """ @@ -408,12 +406,10 @@ class VlsiLayout: #add the sref to the root structure self.structures[self.rootStructureName].paths.append(pathToAdd) - def addText(self, text, layerNumber=0, purposeNumber=None, offsetInMicrons=(0,0), magnification=0.1, rotate = None): + def addText(self, text, layerNumber=0, offsetInMicrons=(0,0), magnification=0.1, rotate = None): offsetInLayoutUnits = (self.userUnits(offsetInMicrons[0]),self.userUnits(offsetInMicrons[1])) textToAdd = GdsText() textToAdd.drawingLayer = layerNumber - textToAdd.purposeLayer = purposeNumber - textToAdd.dataType = 0 textToAdd.coordinates = [offsetInLayoutUnits] textToAdd.transFlags = [0,0,0] textToAdd.textString = self.padText(text) @@ -757,7 +753,7 @@ class VlsiLayout: for boundary in shapes: vectors = [] for i in range(0, len(boundary), 2): - vectors.append(vector(boundary[i], boundary[i+1])) + vectors.append((boundary[i], boundary[i+1])) blockages.append(vectors) return blockages diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index f3180840..33098e7c 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -124,18 +124,18 @@ class ptx(design.design): # The contacted poly pitch (or uncontacted in an odd technology) - self.poly_pitch = max(2 * self.contact_to_gate + self.contact_width + self.poly_width, + self.poly_pitch = max(2 * self.active_contact_to_gate + self.contact_width + self.poly_width, self.poly_space) # The contacted poly pitch (or uncontacted in an odd technology) - self.contact_pitch = 2 * self.contact_to_gate + self.contact_width + self.poly_width + self.contact_pitch = 2 * self.active_contact_to_gate + self.contact_width + self.poly_width # The enclosure of an active contact. Not sure about second term. - active_enclose_contact = max(drc("active_enclosure_contact"), + active_enclose_contact = max(drc("active_enclosure_active_contact"), (self.active_width - self.contact_width) / 2) # This is the distance from the edge of poly to the contacted end of active - self.end_to_poly = active_enclose_contact + self.contact_width + self.contact_to_gate + self.end_to_poly = active_enclose_contact + self.contact_width + self.active_contact_to_gate # Active width is determined by enclosure on both ends and contacted pitch, diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 13e7ccff..16c2b393 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -44,9 +44,8 @@ layer["vtg"] = (6, 0) layer["vth"] = (7, 0) layer["thkox"] = (8, 0) layer["poly"] = (9, 0) -layer["contact"] = (10, 0) layer["active_contact"] = (10, 0) -layer["poly_contact"] = None +layer["poly_contact"] = (10, 0) layer["metal1"] = (11, 0) layer["via1"] = (12, 0) layer["metal2"] = (13, 0) @@ -117,7 +116,7 @@ drc["poly_to_poly"] = 0.14 # POLY.3 Minimum poly extension beyond active drc["poly_extend_active"] = 0.055 # Not a rule -drc["poly_to_polycontact"] = 0.075 +drc["poly_to_poly_contact"] = 0.075 # POLY.4 Minimum enclosure of active around gate drc["active_enclosure_gate"] = 0.07 # POLY.5 Minimum spacing of field poly to active @@ -154,30 +153,51 @@ drc["implant_to_implant"] = 0.045 drc["minwidth_implant"] = 0.045 # CONTACT.1 Minimum width of contact -drc["minwidth_contact"] = 0.065 +drc["minwidth_active_contact"] = 0.065 # CONTACT.2 Minimum spacing of contact -drc["contact_to_contact"] = 0.075 +drc["active_contact_to_active_contact"] = 0.075 # CONTACT.4 Minimum enclosure of active around contact -drc["active_enclosure_contact"] = 0.005 +drc["active_enclosure_active_contact"] = 0.005 +# Reserved for asymmetric enclosures +drc["active_extend_active_contact"] = 0.005 +# CONTACT.5 Minimum enclosure of poly around contact +drc["poly_enclosure_active_contact"] = 0.005 +# Reserved for asymmetric enclosures +drc["poly_extend_active_contact"] = 0.005 +# CONTACT.6 Minimum spacing of contact and gate +drc["active_contact_to_gate"] = 0.0375 #changed from 0.035 +# CONTACT.7 Minimum spacing of contact and poly +drc["active_contact_to_poly"] = 0.090 + +# CONTACT.1 Minimum width of contact +drc["minwidth_poly_contact"] = 0.065 +# CONTACT.2 Minimum spacing of contact +drc["poly_contact_to_poly_contact"] = 0.075 +# CONTACT.4 Minimum enclosure of active around contact +drc["active_enclosure_poly_contact"] = 0.005 # Reserved for asymmetric enclosures drc["active_extend_contact"] = 0.005 # CONTACT.5 Minimum enclosure of poly around contact -drc["poly_enclosure_contact"] = 0.005 +drc["poly_enclosure_poly_contact"] = 0.005 # Reserved for asymmetric enclosures -drc["poly_extend_contact"] = 0.005 +drc["poly_extend_poly_contact"] = 0.005 # CONTACT.6 Minimum spacing of contact and gate -drc["contact_to_gate"] = 0.0375 #changed from 0.035 +drc["poly_contact_to_gate"] = 0.0375 #changed from 0.035 # CONTACT.7 Minimum spacing of contact and poly -drc["contact_to_poly"] = 0.090 +drc["poly_contact_to_poly"] = 0.090 # METAL1.1 Minimum width of metal1 drc["minwidth_metal1"] = 0.065 # METAL1.2 Minimum spacing of metal1 drc["metal1_to_metal1"] = 0.065 # METAL1.3 Minimum enclosure around contact on two opposite sides -drc["metal1_enclosure_contact"] = 0 +drc["metal1_enclosure_active_contact"] = 0 # Reserved for asymmetric enclosures -drc["metal1_extend_contact"] = 0.035 +drc["metal1_extend_active_contact"] = 0.035 +# METAL1.3 Minimum enclosure around contact on two opposite sides +drc["metal1_enclosure_poly_contact"] = 0 +# Reserved for asymmetric enclosures +drc["metal1_extend_poly_contact"] = 0.035 # METAL1.4 inimum enclosure around via1 on two opposite sides drc["metal1_extend_via1"] = 0.035 # Reserved for asymmetric enclosures diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 2d1d5e15..deaab30c 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -43,9 +43,8 @@ layer["active"] = (43, 0) layer["pimplant"] = (44, 0) layer["nimplant"] = (45, 0) layer["poly"] = (46, 0) -layer["poly_contact"] = None -layer["contact"] = (47, 0) layer["active_contact"] = (48, 0) +layer["poly_contact"] = (47, 0) layer["metal1"] = (49, 0) layer["via1"] = (50, 0) layer["metal2"] = (51, 0) @@ -105,7 +104,7 @@ drc["poly_to_poly"] = 3*_lambda_ # 3.3 Minimum gate extension of active drc["poly_extend_active"] = 2*_lambda_ # 5.5.b Minimum spacing between poly contact and other poly (alternative rules) -drc["poly_to_polycontact"] = 4*_lambda_ +drc["poly_to_poly_contact"] = 4*_lambda_ # ?? drc["active_enclosure_gate"] = 0.0 # 3.5 Minimum field poly to active @@ -142,30 +141,51 @@ drc["implant_to_implant"] = 0 drc["minwidth_implant"] = 0 # 6.1 Exact contact size -drc["minwidth_contact"] = 2*_lambda_ +drc["minwidth_active_contact"] = 2*_lambda_ # 5.3 Minimum contact spacing -drc["contact_to_contact"] = 3*_lambda_ +drc["active_contact_to_active_contact"] = 3*_lambda_ # 6.2.b Minimum active overlap -drc["active_enclosure_contact"] = _lambda_ +drc["active_enclosure_active_contact"] = _lambda_ # Reserved for asymmetric enclosure -drc["active_extend_contact"] = _lambda_ +drc["active_extend_active_contact"] = _lambda_ # 5.2.b Minimum poly overlap -drc["poly_enclosure_contact"] = _lambda_ +drc["poly_enclosure_active_contact"] = _lambda_ # Reserved for asymmetric enclosures -drc["poly_extend_contact"] = _lambda_ +drc["poly_extend_active_contact"] = _lambda_ # Reserved for other technologies -drc["contact_to_gate"] = 2*_lambda_ +drc["active_contact_to_gate"] = 2*_lambda_ # 5.4 Minimum spacing to gate of transistor -drc["contact_to_poly"] = 2*_lambda_ - +drc["active_contact_to_poly"] = 2*_lambda_ + +# 6.1 Exact contact size +drc["minwidth_poly_contact"] = 2*_lambda_ +# 5.3 Minimum contact spacing +drc["poly_contact_to_poly_contact"] = 3*_lambda_ +# 6.2.b Minimum active overlap +drc["active_enclosure_poly_contact"] = _lambda_ +# Reserved for asymmetric enclosure +drc["active_extend_poly_contact"] = _lambda_ +# 5.2.b Minimum poly overlap +drc["poly_enclosure_poly_contact"] = _lambda_ +# Reserved for asymmetric enclosures +drc["poly_extend_poly_contact"] = _lambda_ +# Reserved for other technologies +drc["poly_contact_to_gate"] = 2*_lambda_ +# 5.4 Minimum spacing to gate of transistor +drc["poly_contact_to_poly"] = 2*_lambda_ + # 7.1 Minimum width drc["minwidth_metal1"] = 3*_lambda_ # 7.2 Minimum spacing drc["metal1_to_metal1"] = 3*_lambda_ # 7.3 Minimum overlap of any contact -drc["metal1_enclosure_contact"] = _lambda_ +drc["metal1_enclosure_active_contact"] = _lambda_ # Reserved for asymmetric enclosure -drc["metal1_extend_contact"] = _lambda_ +drc["metal1_extend_active_contact"] = _lambda_ +# 7.3 Minimum overlap of any contact +drc["metal1_enclosure_poly_contact"] = _lambda_ +# Reserved for asymmetric enclosure +drc["metal1_extend_poly_contact"] = _lambda_ # 8.3 Minimum overlap by metal1 drc["metal1_enclosure_via1"] = _lambda_ # Reserve for asymmetric enclosures From d519c00aa1ada260ff30bebace856a79b03d4914 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Thu, 5 Dec 2019 01:06:31 +0000 Subject: [PATCH 043/521] Fix contact order in test --- compiler/tests/03_wire_test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 2e2db319..74d5ae1e 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -42,7 +42,7 @@ class wire_test(openram_test): min_space = 2 * (tech.drc["minwidth_poly"] + tech.drc["minwidth_metal1"]) - layer_stack = ("metal1", "contact", "poly") + layer_stack = ("poly", "contact", "metal1") old_position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], From 8f473b26a978c42d88258e112a69dca4e1467df8 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Thu, 5 Dec 2019 01:14:06 +0000 Subject: [PATCH 044/521] Add replica bitcell test for 1 port --- .../tests/05_replica_bitcell_array_test.py | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 compiler/tests/05_replica_bitcell_array_test.py diff --git a/compiler/tests/05_replica_bitcell_array_test.py b/compiler/tests/05_replica_bitcell_array_test.py new file mode 100644 index 00000000..d229b99c --- /dev/null +++ b/compiler/tests/05_replica_bitcell_array_test.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class replica_bitcell_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + + factory.reset() + debug.info(2, "Testing 4x4 array for bitcell") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 7397f110c5da825131f5c75152be706e43c5324e Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Thu, 5 Dec 2019 23:14:25 +0000 Subject: [PATCH 045/521] Add bbox for special DRC rule boundary --- compiler/base/contact.py | 1 - compiler/base/hierarchy_layout.py | 53 +++++++++++++++++++++++---- compiler/bitcells/dummy_pbitcell.py | 1 + compiler/bitcells/replica_pbitcell.py | 3 +- compiler/pgates/ptx.py | 10 ++++- technology/freepdk45/tech/tech.py | 8 ---- technology/scn4m_subm/tech/tech.py | 8 ---- 7 files changed, 57 insertions(+), 27 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index fb8ea0e8..e363a2fa 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -48,7 +48,6 @@ class contact(hierarchy_design.hierarchy_design): # Module does not have pins, but has empty pin list. self.pins = [] self.create_layout() - self.add_boundary() def create_layout(self): diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index b6ca8f33..7dcb62f9 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -32,6 +32,7 @@ class layout(): self.name = name self.width = None self.height = None + self.boundary = None self.insts = [] # Holds module/cell layout instances self.objs = [] # Holds all other objects (labels, geometries, etc) self.pin_map = {} # Holds name->pin_layout map for all pins @@ -80,7 +81,10 @@ class layout(): lowesty2 = min(inst.by() for inst in self.insts) else: lowestx2=lowesty2=None - if lowestx1==None: + + if lowestx1==None and lowestx2==None: + return None + elif lowestx1==None: return vector(lowestx2,lowesty2) elif lowestx2==None: return vector(lowestx1,lowesty1) @@ -101,7 +105,9 @@ class layout(): highesty2 = max(inst.uy() for inst in self.insts) else: highestx2=highesty2=None - if highestx1==None: + if highestx1==None and highestx2==None: + return None + elif highestx1==None: return vector(highestx2,highesty2) elif highestx2==None: return vector(highestx1,highesty1) @@ -500,6 +506,33 @@ class layout(): for pin_name in self.pin_map.keys(): for pin in self.pin_map[pin_name]: pin.gds_write_file(gds_layout) + + # If it's not a premade cell + # and we didn't add our own boundary, + # we should add a boundary just for DRC in some technologies + if not self.is_library_cell and not self.boundary: + # If there is a boundary layer, and we didn't create one, add one. + if "stdc" in techlayer.keys(): + boundary_layer = "stdc" + elif "boundary" in techlayer.keys(): + boundary_layer = "boundary" + else: + boundary_layer = None + + if boundary_layer: + boundary = [self.find_lowest_coords(), self.find_highest_coords()] + height = boundary[1][1] - boundary[0][1] + width = boundary[1][0] - boundary[0][0] + (layer_number, layer_purpose) = techlayer[boundary_layer] + gds_layout.addBox(layerNumber=layer_number, + purposeNumber=layer_purpose, + offsetInMicrons=boundary[0], + width=width, + height=height, + center=False) + debug.info(0, "Adding {0} boundary {1}".format(self.name, boundary)) + + self.visited.append(self.name) def gds_write(self, gds_name): @@ -937,16 +970,22 @@ class layout(): """ self.create_channel_route(netlist, offset, layer_stack, vertical=False) - def add_boundary(self, offset=vector(0,0)): + def add_boundary(self, ll=vector(0,0), ur=None): """ Add boundary for debugging dimensions """ if "stdc" in techlayer.keys(): boundary_layer = "stdc" else: boundary_layer = "boundary" - self.add_rect(layer=boundary_layer, - offset=offset, - height=self.height, - width=self.width) + if ur == None: + self.boundary = self.add_rect(layer=boundary_layer, + offset=ll, + height=self.height, + width=self.width) + else: + self.boundary = self.add_rect(layer=boundary_layer, + offset=ll, + height=ur.y-ll.y, + width=ur.x-ll.x) def add_enclosure(self, insts, layer="nwell"): """ Add a layer that surrounds the given instances. Useful diff --git a/compiler/bitcells/dummy_pbitcell.py b/compiler/bitcells/dummy_pbitcell.py index ee15e03c..ead3d7f3 100644 --- a/compiler/bitcells/dummy_pbitcell.py +++ b/compiler/bitcells/dummy_pbitcell.py @@ -30,6 +30,7 @@ class dummy_pbitcell(design.design): self.create_netlist() self.create_layout() + self.add_boundary() def create_netlist(self): self.add_pins() diff --git a/compiler/bitcells/replica_pbitcell.py b/compiler/bitcells/replica_pbitcell.py index 4fcfb4c5..5a588c1e 100644 --- a/compiler/bitcells/replica_pbitcell.py +++ b/compiler/bitcells/replica_pbitcell.py @@ -30,6 +30,7 @@ class replica_pbitcell(design.design): self.create_netlist() self.create_layout() + self.add_boundary() def create_netlist(self): self.add_pins() @@ -84,4 +85,4 @@ class replica_pbitcell(design.design): self.copy_layout_pin(self.prbc_inst, "wl{}".format(port)) self.copy_layout_pin(self.prbc_inst, "vdd") self.copy_layout_pin(self.prbc_inst, "gnd") - \ No newline at end of file + diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 33098e7c..3a7311ae 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -58,7 +58,14 @@ class ptx(design.design): # We must always create ptx layout for pbitcell # some transistor sizes in other netlist depend on pbitcell self.create_layout() - + + ll = self.find_lowest_coords() + ur = self.find_highest_coords() + self.add_boundary(ll, ur) + + # (0,0) will be the corner ofthe active area (not the larger well) + self.translate_all(self.active_offset) + def create_layout(self): """Calls all functions related to the generation of the layout""" self.setup_layout_constants() @@ -66,7 +73,6 @@ class ptx(design.design): self.add_well_implant() self.add_poly() self.add_active_contacts() - self.translate_all(self.active_offset) # for run-time, we won't check every transitor DRC independently # but this may be uncommented for debug purposes diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 16c2b393..31c712ec 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -160,10 +160,6 @@ drc["active_contact_to_active_contact"] = 0.075 drc["active_enclosure_active_contact"] = 0.005 # Reserved for asymmetric enclosures drc["active_extend_active_contact"] = 0.005 -# CONTACT.5 Minimum enclosure of poly around contact -drc["poly_enclosure_active_contact"] = 0.005 -# Reserved for asymmetric enclosures -drc["poly_extend_active_contact"] = 0.005 # CONTACT.6 Minimum spacing of contact and gate drc["active_contact_to_gate"] = 0.0375 #changed from 0.035 # CONTACT.7 Minimum spacing of contact and poly @@ -171,10 +167,6 @@ drc["active_contact_to_poly"] = 0.090 # CONTACT.1 Minimum width of contact drc["minwidth_poly_contact"] = 0.065 -# CONTACT.2 Minimum spacing of contact -drc["poly_contact_to_poly_contact"] = 0.075 -# CONTACT.4 Minimum enclosure of active around contact -drc["active_enclosure_poly_contact"] = 0.005 # Reserved for asymmetric enclosures drc["active_extend_contact"] = 0.005 # CONTACT.5 Minimum enclosure of poly around contact diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index deaab30c..8e189efd 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -148,10 +148,6 @@ drc["active_contact_to_active_contact"] = 3*_lambda_ drc["active_enclosure_active_contact"] = _lambda_ # Reserved for asymmetric enclosure drc["active_extend_active_contact"] = _lambda_ -# 5.2.b Minimum poly overlap -drc["poly_enclosure_active_contact"] = _lambda_ -# Reserved for asymmetric enclosures -drc["poly_extend_active_contact"] = _lambda_ # Reserved for other technologies drc["active_contact_to_gate"] = 2*_lambda_ # 5.4 Minimum spacing to gate of transistor @@ -161,10 +157,6 @@ drc["active_contact_to_poly"] = 2*_lambda_ drc["minwidth_poly_contact"] = 2*_lambda_ # 5.3 Minimum contact spacing drc["poly_contact_to_poly_contact"] = 3*_lambda_ -# 6.2.b Minimum active overlap -drc["active_enclosure_poly_contact"] = _lambda_ -# Reserved for asymmetric enclosure -drc["active_extend_poly_contact"] = _lambda_ # 5.2.b Minimum poly overlap drc["poly_enclosure_poly_contact"] = _lambda_ # Reserved for asymmetric enclosures From 3deeaf7164703a92915c30413c18873153986da4 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Thu, 5 Dec 2019 23:33:23 +0000 Subject: [PATCH 046/521] Decrease verbosity of boundary layer --- compiler/base/hierarchy_layout.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 7dcb62f9..7a4fc4c7 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -530,7 +530,7 @@ class layout(): width=width, height=height, center=False) - debug.info(0, "Adding {0} boundary {1}".format(self.name, boundary)) + debug.info(2, "Adding {0} boundary {1}".format(self.name, boundary)) self.visited.append(self.name) From b1d8a35aa70f5c9eb6d084f2ce8777cb2a238142 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 5 Dec 2019 15:38:25 -0800 Subject: [PATCH 047/521] Add contact variation --- compiler/base/contact.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index fb8ea0e8..9e947082 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -48,7 +48,6 @@ class contact(hierarchy_design.hierarchy_design): # Module does not have pins, but has empty pin list. self.pins = [] self.create_layout() - self.add_boundary() def create_layout(self): @@ -72,12 +71,15 @@ class contact(hierarchy_design.hierarchy_design): (first_layer, via_layer, second_layer) = self.layer_stack self.first_layer_name = first_layer + self.second_layer_name = second_layer # Contacts will have unique per first layer if via_layer == "contact": - self.via_layer_name = first_layer + "_" + via_layer + if first_layer in ("active", "poly"): + self.via_layer_name = first_layer + "_" + via_layer + else: + self.via_layer_name = second_layer + "_" + via_layer else: self.via_layer_name = via_layer - self.second_layer_name = second_layer def setup_layout_constants(self): """ Determine the design rules for the enclosure layers """ From d2cbc4652726474d14e0229b556ecfa40af0fde0 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Fri, 6 Dec 2019 00:05:26 +0000 Subject: [PATCH 048/521] Fix error --- technology/freepdk45/tech/tech.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 31c712ec..a8b9d263 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -167,8 +167,10 @@ drc["active_contact_to_poly"] = 0.090 # CONTACT.1 Minimum width of contact drc["minwidth_poly_contact"] = 0.065 +# CONTACT.2 Minimum spacing of contact +drc["poly_contact_to_poly_contact"] = 0.075 # Reserved for asymmetric enclosures -drc["active_extend_contact"] = 0.005 +drc["poly_extend_contact"] = 0.005 # CONTACT.5 Minimum enclosure of poly around contact drc["poly_enclosure_poly_contact"] = 0.005 # Reserved for asymmetric enclosures From 5af22b79e2cbea5df4faf370b760d825ee103821 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Fri, 6 Dec 2019 02:17:58 +0000 Subject: [PATCH 049/521] Only add boundary for if there's a DRC stdc layer --- compiler/base/hierarchy_layout.py | 6 ------ 1 file changed, 6 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 7a4fc4c7..494ab4ca 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -514,12 +514,6 @@ class layout(): # If there is a boundary layer, and we didn't create one, add one. if "stdc" in techlayer.keys(): boundary_layer = "stdc" - elif "boundary" in techlayer.keys(): - boundary_layer = "boundary" - else: - boundary_layer = None - - if boundary_layer: boundary = [self.find_lowest_coords(), self.find_highest_coords()] height = boundary[1][1] - boundary[0][1] width = boundary[1][0] - boundary[0][0] From f3286fb0c260af48138b305d44fe1528c59c5fc4 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Fri, 6 Dec 2019 02:37:12 +0000 Subject: [PATCH 050/521] Don't add boundary to ptx --- compiler/pgates/ptx.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 3a7311ae..a1606ac3 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -59,9 +59,9 @@ class ptx(design.design): # some transistor sizes in other netlist depend on pbitcell self.create_layout() - ll = self.find_lowest_coords() - ur = self.find_highest_coords() - self.add_boundary(ll, ur) + #ll = self.find_lowest_coords() + #ur = self.find_highest_coords() + #self.add_boundary(ll, ur) # (0,0) will be the corner ofthe active area (not the larger well) self.translate_all(self.active_offset) From 4a1b10ff0d3fb1c2de5f649d225f4532aebded5d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 5 Dec 2019 21:33:13 -0800 Subject: [PATCH 051/521] Remove extra cast --- compiler/base/geometry.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index e5c86546..46cfe7c7 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -193,7 +193,7 @@ class instance(geometry): blockages = [] blockages = self.mod.gds.getBlockages(lpp) for b in blockages: - new_blockages.append(self.transform_coords(vector(b),self.offset, mirr, angle)) + new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) else: blockages = self.mod.get_blockages(lpp) for b in blockages: From 000d2f9f0f28a789226cc990cde430b929a55930 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Fri, 6 Dec 2019 17:50:03 +0000 Subject: [PATCH 052/521] Remove tools and add nominal corner option to README --- README.md | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index f141b317..64c8aa25 100644 --- a/README.md +++ b/README.md @@ -112,12 +112,16 @@ num_words = 16 # Technology to use in $OPENRAM_TECH tech_name = "scn4m_subm" + +# You can use the technology nominal corner only +nominal_corner_only = True +# Or you can specify particular corners # Process corners to characterize -process_corners = ["TT"] +# process_corners = ["SS", "TT", "FF"] # Voltage corners to characterize -supply_voltages = [ 3.3 ] +# supply_voltages = [ 3.0, 3.3, 3.5 ] # Temperature corners to characterize -temperatures = [ 25 ] +# temperatures = [ 0, 25 100] # Output directory for the results output_path = "temp" @@ -127,11 +131,6 @@ output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) # Disable analytical models for full characterization (WARNING: slow!) # analytical_delay = False -# To force this to use magic and netgen for DRC/LVS/PEX -# Could be calibre for FreePDK45 -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" ``` You can then run OpenRAM by executing: From d32fd96d1dc0f2dcc3aeaad0d003fc105debdbbd Mon Sep 17 00:00:00 2001 From: Tim Ansell Date: Sat, 7 Dec 2019 09:50:05 +1030 Subject: [PATCH 053/521] Fix LICENSE file. Match the `BSD 3-Clause "New" or "Revised" License` template that GitHub provides so that license detection actually works correctly. --- LICENSE | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/LICENSE b/LICENSE index 761f6e8b..6fdf3ae0 100644 --- a/LICENSE +++ b/LICENSE @@ -1,23 +1,21 @@ BSD 3-Clause License -Copyright (c) 2019 Regents of the University of California and The Board -of Regents for the Oklahoma Agricultural and Mechanical College -(acting for and on behalf of Oklahoma State University) +Copyright (c) 2019, Regents of the University of California and The Board of Regents for the Oklahoma Agricultural and Mechanical College (acting for and on behalf of Oklahoma State University) All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. -* Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. +3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE From 5b3846e1e52ecfe4fcaeac8c98d52b6e67b705a8 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Sun, 8 Dec 2019 13:24:39 +0000 Subject: [PATCH 054/521] Changed replica bitcell array to work with bank tests for non power of two rows --- compiler/modules/bank.py | 7 ++++--- compiler/modules/port_address.py | 4 ++-- compiler/modules/replica_bitcell_array.py | 9 +++++---- compiler/sram/sram_config.py | 8 +++++--- 4 files changed, 16 insertions(+), 12 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 3e105d09..18ced346 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -289,13 +289,14 @@ class bank(design.design): """ Computes the required sizes to create the bank """ self.num_cols = int(self.words_per_row*self.word_size) - self.num_rows = int(self.num_words / self.words_per_row) + self.num_rows_temp = int(self.num_words / self.words_per_row) + self.num_rows = self.num_rows_temp + self.num_spare_rows - self.row_addr_size = int(log(self.num_rows, 2)) + self.row_addr_size = ceil(log(self.num_rows, 2)) self.col_addr_size = int(log(self.words_per_row, 2)) self.addr_size = self.col_addr_size + self.row_addr_size - debug.check(self.num_rows*self.num_cols==self.word_size*self.num_words,"Invalid bank sizes.") + debug.check(self.num_rows_temp*self.num_cols==self.word_size*self.num_words,"Invalid bank sizes.") debug.check(self.addr_size==self.col_addr_size + self.row_addr_size,"Invalid address break down.") # The order of the control signals on the control bus: diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 0a624c60..11035f30 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -5,7 +5,7 @@ # import sys from tech import drc, parameter -from math import log +from math import log, ceil import debug import design from sram_factory import factory @@ -22,7 +22,7 @@ class port_address(design.design): self.num_cols = cols self.num_rows = rows - self.addr_size = int(log(self.num_rows, 2)) + self.addr_size = ceil(log(self.num_rows, 2)) if name == "": name = "port_address_{0}_{1}".format(cols,rows) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 639d0714..0f922eb0 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -264,8 +264,9 @@ class replica_bitcell_array(design.design): # Far top dummy row (first row above array is NOT flipped) flip_dummy = self.right_rbl%2 - self.dummy_row_top_inst.place(offset=offset.scale(0,self.right_rbl+flip_dummy)+self.bitcell_array_inst.ul(), - mirror="MX" if flip_dummy else "R0") + odd_rows = self.row_size%2 + self.dummy_row_top_inst.place(offset=offset.scale(0,self.right_rbl+(flip_dummy ^ odd_rows))+self.bitcell_array_inst.ul(), + mirror="MX" if (flip_dummy ^ odd_rows) else "R0") # Far bottom dummy row (first row below array IS flipped) flip_dummy = (self.left_rbl+1)%2 self.dummy_row_bot_inst.place(offset=offset.scale(0,-self.left_rbl-1+flip_dummy), @@ -280,8 +281,8 @@ class replica_bitcell_array(design.design): self.dummy_row_replica_inst[bit].place(offset=offset.scale(0,-bit-bit%2), mirror="R0" if bit%2 else "MX") for bit in range(self.right_rbl): - self.dummy_row_replica_inst[self.left_rbl+bit].place(offset=offset.scale(0,bit+bit%2)+self.bitcell_array_inst.ul(), - mirror="MX" if bit%2 else "R0") + self.dummy_row_replica_inst[self.left_rbl+bit].place(offset=offset.scale(0,bit+bit%2+odd_rows)+self.bitcell_array_inst.ul(), + mirror="MX" if (bit%2 or odd_rows) else "R0") self.translate_all(offset.scale(-1-self.left_rbl,-1-self.left_rbl)) diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index 376bf42b..265cdba8 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -14,11 +14,12 @@ from sram_factory import factory class sram_config: """ This is a structure that is used to hold the SRAM configuration options. """ - def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None): + def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None, num_spare_rows=0): self.word_size = word_size self.num_words = num_words self.write_size = write_size self.num_banks = num_banks + self.num_spare_rows = num_spare_rows # This will get over-written when we determine the organization self.words_per_row = words_per_row @@ -78,11 +79,12 @@ class sram_config: # Fix the number of columns and rows self.num_cols = int(self.words_per_row*self.word_size) - self.num_rows = int(self.num_words_per_bank/self.words_per_row) + self.num_rows_temp = int(self.num_words_per_bank/self.words_per_row) + self.num_rows = self.num_rows_temp + self.num_spare_rows debug.info(1,"Rows: {} Cols: {}".format(self.num_rows,self.num_cols)) # Compute the address and bank sizes - self.row_addr_size = int(log(self.num_rows, 2)) + self.row_addr_size = ceil(log(self.num_rows, 2)) self.col_addr_size = int(log(self.words_per_row, 2)) self.bank_addr_size = self.col_addr_size + self.row_addr_size self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2)) From 928b02aa1fd3929919542564b3648e4b79d8d421 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 11 Dec 2019 10:37:17 +0100 Subject: [PATCH 055/521] gdsMill: Fix reader/writer ignoring the 'DATATYPE' of 'PATH' records most readers (like KLayout/Calibre) will not open gds files omiting the DATATYPE. Signed-off-by: Bastian Koppelmann --- compiler/gdsMill/gdsMill/gds2reader.py | 5 +++++ compiler/gdsMill/gdsMill/gds2writer.py | 4 ++++ compiler/gdsMill/gdsMill/gdsPrimitives.py | 1 + 3 files changed, 10 insertions(+) diff --git a/compiler/gdsMill/gdsMill/gds2reader.py b/compiler/gdsMill/gdsMill/gds2reader.py index 7e519c36..56dc4bef 100644 --- a/compiler/gdsMill/gdsMill/gds2reader.py +++ b/compiler/gdsMill/gdsMill/gds2reader.py @@ -251,6 +251,11 @@ class Gds2reader: thisPath.pathType=pathType if(self.debugToTerminal==1): print("\t\t\tPath Type: "+str(pathType)) + elif(idBits==b'\x0E\x02'): #Data type + dataType = struct.unpack(">h",record[2:4])[0] + thisPath.dataType=dataType + if(self.debugToTerminal==1): + print("\t\t\tData Type: "+str(dataType)) elif(idBits==b'\x0F\x03'): #Path width pathWidth = struct.unpack(">i",record[2:6])[0] thisPath.pathWidth=pathWidth diff --git a/compiler/gdsMill/gdsMill/gds2writer.py b/compiler/gdsMill/gdsMill/gds2writer.py index 402416cd..059c156d 100644 --- a/compiler/gdsMill/gdsMill/gds2writer.py +++ b/compiler/gdsMill/gdsMill/gds2writer.py @@ -238,6 +238,10 @@ class Gds2writer: idBits=b'\x16\x02' #purpose layer purposeLayer = struct.pack(">h",thisPath.purposeLayer) self.writeRecord(idBits+purposeLayer) + if(thisPath.dataType is not None): + idBits=b'\x0E\x02' #Data type + dataType = struct.pack(">h",thisPath.dataType) + self.writeRecord(idBits+dataType) if(thisPath.pathType): idBits=b'\x21\x02' #Path type pathType = struct.pack(">h",thisPath.pathType) diff --git a/compiler/gdsMill/gdsMill/gdsPrimitives.py b/compiler/gdsMill/gdsMill/gdsPrimitives.py index dc43fea6..ef87cec8 100644 --- a/compiler/gdsMill/gdsMill/gdsPrimitives.py +++ b/compiler/gdsMill/gdsMill/gdsPrimitives.py @@ -33,6 +33,7 @@ class GdsPath: self.drawingLayer="" self.purposeLayer = None self.pathType="" + self.dataType=None self.pathWidth="" self.coordinates="" From f9a66e86b4103182e0b3df528d4bcc8ace5b6763 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 11 Dec 2019 09:09:59 -0800 Subject: [PATCH 056/521] Add npc option to contact --- compiler/base/contact.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 9e947082..acfcc265 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -56,6 +56,7 @@ class contact(hierarchy_design.hierarchy_design): self.create_contact_array() self.create_first_layer_enclosure() self.create_second_layer_enclosure() + self.create_nitride_cut_enclosure() self.height = max(obj.offset.y + obj.height for obj in self.objs) self.width = max(obj.offset.x + obj.width for obj in self.objs) @@ -72,6 +73,7 @@ class contact(hierarchy_design.hierarchy_design): (first_layer, via_layer, second_layer) = self.layer_stack self.first_layer_name = first_layer self.second_layer_name = second_layer + # Contacts will have unique per first layer if via_layer == "contact": if first_layer in ("active", "poly"): @@ -81,6 +83,7 @@ class contact(hierarchy_design.hierarchy_design): else: self.via_layer_name = via_layer + def setup_layout_constants(self): """ Determine the design rules for the enclosure layers """ @@ -150,6 +153,25 @@ class contact(hierarchy_design.hierarchy_design): height=self.contact_width) offset = offset + vector(self.contact_pitch, 0) + def create_nitride_cut_enclosure(self): + """ Special layer that encloses poly contacts in some processes """ + # Check if there is a special poly nitride cut layer + if "npc" not in layer.keys(): + return + + # Only add for poly layers + if self.first_layer_name == "poly": + self.add_rect(layer="npc", + offset=self.first_layer_position, + width=self.first_layer_width, + height=self.first_layer_height) + elif self.second_layer_name == "poly": + self.add_rect(layer="npc", + offset=self.second_layer_position, + width=self.second_layer_width, + height=self.second_layer_height) + + def create_first_layer_enclosure(self): # this is if the first and second layers are different self.first_layer_position = vector( From e048ada23c256dabc090f38a737c010b51f4ff15 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 11 Dec 2019 17:56:55 -0800 Subject: [PATCH 057/521] Abstract basic DRC checks --- compiler/base/contact.py | 32 ++-- compiler/base/design.py | 9 +- compiler/drc/design_rules.py | 16 +- compiler/pgates/ptx.py | 8 +- compiler/tests/03_contact_test.py | 8 +- technology/freepdk45/tech/tech.py | 243 +++++++++++++++-------------- technology/scn4m_subm/tech/tech.py | 216 +++++++++++++------------ 7 files changed, 297 insertions(+), 235 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index acfcc265..26a59d31 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -7,7 +7,7 @@ # import hierarchy_design import debug -from tech import drc, layer +from tech import * from vector import vector @@ -75,13 +75,18 @@ class contact(hierarchy_design.hierarchy_design): self.second_layer_name = second_layer # Contacts will have unique per first layer - if via_layer == "contact": + if via_layer in layer.keys(): + self.via_layer_name = via_layer + elif via_layer == "contact": if first_layer in ("active", "poly"): self.via_layer_name = first_layer + "_" + via_layer + elif second_layer in ("active", "poly"): + self.via_layer_name = second_layer + "_" + via_layer else: - self.via_layer_name = second_layer + "_" + via_layer + debug.error("Invalid via layer {}".format(via_layer), -1) else: - self.via_layer_name = via_layer + debug.error("Invalid via layer {}".format(via_layer), -1) + def setup_layout_constants(self): @@ -224,23 +229,30 @@ from sram_factory import factory # This is not instantiated and used for calculations only. # These are static 1x1 contacts to reuse in all the design modules. well = factory.create(module_type="contact", - layer_stack=("active", "contact", "metal1"), + layer_stack=active_stack, directions=("H", "V")) active = factory.create(module_type="contact", - layer_stack=("active", "contact", "metal1"), + layer_stack=active_stack, directions=("H", "V")) poly = factory.create(module_type="contact", - layer_stack=("poly", "contact", "metal1"), + layer_stack=poly_stack, directions=("V", "H")) +if "li" in layer.keys(): + lim1 = factory.create(module_type="contact", + layer_stack=li_stack, + directions=("V", "H")) +else: + lim1 = None + m1m2 = factory.create(module_type="contact", - layer_stack=("metal1", "via1", "metal2"), + layer_stack=metal1_stack, directions=("H", "V")) m2m3 = factory.create(module_type="contact", - layer_stack=("metal2", "via2", "metal3"), + layer_stack=metal2_stack, directions=("V", "H")) if "metal4" in layer.keys(): m3m4 = factory.create(module_type="contact", - layer_stack=("metal3", "via3", "metal4"), + layer_stack=metal3_stack, directions=("H", "V")) else: m3m4 = None diff --git a/compiler/base/design.py b/compiler/base/design.py index c6385243..0ecfbbd4 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -48,12 +48,15 @@ class design(hierarchy_design): self.m4_space = drc("metal4_to_metal4") self.active_width = drc("minwidth_active") self.active_space = drc("active_to_body_active") - self.contact_width = drc("minwidth_active_contact") + if "contact" in layer: + self.contact_width = drc("minwidth_contact") + else: + self.contact_width = drc("minwidth_active_contact") self.poly_to_active = drc("poly_to_active") self.poly_extend_active = drc("poly_extend_active") - self.poly_to_poly_contact = drc("poly_to_poly_contact") - self.active_contact_to_gate = drc("active_contact_to_gate") + self.poly_to_contact = drc("poly_to_contact") + self.contact_to_gate = drc("contact_to_gate") self.well_enclose_active = drc("well_enclosure_active") self.implant_enclose_active = drc("implant_enclosure_active") self.implant_space = drc("implant_to_implant") diff --git a/compiler/drc/design_rules.py b/compiler/drc/design_rules.py index 1017aca6..cf54bdb3 100644 --- a/compiler/drc/design_rules.py +++ b/compiler/drc/design_rules.py @@ -43,6 +43,20 @@ class design_rules(): else: debug.error("Must call complex DRC rule {} with arguments.".format(b),-1) + + def add_layer(self, name, width, spacing, area=0): + # Minimum width + self.add("minwidth_{}".format(name), width) + # Minimum spacing (could be a table too) + self.add("{0}_to_{0}".format(name), spacing) + # Minimum area + self.add("minarea_{}".format(name), area) - + def add_enclosure(self, name, layer, enclosure, extension=None): + self.add("{0}_enclosure_{1}".format(name, layer), enclosure) + # Reserved for asymmetric enclosures + if extension: + self.add("{0}_extend_{1}".format(name, layer), extension) + else: + self.add("{0}_extend_{1}".format(name, layer), enclosure) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index a1606ac3..588152c0 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -130,18 +130,18 @@ class ptx(design.design): # The contacted poly pitch (or uncontacted in an odd technology) - self.poly_pitch = max(2 * self.active_contact_to_gate + self.contact_width + self.poly_width, + self.poly_pitch = max(2 * self.contact_to_gate + self.contact_width + self.poly_width, self.poly_space) # The contacted poly pitch (or uncontacted in an odd technology) - self.contact_pitch = 2 * self.active_contact_to_gate + self.contact_width + self.poly_width + self.contact_pitch = 2 * self.contact_to_gate + self.contact_width + self.poly_width # The enclosure of an active contact. Not sure about second term. - active_enclose_contact = max(drc("active_enclosure_active_contact"), + active_enclose_contact = max(drc("active_enclosure_contact"), (self.active_width - self.contact_width) / 2) # This is the distance from the edge of poly to the contacted end of active - self.end_to_poly = active_enclose_contact + self.contact_width + self.active_contact_to_gate + self.end_to_poly = active_enclose_contact + self.contact_width + self.contact_to_gate # Active width is determined by enclosure on both ends and contacted pitch, diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 2e3f4f0f..60d8cd6b 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -21,7 +21,9 @@ class contact_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]: + from tech import poly_stack, beol_stacks + + for layer_stack in [poly_stack] + beol_stacks: stack_name = ":".join(map(str, layer_stack)) # Check single 1 x 1 contact" @@ -43,6 +45,10 @@ class contact_test(openram_test): debug.info(2, "1 x 1 {} test".format(stack_name)) c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 1), directions=("V","V")) self.local_drc_check(c) + + # Only do multiple contacts for BEOL + for layer_stack in beol_stacks: + stack_name = ":".join(map(str, layer_stack)) # check vertical array with one in the middle and two ends debug.info(2, "1 x 3 {} test".format(stack_name)) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index a8b9d263..f8dc7d06 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -29,7 +29,28 @@ GDS["unit"] = (0.0005,1e-9) GDS["zoom"] = 0.05 ################################################### -##GDS Layer Map +# Interconnect stacks +################################################### + +poly_stack = ("poly", "contact", "metal1") +active_stack = ("active", "contact", "metal1") +metal1_stack = ("metal1", "via1", "metal2") +metal2_stack = ("metal2", "via2", "metal3") +metal3_stack = ("metal3", "via3", "metal4") + +# The FEOL stacks get us up to metal1 +feol_stacks = [poly_stack, + active_stack] + +# The BEOL stacks are metal1 and up +beol_stacks = [metal1_stack, + metal2_stack, + metal3_stack] + +layer_stacks = feol_stacks + beol_stacks + +################################################### +# GDS Layer Map ################################################### # create the GDS layer map @@ -44,8 +65,7 @@ layer["vtg"] = (6, 0) layer["vth"] = (7, 0) layer["thkox"] = (8, 0) layer["poly"] = (9, 0) -layer["active_contact"] = (10, 0) -layer["poly_contact"] = (10, 0) +layer["contact"] = (10, 0) layer["metal1"] = (11, 0) layer["via1"] = (12, 0) layer["metal2"] = (13, 0) @@ -69,11 +89,7 @@ layer["text"] = (239, 0) layer["boundary"]= (239, 0) ################################################### -##END GDS Layer Map -################################################### - -################################################### -##DRC/LVS Rules Setup +# DRC/LVS Rules Setup ################################################### #technology parameter @@ -105,18 +121,21 @@ drc["minlength_channel"] = 0.05 # WELL.2 Minimum spacing of nwell/pwell at different potential drc["pwell_to_nwell"] = 0.225 # WELL.3 Minimum spacing of nwell/pwell at the same potential -drc["well_to_well"] = 0.135 # WELL.4 Minimum width of nwell/pwell -drc["minwidth_well"] = 0.2 +drc.add_layer("well", + width = 0.2, + spacing = 0.135) # POLY.1 Minimum width of poly -drc["minwidth_poly"] = 0.05 # POLY.2 Minimum spacing of poly AND active -drc["poly_to_poly"] = 0.14 +drc.add_layer("poly", + width = 0.05, + spacing = 0.14) + # POLY.3 Minimum poly extension beyond active drc["poly_extend_active"] = 0.055 # Not a rule -drc["poly_to_poly_contact"] = 0.075 +drc["poly_to_contact"] = 0.075 # POLY.4 Minimum enclosure of active around gate drc["active_enclosure_gate"] = 0.07 # POLY.5 Minimum spacing of field poly to active @@ -129,162 +148,164 @@ drc["minarea_poly"] = 0.0 # ACTIVE.2 Minimum spacing of active drc["active_to_body_active"] = 0.08 # ACTIVE.1 Minimum width of active -drc["minwidth_active"] = 0.09 -# Not a rule -drc["active_to_active"] = 0 +drc.add_layer("active", + width = 0.09, + spacing = 0) # ACTIVE.3 Minimum enclosure/spacing of nwell/pwell to active -drc["well_enclosure_active"] = 0.055 -# Reserved for asymmetric enclosures -drc["well_extend_active"] = 0.055 -# Not a rule -drc["minarea_active"] = 0 +drc.add_enclosure("well", + layer = "active", + enclosure = 0.055) # IMPLANT.1 Minimum spacing of nimplant/ pimplant to channel drc["implant_to_channel"] = 0.07 # Not a rule -drc["implant_enclosure_active"] = 0 +drc.add_enclosure("implant", + layer = "active", + enclosure = 0) # Not a rule -drc["implant_enclosure_contact"] = 0 +drc.add_enclosure("implant", + layer = "contact", + enclosure = 0) # IMPLANT.2 Minimum spacing of nimplant/ pimplant to contact drc["implant_to_contact"] = 0.025 # IMPLANT.3 Minimum width/ spacing of nimplant/ pimplant -drc["implant_to_implant"] = 0.045 # IMPLANT.4 Minimum width/ spacing of nimplant/ pimplant -drc["minwidth_implant"] = 0.045 +drc.add_layer("implant", + width = 0.045, + spacing = 0.045) # CONTACT.1 Minimum width of contact -drc["minwidth_active_contact"] = 0.065 # CONTACT.2 Minimum spacing of contact -drc["active_contact_to_active_contact"] = 0.075 +drc.add_layer("contact", + width = 0.065, + spacing = 0.075) # CONTACT.4 Minimum enclosure of active around contact -drc["active_enclosure_active_contact"] = 0.005 -# Reserved for asymmetric enclosures -drc["active_extend_active_contact"] = 0.005 +drc.add_enclosure("active", + layer = "contact", + enclosure = 0.005) + # CONTACT.6 Minimum spacing of contact and gate -drc["active_contact_to_gate"] = 0.0375 #changed from 0.035 +drc["contact_to_gate"] = 0.0375 #changed from 0.035 # CONTACT.7 Minimum spacing of contact and poly -drc["active_contact_to_poly"] = 0.090 +drc["contact_to_poly"] = 0.090 # CONTACT.1 Minimum width of contact -drc["minwidth_poly_contact"] = 0.065 # CONTACT.2 Minimum spacing of contact -drc["poly_contact_to_poly_contact"] = 0.075 -# Reserved for asymmetric enclosures -drc["poly_extend_contact"] = 0.005 +drc.add_layer("contact", + width = 0.065, + spacing = 0.075) # CONTACT.5 Minimum enclosure of poly around contact -drc["poly_enclosure_poly_contact"] = 0.005 -# Reserved for asymmetric enclosures -drc["poly_extend_poly_contact"] = 0.005 +drc.add_enclosure("poly", + layer = "contact", + enclosure = 0.005) # CONTACT.6 Minimum spacing of contact and gate -drc["poly_contact_to_gate"] = 0.0375 #changed from 0.035 +drc["contact_to_gate"] = 0.0375 #changed from 0.035 # CONTACT.7 Minimum spacing of contact and poly -drc["poly_contact_to_poly"] = 0.090 +drc["contact_to_poly"] = 0.090 # METAL1.1 Minimum width of metal1 -drc["minwidth_metal1"] = 0.065 # METAL1.2 Minimum spacing of metal1 -drc["metal1_to_metal1"] = 0.065 +drc.add_layer("metal1", + width = 0.065, + spacing = 0.065) + # METAL1.3 Minimum enclosure around contact on two opposite sides -drc["metal1_enclosure_active_contact"] = 0 -# Reserved for asymmetric enclosures -drc["metal1_extend_active_contact"] = 0.035 -# METAL1.3 Minimum enclosure around contact on two opposite sides -drc["metal1_enclosure_poly_contact"] = 0 -# Reserved for asymmetric enclosures -drc["metal1_extend_poly_contact"] = 0.035 +drc.add_enclosure("metal1", + layer = "contact", + enclosure = 0, + extension = 0.035) # METAL1.4 inimum enclosure around via1 on two opposite sides -drc["metal1_extend_via1"] = 0.035 -# Reserved for asymmetric enclosures -drc["metal1_enclosure_via1"] = 0 -# Not a rule -drc["minarea_metal1"] = 0 +drc.add_enclosure("metal1", + layer = "via1", + enclosure = 0, + extension = 0.035) # VIA1.1 Minimum width of via1 -drc["minwidth_via1"] = 0.065 # VIA1.2 Minimum spacing of via1 -drc["via1_to_via1"] = 0.075 +drc.add_layer("via1", + width = 0.065, + spacing = 0.075) + # METALINT.1 Minimum width of intermediate metal -drc["minwidth_metal2"] = 0.07 # METALINT.2 Minimum spacing of intermediate metal -drc["metal2_to_metal2"] = 0.07 +drc.add_layer("metal2", + width = 0.07, + spacing = 0.07) + # METALINT.3 Minimum enclosure around via1 on two opposite sides -drc["metal2_extend_via1"] = 0.035 -# Reserved for asymmetric enclosures -drc["metal2_enclosure_via1"] = 0 +drc.add_enclosure("metal2", + layer = "via1", + enclosure = 0, + extension = 0.035) + # METALINT.4 Minimum enclosure around via[2-3] on two opposite sides -drc["metal2_extend_via2"] = 0.035 -# Reserved for asymmetric enclosures -drc["metal2_enclosure_via2"] = 0 -# Not a rule -drc["minarea_metal2"] = 0 +drc.add_enclosure("metal2", + layer = "via2", + enclosure = 0, + extension = 0.035) # VIA2-3.1 Minimum width of Via[2-3] -drc["minwidth_via2"] = 0.065 # VIA2-3.2 Minimum spacing of Via[2-3] -drc["via2_to_via2"] = 0.075 +drc.add_layer("via2", + width = 0.065, + spacing = 0.075) # METALINT.1 Minimum width of intermediate metal -drc["minwidth_metal3"] = 0.07 # METALINT.2 Minimum spacing of intermediate metal -#drc["metal3_to_metal3"] = 0.07 # Minimum spacing of metal3 wider than 0.09 & longer than 0.3 = 0.09 # Minimum spacing of metal3 wider than 0.27 & longer than 0.9 = 0.27 # Minimum spacing of metal3 wider than 0.5 & longer than 1.8 = 0.5 # Minimum spacing of metal3 wider than 0.9 & longer than 2.7 = 0.9 # Minimum spacing of metal3 wider than 1.5 & longer than 4.0 = 1.5 -drc["metal3_to_metal3"] = drc_lut({(0.00, 0.0) : 0.07, - (0.09, 0.3) : 0.09, - (0.27, 0.9) : 0.27, - (0.50, 1.8) : 0.5, - (0.90, 2.7) : 0.9, - (1.50, 4.0) : 1.5}) +drc.add_layer("metal3", + width = 0.07, + spacing = drc_lut({(0.00, 0.0) : 0.07, + (0.09, 0.3) : 0.09, + (0.27, 0.9) : 0.27, + (0.50, 1.8) : 0.5, + (0.90, 2.7) : 0.9, + (1.50, 4.0) : 1.5})) # METALINT.3 Minimum enclosure around via1 on two opposite sides -drc["metal3_extend_via2"] = 0.035 -# Reserved for asymmetric enclosures -drc["metal3_enclosure_via2"] = 0 +drc.add_enclosure("metal3", + layer = "via2", + enclosure = 0, + extension = 0.035) + # METALINT.4 Minimum enclosure around via[2-3] on two opposite sides -drc["metal3_extend_via3"]=0.035 -# Reserved for asymmetric enclosures -drc["metal3_enclosure_via3"] = 0 -# Not a rule -drc["minarea_metal3"] = 0 +drc.add_enclosure("metal3", + layer = "via3", + enclosure = 0, + extension = 0.035) # VIA2-3.1 Minimum width of Via[2-3] -drc["minwidth_via3"] = 0.07 # VIA2-3.2 Minimum spacing of Via[2-3] -drc["via3_to_via3"] = 0.085 +drc.add_layer("via3", + width = 0.07, + spacing = 0.085) # METALSMG.1 Minimum width of semi-global metal -drc["minwidth_metal4"] = 0.14 # METALSMG.2 Minimum spacing of semi-global metal -#drc["metal4_to_metal4"] = 0.14 # Minimum spacing of metal4 wider than 0.27 & longer than 0.9 = 0.27 # Minimum spacing of metal4 wider than 0.5 & longer than 1.8 = 0.5 # Minimum spacing of metal4 wider than 0.9 & longer than 2.7 = 0.9 # Minimum spacing of metal4 wider than 1.5 & longer than 4.0 = 1.5 -drc["metal4_to_metal4"] = drc_lut({(0.00, 0.0) : 0.14, - (0.27, 0.9) : 0.27, - (0.50, 1.8) : 0.5, - (0.90, 2.7) : 0.9, - (1.50, 4.0) : 1.5}) +drc.add_layer("metal4", + width = 0.14, + spacing = drc_lut({(0.00, 0.0) : 0.14, + (0.27, 0.9) : 0.27, + (0.50, 1.8) : 0.5, + (0.90, 2.7) : 0.9, + (1.50, 4.0) : 1.5})) # METALSMG.3 Minimum enclosure around via[3-6] on two opposite sides -drc["metal4_extend_via3"] = 0.0025 -# Reserved for asymmetric enclosure -drc["metal4_enclosure_via3"] = 0.0025 -# Not a rule -drc["minarea_metal4"] = 0 +drc.add_enclosure("metal4", + layer = "via3", + enclosure = 0.0025) # Metal 5-10 are ommitted - - ################################################### -##END DRC/LVS Rules -################################################### - -################################################### -##Spice Simulation Parameters +# Spice Simulation Parameters ################################################### #spice info @@ -347,11 +368,7 @@ parameter["sa_inv_nmos_size"] = 0.27 #micro-meters parameter["bitcell_drain_cap"] = 0.1 #In Femto-Farad, approximation of drain capacitance ################################################### -##END Spice Simulation Parameters -################################################### - -################################################### -##BEGIN Technology Tool Preferences +# Technology Tool Preferences ################################################### drc_name = "calibre" @@ -359,7 +376,3 @@ lvs_name = "calibre" pex_name = "calibre" blackbox_bitcell = False - -################################################### -##END Technology Tool Preferences -################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 8e189efd..23a0d9fe 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -28,6 +28,27 @@ GDS["unit"]=(0.001,1e-6) # default label zoom GDS["zoom"] = 0.5 +################################################### +# Interconnect stacks +################################################### + +poly_stack = ("poly", "poly_contact", "metal1") +active_stack = ("active", "active_contact", "metal1") +metal1_stack = ("metal1", "via1", "metal2") +metal2_stack = ("metal2", "via2", "metal3") +metal3_stack = ("metal3", "via3", "metal4") + +# The FEOL stacks get us up to metal1 +feol_stacks = [poly_stack, + active_stack] + +# The BEOL stacks are metal1 and up +beol_stacks = [metal1_stack, + metal2_stack, + metal3_stack] + +layer_stacks = feol_stacks + beol_stacks + ################################################### ##GDS Layer Map @@ -43,8 +64,8 @@ layer["active"] = (43, 0) layer["pimplant"] = (44, 0) layer["nimplant"] = (45, 0) layer["poly"] = (46, 0) -layer["active_contact"] = (48, 0) layer["poly_contact"] = (47, 0) +layer["active_contact"] = (48, 0) layer["metal1"] = (49, 0) layer["via1"] = (50, 0) layer["metal2"] = (51, 0) @@ -56,11 +77,7 @@ layer["text"] = (63, 0) layer["boundary"] = (63, 0) ################################################### -##END GDS Layer Map -################################################### - -################################################### -##DRC/LVS Rules Setup +# DRC/LVS Rules Setup ################################################### _lambda_ = 0.2 @@ -90,163 +107,168 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map" drc["minwidth_tx"] = 4*_lambda_ drc["minlength_channel"] = 2*_lambda_ -# 1.3 Minimum spacing between wells of same type (if both are drawn) -drc["well_to_well"] = 6*_lambda_ # 1.4 Minimum spacing between wells of different type (if both are drawn) drc["pwell_to_nwell"] = 0 +# 1.3 Minimum spacing between wells of same type (if both are drawn) # 1.1 Minimum width -drc["minwidth_well"] = 12*_lambda_ +drc.add_layer("well", + width = 12*_lambda_, + spacing = 6*_lambda_) # 3.1 Minimum width -drc["minwidth_poly"] = 2*_lambda_ # 3.2 Minimum spacing over active -drc["poly_to_poly"] = 3*_lambda_ +drc.add_layer("poly", + width = 2*_lambda_, + spacing = 3*_lambda_) # 3.3 Minimum gate extension of active drc["poly_extend_active"] = 2*_lambda_ # 5.5.b Minimum spacing between poly contact and other poly (alternative rules) -drc["poly_to_poly_contact"] = 4*_lambda_ +drc["poly_to_contact"] = 4*_lambda_ # ?? drc["active_enclosure_gate"] = 0.0 # 3.5 Minimum field poly to active drc["poly_to_active"] = _lambda_ # 3.2.a Minimum spacing over field poly drc["poly_to_field_poly"] = 3*_lambda_ -# Not a rule -drc["minarea_poly"] = 0.0 # ?? drc["active_to_body_active"] = 4*_lambda_ # Fix me # 2.1 Minimum width -drc["minwidth_active"] = 3*_lambda_ # 2.2 Minimum spacing -drc["active_to_active"] = 3*_lambda_ +drc.add_layer("active", + width = 3*_lambda_, + spacing = 3*_lambda_) # 2.3 Source/drain active to well edge -drc["well_enclosure_active"] = 6*_lambda_ -# Reserved for asymmetric enclosures -drc["well_extend_active"] = 6*_lambda_ -# Not a rule -drc["minarea_active"] = 0.0 +drc.add_enclosure("well", + layer = "active", + enclosure = 6*_lambda_) # 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width drc["implant_to_channel"] = 3*_lambda_ # 4.2 Minimum select overlap of active -drc["implant_enclosure_active"] = 2*_lambda_ +drc.add_enclosure("implant", + layer = "active", + enclosure = 2*_lambda_) # 4.3 Minimum select overlap of contact -drc["implant_enclosure_contact"] = _lambda_ +drc.add_enclosure("implant", + layer = "contact", + enclosure = _lambda_) # Not a rule drc["implant_to_contact"] = 0 # Not a rule -drc["implant_to_implant"] = 0 -# Not a rule -drc["minwidth_implant"] = 0 +drc.add_layer("implant", + width = 0, + spacing = 0) # 6.1 Exact contact size -drc["minwidth_active_contact"] = 2*_lambda_ # 5.3 Minimum contact spacing -drc["active_contact_to_active_contact"] = 3*_lambda_ -# 6.2.b Minimum active overlap -drc["active_enclosure_active_contact"] = _lambda_ -# Reserved for asymmetric enclosure -drc["active_extend_active_contact"] = _lambda_ +drc.add_layer("active_contact", + width = 2*_lambda_, + spacing = 3*_lambda_) +# 6.2.b Minimum active overlap +drc.add_enclosure("active", + layer = "active_contact", + enclosure = _lambda_) +drc.add_enclosure("active", + layer = "contact", + enclosure = _lambda_) # Reserved for other technologies -drc["active_contact_to_gate"] = 2*_lambda_ +drc["contact_to_gate"] = 2*_lambda_ # 5.4 Minimum spacing to gate of transistor -drc["active_contact_to_poly"] = 2*_lambda_ +drc["contact_to_poly"] = 2*_lambda_ # 6.1 Exact contact size -drc["minwidth_poly_contact"] = 2*_lambda_ # 5.3 Minimum contact spacing -drc["poly_contact_to_poly_contact"] = 3*_lambda_ +drc.add_layer("poly_contact", + width = 2*_lambda_, + spacing = 3*_lambda_) # 5.2.b Minimum poly overlap -drc["poly_enclosure_poly_contact"] = _lambda_ -# Reserved for asymmetric enclosures -drc["poly_extend_poly_contact"] = _lambda_ +drc.add_enclosure("poly", + layer = "poly_contact", + enclosure = _lambda_) # Reserved for other technologies drc["poly_contact_to_gate"] = 2*_lambda_ # 5.4 Minimum spacing to gate of transistor drc["poly_contact_to_poly"] = 2*_lambda_ # 7.1 Minimum width -drc["minwidth_metal1"] = 3*_lambda_ # 7.2 Minimum spacing -drc["metal1_to_metal1"] = 3*_lambda_ +drc.add_layer("metal1", + width = 3*_lambda_, + spacing = 3*_lambda_) # 7.3 Minimum overlap of any contact -drc["metal1_enclosure_active_contact"] = _lambda_ -# Reserved for asymmetric enclosure -drc["metal1_extend_active_contact"] = _lambda_ -# 7.3 Minimum overlap of any contact -drc["metal1_enclosure_poly_contact"] = _lambda_ -# Reserved for asymmetric enclosure -drc["metal1_extend_poly_contact"] = _lambda_ -# 8.3 Minimum overlap by metal1 -drc["metal1_enclosure_via1"] = _lambda_ -# Reserve for asymmetric enclosures -drc["metal1_extend_via1"] = _lambda_ -# Not a rule -drc["minarea_metal1"] = 0 +drc.add_enclosure("metal1", + layer = "poly_contact", + enclosure = _lambda_) +drc.add_enclosure("metal1", + layer = "active_contact", + enclosure = _lambda_) +# 8.3 Minimum overlap by metal1 +drc.add_enclosure("metal1", + layer = "via1", + enclosure = _lambda_) # 8.1 Exact size -drc["minwidth_via1"] = 2*_lambda_ # 8.2 Minimum via1 spacing -drc["via1_to_via1"] = 3*_lambda_ +drc.add_layer("via1", + width = 2*_lambda_, + spacing = 3*_lambda_) # 9.1 Minimum width -drc["minwidth_metal2"] = 3*_lambda_ # 9.2 Minimum spacing -drc["metal2_to_metal2"] = 3*_lambda_ +drc.add_layer("metal2", + width = 3*_lambda_, + spacing = 3*_lambda_) # 9.3 Minimum overlap of via1 -drc["metal2_extend_via1"] = _lambda_ -# Reserved for asymmetric enclosures -drc["metal2_enclosure_via1"] = _lambda_ +drc.add_enclosure("metal2", + layer = "via1", + enclosure = _lambda_) # 14.3 Minimum overlap by metal2 -drc["metal2_extend_via2"] = _lambda_ -# Reserved for asymmetric enclosures -drc["metal2_enclosure_via2"] = _lambda_ -# Not a rule -drc["minarea_metal2"] = 0 +drc.add_enclosure("metal2", + layer = "via2", + enclosure = _lambda_) # 14.1 Exact size -drc["minwidth_via2"] = 2*_lambda_ # 14.2 Minimum spacing -drc["via2_to_via2"] = 3*_lambda_ +drc.add_layer("via2", + width = 2*_lambda_, + spacing = 3*_lambda_) # 15.1 Minimum width -drc["minwidth_metal3"] = 3*_lambda_ # 15.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 3*_lambda_ +drc.add_layer("metal3", + width = 3*_lambda_, + spacing = 3*_lambda_) + # 15.3 Minimum overlap of via 2 -drc["metal3_extend_via2"] = _lambda_ -# Reserved for asymmetric enclosures -drc["metal3_enclosure_via2"] = _lambda_ +drc.add_enclosure("metal3", + layer = "via2", + enclosure = _lambda_) + # 21.3 Minimum overlap by metal3 -drc["metal3_extend_via3"] = _lambda_ -# Reserved for asymmetric enclosures -drc["metal3_enclosure_via3"] = _lambda_ -# Not a rule -drc["minarea_metal3"] = 0 +drc.add_enclosure("metal3", + layer = "via3", + enclosure = _lambda_) # 21.1 Exact size -drc["minwidth_via3"] = 2*_lambda_ # 21.2 Minimum spacing -drc["via3_to_via3"] = 3*_lambda_ +drc.add_layer("via3", + width = 2*_lambda_, + spacing = 3*_lambda_) # 22.1 Minimum width -drc["minwidth_metal4"] = 6*_lambda_ # 22.2 Minimum spacing to metal4 -drc["metal4_to_metal4"] = 6*_lambda_ +drc.add_layer("metal4", + width = 6*_lambda_, + spacing = 6*_lambda_) + # 22.3 Minimum overlap of via 3 -drc["metal4_extend_via3"] = 2*_lambda_ -# Reserved for asymmetric enclosures -drc["metal4_enclosure_via3"] = 2*_lambda_ -# Not a rule -drc["minarea_metal4"] = 0 +drc.add_enclosure("metal4", + layer = "via3", + enclosure = 2*_lambda_) ################################################### -##END DRC/LVS Rules -################################################### - -################################################### -##Spice Simulation Parameters +# Spice Simulation Parameters ################################################### # spice model info @@ -311,11 +333,7 @@ parameter["sa_inv_nmos_size"] = 9*_lambda_ parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of drain capacitance ################################################### -##END Spice Simulation Parameters -################################################### - -################################################### -##BEGIN Technology Tool Preferences +# Technology Tool Preferences ################################################### drc_name = "magic" @@ -323,7 +341,3 @@ lvs_name = "netgen" pex_name = "magic" blackbox_bitcell = False - -################################################### -##END Technology Tool Preferences -################################################### From 8d3f1d19cb2dcdb2fbba62f1a98779a914994916 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 11 Dec 2019 18:02:32 -0800 Subject: [PATCH 058/521] Fix missing rule --- compiler/bitcells/pbitcell.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 0e0e1bf7..1e3eb506 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -243,7 +243,7 @@ class pbitcell(bitcell_base.bitcell_base): (self.inverter_nmos.active_contact.height - self.inverter_nmos.active_height) self.inverter_gap = max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + self.poly_to_poly_contact + 2 * contact.poly.width \ + + self.poly_to_contact + 2 * contact.poly.width \ + self.m1_space + inverter_pmos_contact_extension self.cross_couple_lower_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ @@ -254,7 +254,7 @@ class pbitcell(bitcell_base.bitcell_base): + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + self.poly_to_poly_contact \ + + self.poly_to_contact \ + 1.5 * contact.poly.width # spacing between wordlines (and gnd) @@ -926,14 +926,14 @@ class pbitcell(bitcell_base.bitcell_base): """ # add poly to metal1 contacts for gates of the inverters left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x \ - - self.poly_to_poly_contact - 0.5*contact.poly.width, + - self.poly_to_contact - 0.5*contact.poly.width, self.cross_couple_upper_ypos) self.add_via_center(layers=("poly", "contact", "metal1"), offset=left_storage_contact, directions=("H", "H")) right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \ - + self.poly_to_poly_contact + 0.5*contact.poly.width, + + self.poly_to_contact + 0.5*contact.poly.width, self.cross_couple_upper_ypos) self.add_via_center(layers=("poly", "contact", "metal1"), offset=right_storage_contact, From e143a6033fdd26c3e8cd0b28b379c49a608c744e Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 13 Dec 2019 14:13:41 -0800 Subject: [PATCH 059/521] Use layer stacks from tech file in design class and throughout --- compiler/base/contact.py | 6 ++-- compiler/base/design.py | 18 ++++++++++-- compiler/base/hierarchy_layout.py | 14 ++++----- compiler/bitcells/pbitcell.py | 28 +++++++++--------- compiler/modules/bank.py | 14 ++++----- compiler/modules/bank_select.py | 10 +++---- compiler/modules/hierarchical_decoder.py | 10 +++---- compiler/modules/hierarchical_predecode.py | 10 +++---- compiler/modules/multibank.py | 14 ++++----- compiler/modules/port_data.py | 4 +-- compiler/modules/sense_amp_array.py | 4 +-- .../modules/single_level_column_mux_array.py | 8 ++--- compiler/modules/tri_gate_array.py | 2 +- compiler/modules/wordline_driver.py | 6 ++-- compiler/modules/write_driver_array.py | 2 +- compiler/modules/write_mask_and_array.py | 8 ++--- compiler/pgates/pgate.py | 2 +- compiler/pgates/pinv.py | 4 +-- compiler/pgates/pinvbuf.py | 10 +++---- compiler/pgates/pnand2.py | 6 ++-- compiler/pgates/pnand3.py | 8 ++--- compiler/pgates/pnor2.py | 6 ++-- compiler/pgates/precharge.py | 13 ++++----- compiler/pgates/ptx.py | 1 - compiler/pgates/single_level_column_mux.py | 12 ++++---- compiler/sram/sram_1bank.py | 29 ++++++++++--------- compiler/tests/03_wire_test.py | 12 ++++---- technology/scn4m_subm/tech/tech.py | 12 ++++---- 28 files changed, 141 insertions(+), 132 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 26a59d31..5f169e07 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -245,14 +245,14 @@ else: lim1 = None m1m2 = factory.create(module_type="contact", - layer_stack=metal1_stack, + layer_stack=m1_stack, directions=("H", "V")) m2m3 = factory.create(module_type="contact", - layer_stack=metal2_stack, + layer_stack=m2_stack, directions=("V", "H")) if "metal4" in layer.keys(): m3m4 = factory.create(module_type="contact", - layer_stack=metal3_stack, + layer_stack=m3_stack, directions=("H", "V")) else: m3m4 = None diff --git a/compiler/base/design.py b/compiler/base/design.py index 0ecfbbd4..16237cfd 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -13,7 +13,7 @@ from globals import OPTS class design(hierarchy_design): """ This is the same as the hierarchy_design class except it contains - some DRC constants and analytical models for other modules to reuse. + some DRC/layer constants and analytical models for other modules to reuse. """ @@ -21,16 +21,28 @@ class design(hierarchy_design): hierarchy_design.__init__(self, name) self.setup_drc_constants() + self.setup_layer_constants() self.setup_multiport_constants() - from tech import layer + + def setup_layer_constants(self): + """ These are some layer constants used in many places in the compiler.""" + + import tech + self.m1_pitch = max(contact.m1m2.width, contact.m1m2.height) + max(self.m1_space, self.m2_space) self.m2_pitch = max(contact.m2m3.width, contact.m2m3.height) + max(self.m2_space, self.m3_space) - if "metal4" in layer: + if "metal4" in tech.layer: self.m3_pitch = max(contact.m3m4.width, contact.m3m4.height) + max(self.m3_space, self.m4_space) else: self.m3_pitch = self.m2_pitch + self.poly_stack = tech.poly_stack + self.active_stack = tech.active_stack + self.m1_stack = tech.m1_stack + self.m2_stack = tech.m2_stack + self.m3_stack = tech.m3_stack + def setup_drc_constants(self): """ These are some DRC constants used in many places in the compiler.""" from tech import drc, layer diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 494ab4ca..ad1e3edb 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -824,7 +824,7 @@ class layout(): def create_channel_route(self, netlist, offset, - layer_stack=("metal1", "via1", "metal2"), + layer_stack, vertical=False): """ The net list is a list of the nets. Each net is a list of pins @@ -950,15 +950,13 @@ class layout(): offset += vector(0,self.horizontal_pitch) - def create_vertical_channel_route(self, netlist, offset, - layer_stack=("metal1", "via1", "metal2")): + def create_vertical_channel_route(self, netlist, offset, layer_stack): """ Wrapper to create a vertical channel route """ self.create_channel_route(netlist, offset, layer_stack, vertical=True) - def create_horizontal_channel_route(self, netlist, offset, - layer_stack=("metal1", "via1", "metal2")): + def create_horizontal_channel_route(self, netlist, offset, layer_stack): """ Wrapper to create a horizontal channel route """ @@ -1028,13 +1026,13 @@ class layout(): direction=("H","H") if start_layer=="metal1": - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=loc, directions=direction) if start_layer=="metal1" or start_layer=="metal2": - via=self.add_via_center(layers=("metal2", "via2", "metal3"), + via=self.add_via_center(layers=self.m2_stack, offset=loc, directions=direction) @@ -1159,7 +1157,7 @@ class layout(): vector(self.right_vdd_x_center, self.top_vdd_y_center)] for pt in via_points: - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=pt, size = (self.supply_vias, self.supply_vias)) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 1e3eb506..0f4b8183 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -378,7 +378,7 @@ class pbitcell(bitcell_base.bitcell_base): contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x \ + 0.5 * contact.poly.height, self.cross_couple_upper_ypos) - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=contact_offset_left, directions=("H", "H")) @@ -386,7 +386,7 @@ class pbitcell(bitcell_base.bitcell_base): contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x \ - 0.5*contact.poly.height, self.cross_couple_lower_ypos) - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=contact_offset_right, directions=("H", "H")) @@ -771,7 +771,7 @@ class pbitcell(bitcell_base.bitcell_base): # first transistor on either side of the cross coupled inverters # does not need to route to wordline on metal2 if (k == 0) or (k == 1): - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=port_contact_offset) self.add_path("poly", [gate_offset, port_contact_offset]) @@ -779,12 +779,12 @@ class pbitcell(bitcell_base.bitcell_base): [port_contact_offset, wl_contact_offset]) else: - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=port_contact_offset) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=port_contact_offset) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=wl_contact_offset, directions=("H", "H")) @@ -824,7 +824,7 @@ class pbitcell(bitcell_base.bitcell_base): # Leave bitline disconnected if a dummy cell if not self.dummy_bitcell: - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=port_contact_offest) self.add_path("metal2", @@ -836,7 +836,7 @@ class pbitcell(bitcell_base.bitcell_base): # Leave bitline disconnected if a dummy cell if not self.dummy_bitcell: - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=port_contact_offest) self.add_path("metal2", @@ -853,7 +853,7 @@ class pbitcell(bitcell_base.bitcell_base): nmos_contact_positions.append(self.read_access_nmos_right[k].get_pin("S").center()) for position in nmos_contact_positions: - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=position) if position.x > 0: @@ -862,7 +862,7 @@ class pbitcell(bitcell_base.bitcell_base): contact_correct = -0.5 * contact.m1m2.height supply_offset = vector(position.x + contact_correct, self.gnd_position.y) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=supply_offset, directions=("H", "H")) @@ -928,14 +928,14 @@ class pbitcell(bitcell_base.bitcell_base): left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x \ - self.poly_to_contact - 0.5*contact.poly.width, self.cross_couple_upper_ypos) - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=left_storage_contact, directions=("H", "H")) right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \ + self.poly_to_contact + 0.5*contact.poly.width, self.cross_couple_upper_ypos) - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=right_storage_contact, directions=("H", "H")) @@ -952,7 +952,7 @@ class pbitcell(bitcell_base.bitcell_base): + vector(0, self.gate_contact_yoffset - self.poly_extend_active) - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=port_contact_offset) self.add_path("poly", @@ -967,7 +967,7 @@ class pbitcell(bitcell_base.bitcell_base): + vector(0, self.gate_contact_yoffset - self.poly_extend_active) - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=port_contact_offset) self.add_path("poly", diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 3e105d09..b1ce2d55 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -606,11 +606,11 @@ class bank(design.design): name = self.control_signals[port][signal] bus_pos = vector(self.bus_xoffset[port][name].x, out_pos.y) self.add_path("metal3",[out_pos, bus_pos]) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=bus_pos) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=out_pos) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=out_pos) @@ -756,7 +756,7 @@ class bank(design.design): bottom_names = [bottom_inst.get_pin(bottom_bl_name.format(bit)), bottom_inst.get_pin(bottom_br_name.format(bit))] top_names = [top_inst.get_pin(top_bl_name.format(bit)), top_inst.get_pin(top_br_name.format(bit))] route_map = list(zip(bottom_names, top_names)) - self.create_horizontal_channel_route(route_map, offset) + self.create_horizontal_channel_route(route_map, offset, self.m1_stack) def connect_bitline(self, inst1, inst2, inst1_name, inst2_name): """ @@ -865,7 +865,7 @@ class bank(design.design): column_mux_pins = [self.port_data_inst[port].get_pin(x) for x in sel_names] route_map = list(zip(decode_pins, column_mux_pins)) - self.create_vertical_channel_route(route_map, offset) + self.create_vertical_channel_route(route_map, offset, self.m1_stack) def add_lvs_correspondence_points(self): @@ -942,7 +942,7 @@ class bank(design.design): control_mid_pos = self.bus_xoffset[port][control_signal] control_pos = vector(self.bus_xoffset[port][control_signal].x ,pin_pos.y) self.add_wire(("metal1","via1","metal2"), [control_mid_pos, control_pos, pin_pos]) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=control_pos) @@ -957,7 +957,7 @@ class bank(design.design): control_x_offset = self.bus_xoffset[port][control_signal].x control_pos = vector(control_x_offset, mid_pos.y) self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos]) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=control_pos) def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index 296cef8b..14b6b203 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -258,7 +258,7 @@ class bank_select(design.design): logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1m2.height,0) input_pos = vector(xoffset_bank_signal, logic_pos.y) self.add_path("metal2",[logic_pos, input_pos]) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=logic_pos, directions=("H","H")) @@ -266,10 +266,10 @@ class bank_select(design.design): # Connect the logic A input to the input pin logic_pos = logic_inst.get_pin("A").lc() input_pos = vector(0,logic_pos.y) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=logic_pos, directions=("H","H")) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=logic_pos, directions=("H","H")) self.add_layout_pin_segment_center(text=input_name, @@ -301,10 +301,10 @@ class bank_select(design.design): # Add pins in two locations for xoffset in [a_xoffset, b_xoffset]: pin_pos = vector(xoffset, supply_pin.cy()) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=pin_pos, directions=("H","H")) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=pin_pos, directions=("H","H")) self.add_layout_pin_rect_center(text=n, diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 4648519a..9c7cafd8 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -221,9 +221,9 @@ class hierarchical_decoder(design.design): def route_input_rail(self, input_offset, output_offset): """ Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """ - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=input_offset) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=output_offset) self.add_path(("metal3"), [input_offset, output_offset]) @@ -585,7 +585,7 @@ class hierarchical_decoder(design.design): """ Connect the routing rail to the given metal1 pin """ rail_pos = vector(self.predecode_rails[rail_name].x,pin.lc().y) self.add_path("metal1", [rail_pos, pin.lc()]) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=rail_pos) @@ -595,10 +595,10 @@ class hierarchical_decoder(design.design): # It would be fixed with a channel router. mid_point = vector(pin.cx(), pin.cy()+self.inv.height/2) rail_pos = vector(self.predecode_rails[rail_name].x,mid_point.y) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=pin.center()) self.add_wire(("metal3","via2","metal2"), [rail_pos, mid_point, pin.uc()]) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=rail_pos) def input_load(self): diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index bec0ce06..0de67cae 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -184,9 +184,9 @@ class hierarchical_predecode(design.design): in_pos = vector(self.input_rails[in_pin].x,y_offset) a_pos = vector(self.decode_rails[a_pin].x,y_offset) self.add_path("metal1",[in_pos, a_pos]) - self.add_via_center(layers = ("metal1", "via1", "metal2"), + self.add_via_center(layers = self.m1_stack, offset=[self.input_rails[in_pin].x, y_offset]) - self.add_via_center(layers = ("metal1", "via1", "metal2"), + self.add_via_center(layers = self.m1_stack, offset=[self.decode_rails[a_pin].x, y_offset]) def route_output_inverters(self): @@ -227,7 +227,7 @@ class hierarchical_predecode(design.design): right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(),0) rail_pos = vector(self.decode_rails[out_pin].x,y_offset) self.add_path("metal1", [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) - self.add_via_center(layers = ("metal1", "via1", "metal2"), + self.add_via_center(layers = self.m1_stack, offset=rail_pos) @@ -235,7 +235,7 @@ class hierarchical_predecode(design.design): inv_in_pos = self.in_inst[inv_num].get_pin("A").lc() in_pos = vector(self.input_rails[in_pin].x,inv_in_pos.y) self.add_path("metal1", [in_pos, inv_in_pos]) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=in_pos) @@ -256,7 +256,7 @@ class hierarchical_predecode(design.design): pin_pos = self.nand_inst[k].get_pin(gate_pin).lc() rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y) self.add_path("metal1", [rail_pos, pin_pos]) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=rail_pos) diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index 2f933a2d..3459f5e0 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -452,13 +452,13 @@ class multibank(design.design): out_pos = self.bank_select_inst.get_pin(gated_name).rc() bus_pos = vector(self.bus_xoffset[gated_name], out_pos.y) self.add_path("metal3",[out_pos, bus_pos]) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=bus_pos, rotate=90) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=out_pos, rotate=90) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=out_pos, rotate=90) @@ -586,9 +586,9 @@ class multibank(design.design): tri_gate_in = self.tri_gate_array_inst.get_pin("in_{}".format(i)).lc() sa_data_out = self.sense_amp_array_inst.get_pin("data_{}".format(i)).bc() - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=tri_gate_in) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=sa_data_out) self.add_path("metal3",[sa_data_out,tri_gate_in]) @@ -766,7 +766,7 @@ class multibank(design.design): for (control_signal, pin_pos) in connection: control_pos = vector(self.bus_xoffset[control_signal].x ,pin_pos.y) self.add_path("metal1", [control_pos, pin_pos]) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=control_pos, rotate=90) @@ -778,7 +778,7 @@ class multibank(design.design): control_pos = vector(control_x_offset + self.m1_width, mid_pos.y) self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos]) control_via_pos = vector(control_x_offset, mid_pos.y) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=control_via_pos, rotate=90) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index c3473803..a5bc4399 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -475,7 +475,7 @@ class port_data(design.design): end_pos = vector(length, wdriver_en_pin.cy()) # Add via for the write driver array's enable input - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=end_pos) # Route between write mask AND array and write driver array @@ -626,7 +626,7 @@ class port_data(design.design): bottom_names = [bottom_inst.get_pin(bottom_bl_name.format(bit+bottom_start_bit)), bottom_inst.get_pin(bottom_br_name.format(bit+bottom_start_bit))] top_names = [top_inst.get_pin(top_bl_name.format(bit+top_start_bit)), top_inst.get_pin(top_br_name.format(bit+top_start_bit))] route_map = list(zip(bottom_names, top_names)) - self.create_horizontal_channel_route(route_map, offset) + self.create_horizontal_channel_route(route_map, offset, self.m1_stack) def connect_bitlines(self, inst1, inst2, num_bits, diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 598886c0..21ee4a8d 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -99,13 +99,13 @@ class sense_amp_array(design.design): inst = self.local_insts[i] gnd_pos = inst.get_pin("gnd").center() - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=gnd_pos) self.add_layout_pin_rect_center(text="gnd", layer="metal3", offset=gnd_pos) vdd_pos = inst.get_pin("vdd").center() - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=vdd_pos) self.add_layout_pin_rect_center(text="vdd", layer="metal3", diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 7e3beaad..3e6420b9 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -191,11 +191,11 @@ class single_level_column_mux_array(design.design): # This via is on the right of the wire - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=bl_out_offset) # This via is on the left of the wire - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=br_out_offset) else: @@ -204,10 +204,10 @@ class single_level_column_mux_array(design.design): self.add_path("metal2", [ br_out_offset, br_out_offset_end]) # This via is on the right of the wire - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=bl_out_offset) # This via is on the left of the wire - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=br_out_offset) def get_drain_cin(self): diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index 7d1c21d0..501e2389 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -100,7 +100,7 @@ class tri_gate_array(design.design): for n in ["vdd", "gnd"]: for supply_pin in self.tri_inst[i].get_pins(n): pin_pos = supply_pin.center() - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=pin_pos) self.add_layout_pin_rect_center(text=n, layer="metal3", diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index fbd800b2..99365659 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -158,7 +158,7 @@ class wordline_driver(design.design): self.add_segment_center(layer="metal1", start=clk_offset, end=a_pos) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=clk_offset) # Nand2 out to 2nd inv @@ -185,14 +185,14 @@ class wordline_driver(design.design): layer="metal1", start=input_offset, end=mid_via_offset) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=mid_via_offset, directions=("V", "V")) # now connect to the nand2 B self.add_path("metal2", [mid_via_offset, b_pos]) contact_offset = b_pos - vector(0.5 * contact.m1m2.height, 0) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=contact_offset, directions=("H", "H")) diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 100ee3a2..4dfa938c 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -143,7 +143,7 @@ class write_driver_array(design.design): for pin in pin_list: pin_pos = pin.center() # Add the M2->M3 stack - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=pin_pos) self.add_layout_pin_rect_center(text=n, layer="metal3", diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 258bbd8d..3a4ec651 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -117,9 +117,9 @@ class write_mask_and_array(design.design): layer="metal3", offset=beg_en_pin.bc(), width=end_en_pin.cx() - beg_en_pin.cx() + en_to_edge) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy())) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy())) else: self.add_layout_pin(text="en", @@ -134,9 +134,9 @@ class write_mask_and_array(design.design): # Add via connections to metal3 for AND array's B pin en_pin = self.and2_insts[i].get_pin("B") - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=en_pin.center()) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=en_pin.center()) self.add_power_pin("gnd", vector(supply_pin.width() + i * self.wmask_en_len, 0)) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 0c1c0b52..5ad98fad 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -115,7 +115,7 @@ class pgate(design.design): # Non-preferred direction via - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=contact_offset, directions=directions) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 2b8ec7b7..5c53480b 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -115,8 +115,8 @@ class pinv(pgate.pgate): # Divide the height in half. Could divide proportional to beta, # but this makes connecting wells of multiple cells easier. # Subtract the poly space under the rail of the tx - nmos_height_available = 0.5 * tx_height_available - 0.5 * drc("poly_to_poly") - pmos_height_available = 0.5 * tx_height_available - 0.5 * drc("poly_to_poly") + nmos_height_available = 0.5 * tx_height_available - 0.5 * self.poly_space + pmos_height_available = 0.5 * tx_height_available - 0.5 * self.poly_space debug.info(2, "Height avail {0:.4f} PMOS {1:.4f} NMOS {2:.4f}".format(tx_height_available, diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index 75b7ce6f..579e1198 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -126,9 +126,9 @@ class pinvbuf(pgate.pgate): z1_pin = self.inv1_inst.get_pin("Z") a4_pin = self.inv4_inst.get_pin("A") mid_point = vector(z1_pin.cx(), a4_pin.cy()) - self.add_wire(("metal1", "via1", "metal2"), + self.add_wire(self.m1_stack, [z1_pin.center(), mid_point, a4_pin.center()]) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=z1_pin.center()) def add_layout_pins(self): @@ -161,21 +161,21 @@ class pinvbuf(pgate.pgate): self.add_layout_pin_rect_center(text="Z", layer="metal2", offset=z_pin.center()) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=z_pin.center()) zb_pin = self.inv3_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Zb", layer="metal2", offset=zb_pin.center()) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=zb_pin.center()) a_pin = self.inv1_inst.get_pin("A") self.add_layout_pin_rect_center(text="A", layer="metal2", offset=a_pin.center()) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) def determine_clk_buf_stage_efforts(self, external_cout, inp_is_rise=False): diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index c5c69fd4..4623048c 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -225,13 +225,13 @@ class pnand2(pgate.pgate): mid1_offset = vector(out_offset.x, top_pin_offset.y) mid2_offset = vector(out_offset.x, bottom_pin_offset.y) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=pmos_pin.center(), directions=("V", "H")) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=nmos_pin.center(), directions=("V", "H")) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=out_offset) # PMOS1 to mid-drain to NMOS2 drain diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 621829f1..6d885e25 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -237,11 +237,11 @@ class pnand3(pgate.pgate): nmos3_pin = self.nmos3_inst.get_pin("D") # Go up to metal2 for ease on all output pins - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=pmos1_pin.center()) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=pmos3_pin.center()) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=nmos3_pin.center()) # PMOS3 and NMOS3 are drain aligned @@ -251,7 +251,7 @@ class pnand3(pgate.pgate): self.add_path("metal2", [pmos1_pin.bc(), mid_offset, nmos3_pin.uc()]) # This extends the output to the edge of the cell - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=mid_offset) self.add_layout_pin_rect_center(text="Z", layer="metal1", diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index a99253cd..a79d19a0 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -216,9 +216,9 @@ class pnor2(pgate.pgate): nmos2_pin = self.nmos2_inst.get_pin("D") # Go up to metal2 for ease on all output pins - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=pmos_pin.center()) - m1m2_contact = self.add_via_center(layers=("metal1", "via1", "metal2"), + m1m2_contact = self.add_via_center(layers=self.m1_stack, offset=nmos_pin.center()) mid1_offset = vector(pmos_pin.center().x, nmos2_pin.center().y) @@ -231,7 +231,7 @@ class pnor2(pgate.pgate): self.add_path("metal2", [nmos_pin.rc(), mid1_offset, mid2_offset]) # This extends the output to the edge of the cell - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=mid3_offset) self.add_layout_pin_rect_center(text="Z", layer="metal1", diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index bd391ecc..d27b9f9c 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -159,7 +159,7 @@ class precharge(design.design): # adds the en contact to connect the gates to the en rail on metal1 offset = self.lower_pmos_inst.get_pin("G").ul() \ + vector(0, 0.5 * self.poly_space) - self.add_via_center(layers=("poly", "contact", "metal1"), + self.add_via_center(layers=self.poly_stack, offset=offset) # adds the en rail on metal1 @@ -202,7 +202,6 @@ class precharge(design.design): self.bl_pin = self.add_layout_pin(text="bl", layer="metal2", offset=offset, - width=drc("minwidth_metal2"), height=self.height) # adds the BR on metal 2 @@ -211,7 +210,6 @@ class precharge(design.design): self.br_pin = self.add_layout_pin(text="br", layer="metal2", offset=offset, - width=drc("minwidth_metal2"), height=self.height) def connect_to_bitlines(self): @@ -233,23 +231,22 @@ class precharge(design.design): Adds contacts/via from metal1 to metal2 for bit-lines """ - stack = ("metal1", "via1", "metal2") upper_pin = self.upper_pmos1_inst.get_pin("S") lower_pin = self.lower_pmos_inst.get_pin("S") # BL goes up to M2 at the transistor - self.bl_contact =self.add_via_center(layers=stack, + self.bl_contact =self.add_via_center(layers=self.m1_stack, offset=upper_pin.center(), directions=("V", "V")) - self.add_via_center(layers=stack, + self.add_via_center(layers=self.m1_stack, offset=lower_pin.center(), directions=("V", "V")) # BR routes over on M1 first - self.add_via_center(layers=stack, + self.add_via_center(layers=self.m1_stack, offset=vector(self.br_pin.cx(), upper_pin.cy()), directions=("V", "V")) - self.add_via_center(layers=stack, + self.add_via_center(layers=self.m1_stack, offset=vector(self.br_pin.cx(), lower_pin.cy()), directions=("V", "V")) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 588152c0..d0854711 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -52,7 +52,6 @@ class ptx(design.design): self.connect_poly = connect_poly self.num_contacts = num_contacts - # Do NOT create the netlist and layout (not a pgate) # Since it has variable height, it is not a pgate. self.create_netlist() # We must always create ptx layout for pbitcell diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index ffe313c8..a642eeca 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -126,16 +126,16 @@ class single_level_column_mux(pgate.pgate): nmos_upper_d_pin = self.nmos_upper.get_pin("D") # Add vias to bl, br_out, nmos_upper/S, nmos_lower/D - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=bl_pin.bc(), directions=("V", "V")) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=br_out_pin.uc(), directions=("V", "V")) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=nmos_upper_s_pin.center(), directions=("V", "V")) - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=nmos_lower_d_pin.center(), directions=("V", "V")) @@ -181,9 +181,9 @@ class single_level_column_mux(pgate.pgate): well_type="p") # Add the M1->M2->M3 stack - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=active_pos) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=active_pos) self.add_layout_pin_rect_center(text="gnd", layer="metal3", diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 9e578c7c..6c887790 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -371,12 +371,12 @@ class sram_1bank(sram_base): if self.write_size: for x in dff_names: pin_offset = self.data_dff_insts[port].get_pin(x).center() - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=pin_offset, directions = ("V", "V")) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=pin_offset) - self.add_via_center(layers=("metal3", "via3", "metal4"), + self.add_via_center(layers=self.m3_stack, offset=pin_offset) bank_names = ["din{0}_{1}".format(port,x) for x in range(self.word_size)] @@ -387,20 +387,21 @@ class sram_1bank(sram_base): pin_offset = self.bank_inst.get_pin(x).uc() else: pin_offset = self.bank_inst.get_pin(x).bc() - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=pin_offset) - self.add_via_center(layers=("metal2", "via2", "metal3"), + self.add_via_center(layers=self.m2_stack, offset=pin_offset) - self.add_via_center(layers=("metal3", "via3", "metal4"), + self.add_via_center(layers=self.m3_stack, offset=pin_offset) route_map = list(zip(bank_pins, dff_pins)) if self.write_size: - self.create_horizontal_channel_route(netlist=route_map, - offset=offset, - layer_stack=("metal3", "via3", "metal4")) + layer_stack = self.m3_stack else: - self.create_horizontal_channel_route(route_map, offset) + layer_stack = self.m1_stack + self.create_horizontal_channel_route(netlist=route_map, + offset=offset, + layer_stack=layer_stack) def route_wmask_dff(self): """ Connect the output of the wmask flops to the write mask AND array """ @@ -415,7 +416,7 @@ class sram_1bank(sram_base): dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names] for x in dff_names: offset_pin = self.wmask_dff_insts[port].get_pin(x).center() - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=offset_pin, directions=("V", "V")) @@ -423,12 +424,14 @@ class sram_1bank(sram_base): bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] for x in bank_names: offset_pin = self.bank_inst.get_pin(x).center() - self.add_via_center(layers=("metal1", "via1", "metal2"), + self.add_via_center(layers=self.m1_stack, offset=offset_pin) route_map = list(zip(bank_pins, dff_pins)) - self.create_horizontal_channel_route(route_map,offset) + self.create_horizontal_channel_route(netlist=route_map, + offset=offset, + layer_stack=self.m1_stack) def add_lvs_correspondence_points(self): diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 74d5ae1e..0ea079e4 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -25,7 +25,7 @@ class wire_test(openram_test): min_space = 2 * (tech.drc["minwidth_poly"] + tech.drc["minwidth_metal1"]) - layer_stack = ("poly", "contact", "metal1") + layer_stack = tech.poly_stack old_position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], @@ -42,7 +42,7 @@ class wire_test(openram_test): min_space = 2 * (tech.drc["minwidth_poly"] + tech.drc["minwidth_metal1"]) - layer_stack = ("poly", "contact", "metal1") + layer_stack = tech.poly_stack old_position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], @@ -59,7 +59,7 @@ class wire_test(openram_test): min_space = 2 * (tech.drc["minwidth_metal2"] + tech.drc["minwidth_metal1"]) - layer_stack = ("metal1", "via1", "metal2") + layer_stack = tech.m1_stack position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], @@ -76,7 +76,7 @@ class wire_test(openram_test): min_space = 2 * (tech.drc["minwidth_metal2"] + tech.drc["minwidth_metal1"]) - layer_stack = ("metal2", "via1", "metal1") + layer_stack = tech.m2_stack[::-1] position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], @@ -92,7 +92,7 @@ class wire_test(openram_test): min_space = 2 * (tech.drc["minwidth_metal2"] + tech.drc["minwidth_metal3"]) - layer_stack = ("metal2", "via2", "metal3") + layer_stack = tech.m2_stack position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], @@ -109,7 +109,7 @@ class wire_test(openram_test): min_space = 2 * (tech.drc["minwidth_metal2"] + tech.drc["minwidth_metal3"]) - layer_stack = ("metal3", "via2", "metal2") + layer_stack = tech.m2_stack[::-1] position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 23a0d9fe..3f42e8b3 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -34,18 +34,18 @@ GDS["zoom"] = 0.5 poly_stack = ("poly", "poly_contact", "metal1") active_stack = ("active", "active_contact", "metal1") -metal1_stack = ("metal1", "via1", "metal2") -metal2_stack = ("metal2", "via2", "metal3") -metal3_stack = ("metal3", "via3", "metal4") +m1_stack = ("metal1", "via1", "metal2") +m2_stack = ("metal2", "via2", "metal3") +m3_stack = ("metal3", "via3", "metal4") # The FEOL stacks get us up to metal1 feol_stacks = [poly_stack, active_stack] # The BEOL stacks are metal1 and up -beol_stacks = [metal1_stack, - metal2_stack, - metal3_stack] +beol_stacks = [m1_stack, + m2_stack, + m3_stack] layer_stacks = feol_stacks + beol_stacks From 3ad7c8a8b530e87b2ae75def4b9a4faa214f8f91 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 13 Dec 2019 14:25:00 -0800 Subject: [PATCH 060/521] Fix freepdk45 tech layer stacks --- technology/freepdk45/tech/tech.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index f8dc7d06..fcdb2c10 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -34,18 +34,18 @@ GDS["zoom"] = 0.05 poly_stack = ("poly", "contact", "metal1") active_stack = ("active", "contact", "metal1") -metal1_stack = ("metal1", "via1", "metal2") -metal2_stack = ("metal2", "via2", "metal3") -metal3_stack = ("metal3", "via3", "metal4") +m1_stack = ("metal1", "via1", "metal2") +m2_stack = ("metal2", "via2", "metal3") +m3_stack = ("metal3", "via3", "metal4") # The FEOL stacks get us up to metal1 feol_stacks = [poly_stack, active_stack] # The BEOL stacks are metal1 and up -beol_stacks = [metal1_stack, - metal2_stack, - metal3_stack] +beol_stacks = [m1_stack, + m2_stack, + m3_stack] layer_stacks = feol_stacks + beol_stacks From f71cfe0d9d41c36c3739c49a27c239a26cac01b5 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 13 Dec 2019 14:56:14 -0800 Subject: [PATCH 061/521] Generalize active and poly stacks --- compiler/bitcells/pbitcell.py | 4 ++-- compiler/pgates/pgate.py | 4 ++-- compiler/pgates/precharge.py | 2 +- compiler/pgates/ptristate_inv.py | 2 +- compiler/pgates/ptx.py | 6 +++--- compiler/pgates/single_level_column_mux.py | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 0f4b8183..8f9cd602 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -1019,7 +1019,7 @@ class pbitcell(bitcell_base.bitcell_base): # add well contacts # connect pimplants to gnd offset = vector(0, self.gnd_position.y) - self.add_via_center(layers=("active", "contact", "metal1"), + self.add_via_center(layers=self.active_stack, offset=offset, directions=("H", "H"), implant_type="p", @@ -1027,7 +1027,7 @@ class pbitcell(bitcell_base.bitcell_base): # connect nimplants to vdd offset = vector(0, self.vdd_position.y) - self.add_via_center(layers=("active", "contact", "metal1"), + self.add_via_center(layers=self.active_stack, offset=offset, directions=("H", "H"), implant_type="n", diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 5ad98fad..b55ad9c3 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -168,7 +168,7 @@ class pgate(design.design): def add_nwell_contact(self, pmos, pmos_pos): """ Add an nwell contact next to the given pmos device. """ - layer_stack = ("active", "contact", "metal1") + layer_stack = self.active_stack # To the right a spacing away from the pmos right active edge contact_xoffset = pmos_pos.x + pmos.active_width \ @@ -221,7 +221,7 @@ class pgate(design.design): def add_pwell_contact(self, nmos, nmos_pos): """ Add an pwell contact next to the given nmos device. """ - layer_stack = ("active", "contact", "metal1") + layer_stack = self.active_stack pwell_position = vector(0, -0.5 * self.m1_width) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index d27b9f9c..9641a1f3 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -177,7 +177,7 @@ class precharge(design.design): well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \ + vector(0, self.upper_pmos1_inst.uy() + contact.well.height / 2 \ + drc("well_extend_active")) - self.add_via_center(layers=("active", "contact", "metal1"), + self.add_via_center(layers=self.active_stack, offset=well_contact_pos, implant_type="n", well_type="n") diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index 2a972407..4a17b46a 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -191,7 +191,7 @@ class ptristate_inv(pgate.pgate): supplies AFTER the wells are created """ - layer_stack = ("active", "contact", "metal1") + layer_stack = self.active_stack drain_pos = self.nmos1_inst.get_pin("S").center() vdd_pos = self.get_pin("vdd").center() diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index d0854711..61610a88 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -124,7 +124,7 @@ class ptx(design.design): # This is not actually instantiated but used for calculations self.active_contact = factory.create(module_type="contact", - layer_stack=("active", "contact", "metal1"), + layer_stack=self.active_stack, dimensions=(1, self.num_contacts)) @@ -373,7 +373,7 @@ class ptx(design.design): [source_positions,drain_positions] = self.get_contact_positions() for pos in source_positions: - contact=self.add_via_center(layers=("active", "contact", "metal1"), + contact=self.add_via_center(layers=self.active_stack, offset=pos, size=(1, self.num_contacts), directions=("H","V"), @@ -387,7 +387,7 @@ class ptx(design.design): for pos in drain_positions: - contact=self.add_via_center(layers=("active", "contact", "metal1"), + contact=self.add_via_center(layers=self.active_stack, offset=pos, size=(1, self.num_contacts), directions=("H","V"), diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index a642eeca..525c1680 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -175,7 +175,7 @@ class single_level_column_mux(pgate.pgate): # Add it to the right, aligned in between the two tx active_pos = vector(self.bitcell.width, self.nmos_upper.by() - 0.5 * self.poly_space) - self.add_via_center(layers=("active", "contact", "metal1"), + self.add_via_center(layers=self.active_stack, offset=active_pos, implant_type="p", well_type="p") From 233ec010fffecd2f1fe45d4f9bee3f0ec4dbe00a Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 16 Dec 2019 14:27:06 +0100 Subject: [PATCH 062/521] modules: Create a class that wraps all the module class names this removes hard coded values from the module instatiations. It also allows users to override certain modules with their custom cells. Signed-off-by: Bastian Koppelmann --- compiler/modules/module_type.py | 70 +++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 compiler/modules/module_type.py diff --git a/compiler/modules/module_type.py b/compiler/modules/module_type.py new file mode 100644 index 00000000..624a62c8 --- /dev/null +++ b/compiler/modules/module_type.py @@ -0,0 +1,70 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# + +class ModuleType(): + """ + This is a class that maps cell names to python classes implementing them. + """ + def __init__(self): + self.names = {} + self.names['contact'] = 'contact' + self.names['precharge'] = 'precharge' + self.names['pinv'] = 'pinv' + self.names['dff_buf'] = 'dff_buf' + self.names['sense_amp'] = 'sense_amp' + self.names['bitcell'] = 'bitcell' + self.names['port_data'] = 'port_data' + self.names['port_address'] = 'port_address' + self.names['replica_bitcell_array'] = 'replica_bitcell_array' + self.names['bank_select'] = 'bank_select' + self.names['dff'] = 'dff' + self.names['pinvbuf'] = 'pinvbuf' + self.names['hierarchical_predecode2x4'] = 'hierarchical_predecode2x4' + self.names['hierarchical_predecode3x8'] = 'hierarchical_predecode3x8' + self.names['replica_bitcell'] = 'replica_bitcell' + self.names['dummy_bitcell'] = 'dummy_bitcell' + self.names['bitcell'] = 'bitcell' + self.names['pnor2'] = 'pnor2' + self.names['pnand2'] = 'pnand2' + self.names['precharge_array'] = 'precharge_array' + self.names['sense_amp_array'] = 'sense_amp_array' + self.names['column_mux_array'] = 'column_mux_array' + self.names['write_driver_array'] = 'write_driver_array' + self.names['write_mask_and_array'] = 'write_mask_and_array' + self.names['pand2'] = 'pand2' + self.names['write_driver'] = 'write_driver' + self.names['dff_buf_array'] = 'dff_buf_array' + self.names['pdriver'] = 'pdriver' + self.names['pand3'] = 'pand3' + self.names['delay_chain'] = 'delay_chain' + self.names['decoder'] = 'decoder' + self.names['wordline_driver'] = 'wordline_driver' + self.names['tri_gate'] = 'tri_gate' + self.names['tri_gate_array'] = 'tri_gate_array' + self.names['bitcell_array'] = 'bitcell_array' + self.names['replica_column'] = 'replica_column' + self.names['dummy_array'] = 'dummy_array' + self.names['single_level_column_mux_array'] = 'single_level_column_mux_array' + self.names['single_level_column_mux'] = 'single_level_column_mux' + self.names['sram'] = 'sram' + self.names['ptx'] = 'ptx' + self.names['hierarchical_decoder'] = 'hierarchical_decoder' + self.names['pbuf'] = 'pbuf' + self.names['control_logic'] = 'control_logic' + self.names['bank'] = 'bank' + self.names['pbitcell'] = 'pbitcell' + self.names['pnand3'] = 'pnand3' + self.names['pwrite_driver'] = 'pwrite_driver' + self.names['ptristate_inv'] = 'ptristate_inv' + self.names['ptristate_buf'] = 'ptristate_buf' + + def __setitem__(self, b, c): + self.names[b] = c + + def __getitem__(self, b): + return self.names[b] From 1380cbc50c733ccffeb816111061974fbeb94c0a Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 16 Dec 2019 14:40:52 +0100 Subject: [PATCH 063/521] technology: Add tech_module to all technologies this allows each technology to override each cell class. Signed-off-by: Bastian Koppelmann --- technology/freepdk45/tech/tech.py | 7 +++++++ technology/scn3me_subm/tech/tech.py | 7 +++++++ technology/scn4m_subm/tech/tech.py | 7 +++++++ 3 files changed, 21 insertions(+) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index fcdb2c10..839a38af 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -7,10 +7,17 @@ # import os from design_rules import * +from module_type import * """ File containing the process technology parameters for FreePDK 45nm. """ +# This uses the default classes to instantiate module from +# '$OPENRAM_HOME/compiler/modules'. +# Using tech_modules['cellname'] you can override each class by providing a custom +# implementation in '$OPENRAM_TECHDIR/modules/' +# For example: tech_modules['contact'] = 'contact_freepdk45' +tech_modules = ModuleType() #GDS file info GDS = {} diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 6fc68686..cb476df5 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -1,9 +1,16 @@ import os from design_rules import * +from module_type import * """ File containing the process technology parameters for SCMOS 3me, subm, 180nm. """ +# This uses the default classes to instantiate module from +# '$OPENRAM_HOME/compiler/modules'. +# Using tech_modules['cellname'] you can override each class by providing a custom +# implementation in '$OPENRAM_TECHDIR/modules/' +# For example: tech_modules['contact'] = 'contact_scn3me' +tech_modules = ModuleType() #GDS file info GDS={} diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 3f42e8b3..d17a0927 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -7,10 +7,17 @@ # import os from design_rules import * +from module_type import * """ File containing the process technology parameters for SCMOS 4m, 0.35um """ +# This uses the default classes to instantiate module from +# '$OPENRAM_HOME/compiler/modules'. +# Using tech_modules['cellname'] you can override each class by providing a custom +# implementation in '$OPENRAM_TECHDIR/modules/' +# For example: tech_modules['contact'] = 'contact_scn4m' +tech_modules = ModuleType() #GDS file info GDS={} From 74cd4f989d82ba9a92834cae821e3fdbb96116e3 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 16 Dec 2019 16:56:06 +0100 Subject: [PATCH 064/521] Remove hardcoded module class names Signed-off-by: Bastian Koppelmann --- compiler/sram_factory.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index bd602980..e971efc0 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -6,6 +6,7 @@ # All rights reserved. # from globals import OPTS +from tech import tech_modules class sram_factory: @@ -37,6 +38,8 @@ class sram_factory: A generic function to create a module with a given module_type. The args are passed directly to the module constructor. """ + + module_type = tech_modules[module_type] # if name!="": # # This is a special case where the name and type don't match # # Can't be overridden in the config file From 306c0b92c3a098f391d3b2b064bb428c558a5ac8 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 16 Dec 2019 16:10:09 +0100 Subject: [PATCH 065/521] globals: Add tech module path to Pythonpath if it exists Signed-off-by: Bastian Koppelmann --- compiler/globals.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/compiler/globals.py b/compiler/globals.py index e9b77d66..8bca4b3f 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -504,6 +504,11 @@ def import_tech(): except ImportError: debug.error("Could not load tech module.", -1) + # Add custom modules of the technology to the path, if they exist + custom_mod_path = os.path.join(tech_path, "modules/") + if os.path.exists(custom_mod_path): + sys.path.append(custom_mod_path) + def print_time(name, now_time, last_time=None, indentation=2): """ Print a statement about the time delta. """ From be4893839bd8bd3ca987595253c85b652c7a2ed0 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 16 Dec 2019 10:05:52 -0800 Subject: [PATCH 066/521] Remove old drc/lvs override name --- compiler/example_configs/example_config_1w_1r_scn4m_subm.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py index 330d8d46..55ac4016 100644 --- a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py +++ b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py @@ -19,6 +19,3 @@ output_name = "sram_1w_1r_{0}_{1}_{2}".format(word_size, num_words, tech_name) -drc_name = "magic" -lvs_name = "netgen" -pex_name = "magic" From 2a9129ef45bd916385289ef8f023cb93d70f6bd8 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 16 Dec 2019 10:11:26 -0800 Subject: [PATCH 067/521] Small fix to tech and config over-rides --- compiler/sram_factory.py | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index e971efc0..d3dadf7d 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -6,8 +6,6 @@ # All rights reserved. # from globals import OPTS -from tech import tech_modules - class sram_factory: """ @@ -38,8 +36,8 @@ class sram_factory: A generic function to create a module with a given module_type. The args are passed directly to the module constructor. """ - - module_type = tech_modules[module_type] + from tech import tech_modules + real_module_type = tech_modules[module_type] # if name!="": # # This is a special case where the name and type don't match # # Can't be overridden in the config file @@ -47,21 +45,21 @@ class sram_factory: if hasattr(OPTS, module_type): # Retrieve the name from OPTS if it exists, # otherwise just use the name - module_type = getattr(OPTS, module_type) + real_module_type = getattr(OPTS, module_type) # Either retrieve the already loaded module or load it try: - mod = self.modules[module_type] + mod = self.modules[real_module_type] except KeyError: import importlib - c = importlib.reload(__import__(module_type)) - mod = getattr(c, module_type) - self.modules[module_type] = mod - self.module_indices[module_type] = 0 - self.objects[module_type] = [] + c = importlib.reload(__import__(real_module_type)) + mod = getattr(c, real_module_type) + self.modules[real_module_type] = mod + self.module_indices[real_module_type] = 0 + self.objects[real_module_type] = [] # Either retreive a previous object or create a new one - for obj in self.objects[module_type]: + for obj in self.objects[real_module_type]: (obj_kwargs, obj_item) = obj # Must have the same dictionary exactly (conservative) if obj_kwargs == kwargs: @@ -72,19 +70,19 @@ class sram_factory: # spice and gds files can be found. if len(kwargs) > 0: # Create a unique name and increment the index - module_name = "{0}_{1}".format(module_type, - self.module_indices[module_type]) - self.module_indices[module_type] += 1 + module_name = "{0}_{1}".format(real_module_type, + self.module_indices[real_module_type]) + self.module_indices[real_module_type] += 1 else: - module_name = module_type + module_name = real_module_type - # type_str = "type={}".format(module_type) + # type_str = "type={}".format(real_module_type) # name_str = "name={}".format(module_name) # kwargs_str = "kwargs={}".format(str(kwargs)) # import debug # debug.info(0, "New module:" + type_str + name_str + kwargs_str) obj = mod(name=module_name, **kwargs) - self.objects[module_type].append((kwargs, obj)) + self.objects[real_module_type].append((kwargs, obj)) return obj def get_mods(self, module_type): From 5176a70f846527bc97008716567608f4a12c6651 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 16 Dec 2019 10:21:24 -0800 Subject: [PATCH 068/521] Add comments to module importing routines --- compiler/sram_factory.py | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index d3dadf7d..4b9b13d9 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -36,12 +36,14 @@ class sram_factory: A generic function to create a module with a given module_type. The args are passed directly to the module constructor. """ - from tech import tech_modules - real_module_type = tech_modules[module_type] - # if name!="": - # # This is a special case where the name and type don't match - # # Can't be overridden in the config file - # module_name = name + try: + from tech import tech_modules + real_module_type = tech_modules[module_type] + except ImportError: + # If they didn't define these, then don't use the option types. + # Primarily for backward compatibility and simplicity of tech files. + pass + if hasattr(OPTS, module_type): # Retrieve the name from OPTS if it exists, # otherwise just use the name @@ -49,8 +51,10 @@ class sram_factory: # Either retrieve the already loaded module or load it try: + # Load a cached version from previous usage mod = self.modules[real_module_type] except KeyError: + # Dynamically load the module import importlib c = importlib.reload(__import__(real_module_type)) mod = getattr(c, real_module_type) From f30d0b919784c39d13788f572fc01a405c03c405 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 16 Dec 2019 12:04:33 -0800 Subject: [PATCH 069/521] Fix KeyError for bitell types. --- compiler/modules/module_type.py | 4 ++++ compiler/sram_factory.py | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/compiler/modules/module_type.py b/compiler/modules/module_type.py index 624a62c8..90e1fdbe 100644 --- a/compiler/modules/module_type.py +++ b/compiler/modules/module_type.py @@ -67,4 +67,8 @@ class ModuleType(): self.names[b] = c def __getitem__(self, b): + if b not in self.names.keys(): + raise KeyError + return self.names[b] + diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 4b9b13d9..f5e19d87 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -36,6 +36,8 @@ class sram_factory: A generic function to create a module with a given module_type. The args are passed directly to the module constructor. """ + real_module_type = module_type + try: from tech import tech_modules real_module_type = tech_modules[module_type] @@ -43,6 +45,9 @@ class sram_factory: # If they didn't define these, then don't use the option types. # Primarily for backward compatibility and simplicity of tech files. pass + except KeyError: + # If it wasn't a tech module type, we can ignore that too. + pass if hasattr(OPTS, module_type): # Retrieve the name from OPTS if it exists, From acbbbe94031ce62f6fd222d155630a6115961935 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 16 Dec 2019 12:07:40 -0800 Subject: [PATCH 070/521] Make exception more readable. --- compiler/sram_factory.py | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index f5e19d87..6bb3578c 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -36,18 +36,16 @@ class sram_factory: A generic function to create a module with a given module_type. The args are passed directly to the module constructor. """ - real_module_type = module_type - try: from tech import tech_modules real_module_type = tech_modules[module_type] except ImportError: # If they didn't define these, then don't use the option types. # Primarily for backward compatibility and simplicity of tech files. - pass + real_module_type = module_type except KeyError: # If it wasn't a tech module type, we can ignore that too. - pass + real_module_type = module_type if hasattr(OPTS, module_type): # Retrieve the name from OPTS if it exists, From 3eb0dad06a0f4cb6842c5156560cc09a278b0e27 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 16 Dec 2019 15:33:30 -0800 Subject: [PATCH 071/521] Remove cells from DRC/LVS in the blackbox tech list. --- compiler/tests/01_library_drc_test.py | 12 +++++++----- compiler/tests/02_library_lvs_test.py | 9 +++++++-- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index ad8671d2..42fa1335 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -42,11 +42,13 @@ def setup_files(): files = os.listdir(gds_dir) nametest = re.compile("\.gds$", re.IGNORECASE) gds_files = list(filter(nametest.search, files)) - import tech - if tech.blackbox_bitcell: - # Ignore DRC of all bitcells - nametest = re.compile("cell", re.IGNORECASE) - gds_files = list(filter(lambda v: not nametest.search(v), gds_files)) + + try: + from tech import blackbox_cells + gds_files = list(set(gds_files) - set(blackbox_cells)) + except ImportError: + pass + return (gds_dir, gds_files) diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 5f53753b..35ac5d76 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -62,8 +62,13 @@ def setup_files(): tempnames[i] = re.sub('\.gds$', '', tempnames[i]) tempnames[i] = re.sub('\.sp$', '', tempnames[i]) - # remove duplicate base names - nameset = set(tempnames) + try: + from tech import blackbox_cells + nameset = list(set(tempnames) - set(blackbox_cells)) + except ImportError: + # remove duplicate base names + nameset = set(tempnames) + allnames = list(nameset) return (gds_dir, sp_dir, allnames) From 6058af994cd446836fb5148b3a465498738bae19 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 16 Dec 2019 15:39:32 -0800 Subject: [PATCH 072/521] Fix ignore gds files --- compiler/tests/01_library_drc_test.py | 28 +++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index 42fa1335..8b254bbc 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -21,16 +21,15 @@ class library_drc_test(openram_test): globals.init_openram(config_file) import verify - (gds_dir, gds_files) = setup_files() + (gds_dir, allnames) = setup_files() drc_errors = 0 - debug.info(1, "\nPerforming DRC on: " + ", ".join(gds_files)) - for f in gds_files: - name = re.sub('\.gds$', '', f) - gds_name = "{0}/{1}".format(gds_dir, f) + debug.info(1, "\nPerforming DRC on: " + ", ".join(allnames)) + for f in allnames: + gds_name = "{0}/{1}.gds".format(gds_dir, f) if not os.path.isfile(gds_name): drc_errors += 1 debug.error("Missing GDS file: {}".format(gds_name)) - drc_errors += verify.run_drc(name, gds_name) + drc_errors += verify.run_drc(f, gds_name) # fails if there are any DRC errors on any cells self.assertEqual(drc_errors, 0) @@ -42,14 +41,23 @@ def setup_files(): files = os.listdir(gds_dir) nametest = re.compile("\.gds$", re.IGNORECASE) gds_files = list(filter(nametest.search, files)) + + tempnames = gds_files + # remove the .gds and .sp suffixes + for i in range(len(tempnames)): + gds_files[i] = re.sub('\.gds$', '', tempnames[i]) + try: from tech import blackbox_cells - gds_files = list(set(gds_files) - set(blackbox_cells)) + nameset = list(set(tempnames) - set(blackbox_cells)) except ImportError: - pass - - return (gds_dir, gds_files) + # remove duplicate base names + nameset = set(tempnames) + + allnames = list(nameset) + + return (gds_dir, allnames) # run the test from the command line From d3a2c46cb93200065c3b59ebf3132e78a2c19627 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 16 Dec 2019 17:15:29 -0800 Subject: [PATCH 073/521] Remove some contact tests --- compiler/tests/03_contact_test.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 60d8cd6b..18604213 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -23,7 +23,9 @@ class contact_test(openram_test): from tech import poly_stack, beol_stacks - for layer_stack in [poly_stack] + beol_stacks: + # Don't do active because of nwell contact rules + # Don't do metal3 because of min area rules + for layer_stack in [poly_stack] + [beol_stacks[0]]: stack_name = ":".join(map(str, layer_stack)) # Check single 1 x 1 contact" From a79d03fef40c2cd04c8fb776929734d8e0cc8fe1 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 16 Dec 2019 17:18:49 -0800 Subject: [PATCH 074/521] Remove poly contact --- compiler/base/design.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler/base/design.py b/compiler/base/design.py index 16237cfd..7ee1624d 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -67,7 +67,10 @@ class design(hierarchy_design): self.poly_to_active = drc("poly_to_active") self.poly_extend_active = drc("poly_extend_active") - self.poly_to_contact = drc("poly_to_contact") + if "contact" in layer: + self.poly_to_contact = drc("poly_to_contact") + else: + self.poly_to_contact = drc("poly_to_active_contact") self.contact_to_gate = drc("contact_to_gate") self.well_enclose_active = drc("well_enclosure_active") self.implant_enclose_active = drc("implant_enclosure_active") From ed28b4983bdd6232e91472fd82022fd7cc2f1966 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 17 Dec 2019 11:03:36 -0800 Subject: [PATCH 075/521] Clean up and generalize layer rules. Convert metalN to mN. Generalize helper constants in modules for space, width, enclose, etc. Use layer stacks whever possible. Try to remove drc() calls in liu of helper constants. --- compiler/base/contact.py | 18 ++-- compiler/base/design.py | 88 ++++++++++++------- compiler/base/hierarchy_layout.py | 54 ++++++------ compiler/bitcells/pbitcell.py | 54 ++++++------ compiler/drc/design_rules.py | 8 +- compiler/modules/bank.py | 26 +++--- compiler/modules/bank_select.py | 26 +++--- compiler/modules/bitcell_array.py | 4 +- compiler/modules/control_logic.py | 54 ++++++------ compiler/modules/delay_chain.py | 28 +++--- compiler/modules/dff_array.py | 12 +-- compiler/modules/dff_buf.py | 26 +++--- compiler/modules/dff_buf_array.py | 16 ++-- compiler/modules/dff_inv.py | 16 ++-- compiler/modules/dff_inv_array.py | 16 ++-- compiler/modules/dummy_array.py | 4 +- compiler/modules/hierarchical_decoder.py | 16 ++-- compiler/modules/hierarchical_predecode.py | 18 ++-- compiler/modules/multibank.py | 58 ++++++------ compiler/modules/port_address.py | 4 +- compiler/modules/port_data.py | 8 +- compiler/modules/precharge_array.py | 12 +-- compiler/modules/replica_bitcell_array.py | 2 +- compiler/modules/replica_column.py | 4 +- compiler/modules/sense_amp_array.py | 14 +-- .../modules/single_level_column_mux_array.py | 20 ++--- compiler/modules/tri_gate_array.py | 14 +-- compiler/modules/wordline_driver.py | 12 +-- compiler/modules/write_driver_array.py | 10 +-- compiler/modules/write_mask_and_array.py | 6 +- compiler/pgates/pand2.py | 6 +- compiler/pgates/pand3.py | 6 +- compiler/pgates/pbuf.py | 6 +- compiler/pgates/pdriver.py | 6 +- compiler/pgates/pgate.py | 12 +-- compiler/pgates/pinv.py | 16 ++-- compiler/pgates/pinvbuf.py | 16 ++-- compiler/pgates/pnand2.py | 14 +-- compiler/pgates/pnand3.py | 16 ++-- compiler/pgates/pnor2.py | 17 ++-- compiler/pgates/precharge.py | 16 ++-- compiler/pgates/ptristate_inv.py | 8 +- compiler/pgates/ptx.py | 26 +++--- compiler/pgates/pwrite_driver.py | 58 ++++++------ compiler/pgates/single_level_column_mux.py | 18 ++-- compiler/sram/sram_1bank.py | 22 ++--- compiler/sram/sram_2bank.py | 60 ++++++------- compiler/sram/sram_base.py | 34 +++---- compiler/tests/03_path_test.py | 16 ++-- compiler/tests/03_wire_test.py | 20 ++--- technology/freepdk45/tech/tech.py | 78 ++++++++-------- technology/scn4m_subm/tech/tech.py | 63 +++++++------ 52 files changed, 604 insertions(+), 578 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 5f169e07..c5b1ef9e 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -104,11 +104,11 @@ class contact(hierarchy_design.hierarchy_design): # The enclosure rule applies to symmetric enclosure component. first_layer_minwidth = drc("minwidth_{0}".format(self.first_layer_name)) - first_layer_enclosure = drc("{0}_enclosure_{1}".format(self.first_layer_name, self.via_layer_name)) + first_layer_enclosure = drc("{0}_enclose_{1}".format(self.first_layer_name, self.via_layer_name)) first_layer_extend = drc("{0}_extend_{1}".format(self.first_layer_name, self.via_layer_name)) second_layer_minwidth = drc("minwidth_{0}".format(self.second_layer_name)) - second_layer_enclosure = drc("{0}_enclosure_{1}".format(self.second_layer_name, self.via_layer_name)) + second_layer_enclosure = drc("{0}_enclose_{1}".format(self.second_layer_name, self.via_layer_name)) second_layer_extend = drc("{0}_extend_{1}".format(self.second_layer_name, self.via_layer_name)) # In some technologies, the minimum width may be larger @@ -204,16 +204,16 @@ class contact(hierarchy_design.hierarchy_design): height=self.second_layer_height) def create_implant_well_enclosures(self): - implant_position = self.first_layer_position - [drc("implant_enclosure_active")] * 2 - implant_width = self.first_layer_width + 2 * drc("implant_enclosure_active") - implant_height = self.first_layer_height + 2 * drc("implant_enclosure_active") + implant_position = self.first_layer_position - [drc("implant_enclose_active")] * 2 + implant_width = self.first_layer_width + 2 * drc("implant_enclose_active") + implant_height = self.first_layer_height + 2 * drc("implant_enclose_active") self.add_rect(layer="{}implant".format(self.implant_type), offset=implant_position, width=implant_width, height=implant_height) - well_position = self.first_layer_position - [drc("well_enclosure_active")] * 2 - well_width = self.first_layer_width + 2 * drc("well_enclosure_active") - well_height = self.first_layer_height + 2 * drc("well_enclosure_active") + well_position = self.first_layer_position - [drc("well_enclose_active")] * 2 + well_width = self.first_layer_width + 2 * drc("well_enclose_active") + well_height = self.first_layer_height + 2 * drc("well_enclose_active") self.add_rect(layer="{}well".format(self.well_type), offset=well_position, width=well_width, @@ -250,7 +250,7 @@ m1m2 = factory.create(module_type="contact", m2m3 = factory.create(module_type="contact", layer_stack=m2_stack, directions=("V", "H")) -if "metal4" in layer.keys(): +if "m4" in layer.keys(): m3m4 = factory.create(module_type="contact", layer_stack=m3_stack, directions=("H", "V")) diff --git a/compiler/base/design.py b/compiler/base/design.py index 7ee1624d..3b6ae914 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -8,7 +8,7 @@ from hierarchy_design import hierarchy_design import contact from globals import OPTS - +import re class design(hierarchy_design): """ @@ -32,7 +32,7 @@ class design(hierarchy_design): self.m1_pitch = max(contact.m1m2.width, contact.m1m2.height) + max(self.m1_space, self.m2_space) self.m2_pitch = max(contact.m2m3.width, contact.m2m3.height) + max(self.m2_space, self.m3_space) - if "metal4" in tech.layer: + if "m4" in tech.layer: self.m3_pitch = max(contact.m3m4.width, contact.m3m4.height) + max(self.m3_space, self.m4_space) else: self.m3_pitch = self.m2_pitch @@ -46,36 +46,62 @@ class design(hierarchy_design): def setup_drc_constants(self): """ These are some DRC constants used in many places in the compiler.""" from tech import drc, layer - self.well_width = drc("minwidth_well") - self.poly_width = drc("minwidth_poly") - self.poly_space = drc("poly_to_poly") - self.m1_width = drc("minwidth_metal1") - self.m1_space = drc("metal1_to_metal1") - self.m2_width = drc("minwidth_metal2") - self.m2_space = drc("metal2_to_metal2") - self.m3_width = drc("minwidth_metal3") - self.m3_space = drc("metal3_to_metal3") - if "metal4" in layer: - self.m4_width = drc("minwidth_metal4") - self.m4_space = drc("metal4_to_metal4") - self.active_width = drc("minwidth_active") - self.active_space = drc("active_to_body_active") - if "contact" in layer: - self.contact_width = drc("minwidth_contact") - else: - self.contact_width = drc("minwidth_active_contact") - self.poly_to_active = drc("poly_to_active") - self.poly_extend_active = drc("poly_extend_active") - if "contact" in layer: - self.poly_to_contact = drc("poly_to_contact") - else: - self.poly_to_contact = drc("poly_to_active_contact") - self.contact_to_gate = drc("contact_to_gate") - self.well_enclose_active = drc("well_enclosure_active") - self.implant_enclose_active = drc("implant_enclosure_active") - self.implant_space = drc("implant_to_implant") - + # Make some local rules for convenience + for rule in drc.keys(): + # Single layer width rules + match = re.search(r"minwidth_(.*)", rule) + if match: + if match.group(1)=="active_contact": + setattr(self, "contact_width", drc(match.group(0))) + else: + setattr(self, match.group(1)+"_width", drc(match.group(0))) + + # Single layer area rules + match = re.search(r"minarea_(.*)", rule) + if match: + setattr(self, match.group(0), drc(match.group(0))) + + # Single layer spacing rules + match = re.search(r"(.*)_to_(.*)", rule) + if match and match.group(1)==match.group(2): + setattr(self, match.group(1)+"_space", drc(match.group(0))) + elif match and match.group(1)!=match.group(2): + if match.group(2)=="poly_active": + setattr(self, match.group(1)+"_to_contact", drc(match.group(0))) + else: + setattr(self, match.group(0), drc(match.group(0))) + + match = re.search(r"(.*)_enclose_(.*)", rule) + if match: + setattr(self, match.group(0), drc(match.group(0))) + + match = re.search(r"(.*)_extend_(.*)", rule) + if match: + setattr(self, match.group(0), drc(match.group(0))) + + # These are for debugging previous manual rules + # print("poly_width", self.poly_width) + # print("poly_space", self.poly_space) + # print("m1_width", self.m1_width) + # print("m1_space", self.m1_space) + # print("m2_width", self.m2_width) + # print("m2_space", self.m2_space) + # print("m3_width", self.m3_width) + # print("m3_space", self.m3_space) + # print("m4_width", self.m4_width) + # print("m4_space", self.m4_space) + # print("active_width", self.active_width) + # print("active_space", self.active_space) + # print("contact_width", self.contact_width) + # print("poly_to_active", self.poly_to_active) + # print("poly_extend_active", self.poly_extend_active) + # print("poly_to_contact", self.poly_to_contact) + # print("contact_to_gate", self.contact_to_gate) + # print("well_enclose_active", self.well_enclose_active) + # print("implant_enclose_active", self.implant_enclose_active) + # print("implant_space", self.implant_space) + def setup_multiport_constants(self): """ These are contants and lists that aid multiport design. diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index ad1e3edb..7f23e942 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -61,7 +61,7 @@ class layout(): y_dir = 1 else: # we lose a rail after every 2 gates - base_offset=vector(x_offset, (inv_num+1) * height - (inv_num%2)*drc["minwidth_metal1"]) + base_offset=vector(x_offset, (inv_num+1) * height - (inv_num%2)*drc["minwidth_m1"]) y_dir = -1 return (base_offset,y_dir) @@ -388,9 +388,9 @@ class layout(): def get_preferred_direction(self, layer): """ Return the preferred routing directions """ - if layer in ["metal1", "metal3", "metal5"]: + if layer in ["m1", "m3", "m5"]: return "H" - elif layer in ["active", "poly", "metal2", "metal4"]: + elif layer in ["active", "poly", "m2", "m4"]: return "V" else: return "N" @@ -682,12 +682,12 @@ class layout(): return line_positions def connect_horizontal_bus(self, mapping, inst, bus_offsets, - layer_stack=("metal1","via1","metal2")): + layer_stack=("m1", "via1", "m2")): """ Horizontal version of connect_bus. """ self.connect_bus(mapping, inst, bus_offsets, layer_stack, True) def connect_vertical_bus(self, mapping, inst, bus_offsets, - layer_stack=("metal1","via1","metal2")): + layer_stack=("m1", "via1", "m2")): """ Vertical version of connect_bus. """ self.connect_bus(mapping, inst, bus_offsets, layer_stack, False) @@ -734,15 +734,15 @@ class layout(): rotate=90) def get_layer_pitch(self, layer): """ Return the track pitch on a given layer """ - if layer=="metal1": + if layer=="m1": return (self.m1_pitch,self.m1_pitch-self.m1_space,self.m1_space) - elif layer=="metal2": + elif layer=="m2": return (self.m2_pitch,self.m2_pitch-self.m2_space,self.m2_space) - elif layer=="metal3": + elif layer=="m3": return (self.m3_pitch,self.m3_pitch-self.m3_space,self.m3_space) - elif layer=="metal4": + elif layer=="m4": from tech import layer as tech_layer - if "metal4" in tech_layer: + if "m4" in tech_layer: return (self.m3_pitch,self.m3_pitch-self.m4_space,self.m4_space) else: return (self.m3_pitch,self.m3_pitch-self.m3_space,self.m3_space) @@ -1006,16 +1006,16 @@ class layout(): """ pins=inst.get_pins(name) for pin in pins: - if pin.layer=="metal3": + if pin.layer=="m3": self.add_layout_pin(name, pin.layer, pin.ll(), pin.width(), pin.height()) - elif pin.layer=="metal1": + elif pin.layer=="m1": self.add_power_pin(name, pin.center()) else: debug.warning("{0} pins of {1} should be on metal3 or metal1 for supply router.".format(name,inst.name)) - def add_power_pin(self, name, loc, vertical=False, start_layer="metal1"): + def add_power_pin(self, name, loc, vertical=False, start_layer="m1"): """ Add a single power pin from M3 down to M1 at the given center location. The starting layer is specified to determine which vias are needed. @@ -1025,24 +1025,24 @@ class layout(): else: direction=("H","H") - if start_layer=="metal1": + if start_layer=="m1": self.add_via_center(layers=self.m1_stack, offset=loc, directions=direction) - if start_layer=="metal1" or start_layer=="metal2": + if start_layer=="m1" or start_layer=="m2": via=self.add_via_center(layers=self.m2_stack, offset=loc, directions=direction) - if start_layer=="metal3": + if start_layer=="m3": self.add_layout_pin_rect_center(text=name, - layer="metal3", + layer="m3", offset=loc) else: self.add_layout_pin_rect_center(text=name, - layer="metal3", + layer="m3", offset=loc, width=via.width, height=via.height) @@ -1064,7 +1064,7 @@ class layout(): # LEFT vertical rails offset = ll + vector(-2*self.supply_rail_pitch, -2*self.supply_rail_pitch) left_gnd_pin=self.add_layout_pin(text="gnd", - layer="metal2", + layer="m2", offset=offset, width=self.supply_rail_width, height=height) @@ -1072,7 +1072,7 @@ class layout(): offset = ll + vector(-1*self.supply_rail_pitch, -1*self.supply_rail_pitch) left_vdd_pin=self.add_layout_pin(text="vdd", - layer="metal2", + layer="m2", offset=offset, width=self.supply_rail_width, height=height) @@ -1080,14 +1080,14 @@ class layout(): # RIGHT vertical rails offset = vector(ur.x,ll.y) + vector(0,-2*self.supply_rail_pitch) right_gnd_pin = self.add_layout_pin(text="gnd", - layer="metal2", + layer="m2", offset=offset, width=self.supply_rail_width, height=height) offset = vector(ur.x,ll.y) + vector(self.supply_rail_pitch,-1*self.supply_rail_pitch) right_vdd_pin=self.add_layout_pin(text="vdd", - layer="metal2", + layer="m2", offset=offset, width=self.supply_rail_width, height=height) @@ -1095,14 +1095,14 @@ class layout(): # BOTTOM horizontal rails offset = ll + vector(-2*self.supply_rail_pitch, -2*self.supply_rail_pitch) bottom_gnd_pin=self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=offset, width=width, height=self.supply_rail_width) offset = ll + vector(-1*self.supply_rail_pitch, -1*self.supply_rail_pitch) bottom_vdd_pin=self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=offset, width=width, height=self.supply_rail_width) @@ -1110,14 +1110,14 @@ class layout(): # TOP horizontal rails offset = vector(ll.x, ur.y) + vector(-2*self.supply_rail_pitch,0) top_gnd_pin=self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=offset, width=width, height=self.supply_rail_width) offset = vector(ll.x, ur.y) + vector(-1*self.supply_rail_pitch, self.supply_rail_pitch) top_vdd_pin=self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=offset, width=width, height=self.supply_rail_width) @@ -1139,7 +1139,7 @@ class layout(): from sram_factory import factory while True: c=factory.create(module_type="contact", - layer_stack=("metal1","via1","metal2"), + layer_stack=self.m1_stack, dimensions=(self.supply_vias, self.supply_vias)) if c.second_layer_width < self.supply_rail_width and c.second_layer_height < self.supply_rail_width: self.supply_vias += 1 diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 8f9cd602..bdb9161b 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -364,11 +364,11 @@ class pbitcell(bitcell_base.bitcell_base): self.inverter_pmos_right.get_pin("G").bc()]) # connect output (drain/source) of inverters - self.add_path("metal1", + self.add_path("m1", [self.inverter_nmos_left.get_pin("D").uc(), self.inverter_pmos_left.get_pin("D").bc()], width=contact.active.second_layer_width) - self.add_path("metal1", + self.add_path("m1", [self.inverter_nmos_right.get_pin("S").uc(), self.inverter_pmos_right.get_pin("S").bc()], width=contact.active.second_layer_width) @@ -404,7 +404,7 @@ class pbitcell(bitcell_base.bitcell_base): # Add rails for vdd and gnd gnd_ypos = self.m1_offset - self.total_ports * self.m1_pitch self.gnd_position = vector(0, gnd_ypos) - self.add_rect_center(layer="metal1", + self.add_rect_center(layer="m1", offset=self.gnd_position, width=self.width) self.add_power_pin("gnd", vector(0, gnd_ypos)) @@ -416,7 +416,7 @@ class pbitcell(bitcell_base.bitcell_base): + self.inverter_pmos.active_height \ + self.vdd_offset self.vdd_position = vector(0, vdd_ypos) - self.add_rect_center(layer="metal1", + self.add_rect_center(layer="m1", offset=self.vdd_position, width=self.width) self.add_power_pin("vdd", vector(0, vdd_ypos)) @@ -489,7 +489,7 @@ class pbitcell(bitcell_base.bitcell_base): rwwl_ypos = self.m1_offset - k * self.m1_pitch self.rwwl_positions[k] = vector(0, rwwl_ypos) self.add_layout_pin_rect_center(text=self.rw_wl_names[k], - layer="metal1", + layer="m1", offset=self.rwwl_positions[k], width=self.width) @@ -499,7 +499,7 @@ class pbitcell(bitcell_base.bitcell_base): + 0.5 * self.m2_width self.rwbl_positions[k] = vector(rwbl_xpos, self.center_ypos) self.add_layout_pin_rect_center(text=self.rw_bl_names[k], - layer="metal2", + layer="m2", offset=self.rwbl_positions[k], height=self.height) @@ -509,7 +509,7 @@ class pbitcell(bitcell_base.bitcell_base): - 0.5 * self.m2_width self.rwbr_positions[k] = vector(rwbr_xpos, self.center_ypos) self.add_layout_pin_rect_center(text=self.rw_br_names[k], - layer="metal2", + layer="m2", offset=self.rwbr_positions[k], height=self.height) @@ -586,7 +586,7 @@ class pbitcell(bitcell_base.bitcell_base): - k * self.m1_pitch self.wwl_positions[k] = vector(0, wwl_ypos) self.add_layout_pin_rect_center(text=self.w_wl_names[k], - layer="metal1", + layer="m1", offset=self.wwl_positions[k], width=self.width) @@ -596,7 +596,7 @@ class pbitcell(bitcell_base.bitcell_base): + 0.5 * self.m2_width self.wbl_positions[k] = vector(wbl_xpos, self.center_ypos) self.add_layout_pin_rect_center(text=self.w_bl_names[k], - layer="metal2", + layer="m2", offset=self.wbl_positions[k], height=self.height) @@ -606,7 +606,7 @@ class pbitcell(bitcell_base.bitcell_base): - 0.5 * self.m2_width self.wbr_positions[k] = vector(wbr_xpos, self.center_ypos) self.add_layout_pin_rect_center(text=self.w_br_names[k], - layer="metal2", + layer="m2", offset=self.wbr_positions[k], height=self.height) @@ -713,7 +713,7 @@ class pbitcell(bitcell_base.bitcell_base): - k * self.m1_pitch self.rwl_positions[k] = vector(0, rwl_ypos) self.add_layout_pin_rect_center(text=self.r_wl_names[k], - layer="metal1", + layer="m1", offset=self.rwl_positions[k], width=self.width) @@ -723,7 +723,7 @@ class pbitcell(bitcell_base.bitcell_base): + 0.5 * self.m2_width self.rbl_positions[k] = vector(rbl_xpos, self.center_ypos) self.add_layout_pin_rect_center(text=self.r_bl_names[k], - layer="metal2", + layer="m2", offset=self.rbl_positions[k], height=self.height) @@ -733,7 +733,7 @@ class pbitcell(bitcell_base.bitcell_base): - 0.5 * self.m2_width self.rbr_positions[k] = vector(rbr_xpos, self.center_ypos) self.add_layout_pin_rect_center(text=self.r_br_names[k], - layer="metal2", + layer="m2", offset=self.rbr_positions[k], height=self.height) @@ -775,7 +775,7 @@ class pbitcell(bitcell_base.bitcell_base): offset=port_contact_offset) self.add_path("poly", [gate_offset, port_contact_offset]) - self.add_path("metal1", + self.add_path("m1", [port_contact_offset, wl_contact_offset]) else: @@ -789,7 +789,7 @@ class pbitcell(bitcell_base.bitcell_base): directions=("H", "H")) self.add_path("poly", [gate_offset, port_contact_offset]) - self.add_path("metal2", + self.add_path("m2", [port_contact_offset, wl_contact_offset]) def route_bitlines(self): @@ -827,7 +827,7 @@ class pbitcell(bitcell_base.bitcell_base): self.add_via_center(layers=self.m1_stack, offset=port_contact_offest) - self.add_path("metal2", + self.add_path("m2", [port_contact_offest, bl_offset], width=contact.m1m2.height) for k in range(self.total_ports): @@ -839,7 +839,7 @@ class pbitcell(bitcell_base.bitcell_base): self.add_via_center(layers=self.m1_stack, offset=port_contact_offest) - self.add_path("metal2", + self.add_path("m2", [port_contact_offest, br_offset], width=contact.m1m2.height) def route_supply(self): @@ -866,17 +866,17 @@ class pbitcell(bitcell_base.bitcell_base): offset=supply_offset, directions=("H", "H")) - self.add_path("metal2", [position, supply_offset]) + self.add_path("m2", [position, supply_offset]) # route inverter pmos to vdd vdd_pos_left = vector(self.inverter_nmos_left.get_pin("S").uc().x, self.vdd_position.y) - self.add_path("metal1", + self.add_path("m1", [self.inverter_pmos_left.get_pin("S").uc(), vdd_pos_left]) vdd_pos_right = vector(self.inverter_nmos_right.get_pin("D").uc().x, self.vdd_position.y) - self.add_path("metal1", + self.add_path("m1", [self.inverter_pmos_right.get_pin("D").uc(), vdd_pos_right]) def route_readwrite_access(self): @@ -889,14 +889,14 @@ class pbitcell(bitcell_base.bitcell_base): self.cross_couple_lower_ypos) Q_pos = vector(self.inverter_nmos_left.get_pin("D").lx(), self.cross_couple_lower_ypos) - self.add_path("metal1", + self.add_path("m1", [self.readwrite_nmos_left[k].get_pin("D").uc(), mid, Q_pos]) mid = vector(self.readwrite_nmos_right[k].get_pin("S").uc().x, self.cross_couple_lower_ypos) Q_bar_pos = vector(self.inverter_nmos_right.get_pin("S").rx(), self.cross_couple_lower_ypos) - self.add_path("metal1", + self.add_path("m1", [self.readwrite_nmos_right[k].get_pin("S").uc(), mid, Q_bar_pos]) def route_write_access(self): @@ -909,14 +909,14 @@ class pbitcell(bitcell_base.bitcell_base): self.cross_couple_lower_ypos) Q_pos = vector(self.inverter_nmos_left.get_pin("D").lx(), self.cross_couple_lower_ypos) - self.add_path("metal1", + self.add_path("m1", [self.write_nmos_left[k].get_pin("D").uc(), mid, Q_pos]) mid = vector(self.write_nmos_right[k].get_pin("S").uc().x, self.cross_couple_lower_ypos) Q_bar_pos = vector(self.inverter_nmos_right.get_pin("S").rx(), self.cross_couple_lower_ypos) - self.add_path("metal1", + self.add_path("m1", [self.write_nmos_right[k].get_pin("S").uc(), mid, Q_bar_pos]) def route_read_access(self): @@ -960,7 +960,7 @@ class pbitcell(bitcell_base.bitcell_base): mid = vector(self.read_access_nmos_left[k].get_pin("G").uc().x, self.cross_couple_upper_ypos) - self.add_path("metal1", + self.add_path("m1", [port_contact_offset, mid, left_storage_contact]) port_contact_offset = self.read_access_nmos_right[k].get_pin("G").uc() \ @@ -975,7 +975,7 @@ class pbitcell(bitcell_base.bitcell_base): mid = vector(self.read_access_nmos_right[k].get_pin("G").uc().x, self.cross_couple_upper_ypos) - self.add_path("metal1", + self.add_path("m1", [port_contact_offset, mid, right_storage_contact]) def extend_well(self): @@ -1076,7 +1076,7 @@ class pbitcell(bitcell_base.bitcell_base): """ Q_bar_pos = self.inverter_pmos_right.get_pin("S").center() vdd_pos = self.inverter_pmos_right.get_pin("D").center() - self.add_path("metal1", [Q_bar_pos, vdd_pos]) + self.add_path("m1", [Q_bar_pos, vdd_pos]) def get_storage_net_names(self): """ diff --git a/compiler/drc/design_rules.py b/compiler/drc/design_rules.py index cf54bdb3..05168b77 100644 --- a/compiler/drc/design_rules.py +++ b/compiler/drc/design_rules.py @@ -9,7 +9,7 @@ import debug from drc_value import * from drc_lut import * -class design_rules(): +class design_rules(dict): """ This is a class that implements the design rules structures. """ @@ -43,7 +43,9 @@ class design_rules(): else: debug.error("Must call complex DRC rule {} with arguments.".format(b),-1) - + def keys(self): + return self.rules.keys() + def add_layer(self, name, width, spacing, area=0): # Minimum width self.add("minwidth_{}".format(name), width) @@ -53,7 +55,7 @@ class design_rules(): self.add("minarea_{}".format(name), area) def add_enclosure(self, name, layer, enclosure, extension=None): - self.add("{0}_enclosure_{1}".format(name, layer), enclosure) + self.add("{0}_enclose_{1}".format(name, layer), enclosure) # Reserved for asymmetric enclosures if extension: self.add("{0}_extend_{1}".format(name, layer), extension) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index b1ce2d55..4527044c 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -333,7 +333,7 @@ class bank(design.design): self.col_addr_bus_width = self.m2_pitch*self.num_col_addr_lines # A space for wells or jogging m2 - self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), + self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"), 3*self.m2_pitch) @@ -605,7 +605,7 @@ class bank(design.design): out_pos = self.bank_select_inst[port].get_pin(gated_bank_sel_signals[signal]).rc() name = self.control_signals[port][signal] bus_pos = vector(self.bus_xoffset[port][name].x, out_pos.y) - self.add_path("metal3",[out_pos, bus_pos]) + self.add_path("m3",[out_pos, bus_pos]) self.add_via_center(layers=self.m2_stack, offset=bus_pos) self.add_via_center(layers=self.m1_stack, @@ -648,7 +648,7 @@ class bank(design.design): control_bus_offset = vector(-self.m2_pitch * self.num_control_lines[0] - self.m2_pitch, self.min_y_offset) # The control bus is routed up to two pitches below the bitcell array control_bus_length = self.main_bitcell_array_bottom - self.min_y_offset - 2*self.m1_pitch - self.bus_xoffset[0] = self.create_bus(layer="metal2", + self.bus_xoffset[0] = self.create_bus(layer="m2", pitch=self.m2_pitch, offset=control_bus_offset, names=self.control_signals[0], @@ -663,7 +663,7 @@ class bank(design.design): control_bus_offset = vector(self.bitcell_array_right + self.m2_pitch, self.max_y_offset - control_bus_length) # The bus for the right port is reversed so that the rbl_wl is closest to the array - self.bus_xoffset[1] = self.create_bus(layer="metal2", + self.bus_xoffset[1] = self.create_bus(layer="m2", pitch=self.m2_pitch, offset=control_bus_offset, names=list(reversed(self.control_signals[1])), @@ -817,7 +817,7 @@ class bank(design.design): bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port]+"_{}".format(row)).lc() mid1 = driver_wl_pos.scale(0,1) + vector(0.5*self.port_address_inst[port].rx() + 0.5*self.bitcell_array_inst.lx(),0) mid2 = mid1.scale(1,0)+bitcell_wl_pos.scale(0.5,1) - self.add_path("metal1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) + self.add_path("m1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) def route_port_address_right(self, port): @@ -829,7 +829,7 @@ class bank(design.design): bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port]+"_{}".format(row)).rc() mid1 = driver_wl_pos.scale(0,1) + vector(0.5*self.port_address_inst[port].lx() + 0.5*self.bitcell_array_inst.rx(),0) mid2 = mid1.scale(1,0)+bitcell_wl_pos.scale(0,1) - self.add_path("metal1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) + self.add_path("m1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) def route_column_address_lines(self, port): """ Connecting the select lines of column mux to the address bus """ @@ -878,7 +878,7 @@ class bank(design.design): wl_name = "wl_{}".format(i) wl_pin = self.bitcell_array_inst.get_pin(wl_name) self.add_label(text=wl_name, - layer="metal1", + layer="m1", offset=wl_pin.center()) # Add the bitline names @@ -888,10 +888,10 @@ class bank(design.design): bl_pin = self.bitcell_array_inst.get_pin(bl_name) br_pin = self.bitcell_array_inst.get_pin(br_name) self.add_label(text=bl_name, - layer="metal2", + layer="m2", offset=bl_pin.center()) self.add_label(text=br_name, - layer="metal2", + layer="m2", offset=br_pin.center()) # # Add the data output names to the sense amp output @@ -899,7 +899,7 @@ class bank(design.design): # data_name = "data_{}".format(i) # data_pin = self.sense_amp_array_inst.get_pin(data_name) # self.add_label(text="sa_out_{}".format(i), - # layer="metal2", + # layer="m2", # offset=data_pin.center()) # Add labels on the decoder @@ -909,7 +909,7 @@ class bank(design.design): pin_name = "in_{}".format(i) data_pin = self.wordline_driver_inst[port].get_pin(pin_name) self.add_label(text=data_name, - layer="metal1", + layer="m1", offset=data_pin.center()) @@ -941,7 +941,7 @@ class bank(design.design): for (control_signal, pin_pos) in connection: control_mid_pos = self.bus_xoffset[port][control_signal] control_pos = vector(self.bus_xoffset[port][control_signal].x ,pin_pos.y) - self.add_wire(("metal1","via1","metal2"), [control_mid_pos, control_pos, pin_pos]) + self.add_wire(self.m1_stack, [control_mid_pos, control_pos, pin_pos]) self.add_via_center(layers=self.m1_stack, offset=control_pos) @@ -956,7 +956,7 @@ class bank(design.design): mid_pos = pin_pos - vector(0,2*self.m2_gap) # to route down to the top of the bus control_x_offset = self.bus_xoffset[port][control_signal].x control_pos = vector(control_x_offset, mid_pos.y) - self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos]) + self.add_wire(self.m1_stack,[pin_pos, mid_pos, control_pos]) self.add_via_center(layers=self.m1_stack, offset=control_pos) diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index 14b6b203..4b49750d 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -208,18 +208,18 @@ class bank_select(design.design): xoffset_bank_sel = bank_sel_inv_pin.lx() bank_sel_line_pos = vector(xoffset_bank_sel, 0) bank_sel_line_end = vector(xoffset_bank_sel, self.yoffset_maxpoint) - self.add_path("metal2", [bank_sel_line_pos, bank_sel_line_end]) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_path("m2", [bank_sel_line_pos, bank_sel_line_end]) + self.add_via_center(layers=self.m1_stack, offset=bank_sel_inv_pin.lc()) # Route the pin to the left edge as well bank_sel_pin_pos=vector(0, 0) bank_sel_pin_end=vector(bank_sel_line_pos.x, bank_sel_pin_pos.y) self.add_layout_pin_segment_center(text="bank_sel", - layer="metal3", + layer="m3", start=bank_sel_pin_pos, end=bank_sel_pin_end) - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_via_center(layers=self.m2_stack, offset=bank_sel_pin_end, directions=("H","H")) @@ -227,10 +227,10 @@ class bank_select(design.design): bank_sel_bar_pin = self.bank_sel_inv.get_pin("Z") xoffset_bank_sel_bar = bank_sel_bar_pin.rx() self.add_label_pin(text="bank_sel_bar", - layer="metal2", + layer="m2", offset=vector(xoffset_bank_sel_bar, 0), height=self.inv4x.height) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=bank_sel_bar_pin.rc()) @@ -251,13 +251,13 @@ class bank_select(design.design): out_position = logic_inst.get_pin("Z").rc() + vector(0.5*self.m1_width,0) in_position = inv_inst.get_pin("A").lc() + vector(0.5*self.m1_width,0) post = inv_inst.get_pin("A").rc() - self.add_path("metal1", [pre, out_position, in_position, post]) + self.add_path("m1", [pre, out_position, in_position, post]) # Connect the logic B input to bank_sel/bank_sel_bar logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1m2.height,0) input_pos = vector(xoffset_bank_signal, logic_pos.y) - self.add_path("metal2",[logic_pos, input_pos]) + self.add_path("m2",[logic_pos, input_pos]) self.add_via_center(layers=self.m1_stack, offset=logic_pos, directions=("H","H")) @@ -273,7 +273,7 @@ class bank_select(design.design): offset=logic_pos, directions=("H","H")) self.add_layout_pin_segment_center(text=input_name, - layer="metal3", + layer="m3", start=input_pos, end=logic_pos) @@ -294,7 +294,7 @@ class bank_select(design.design): for n in ["vdd", "gnd"]: supply_pin = self.inv_inst[num].get_pin(n) supply_offset = supply_pin.ll().scale(0,1) - self.add_rect(layer="metal1", + self.add_rect(layer="m1", offset=supply_offset, width=self.width) @@ -308,20 +308,20 @@ class bank_select(design.design): offset=pin_pos, directions=("H","H")) self.add_layout_pin_rect_center(text=n, - layer="metal3", + layer="m3", offset=pin_pos) # Add vdd/gnd supply rails gnd_pin = inv_inst.get_pin("gnd") left_gnd_pos = vector(0, gnd_pin.cy()) self.add_layout_pin_segment_center(text="gnd", - layer="metal1", + layer="m1", start=left_gnd_pos, end=gnd_pin.rc()) vdd_pin = inv_inst.get_pin("vdd") left_vdd_pos = vector(0, vdd_pin.cy()) self.add_layout_pin_segment_center(text="vdd", - layer="metal1", + layer="m1", start=left_vdd_pos, end=vdd_pin.rc()) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index b1b61487..bf43736b 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -173,7 +173,7 @@ class bitcell_array(design.design): width = 0 else: width = self.width - wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_metal1")) + wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_m1")) wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell return wl_wire @@ -183,7 +183,7 @@ class bitcell_array(design.design): else: height = self.height bl_pos = 0 - bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_metal1")) + bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_m1")) bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell return bl_wire diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 3256c9ac..dbb7c3b7 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -371,7 +371,7 @@ class control_logic(design.design): height = self.control_logic_center.y - self.m2_pitch offset = vector(self.ctrl_dff_array.width,0) - self.rail_offsets = self.create_vertical_bus("metal2", self.m2_pitch, offset, self.internal_bus_list, height) + self.rail_offsets = self.create_vertical_bus("m2", self.m2_pitch, offset, self.internal_bus_list, height) def create_instances(self): @@ -483,8 +483,8 @@ class control_logic(design.design): vdd_ypos = self.p_en_bar_nand_inst.get_pin("vdd").by() in_pos = vector(self.rail_offsets["rbl_bl_delay"].x,vdd_ypos) mid1 = vector(out_pos.x,in_pos.y) - self.add_wire(("metal1","via1","metal2"),[out_pos, mid1, in_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_wire(self.m1_stack,[out_pos, mid1, in_pos]) + self.add_via_center(layers=self.m1_stack, offset=in_pos) @@ -509,10 +509,10 @@ class control_logic(design.design): clk_pin = self.clk_buf_inst.get_pin("A") clk_pos = clk_pin.center() self.add_layout_pin_segment_center(text="clk", - layer="metal2", + layer="m2", start=clk_pos, end=clk_pos.scale(1,0)) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=clk_pos) @@ -521,9 +521,9 @@ class control_logic(design.design): mid1 = vector(out_pos.x,2*self.m2_pitch) mid2 = vector(self.rail_offsets["clk_buf"].x, mid1.y) bus_pos = self.rail_offsets["clk_buf"] - self.add_wire(("metal3","via2","metal2"),[out_pos, mid1, mid2, bus_pos]) + self.add_wire(("m3","via2","m2"),[out_pos, mid1, mid2, bus_pos]) # The pin is on M1, so we need another via as well - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=self.clk_buf_inst.get_pin("Z").center()) self.connect_output(self.clk_buf_inst, "Z", "clk_buf") @@ -552,21 +552,21 @@ class control_logic(design.design): out_pos = self.clk_bar_inst.get_pin("Z").center() in_pos = self.gated_clk_bar_inst.get_pin("B").center() mid1 = vector(in_pos.x,out_pos.y) - self.add_path("metal1",[out_pos, mid1, in_pos]) + self.add_path("m1",[out_pos, mid1, in_pos]) # This is the second gate over, so it needs to be on M3 clkbuf_map = zip(["A"], ["cs"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("m3", "via2", "m2")) # The pin is on M1, so we need another via as well - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=self.gated_clk_bar_inst.get_pin("A").center()) # This is the second gate over, so it needs to be on M3 clkbuf_map = zip(["Z"], ["gated_clk_bar"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("m3", "via2", "m2")) # The pin is on M1, so we need another via as well - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=self.gated_clk_bar_inst.get_pin("Z").center()) def create_gated_clk_buf_row(self): @@ -587,9 +587,9 @@ class control_logic(design.design): clkbuf_map = zip(["Z"], ["gated_clk_buf"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets, ("m3", "via2", "m2")) # The pin is on M1, so we need another via as well - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=self.gated_clk_buf_inst.get_pin("Z").center()) def create_wlen_row(self): @@ -637,7 +637,7 @@ class control_logic(design.design): out_pos = self.p_en_bar_nand_inst.get_pin("Z").rc() in_pos = self.p_en_bar_driver_inst.get_pin("A").lc() mid1 = vector(out_pos.x,in_pos.y) - self.add_wire(("metal1","via1","metal2"),[out_pos, mid1,in_pos]) + self.add_wire(self.m1_stack,[out_pos, mid1,in_pos]) self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar") @@ -694,9 +694,9 @@ class control_logic(design.design): # Connect to rail rbl_map = zip(["Z"], ["rbl_bl_delay_bar"]) - self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets, ("m3", "via2", "m2")) # The pin is on M1, so we need another via as well - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=self.rbl_bl_delay_inv_inst.get_pin("Z").center()) @@ -754,14 +754,14 @@ class control_logic(design.design): dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) else: dff_out_map = zip(["dout_bar_0"], ["cs"]) - self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets, ("m3", "via2", "m2")) # Connect the clock rail to the other clock rail in_pos = self.ctrl_dff_inst.get_pin("clk").uc() mid_pos = in_pos + vector(0,2*self.m2_pitch) rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y) - self.add_wire(("metal1","via1","metal2"),[in_pos, mid_pos, rail_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_wire(self.m1_stack,[in_pos, mid_pos, rail_pos]) + self.add_via_center(layers=self.m1_stack, offset=rail_pos) self.copy_layout_pin(self.ctrl_dff_inst, "din_0", "csb") @@ -786,7 +786,7 @@ class control_logic(design.design): out_pin = inst.get_pin(pin_name) right_pos=out_pin.center() + vector(self.width-out_pin.cx(),0) self.add_layout_pin_segment_center(text=out_name, - layer="metal1", + layer="m1", start=out_pin.center(), end=right_pos) @@ -799,19 +799,19 @@ class control_logic(design.design): for inst in self.row_end_inst: pins = inst.get_pins("vdd") for pin in pins: - if pin.layer == "metal1": + if pin.layer == "m1": row_loc = pin.rc() pin_loc = vector(max_row_x_loc, pin.rc().y) self.add_power_pin("vdd", pin_loc) - self.add_path("metal1", [row_loc, pin_loc]) + self.add_path("m1", [row_loc, pin_loc]) pins = inst.get_pins("gnd") for pin in pins: - if pin.layer == "metal1": + if pin.layer == "m1": row_loc = pin.rc() pin_loc = vector(max_row_x_loc, pin.rc().y) self.add_power_pin("gnd", pin_loc) - self.add_path("metal1", [row_loc, pin_loc]) + self.add_path("m1", [row_loc, pin_loc]) self.copy_layout_pin(self.delay_inst,"gnd") self.copy_layout_pin(self.delay_inst,"vdd") @@ -828,14 +828,14 @@ class control_logic(design.design): """ # pin=self.clk_inv1.get_pin("Z") # self.add_label_pin(text="clk1_bar", - # layer="metal1", + # layer="m1", # offset=pin.ll(), # height=pin.height(), # width=pin.width()) # pin=self.clk_inv2.get_pin("Z") # self.add_label_pin(text="clk2", - # layer="metal1", + # layer="m1", # offset=pin.ll(), # height=pin.height(), # width=pin.width()) diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index bc932a26..a07576d4 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -132,11 +132,11 @@ class delay_chain(design.design): pin1_pos = pin1.center() pin2_pos = pin2.center() if pin1_pos.y == pin2_pos.y: - self.add_path("metal2", [pin1_pos, pin2_pos]) + self.add_path("m2", [pin1_pos, pin2_pos]) else: mid_point = vector(pin2_pos.x, 0.5*(pin1_pos.y+pin2_pos.y)) # Written this way to guarantee it goes right first if we are switching rows - self.add_path("metal2", [pin1_pos, vector(pin1_pos.x,mid_point.y), mid_point, vector(mid_point.x,pin2_pos.y), pin2_pos]) + self.add_path("m2", [pin1_pos, vector(pin1_pos.x,mid_point.y), mid_point, vector(mid_point.x,pin2_pos.y), pin2_pos]) def route_inverters(self): """ Add metal routing for each of the fanout stages """ @@ -146,22 +146,22 @@ class delay_chain(design.design): for load in self.load_inst_map[inv]: # Drop a via on each A pin a_pin = load.get_pin("A") - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_via_center(layers=self.m2_stack, offset=a_pin.center()) # Route an M3 horizontal wire to the furthest z_pin = inv.get_pin("Z") a_pin = inv.get_pin("A") a_max = self.rightest_load_inst[inv].get_pin("A") - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=z_pin.center()) - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_via_center(layers=self.m2_stack, offset=z_pin.center()) - self.add_path("metal3",[z_pin.center(), a_max.center()]) + self.add_path("m3",[z_pin.center(), a_max.center()]) # Route Z to the A of the next stage @@ -172,7 +172,7 @@ class delay_chain(design.design): y_mid = (z_pin.cy() + next_a_pin.cy())/2 mid1_point = vector(z_pin.cx(), y_mid) mid2_point = vector(next_a_pin.cx(), y_mid) - self.add_path("metal2",[z_pin.center(), mid1_point, mid2_point, next_a_pin.center()]) + self.add_path("m2",[z_pin.center(), mid1_point, mid2_point, next_a_pin.center()]) def add_layout_pins(self): @@ -205,10 +205,10 @@ class delay_chain(design.design): # input is A pin of first inverter a_pin = self.driver_inst_list[0].get_pin("A") - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) self.add_layout_pin(text="in", - layer="metal2", + layer="m2", offset=a_pin.ll().scale(1,0), height=a_pin.cy()) @@ -216,12 +216,12 @@ class delay_chain(design.design): # output is A pin of last load inverter last_driver_inst = self.driver_inst_list[-1] a_pin = self.rightest_load_inst[last_driver_inst].get_pin("A") - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) mid_point = vector(a_pin.cx()+3*self.m2_width,a_pin.cy()) - self.add_path("metal2",[a_pin.center(), mid_point, mid_point.scale(1,0)]) + self.add_path("m2",[a_pin.center(), mid_point, mid_point.scale(1,0)]) self.add_layout_pin_segment_center(text="out", - layer="metal2", + layer="m2", start=mid_point, end=mid_point.scale(1,0)) diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 89b29476..6ba020c7 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -124,7 +124,7 @@ class dff_array(design.design): for row in range(self.rows): for col in range(self.columns): din_pin = self.dff_insts[row,col].get_pin("D") - debug.check(din_pin.layer=="metal2","DFF D pin not on metal2") + debug.check(din_pin.layer=="m2","DFF D pin not on metal2") self.add_layout_pin(text=self.get_din_name(row,col), layer=din_pin.layer, offset=din_pin.ll(), @@ -132,7 +132,7 @@ class dff_array(design.design): height=din_pin.height()) dout_pin = self.dff_insts[row,col].get_pin("Q") - debug.check(dout_pin.layer=="metal2","DFF Q pin not on metal2") + debug.check(dout_pin.layer=="m2","DFF Q pin not on metal2") self.add_layout_pin(text=self.get_dout_name(row,col), layer=dout_pin.layer, offset=dout_pin.ll(), @@ -144,20 +144,20 @@ class dff_array(design.design): # Create vertical spines to a single horizontal rail clk_pin = self.dff_insts[0,0].get_pin("clk") clk_ypos = 2*self.m3_pitch+self.m3_width - debug.check(clk_pin.layer=="metal2","DFF clk pin not on metal2") + debug.check(clk_pin.layer=="m2","DFF clk pin not on metal2") self.add_layout_pin_segment_center(text="clk", - layer="metal3", + layer="m3", start=vector(0,clk_ypos), end=vector(self.width,clk_ypos)) for col in range(self.columns): clk_pin = self.dff_insts[0,col].get_pin("clk") # Make a vertical strip for each column - self.add_rect(layer="metal2", + self.add_rect(layer="m2", offset=clk_pin.ll().scale(1,0), width=self.m2_width, height=self.height) # Drop a via to the M3 pin - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_via_center(layers=self.m2_stack, offset=vector(clk_pin.cx(),clk_ypos)) def get_clk_cin(self): diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index f6fc1cf2..9e2ff0aa 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -112,12 +112,12 @@ class dff_buf(design.design): mid_x_offset = 0.5*(a1_pin.cx() + q_pin.cx()) mid1 = vector(mid_x_offset, q_pin.cy()) mid2 = vector(mid_x_offset, a1_pin.cy()) - self.add_path("metal3", [q_pin.center(), mid1, mid2, a1_pin.center()]) - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_path("m3", [q_pin.center(), mid1, mid2, a1_pin.center()]) + self.add_via_center(layers=self.m2_stack, offset=q_pin.center()) - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_via_center(layers=self.m2_stack, offset=a1_pin.center()) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=a1_pin.center()) # Route inv1 z to inv2 a @@ -126,14 +126,14 @@ class dff_buf(design.design): mid_x_offset = 0.5*(z1_pin.cx() + a2_pin.cx()) self.mid_qb_pos = vector(mid_x_offset, z1_pin.cy()) mid2 = vector(mid_x_offset, a2_pin.cy()) - self.add_path("metal1", [z1_pin.center(), self.mid_qb_pos, mid2, a2_pin.center()]) + self.add_path("m1", [z1_pin.center(), self.mid_qb_pos, mid2, a2_pin.center()]) def add_layout_pins(self): # Continous vdd rail along with label. vdd_pin=self.dff_inst.get_pin("vdd") self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=vdd_pin.ll(), width=self.width, height=vdd_pin.height()) @@ -141,7 +141,7 @@ class dff_buf(design.design): # Continous gnd rail along with label. gnd_pin=self.dff_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=gnd_pin.ll(), width=self.width, height=vdd_pin.height()) @@ -164,18 +164,18 @@ class dff_buf(design.design): mid_pos = dout_pin.center() + vector(self.m1_pitch,0) q_pos = mid_pos - vector(0,self.m2_pitch) self.add_layout_pin_rect_center(text="Q", - layer="metal2", + layer="m2", offset=q_pos) - self.add_path("metal1", [dout_pin.center(), mid_pos, q_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_path("m1", [dout_pin.center(), mid_pos, q_pos]) + self.add_via_center(layers=self.m1_stack, offset=q_pos) qb_pos = self.mid_qb_pos + vector(0,self.m2_pitch) self.add_layout_pin_rect_center(text="Qb", - layer="metal2", + layer="m2", offset=qb_pos) - self.add_path("metal1", [self.mid_qb_pos, qb_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_path("m1", [self.mid_qb_pos, qb_pos]) + self.add_via_center(layers=self.m1_stack, offset=qb_pos) def get_clk_cin(self): diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 2fafee76..8b8e21dc 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -142,7 +142,7 @@ class dff_buf_array(design.design): for row in range(self.rows): for col in range(self.columns): din_pin = self.dff_insts[row,col].get_pin("D") - debug.check(din_pin.layer=="metal2","DFF D pin not on metal2") + debug.check(din_pin.layer=="m2","DFF D pin not on metal2") self.add_layout_pin(text=self.get_din_name(row,col), layer=din_pin.layer, offset=din_pin.ll(), @@ -150,7 +150,7 @@ class dff_buf_array(design.design): height=din_pin.height()) dout_pin = self.dff_insts[row,col].get_pin("Q") - debug.check(dout_pin.layer=="metal2","DFF Q pin not on metal2") + debug.check(dout_pin.layer=="m2","DFF Q pin not on metal2") self.add_layout_pin(text=self.get_dout_name(row,col), layer=dout_pin.layer, offset=dout_pin.ll(), @@ -158,7 +158,7 @@ class dff_buf_array(design.design): height=dout_pin.height()) dout_bar_pin = self.dff_insts[row,col].get_pin("Qb") - debug.check(dout_bar_pin.layer=="metal2","DFF Qb pin not on metal2") + debug.check(dout_bar_pin.layer=="m2","DFF Qb pin not on metal2") self.add_layout_pin(text=self.get_dout_bar_name(row,col), layer=dout_bar_pin.layer, offset=dout_bar_pin.ll(), @@ -169,28 +169,28 @@ class dff_buf_array(design.design): # Create vertical spines to a single horizontal rail clk_pin = self.dff_insts[0,0].get_pin("clk") clk_ypos = 2*self.m3_pitch+self.m3_width - debug.check(clk_pin.layer=="metal2","DFF clk pin not on metal2") + debug.check(clk_pin.layer=="m2","DFF clk pin not on metal2") if self.columns==1: self.add_layout_pin(text="clk", - layer="metal2", + layer="m2", offset=clk_pin.ll().scale(1,0), width=self.m2_width, height=self.height) else: self.add_layout_pin_segment_center(text="clk", - layer="metal3", + layer="m3", start=vector(0,clk_ypos), end=vector(self.width,clk_ypos)) for col in range(self.columns): clk_pin = self.dff_insts[0,col].get_pin("clk") # Make a vertical strip for each column - self.add_rect(layer="metal2", + self.add_rect(layer="m2", offset=clk_pin.ll().scale(1,0), width=self.m2_width, height=self.height) # Drop a via to the M3 pin - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_via_center(layers=self.m2_stack, offset=vector(clk_pin.cx(),clk_ypos)) def get_clk_cin(self): diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index 207a5ad0..9dcb84c5 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -97,13 +97,13 @@ class dff_inv(design.design): mid_x_offset = 0.5*(a1_pin.cx() + q_pin.cx()) mid1 = vector(mid_x_offset, q_pin.cy()) mid2 = vector(mid_x_offset, a1_pin.cy()) - self.add_path("metal3", + self.add_path("m3", [q_pin.center(), mid1, mid2, a1_pin.center()]) - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_via_center(layers=self.m2_stack, offset=q_pin.center()) - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_via_center(layers=self.m2_stack, offset=a1_pin.center()) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=a1_pin.center()) @@ -112,7 +112,7 @@ class dff_inv(design.design): # Continous vdd rail along with label. vdd_pin=self.dff_inst.get_pin("vdd") self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=vdd_pin.ll(), width=self.width, height=vdd_pin.height()) @@ -120,7 +120,7 @@ class dff_inv(design.design): # Continous gnd rail along with label. gnd_pin=self.dff_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=gnd_pin.ll(), width=self.width, height=vdd_pin.height()) @@ -146,9 +146,9 @@ class dff_inv(design.design): dout_pin = self.inv1_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Qb", - layer="metal2", + layer="m2", offset=dout_pin.center()) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=dout_pin.center()) def get_clk_cin(self): diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 760a2337..aadb4257 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -140,7 +140,7 @@ class dff_inv_array(design.design): for row in range(self.rows): for col in range(self.columns): din_pin = self.dff_insts[row,col].get_pin("D") - debug.check(din_pin.layer=="metal2","DFF D pin not on metal2") + debug.check(din_pin.layer=="m2","DFF D pin not on metal2") self.add_layout_pin(text=self.get_din_name(row,col), layer=din_pin.layer, offset=din_pin.ll(), @@ -148,7 +148,7 @@ class dff_inv_array(design.design): height=din_pin.height()) dout_pin = self.dff_insts[row,col].get_pin("Q") - debug.check(dout_pin.layer=="metal2","DFF Q pin not on metal2") + debug.check(dout_pin.layer=="m2","DFF Q pin not on metal2") self.add_layout_pin(text=self.get_dout_name(row,col), layer=dout_pin.layer, offset=dout_pin.ll(), @@ -156,7 +156,7 @@ class dff_inv_array(design.design): height=dout_pin.height()) dout_bar_pin = self.dff_insts[row,col].get_pin("Qb") - debug.check(dout_bar_pin.layer=="metal2","DFF Qb pin not on metal2") + debug.check(dout_bar_pin.layer=="m2","DFF Qb pin not on metal2") self.add_layout_pin(text=self.get_dout_bar_name(row,col), layer=dout_bar_pin.layer, offset=dout_bar_pin.ll(), @@ -167,27 +167,27 @@ class dff_inv_array(design.design): # Create vertical spines to a single horizontal rail clk_pin = self.dff_insts[0,0].get_pin("clk") clk_ypos = 2*self.m3_pitch+self.m3_width - debug.check(clk_pin.layer=="metal2","DFF clk pin not on metal2") + debug.check(clk_pin.layer=="m2","DFF clk pin not on metal2") if self.columns==1: self.add_layout_pin(text="clk", - layer="metal2", + layer="m2", offset=clk_pin.ll().scale(1,0), width=self.m2_width, height=self.height) else: self.add_layout_pin_segment_center(text="clk", - layer="metal3", + layer="m3", start=vector(0,clk_ypos), end=vector(self.width,clk_ypos)) for col in range(self.columns): clk_pin = self.dff_insts[0,col].get_pin("clk") # Make a vertical strip for each column - self.add_rect(layer="metal2", + self.add_rect(layer="m2", offset=clk_pin.ll().scale(1,0), width=self.m2_width, height=self.height) # Drop a via to the M3 pin - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_via_center(layers=self.m2_stack, offset=vector(clk_pin.cx(),clk_ypos)) def get_clk_cin(self): diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index f1f433ce..1e5a2121 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -122,7 +122,7 @@ class dummy_array(design.design): for cell_column in column_list: bl_pin = self.cell_inst[0,col].get_pin(cell_column) self.add_layout_pin(text=cell_column+"_{0}".format(col), - layer="metal2", + layer="m2", offset=bl_pin.ll(), width=bl_pin.width(), height=self.height) @@ -131,7 +131,7 @@ class dummy_array(design.design): for cell_row in row_list: wl_pin = self.cell_inst[row,0].get_pin(cell_row) self.add_layout_pin(text=cell_row+"_{0}".format(row), - layer="metal1", + layer="m1", offset=wl_pin.ll(), width=self.width, height=wl_pin.height()) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 9c7cafd8..bb637ed1 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -173,7 +173,7 @@ class hierarchical_decoder(design.design): input_offset=vector(min_x - self.input_routing_width,0) input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)] - self.input_rails = self.create_vertical_pin_bus(layer="metal2", + self.input_rails = self.create_vertical_pin_bus(layer="m2", pitch=self.m2_pitch, offset=input_offset, names=input_bus_names, @@ -225,7 +225,7 @@ class hierarchical_decoder(design.design): offset=input_offset) self.add_via_center(layers=self.m2_stack, offset=output_offset) - self.add_path(("metal3"), [input_offset, output_offset]) + self.add_path(("m3"), [input_offset, output_offset]) def add_pins(self): @@ -467,11 +467,11 @@ class hierarchical_decoder(design.design): # ensure the bend is in the middle mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y) mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y) - self.add_path("metal1", [zr_pos, mid1_pos, mid2_pos, al_pos]) + self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos]) z_pin = self.inv_inst[row].get_pin("Z") self.add_layout_pin(text="decode_{0}".format(row), - layer="metal1", + layer="m1", offset=z_pin.ll(), width=z_pin.width(), height=z_pin.height()) @@ -485,7 +485,7 @@ class hierarchical_decoder(design.design): if (self.num_inputs >= 4): input_offset = vector(0.5*self.m2_width,0) input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)] - self.predecode_rails = self.create_vertical_pin_bus(layer="metal2", + self.predecode_rails = self.create_vertical_pin_bus(layer="m2", pitch=self.m2_pitch, offset=input_offset, names=input_bus_names, @@ -570,7 +570,7 @@ class hierarchical_decoder(design.design): start = self.nand_inst[num].get_pin(pin_name).lc() end = self.inv_inst[num].get_pin(pin_name).rc() mid = (start+end).scale(0.5,0.5) - self.add_rect_center(layer="metal1", + self.add_rect_center(layer="m1", offset=mid, width=end.x-start.x) @@ -584,7 +584,7 @@ class hierarchical_decoder(design.design): def route_predecode_rail(self, rail_name, pin): """ Connect the routing rail to the given metal1 pin """ rail_pos = vector(self.predecode_rails[rail_name].x,pin.lc().y) - self.add_path("metal1", [rail_pos, pin.lc()]) + self.add_path("m1", [rail_pos, pin.lc()]) self.add_via_center(layers=self.m1_stack, offset=rail_pos) @@ -597,7 +597,7 @@ class hierarchical_decoder(design.design): rail_pos = vector(self.predecode_rails[rail_name].x,mid_point.y) self.add_via_center(layers=self.m1_stack, offset=pin.center()) - self.add_wire(("metal3","via2","metal2"), [rail_pos, mid_point, pin.uc()]) + self.add_wire(("m3","via2","m2"), [rail_pos, mid_point, pin.uc()]) self.add_via_center(layers=self.m2_stack, offset=rail_pos) diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 0de67cae..dec04073 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -73,7 +73,7 @@ class hierarchical_predecode(design.design): """ Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """ input_names = ["in_{}".format(x) for x in range(self.number_of_inputs)] offset = vector(0.5*self.m2_width,2*self.m1_width) - self.input_rails = self.create_vertical_pin_bus(layer="metal2", + self.input_rails = self.create_vertical_pin_bus(layer="m2", pitch=self.m2_pitch, offset=offset, names=input_names, @@ -83,7 +83,7 @@ class hierarchical_predecode(design.design): non_invert_names = ["A_{}".format(x) for x in range(self.number_of_inputs)] decode_names = invert_names + non_invert_names offset = vector(self.x_off_inv_1 + self.inv.width + 2*self.m2_pitch, 2*self.m1_width) - self.decode_rails = self.create_vertical_bus(layer="metal2", + self.decode_rails = self.create_vertical_bus(layer="m2", pitch=self.m2_pitch, offset=offset, names=decode_names, @@ -183,7 +183,7 @@ class hierarchical_predecode(design.design): a_pin = "A_{}".format(num) in_pos = vector(self.input_rails[in_pin].x,y_offset) a_pos = vector(self.decode_rails[a_pin].x,y_offset) - self.add_path("metal1",[in_pos, a_pos]) + self.add_path("m1",[in_pos, a_pos]) self.add_via_center(layers = self.m1_stack, offset=[self.input_rails[in_pin].x, y_offset]) self.add_via_center(layers = self.m1_stack, @@ -201,11 +201,11 @@ class hierarchical_predecode(design.design): # ensure the bend is in the middle mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y) mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y) - self.add_path("metal1", [zr_pos, mid1_pos, mid2_pos, al_pos]) + self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos]) z_pin = self.inv_inst[num].get_pin("Z") self.add_layout_pin(text="out_{}".format(num), - layer="metal1", + layer="m1", offset=z_pin.ll(), height=z_pin.height(), width=z_pin.width()) @@ -226,7 +226,7 @@ class hierarchical_predecode(design.design): inv_out_pos = self.in_inst[inv_num].get_pin("Z").rc() right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(),0) rail_pos = vector(self.decode_rails[out_pin].x,y_offset) - self.add_path("metal1", [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) + self.add_path("m1", [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) self.add_via_center(layers = self.m1_stack, offset=rail_pos) @@ -234,7 +234,7 @@ class hierarchical_predecode(design.design): #route input inv_in_pos = self.in_inst[inv_num].get_pin("A").lc() in_pos = vector(self.input_rails[in_pin].x,inv_in_pos.y) - self.add_path("metal1", [in_pos, inv_in_pos]) + self.add_path("m1", [in_pos, inv_in_pos]) self.add_via_center(layers=self.m1_stack, offset=in_pos) @@ -255,7 +255,7 @@ class hierarchical_predecode(design.design): for rail_pin,gate_pin in zip(index_lst,gate_lst): pin_pos = self.nand_inst[k].get_pin(gate_pin).lc() rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y) - self.add_path("metal1", [rail_pos, pin_pos]) + self.add_path("m1", [rail_pos, pin_pos]) self.add_via_center(layers=self.m1_stack, offset=rail_pos) @@ -275,7 +275,7 @@ class hierarchical_predecode(design.design): for n in ["vdd", "gnd"]: nand_pin = self.nand_inst[num].get_pin(n) supply_offset = nand_pin.ll().scale(0,1) - self.add_rect(layer="metal1", + self.add_rect(layer="m1", offset=supply_offset, width=self.inv_inst[num].rx()) diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index 3459f5e0..33076bfb 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -160,7 +160,7 @@ class multibank(design.design): self.central_bus_width = self.m2_pitch * self.num_control_lines + 2*self.m2_width # A space for wells or jogging m2 - self.m2_gap = max(2*drc("pwell_to_nwell"] + drc["well_enclosure_active"), + self.m2_gap = max(2*drc("pwell_to_nwell"] + drc["well_enclose_active"), 2*self.m2_pitch) @@ -451,7 +451,7 @@ class multibank(design.design): # Connect the inverter output to the central bus out_pos = self.bank_select_inst.get_pin(gated_name).rc() bus_pos = vector(self.bus_xoffset[gated_name], out_pos.y) - self.add_path("metal3",[out_pos, bus_pos]) + self.add_path("m3",[out_pos, bus_pos]) self.add_via_center(layers=self.m2_stack, offset=bus_pos, rotate=90) @@ -512,7 +512,7 @@ class multibank(design.design): # 2 pitches on the right for vias/jogs to access the inputs control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, 0) control_bus_length = self.bitcell_array_inst.uy() - self.bus_xoffset = self.create_vertical_bus(layer="metal2", + self.bus_xoffset = self.create_vertical_bus(layer="m2", pitch=self.m2_pitch, offset=control_bus_offset, names=self.control_signals, @@ -530,9 +530,9 @@ class multibank(design.design): bitcell_br = self.bitcell_array_inst.get_pin("br_{}".format(i)).uc() yoffset = 0.5*(precharge_bl.y+bitcell_bl.y) - self.add_path("metal2",[precharge_bl, vector(precharge_bl.x,yoffset), + self.add_path("m2",[precharge_bl, vector(precharge_bl.x,yoffset), vector(bitcell_bl.x,yoffset), bitcell_bl]) - self.add_path("metal2",[precharge_br, vector(precharge_br.x,yoffset), + self.add_path("m2",[precharge_br, vector(precharge_br.x,yoffset), vector(bitcell_br.x,yoffset), bitcell_br]) @@ -550,9 +550,9 @@ class multibank(design.design): bitcell_br = self.bitcell_array_inst.get_pin("br_{}".format(i)).bc() yoffset = 0.5*(col_mux_bl.y+bitcell_bl.y) - self.add_path("metal2",[col_mux_bl, vector(col_mux_bl.x,yoffset), + self.add_path("m2",[col_mux_bl, vector(col_mux_bl.x,yoffset), vector(bitcell_bl.x,yoffset), bitcell_bl]) - self.add_path("metal2",[col_mux_br, vector(col_mux_br.x,yoffset), + self.add_path("m2",[col_mux_br, vector(col_mux_br.x,yoffset), vector(bitcell_br.x,yoffset), bitcell_br]) def route_sense_amp_to_col_mux_or_bitcell_array(self): @@ -573,9 +573,9 @@ class multibank(design.design): yoffset = 0.5*(sense_amp_bl.y+connect_bl.y) - self.add_path("metal2",[sense_amp_bl, vector(sense_amp_bl.x,yoffset), + self.add_path("m2",[sense_amp_bl, vector(sense_amp_bl.x,yoffset), vector(connect_bl.x,yoffset), connect_bl]) - self.add_path("metal2",[sense_amp_br, vector(sense_amp_br.x,yoffset), + self.add_path("m2",[sense_amp_br, vector(sense_amp_br.x,yoffset), vector(connect_br.x,yoffset), connect_br]) def route_sense_amp_to_trigate(self): @@ -590,7 +590,7 @@ class multibank(design.design): offset=tri_gate_in) self.add_via_center(layers=self.m2_stack, offset=sa_data_out) - self.add_path("metal3",[sa_data_out,tri_gate_in]) + self.add_path("m3",[sa_data_out,tri_gate_in]) def route_sense_amp_out(self): """ Add pins for the sense amp output """ @@ -644,14 +644,14 @@ class multibank(design.design): driver_in_pos = self.wordline_driver_inst.get_pin("in_{}".format(i)).lc() mid1 = decoder_out_pos.scale(0.5,1)+driver_in_pos.scale(0.5,0) mid2 = decoder_out_pos.scale(0.5,0)+driver_in_pos.scale(0.5,1) - self.add_path("metal1", [decoder_out_pos, mid1, mid2, driver_in_pos]) + self.add_path("m1", [decoder_out_pos, mid1, mid2, driver_in_pos]) # The mid guarantees we exit the input cell to the right. driver_wl_pos = self.wordline_driver_inst.get_pin("wl_{}".format(i)).rc() bitcell_wl_pos = self.bitcell_array_inst.get_pin("wl_{}".format(i)).lc() mid1 = driver_wl_pos.scale(0.5,1)+bitcell_wl_pos.scale(0.5,0) mid2 = driver_wl_pos.scale(0.5,0)+bitcell_wl_pos.scale(0.5,1) - self.add_path("metal1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) + self.add_path("m1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) @@ -698,8 +698,8 @@ class multibank(design.design): else: mid1_pos = vector(decode_out_pos.x + delta_offset + (self.num_col_addr_lines-i)*self.m2_pitch,decode_out_pos.y) mid2_pos = vector(mid1_pos.x,mux_addr_pos.y) - #self.add_wire(("metal1","via1","metal2"),[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos]) - self.add_path("metal1",[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos]) + #self.add_wire(self.m1_stack,[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos]) + self.add_path("m1",[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos]) @@ -715,7 +715,7 @@ class multibank(design.design): wl_name = "wl_{}".format(i) wl_pin = self.bitcell_array_inst.get_pin(wl_name) self.add_label(text=wl_name, - layer="metal1", + layer="m1", offset=wl_pin.center()) # Add the bitline names @@ -725,10 +725,10 @@ class multibank(design.design): bl_pin = self.bitcell_array_inst.get_pin(bl_name) br_pin = self.bitcell_array_inst.get_pin(br_name) self.add_label(text=bl_name, - layer="metal2", + layer="m2", offset=bl_pin.center()) self.add_label(text=br_name, - layer="metal2", + layer="m2", offset=br_pin.center()) # # Add the data output names to the sense amp output @@ -736,7 +736,7 @@ class multibank(design.design): # data_name = "data_{}".format(i) # data_pin = self.sense_amp_array_inst.get_pin(data_name) # self.add_label(text="sa_out_{}".format(i), - # layer="metal2", + # layer="m2", # offset=data_pin.center()) # Add labels on the decoder @@ -745,7 +745,7 @@ class multibank(design.design): pin_name = "in_{}".format(i) data_pin = self.wordline_driver_inst.get_pin(pin_name) self.add_label(text=data_name, - layer="metal1", + layer="m1", offset=data_pin.center()) @@ -765,7 +765,7 @@ class multibank(design.design): for (control_signal, pin_pos) in connection: control_pos = vector(self.bus_xoffset[control_signal].x ,pin_pos.y) - self.add_path("metal1", [control_pos, pin_pos]) + self.add_path("m1", [control_pos, pin_pos]) self.add_via_center(layers=self.m1_stack, offset=control_pos, rotate=90) @@ -776,7 +776,7 @@ class multibank(design.design): mid_pos = pin_pos + vector(0,self.m1_pitch) control_x_offset = self.bus_xoffset[control_signal].x control_pos = vector(control_x_offset + self.m1_width, mid_pos.y) - self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos]) + self.add_wire(self.m1_stack,[pin_pos, mid_pos, control_pos]) control_via_pos = vector(control_x_offset, mid_pos.y) self.add_via_center(layers=self.m1_stack, offset=control_via_pos, @@ -791,13 +791,13 @@ class multibank(design.design): if self.num_banks > 1: # it's not an input pin if we have multiple banks self.add_label_pin(text=ctrl, - layer="metal2", + layer="m2", offset=vector(x_offset, self.min_y_offset), width=self.m2_width, height=self.max_y_offset-self.min_y_offset) else: self.add_layout_pin(text=ctrl, - layer="metal2", + layer="m2", offset=vector(x_offset, self.min_y_offset), width=self.m2_width, height=self.max_y_offset-self.min_y_offset) @@ -807,12 +807,12 @@ class multibank(design.design): """ Helper routine to connect an unrotated/mirrored oriented instance to the rails """ in_pin = inst.get_pin(pin).lc() rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y) - self.add_wire(("metal3","via2","metal2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) + self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) # Bring it up to M2 for M2/M3 routing - self.add_via(layers=("metal1","via1","metal2"), + self.add_via(layers=self.m1_stack, offset=in_pin + contact.m1m2.offset, rotate=90) - self.add_via(layers=("metal2","via2","metal3"), + self.add_via(layers=self.m2_stack, offset=in_pin + self.m2m3_via_offset, rotate=90) @@ -821,10 +821,10 @@ class multibank(design.design): """ Helper routine to connect an unrotated/mirrored oriented instance to the rails """ in_pin = inst.get_pin(pin).rc() rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y) - self.add_wire(("metal3","via2","metal2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) - self.add_via(layers=("metal1","via1","metal2"), + self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) + self.add_via(layers=self.m1_stack, offset=in_pin + contact.m1m2.offset, rotate=90) - self.add_via(layers=("metal2","via2","metal3"), + self.add_via(layers=self.m2_stack, offset=in_pin + self.m2m3_via_offset, rotate=90) diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 0a624c60..7f1fdd49 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -92,7 +92,7 @@ class port_address(design.design): driver_in_pos = self.wordline_driver_inst.get_pin("in_{}".format(row)).lc() mid1 = decoder_out_pos.scale(0.5,1)+driver_in_pos.scale(0.5,0) mid2 = decoder_out_pos.scale(0.5,0)+driver_in_pos.scale(0.5,1) - self.add_path("metal1", [decoder_out_pos, mid1, mid2, driver_in_pos]) + self.add_path("m1", [decoder_out_pos, mid1, mid2, driver_in_pos]) @@ -149,7 +149,7 @@ class port_address(design.design): """ # A space for wells or jogging m2 - self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), + self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"), 3*self.m2_pitch) row_decoder_offset = vector(0,0) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index a5bc4399..33ecdd01 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -212,7 +212,7 @@ class port_data(design.design): # A space for wells or jogging m2 between modules - self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), + self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"), 3*self.m2_pitch) @@ -479,7 +479,7 @@ class port_data(design.design): offset=end_pos) # Route between write mask AND array and write driver array - self.add_wire(("metal1","via1","metal2"), [beg_pos, middle_pos, end_pos]) + self.add_wire(self.m1_stack, [beg_pos, middle_pos, end_pos]) def route_column_mux_to_precharge_array(self, port): @@ -655,9 +655,9 @@ class port_data(design.design): top_br = top_inst.get_pin(top_br_name.format(col+top_start_bit)).bc() yoffset = 0.5*(top_bl.y+bottom_bl.y) - self.add_path("metal2",[bottom_bl, vector(bottom_bl.x,yoffset), + self.add_path("m2",[bottom_bl, vector(bottom_bl.x,yoffset), vector(top_bl.x,yoffset), top_bl]) - self.add_path("metal2",[bottom_br, vector(bottom_br.x,yoffset), + self.add_path("m2",[bottom_br, vector(bottom_br.x,yoffset), vector(top_br.x,yoffset), top_br]) def graph_exclude_precharge(self): diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 2d98ba14..c2617f50 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -68,10 +68,10 @@ class precharge_array(design.design): def add_layout_pins(self): self.add_layout_pin(text="en_bar", - layer="metal1", + layer="m1", offset=self.pc_cell.get_pin("en_bar").ll(), width=self.width, - height=drc("minwidth_metal1")) + height=drc("minwidth_m1")) for inst in self.local_insts: self.copy_layout_pin(inst, "vdd") @@ -80,15 +80,15 @@ class precharge_array(design.design): inst = self.local_insts[i] bl_pin = inst.get_pin("bl") self.add_layout_pin(text="bl_{0}".format(i), - layer="metal2", + layer="m2", offset=bl_pin.ll(), - width=drc("minwidth_metal2"), + width=drc("minwidth_m2"), height=bl_pin.height()) br_pin = inst.get_pin("br") self.add_layout_pin(text="br_{0}".format(i), - layer="metal2", + layer="m2", offset=br_pin.ll(), - width=drc("minwidth_metal2"), + width=drc("minwidth_m2"), height=bl_pin.height()) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 639d0714..74962ba2 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -399,7 +399,7 @@ class replica_bitcell_array(design.design): else: height = self.height bl_pos = 0 - bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_metal1")) + bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_m1")) bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell return bl_wire diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index c3f63b19..5552ed55 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -116,7 +116,7 @@ class replica_column(design.design): for bl_name in self.cell.get_all_bitline_names(): bl_pin = self.cell_inst[0].get_pin(bl_name) self.add_layout_pin(text=bl_name, - layer="metal2", + layer="m2", offset=bl_pin.ll(), width=bl_pin.width(), height=self.height) @@ -125,7 +125,7 @@ class replica_column(design.design): for wl_name in self.cell.get_all_wl_names(): wl_pin = self.cell_inst[row].get_pin(wl_name) self.add_layout_pin(text="{0}_{1}".format(wl_name,row), - layer="metal1", + layer="m1", offset=wl_pin.ll().scale(0,1), width=self.width, height=wl_pin.height()) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 21ee4a8d..2447e4b8 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -102,13 +102,13 @@ class sense_amp_array(design.design): self.add_via_center(layers=self.m2_stack, offset=gnd_pos) self.add_layout_pin_rect_center(text="gnd", - layer="metal3", + layer="m3", offset=gnd_pos) vdd_pos = inst.get_pin("vdd").center() self.add_via_center(layers=self.m2_stack, offset=vdd_pos) self.add_layout_pin_rect_center(text="vdd", - layer="metal3", + layer="m3", offset=vdd_pos) bl_pin = inst.get_pin("bl") @@ -116,18 +116,18 @@ class sense_amp_array(design.design): dout_pin = inst.get_pin("dout") self.add_layout_pin(text="bl_{0}".format(i), - layer="metal2", + layer="m2", offset=bl_pin.ll(), width=bl_pin.width(), height=bl_pin.height()) self.add_layout_pin(text="br_{0}".format(i), - layer="metal2", + layer="m2", offset=br_pin.ll(), width=br_pin.width(), height=br_pin.height()) self.add_layout_pin(text="data_{0}".format(i), - layer="metal2", + layer="m2", offset=dout_pin.ll(), width=dout_pin.width(), height=dout_pin.height()) @@ -137,10 +137,10 @@ class sense_amp_array(design.design): # add sclk rail across entire array sclk_offset = self.amp.get_pin("en").ll().scale(0,1) self.add_layout_pin(text="en", - layer="metal1", + layer="m1", offset=sclk_offset, width=self.width, - height=drc("minwidth_metal1")) + height=drc("minwidth_m1")) def input_load(self): return self.amp.input_load() diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 3e6420b9..09f21cfa 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -113,13 +113,13 @@ class single_level_column_mux_array(design.design): mux_inst = self.mux_inst[col_num] offset = mux_inst.get_pin("bl").ll() self.add_layout_pin(text="bl_{}".format(col_num), - layer="metal2", + layer="m2", offset=offset, height=self.height-offset.y) offset = mux_inst.get_pin("br").ll() self.add_layout_pin(text="br_{}".format(col_num), - layer="metal2", + layer="m2", offset=offset, height=self.height-offset.y) @@ -137,7 +137,7 @@ class single_level_column_mux_array(design.design): for j in range(self.words_per_row): offset = vector(0, self.route_height + (j-self.words_per_row)*self.m1_pitch) self.add_layout_pin(text="sel_{}".format(j), - layer="metal1", + layer="m1", offset=offset, width=self.mux.width * self.columns) @@ -155,7 +155,7 @@ class single_level_column_mux_array(design.design): # use the y offset from the sel pin and the x offset from the gate offset = vector(gate_offset.x,self.get_pin("sel_{}".format(sel_index)).cy()) # Add the poly contact with a shift to account for the rotation - self.add_via_center(layers=("metal1", "contact", "poly"), + self.add_via_center(layers=("m1", "contact", "poly"), offset=offset) self.add_path("poly", [offset, gate_offset]) @@ -176,16 +176,16 @@ class single_level_column_mux_array(design.design): # These will be located below the select lines. Yes, these are M2 width # to ensure vias are enclosed and M1 min width rules. width = self.m2_width + self.mux.width * (self.words_per_row - 1) - self.add_path("metal1", [bl_out_offset, bl_out_offset+vector(width,0)]) - self.add_path("metal1", [br_out_offset, br_out_offset+vector(width,0)]) + self.add_path("m1", [bl_out_offset, bl_out_offset+vector(width,0)]) + self.add_path("m1", [br_out_offset, br_out_offset+vector(width,0)]) # Extend the bitline output rails and gnd downward on the first bit of each n-way mux self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j/self.words_per_row)), - layer="metal2", + layer="m2", start=bl_out_offset, end=bl_out_offset_end) self.add_layout_pin_segment_center(text="br_out_{}".format(int(j/self.words_per_row)), - layer="metal2", + layer="m2", start=br_out_offset, end=br_out_offset_end) @@ -200,8 +200,8 @@ class single_level_column_mux_array(design.design): else: - self.add_path("metal2", [ bl_out_offset, bl_out_offset_end]) - self.add_path("metal2", [ br_out_offset, br_out_offset_end]) + self.add_path("m2", [ bl_out_offset, bl_out_offset_end]) + self.add_path("m2", [ br_out_offset, br_out_offset_end]) # This via is on the right of the wire self.add_via_center(layers=self.m1_stack, diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index 501e2389..e7ebd802 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -83,14 +83,14 @@ class tri_gate_array(design.design): in_pin = self.tri_inst[i].get_pin("in") self.add_layout_pin(text="in_{0}".format(index), - layer="metal2", + layer="m2", offset=in_pin.ll(), width=in_pin.width(), height=in_pin.height()) out_pin = self.tri_inst[i].get_pin("out") self.add_layout_pin(text="out_{0}".format(index), - layer="metal2", + layer="m2", offset=out_pin.ll(), width=out_pin.width(), height=out_pin.height()) @@ -103,21 +103,21 @@ class tri_gate_array(design.design): self.add_via_center(layers=self.m2_stack, offset=pin_pos) self.add_layout_pin_rect_center(text=n, - layer="metal3", + layer="m3", offset=pin_pos) width = self.tri.width * self.columns - (self.words_per_row - 1) * self.tri.width en_pin = self.tri_inst[0].get_pin("en") self.add_layout_pin(text="en", - layer="metal1", + layer="m1", offset=en_pin.ll().scale(0, 1), width=width, - height=drc("minwidth_metal1")) + height=drc("minwidth_m1")) enbar_pin = self.tri_inst[0].get_pin("en_bar") self.add_layout_pin(text="en_bar", - layer="metal1", + layer="m1", offset=enbar_pin.ll().scale(0, 1), width=width, - height=drc("minwidth_metal1")) \ No newline at end of file + height=drc("minwidth_m1")) \ No newline at end of file diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 99365659..2af2c8c9 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -142,7 +142,7 @@ class wordline_driver(design.design): # Wordline enable connection en_offset = [self.m1_width + 2 * self.m1_space, 0] en_pin = self.add_layout_pin(text="en", - layer="metal2", + layer="m2", offset=en_offset, width=self.m2_width, height=self.height) @@ -155,7 +155,7 @@ class wordline_driver(design.design): a_pin = nand_inst.get_pin("A") a_pos = a_pin.lc() clk_offset = vector(en_pin.bc().x, a_pos.y) - self.add_segment_center(layer="metal1", + self.add_segment_center(layer="m1", start=clk_offset, end=a_pos) self.add_via_center(layers=self.m1_stack, @@ -167,7 +167,7 @@ class wordline_driver(design.design): # ensure the bend is in the middle mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y) mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y) - self.add_path("metal1", [zr_pos, mid1_pos, mid2_pos, al_pos]) + self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos]) # connect the decoder input pin to nand2 B b_pin = nand_inst.get_pin("B") @@ -182,7 +182,7 @@ class wordline_driver(design.design): # must under the clk line in M1 self.add_layout_pin_segment_center(text="in_{0}".format(row), - layer="metal1", + layer="m1", start=input_offset, end=mid_via_offset) self.add_via_center(layers=self.m1_stack, @@ -190,7 +190,7 @@ class wordline_driver(design.design): directions=("V", "V")) # now connect to the nand2 B - self.add_path("metal2", [mid_via_offset, b_pos]) + self.add_path("m2", [mid_via_offset, b_pos]) contact_offset = b_pos - vector(0.5 * contact.m1m2.height, 0) self.add_via_center(layers=self.m1_stack, offset=contact_offset, @@ -199,7 +199,7 @@ class wordline_driver(design.design): # output each WL on the right wl_offset = inv2_inst.get_pin("Z").rc() self.add_layout_pin_segment_center(text="wl_{0}".format(row), - layer="metal1", + layer="m1", start=wl_offset, end=wl_offset - vector(self.m1_width, 0)) diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 4dfa938c..ac4dab00 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -120,20 +120,20 @@ class write_driver_array(design.design): for i in range(self.word_size): din_pin = self.driver_insts[i].get_pin("din") self.add_layout_pin(text="data_{0}".format(i), - layer="metal2", + layer="m2", offset=din_pin.ll(), width=din_pin.width(), height=din_pin.height()) bl_pin = self.driver_insts[i].get_pin("bl") self.add_layout_pin(text="bl_{0}".format(i), - layer="metal2", + layer="m2", offset=bl_pin.ll(), width=bl_pin.width(), height=bl_pin.height()) br_pin = self.driver_insts[i].get_pin("br") self.add_layout_pin(text="br_{0}".format(i), - layer="metal2", + layer="m2", offset=br_pin.ll(), width=br_pin.width(), height=br_pin.height()) @@ -146,7 +146,7 @@ class write_driver_array(design.design): self.add_via_center(layers=self.m2_stack, offset=pin_pos) self.add_layout_pin_rect_center(text=n, - layer="metal3", + layer="m3", offset=pin_pos) if self.write_size: for bit in range(self.num_wmasks): @@ -165,7 +165,7 @@ class write_driver_array(design.design): height=en_pin.height()) else: self.add_layout_pin(text="en", - layer="metal1", + layer="m1", offset=self.driver_insts[0].get_pin("en").ll().scale(0,1), width=self.width) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 3a4ec651..40f386d2 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -114,7 +114,7 @@ class write_mask_and_array(design.design): # Extend metal3 to edge of AND array in multiport en_to_edge = self.and2.width - beg_en_pin.cx() self.add_layout_pin(text="en", - layer="metal3", + layer="m3", offset=beg_en_pin.bc(), width=end_en_pin.cx() - beg_en_pin.cx() + en_to_edge) self.add_via_center(layers=self.m1_stack, @@ -123,7 +123,7 @@ class write_mask_and_array(design.design): offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy())) else: self.add_layout_pin(text="en", - layer="metal3", + layer="m3", offset=beg_en_pin.bc(), width=end_en_pin.cx() - beg_en_pin.cx()) @@ -146,7 +146,7 @@ class write_mask_and_array(design.design): for n in ["gnd","vdd"]: pin = self.and2_insts[i].get_pin(n) next_pin = self.and2_insts[i+1].get_pin(n) - self.add_path("metal1",[pin.center(),next_pin.center()]) + self.add_path("m1",[pin.center(),next_pin.center()]) def get_cin(self): """Get the relative capacitance of all the input connections in the bank""" diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index d410a8c7..23fd5e5b 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -76,14 +76,14 @@ class pand2(pgate.pgate): a2_pin = self.inv_inst.get_pin("A") mid1_point = vector(0.5 * (z1_pin.cx() + a2_pin.cx()), z1_pin.cy()) mid2_point = vector(mid1_point, a2_pin.cy()) - self.add_path("metal1", + self.add_path("m1", [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()]) def add_layout_pins(self): # Continous vdd rail along with label. vdd_pin = self.inv_inst.get_pin("vdd") self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=vdd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) @@ -91,7 +91,7 @@ class pand2(pgate.pgate): # Continous gnd rail along with label. gnd_pin = self.inv_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=gnd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index b02e18e4..dd1d87f7 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -76,14 +76,14 @@ class pand3(pgate.pgate): a2_pin = self.inv_inst.get_pin("A") mid1_point = vector(0.5 * (z1_pin.cx()+a2_pin.cx()), z1_pin.cy()) mid2_point = vector(mid1_point, a2_pin.cy()) - self.add_path("metal1", + self.add_path("m1", [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()]) def add_layout_pins(self): # Continous vdd rail along with label. vdd_pin = self.inv_inst.get_pin("vdd") self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=vdd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) @@ -91,7 +91,7 @@ class pand3(pgate.pgate): # Continous gnd rail along with label. gnd_pin = self.inv_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=gnd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 0149f75f..3171324b 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -78,13 +78,13 @@ class pbuf(pgate.pgate): z1_pin = self.inv1_inst.get_pin("Z") a2_pin = self.inv2_inst.get_pin("A") mid_point = vector(z1_pin.cx(), a2_pin.cy()) - self.add_path("metal1", [z1_pin.center(), mid_point, a2_pin.center()]) + self.add_path("m1", [z1_pin.center(), mid_point, a2_pin.center()]) def add_layout_pins(self): # Continous vdd rail along with label. vdd_pin = self.inv1_inst.get_pin("vdd") self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=vdd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) @@ -92,7 +92,7 @@ class pbuf(pgate.pgate): # Continous gnd rail along with label. gnd_pin = self.inv1_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=gnd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index bb7739b7..5aa5393e 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -140,7 +140,7 @@ class pdriver(pgate.pgate): z_inst_list.append(self.inv_inst_list[x].get_pin("Z")) a_inst_list.append(self.inv_inst_list[x + 1].get_pin("A")) mid_point = vector(z_inst_list[x].cx(), a_inst_list[x].cy()) - self.add_path("metal1", + self.add_path("m1", [z_inst_list[x].center(), mid_point, a_inst_list[x].center()]) @@ -148,7 +148,7 @@ class pdriver(pgate.pgate): # Continous vdd rail along with label. vdd_pin = self.inv_inst_list[0].get_pin("vdd") self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=vdd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) @@ -156,7 +156,7 @@ class pdriver(pgate.pgate): # Continous gnd rail along with label. gnd_pin = self.inv_inst_list[0].get_pin("gnd") self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=gnd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index b55ad9c3..d5f2395b 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -59,7 +59,7 @@ class pgate(design.design): debug.error("Invalid supply name.", -1) if abs(height) > 0: - self.add_rect(layer="metal1", + self.add_rect(layer="m1", offset=source_pin.ll(), height=height, width=source_pin.width()) @@ -120,7 +120,7 @@ class pgate(design.design): directions=directions) self.add_layout_pin_rect_center(text=name, - layer="metal1", + layer="m1", offset=contact_offset, width=contact_m1_width, height=contact_m1_height) @@ -172,7 +172,7 @@ class pgate(design.design): # To the right a spacing away from the pmos right active edge contact_xoffset = pmos_pos.x + pmos.active_width \ - + drc("active_to_body_active") + + self.active_space # Must be at least an well enclosure of active down # from the top of the well @@ -189,7 +189,7 @@ class pgate(design.design): directions=("H", "V"), implant_type="n", well_type="n") - self.add_rect_center(layer="metal1", + self.add_rect_center(layer="m1", offset=contact_offset + vector(0, 0.5 * (self.height-contact_offset.y)), width=self.nwell_contact.mod.second_layer_width, height=self.height - contact_offset.y) @@ -227,7 +227,7 @@ class pgate(design.design): # To the right a spacing away from the nmos right active edge contact_xoffset = nmos_pos.x + nmos.active_width \ - + drc("active_to_body_active") + + self.active_space # Must be at least an well enclosure of active up # from the bottom of the well contact_yoffset = max(nmos_pos.y, @@ -243,7 +243,7 @@ class pgate(design.design): directions=("H", "V"), implant_type="p", well_type="p") - self.add_rect_center(layer="metal1", + self.add_rect_center(layer="m1", offset=contact_offset.scale(1,0.5), width=self.pwell_contact.mod.second_layer_width, height=contact_offset.y) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 5c53480b..1ff5b67b 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -96,14 +96,14 @@ class pinv(pgate.pgate): tx_height = nmos.poly_height + pmos.poly_height # rotated m1 pitch or poly to active spacing min_channel = max(contact.poly.width + self.m1_space, - contact.poly.width + 2 * drc("poly_to_active")) + contact.poly.width + 2 * self.poly_to_active) # This is the extra space needed to ensure DRC rules # to the active contacts extra_contact_space = max(-nmos.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space, - drc("poly_extend_active"), self.poly_space) + self.poly_extend_active, self.poly_space) total_height = tx_height + min_channel + 2 * self.top_bottom_space debug.check(self.height > total_height, "Cell height {0} too small for simple min height {1}.".format(self.height, @@ -153,7 +153,7 @@ class pinv(pgate.pgate): # the well width is determined the multi-finger PMOS device width plus # the well contact width and half well enclosure on both sides self.well_width = self.pmos.active_width + self.pmos.active_contact.width \ - + drc("active_to_body_active") + 2*drc("well_enclosure_active") + + self.active_space + 2*self.well_enclose_active self.width = self.well_width # Height is an input parameter, so it is not recomputed. @@ -178,12 +178,12 @@ class pinv(pgate.pgate): def route_supply_rails(self): """ Add vdd/gnd rails to the top and bottom. """ self.add_layout_pin_rect_center(text="gnd", - layer="metal1", + layer="m1", offset=vector(0.5 * self.width, 0), width=self.width) self.add_layout_pin_rect_center(text="vdd", - layer="metal1", + layer="m1", offset=vector(0.5 * self.width, self.height), width=self.width) @@ -238,7 +238,7 @@ class pinv(pgate.pgate): # Pick point at right most of NMOS and connect down to PMOS nmos_drain_pos = nmos_drain_pin.bc() pmos_drain_pos = vector(nmos_drain_pos.x, pmos_drain_pin.uc().y) - self.add_path("metal1", [nmos_drain_pos, pmos_drain_pos]) + self.add_path("m1", [nmos_drain_pos, pmos_drain_pos]) # Remember the mid for the output mid_drain_offset = vector(nmos_drain_pos.x, self.output_pos.y) @@ -247,13 +247,13 @@ class pinv(pgate.pgate): # This extends the output to the edge of the cell output_offset = mid_drain_offset.scale(0, 1) + vector(self.width, 0) self.add_layout_pin_segment_center(text="Z", - layer="metal1", + layer="m1", start=mid_drain_offset, end=output_offset) else: # This leaves the output as an internal pin (min sized) self.add_layout_pin_rect_center(text="Z", - layer="metal1", + layer="m1", offset=mid_drain_offset \ + vector(0.5 * self.m1_width, 0)) diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index 579e1198..b8ecb3bf 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -114,13 +114,13 @@ class pinvbuf(pgate.pgate): z1_pin = self.inv1_inst.get_pin("Z") a2_pin = self.inv2_inst.get_pin("A") mid_point = vector(z1_pin.cx(), a2_pin.cy()) - self.add_path("metal1", [z1_pin.center(), mid_point, a2_pin.center()]) + self.add_path("m1", [z1_pin.center(), mid_point, a2_pin.center()]) # inv2 Z to inv3 A z2_pin = self.inv2_inst.get_pin("Z") a3_pin = self.inv3_inst.get_pin("A") mid_point = vector(z2_pin.cx(), a3_pin.cy()) - self.add_path("metal1", [z2_pin.center(), mid_point, a3_pin.center()]) + self.add_path("m1", [z2_pin.center(), mid_point, a3_pin.center()]) # inv1 Z to inv4 A (up and over) z1_pin = self.inv1_inst.get_pin("Z") @@ -136,7 +136,7 @@ class pinvbuf(pgate.pgate): # Continous vdd rail along with label. vdd_pin = self.inv1_inst.get_pin("vdd") self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=vdd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) @@ -144,7 +144,7 @@ class pinvbuf(pgate.pgate): # Continous vdd rail along with label. gnd_pin = self.inv4_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=gnd_pin.ll().scale(0, 1), width=self.width, height=gnd_pin.height()) @@ -152,28 +152,28 @@ class pinvbuf(pgate.pgate): # Continous gnd rail along with label. gnd_pin = self.inv1_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=gnd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) z_pin = self.inv4_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", - layer="metal2", + layer="m2", offset=z_pin.center()) self.add_via_center(layers=self.m1_stack, offset=z_pin.center()) zb_pin = self.inv3_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Zb", - layer="metal2", + layer="m2", offset=zb_pin.center()) self.add_via_center(layers=self.m1_stack, offset=zb_pin.center()) a_pin = self.inv1_inst.get_pin("A") self.add_layout_pin_rect_center(text="A", - layer="metal2", + layer="m2", offset=a_pin.center()) self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 4623048c..8acde2ce 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -99,8 +99,8 @@ class pnand2(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. self.well_width = 2 * self.pmos.active_width + contact.active.width \ - + 2 * drc("active_to_body_active") \ - + 2 * drc("well_enclosure_active") + + 2 * self.active_space \ + + 2 * self.well_enclose_active self.width = self.well_width # Height is an input parameter, so it is not recomputed. @@ -110,17 +110,17 @@ class pnand2(pgate.pgate): extra_contact_space = max(-self.nmos.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, - drc("poly_extend_active"), self.poly_space) + self.poly_extend_active, self.poly_space) def route_supply_rails(self): """ Add vdd/gnd rails to the top and bottom. """ self.add_layout_pin_rect_center(text="gnd", - layer="metal1", + layer="m1", offset=vector(0.5*self.width, 0), width=self.width) self.add_layout_pin_rect_center(text="vdd", - layer="metal1", + layer="m1", offset=vector(0.5 * self.width, self.height), width=self.width) @@ -235,13 +235,13 @@ class pnand2(pgate.pgate): offset=out_offset) # PMOS1 to mid-drain to NMOS2 drain - self.add_path("metal2", + self.add_path("m2", [top_pin_offset, mid1_offset, out_offset, mid2_offset, bottom_pin_offset]) # This extends the output to the edge of the cell self.add_layout_pin_rect_center(text="Z", - layer="metal1", + layer="m1", offset=out_offset, width=contact.m1m2.first_layer_height, height=contact.m1m2.first_layer_width) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 6d885e25..7a773497 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -92,7 +92,7 @@ class pnand3(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. self.well_width = 3 * self.pmos.active_width + self.pmos.active_contact.width \ - + 2 * drc("active_to_body_active") + 2 * drc("well_enclosure_active") \ + + 2 * self.active_space + 2 * self.well_enclose_active \ - self.overlap_offset.x self.width = self.well_width # Height is an input parameter, so it is not recomputed. @@ -107,18 +107,18 @@ class pnand3(pgate.pgate): # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space \ + extra_contact_space, - drc("poly_extend_active"), + self.poly_extend_active, self.poly_space) def route_supply_rails(self): """ Add vdd/gnd rails to the top and bottom. """ self.add_layout_pin_rect_center(text="gnd", - layer="metal1", + layer="m1", offset=vector(0.5 * self.width, 0), width=self.width) self.add_layout_pin_rect_center(text="vdd", - layer="metal1", + layer="m1", offset=vector(0.5 * self.width, self.height), width=self.width) @@ -205,7 +205,7 @@ class pnand3(pgate.pgate): self.m1_space + 0.5 *contact.poly.width + 0.5 * self.m1_width) active_spacing = max(self.m1_space, - 0.5 * contact.poly.first_layer_width + drc("poly_to_active")) + 0.5 * contact.poly.first_layer_width + self.poly_to_active) inputC_yoffset = self.nmos3_pos.y + self.nmos.active_height + active_spacing self.route_input_gate(self.pmos3_inst, self.nmos3_inst, @@ -245,16 +245,16 @@ class pnand3(pgate.pgate): offset=nmos3_pin.center()) # PMOS3 and NMOS3 are drain aligned - self.add_path("metal2", [pmos3_pin.bc(), nmos3_pin.uc()]) + self.add_path("m2", [pmos3_pin.bc(), nmos3_pin.uc()]) # Route in the A input track (top track) mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset) - self.add_path("metal2", [pmos1_pin.bc(), mid_offset, nmos3_pin.uc()]) + self.add_path("m2", [pmos1_pin.bc(), mid_offset, nmos3_pin.uc()]) # This extends the output to the edge of the cell self.add_via_center(layers=self.m1_stack, offset=mid_offset) self.add_layout_pin_rect_center(text="Z", - layer="metal1", + layer="m1", offset=mid_offset, width=contact.m1m2.first_layer_width, height=contact.m1m2.first_layer_height) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index a79d19a0..d75df0a9 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -97,9 +97,8 @@ class pnor2(pgate.pgate): # Enclosure space on the sides. self.well_width = 2 * self.pmos.active_width \ + self.pmos.active_contact.width \ - + 2 * drc("active_to_body_active") \ - + 2 * drc("well_enclosure_active") - + + 2 * self.active_space \ + + 2 * self.well_enclose_active self.width = self.well_width # Height is an input parameter, so it is not recomputed. @@ -108,18 +107,18 @@ class pnor2(pgate.pgate): extra_contact_space = max(-self.nmos.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, - drc("poly_extend_active"), + self.poly_extend_active, self.poly_space) def route_supply_rails(self): """ Add vdd/gnd rails to the top and bottom. """ self.add_layout_pin_rect_center(text="gnd", - layer="metal1", + layer="m1", offset=vector(0.5 * self.width, 0), width=self.width) self.add_layout_pin_rect_center(text="vdd", - layer="metal1", + layer="m1", offset=vector(0.5 * self.width, self.height), width=self.width) @@ -226,15 +225,15 @@ class pnor2(pgate.pgate): mid3_offset = mid2_offset + vector(self.m2_width, 0) # PMOS1 to mid-drain to NMOS2 drain - self.add_path("metal2", + self.add_path("m2", [pmos_pin.bc(), mid2_offset, mid3_offset]) - self.add_path("metal2", + self.add_path("m2", [nmos_pin.rc(), mid1_offset, mid2_offset]) # This extends the output to the edge of the cell self.add_via_center(layers=self.m1_stack, offset=mid3_offset) self.add_layout_pin_rect_center(text="Z", - layer="metal1", + layer="m1", offset=mid3_offset, width=contact.m1m2.first_layer_height, height=contact.m1m2.first_layer_width) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 9641a1f3..784bb418 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -72,7 +72,7 @@ class precharge(design.design): # Adds the rail across the width of the cell vdd_position = vector(0.5 * self.width, self.height) - self.add_rect_center(layer="metal1", + self.add_rect_center(layer="m1", offset=vdd_position, width=self.width, height=self.m1_width) @@ -80,7 +80,7 @@ class precharge(design.design): pmos_pin = self.upper_pmos2_inst.get_pin("S") # center of vdd rail pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y) - self.add_path("metal1", [pmos_pin.uc(), pmos_vdd_pos]) + self.add_path("m1", [pmos_pin.uc(), pmos_vdd_pos]) # Add vdd pin above the transistor self.add_power_pin("vdd", pmos_pin.center(), vertical=True) @@ -164,7 +164,7 @@ class precharge(design.design): # adds the en rail on metal1 self.add_layout_pin_segment_center(text="en_bar", - layer="metal1", + layer="m1", start=offset.scale(0, 1), end=offset.scale(0, 1) + vector(self.width, 0)) @@ -176,7 +176,7 @@ class precharge(design.design): # adds the contact from active to metal1 well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \ + vector(0, self.upper_pmos1_inst.uy() + contact.well.height / 2 \ - + drc("well_extend_active")) + + self.well_extend_active) self.add_via_center(layers=self.active_stack, offset=well_contact_pos, implant_type="n", @@ -200,7 +200,7 @@ class precharge(design.design): offset = vector(self.bitcell.get_pin(self.bitcell_bl).cx(), 0) \ - vector(0.5 * self.m2_width, 0) self.bl_pin = self.add_layout_pin(text="bl", - layer="metal2", + layer="m2", offset=offset, height=self.height) @@ -208,7 +208,7 @@ class precharge(design.design): offset = vector(self.bitcell.get_pin(self.bitcell_br).cx(), 0) \ - vector(0.5 * self.m2_width, 0) self.br_pin = self.add_layout_pin(text="br", - layer="metal2", + layer="m2", offset=offset, height=self.height) @@ -258,7 +258,7 @@ class precharge(design.design): left_pos = vector(min(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) right_pos = vector(max(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) - self.add_path("metal1", [left_pos, right_pos] ) + self.add_path("m1", [left_pos, right_pos] ) def connect_pmos_m2(self, pmos_pin, bit_pin): """ @@ -268,7 +268,7 @@ class precharge(design.design): left_pos = vector(min(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) right_pos = vector(max(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) - self.add_path("metal2", [left_pos, right_pos], self.bl_contact.height) + self.add_path("m2", [left_pos, right_pos], self.bl_contact.height) def get_en_cin(self): """Get the relative capacitance of the enable in the precharge cell""" diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index 4a17b46a..5c0028b2 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -73,7 +73,7 @@ class ptristate_inv(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.well_width = 2 * self.pmos.active_width + drc("well_enclosure_active") + self.well_width = 2 * self.pmos.active_width + self.well_enclose_active # Add an extra space because we route the output on the right of the S/D self.width = self.well_width + 0.5 * self.m1_space @@ -101,12 +101,12 @@ class ptristate_inv(pgate.pgate): def route_supply_rails(self): """ Add vdd/gnd rails to the top and bottom. """ self.add_layout_pin_rect_center(text="gnd", - layer="metal1", + layer="m1", offset=vector(0.5 * self.width, 0), width=self.width) self.add_layout_pin_rect_center(text="vdd", - layer="metal1", + layer="m1", offset=vector(0.5 * self.width, self.height), width=self.width) @@ -181,7 +181,7 @@ class ptristate_inv(pgate.pgate): pmos_drain_pos = pmos_drain_pin.ur() self.add_layout_pin(text="out", - layer="metal1", + layer="m1", offset=nmos_drain_pos, height=pmos_drain_pos.y - nmos_drain_pos.y) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 61610a88..9907485f 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -91,8 +91,8 @@ class ptx(design.design): # " ".join(self.pins))) # Just make a guess since these will actually # be decided in the layout later. - area_sd = 2.5 * drc("minwidth_poly") * self.tx_width - perimeter_sd = 2 * drc("minwidth_poly") + 2 * self.tx_width + area_sd = 2.5 * self.poly_width * self.tx_width + perimeter_sd = 2 * self.poly_width + 2 * self.tx_width main_str = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], self.mults, self.tx_width, @@ -136,7 +136,7 @@ class ptx(design.design): self.contact_pitch = 2 * self.contact_to_gate + self.contact_width + self.poly_width # The enclosure of an active contact. Not sure about second term. - active_enclose_contact = max(drc("active_enclosure_contact"), + active_enclose_contact = max(self.active_enclose_contact, (self.active_width - self.contact_width) / 2) # This is the distance from the edge of poly to the contacted end of active @@ -180,11 +180,11 @@ class ptx(design.design): # Min area results are just flagged for now. - debug.check(self.active_width * self.active_height >= drc("minarea_active"), + debug.check(self.active_width * self.active_height >= self.minarea_active, "Minimum active area violated.") # We do not want to increase the poly dimensions to fix # an area problem as it would cause an LVS issue. - debug.check(self.poly_width * self.poly_height >= drc("minarea_poly"), + debug.check(self.poly_width * self.poly_height >= self.minarea_poly, "Minimum poly area violated.") def connect_fingered_poly(self, poly_positions): @@ -219,7 +219,7 @@ class ptx(design.design): layer="poly", offset=poly_offset, width=poly_width, - height=drc("minwidth_poly")) + height=self.poly_width) def connect_fingered_active(self, drain_positions, source_positions): @@ -249,12 +249,12 @@ class ptx(design.design): self.remove_layout_pin("S") # remove the individual connections # Add each vertical segment for a in source_positions: - self.add_path(("metal1"), + self.add_path(("m1"), [a, a + pin_offset.scale(source_dir, source_dir)]) # Add a single horizontal pin self.add_layout_pin_segment_center(text="S", - layer="metal1", + layer="m1", start=source_positions[0] + source_offset - end_offset, end=source_positions[-1] + source_offset + end_offset) @@ -263,10 +263,10 @@ class ptx(design.design): self.remove_layout_pin("D") # remove the individual connections # Add each vertical segment for a in drain_positions: - self.add_path(("metal1"), [a,a+drain_offset]) + self.add_path(("m1"), [a,a+drain_offset]) # Add a single horizontal pin self.add_layout_pin_segment_center(text="D", - layer="metal1", + layer="m1", start=drain_positions[0] + drain_offset - end_offset, end=drain_positions[-1] + drain_offset + end_offset) @@ -313,7 +313,7 @@ class ptx(design.design): height=self.active_height) # If the implant must enclose the active, shift offset # and increase width/height - enclose_width = drc("implant_enclosure_active") + enclose_width = self.implant_enclose_active enclose_offset = [enclose_width] * 2 self.add_rect(layer="{}implant".format(self.implant_type), offset=self.active_offset - enclose_offset, @@ -380,7 +380,7 @@ class ptx(design.design): implant_type=self.implant_type, well_type=self.well_type) self.add_layout_pin_rect_center(text="S", - layer="metal1", + layer="m1", offset=pos, width=contact.mod.second_layer_width, height=contact.mod.second_layer_height) @@ -394,7 +394,7 @@ class ptx(design.design): implant_type=self.implant_type, well_type=self.well_type) self.add_layout_pin_rect_center(text="D", - layer="metal1", + layer="m1", offset=pos, width=contact.mod.second_layer_width, height=contact.mod.second_layer_height) diff --git a/compiler/pgates/pwrite_driver.py b/compiler/pgates/pwrite_driver.py index a808737b..2dc356c3 100644 --- a/compiler/pgates/pwrite_driver.py +++ b/compiler/pgates/pwrite_driver.py @@ -131,26 +131,26 @@ class pwrite_driver(design.design): bl_xoffset = left_x bl_out=vector(bl_xoffset, self.height) bl_in=self.bl_inst.get_pin("out").center() - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=bl_in) bl_mid = vector(bl_out.x,bl_in.y) - self.add_path("metal2", [bl_in, bl_mid, bl_out]) + self.add_path("m2", [bl_in, bl_mid, bl_out]) self.add_layout_pin_rect_center(text="bl", - layer="metal2", + layer="m2", offset=bl_out) br_xoffset = right_x br_out=vector(br_xoffset, self.height) br_in=self.br_inst.get_pin("out").center() - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_via_center(layers=self.m1_stack, offset=br_in) br_mid = vector(br_out.x,br_in.y) - self.add_path("metal2", [br_in, br_mid, br_out]) + self.add_path("m2", [br_in, br_mid, br_out]) self.add_layout_pin_rect_center(text="br", - layer="metal2", + layer="m2", offset=br_out) #br_xoffset = b.get_pin("br".cx() @@ -162,19 +162,19 @@ class pwrite_driver(design.design): track_xoff = self.get_m2_track(1) din_loc = self.din_inst.get_pin("A").center() - self.add_via_stack("metal1", "metal2", din_loc) + self.add_via_stack("m1", "m2", din_loc) din_track = vector(track_xoff,din_loc.y) br_in = self.br_inst.get_pin("in").center() - self.add_via_stack("metal1", "metal2", br_in) + self.add_via_stack("m1", "m2", br_in) br_track = vector(track_xoff,br_in.y) din_in = vector(track_xoff,0) - self.add_path("metal2", [din_in, din_track, din_loc, din_track, br_track, br_in]) + self.add_path("m2", [din_in, din_track, din_loc, din_track, br_track, br_in]) self.add_layout_pin_rect_center(text="din", - layer="metal2", + layer="m2", offset=din_in) def route_din_bar(self): @@ -183,19 +183,19 @@ class pwrite_driver(design.design): track_xoff = self.get_m4_track(self.din_bar_track) din_bar_in = self.din_inst.get_pin("Z").center() - self.add_via_stack("metal1", "metal3", din_bar_in) + self.add_via_stack("m1", "m3", din_bar_in) din_bar_track = vector(track_xoff,din_bar_in.y) bl_in = self.bl_inst.get_pin("in").center() - self.add_via_stack("metal1", "metal3", bl_in) + self.add_via_stack("m1", "m3", bl_in) bl_track = vector(track_xoff,bl_in.y) din_in = vector(track_xoff,0) - self.add_wire(("metal3","via3","metal4"), [din_bar_in, din_bar_track, bl_track, bl_in]) + self.add_wire(self.m3_stack, [din_bar_in, din_bar_track, bl_track, bl_in]) self.add_layout_pin_rect_center(text="din", - layer="metal4", + layer="m4", offset=din_in) @@ -206,22 +206,22 @@ class pwrite_driver(design.design): # This M2 pitch is a hack since the A and Z pins align horizontally en_bar_loc = self.en_inst.get_pin("Z").uc() en_bar_track = vector(track_xoff, en_bar_loc.y) - self.add_via_stack("metal1", "metal3", en_bar_loc) + self.add_via_stack("m1", "m3", en_bar_loc) # This is a U route to the right down then left bl_en_loc = self.bl_inst.get_pin("en_bar").center() bl_en_track = vector(track_xoff, bl_en_loc.y) - self.add_via_stack("metal1", "metal3", bl_en_loc) + self.add_via_stack("m1", "m3", bl_en_loc) br_en_loc = self.br_inst.get_pin("en_bar").center() br_en_track = vector(track_xoff, bl_en_loc.y) - self.add_via_stack("metal1", "metal3", br_en_loc) + self.add_via_stack("m1", "m3", br_en_loc) # L shape - self.add_wire(("metal3","via3","metal4"), + self.add_wire(self.m3_stack, [en_bar_loc, en_bar_track, bl_en_track]) # U shape - self.add_wire(("metal3","via3","metal4"), + self.add_wire(self.m3_stack, [bl_en_loc, bl_en_track, br_en_track, br_en_loc]) @@ -233,30 +233,30 @@ class pwrite_driver(design.design): # The en pin will be over the vdd rail vdd_yloc = self.en_inst.get_pin("vdd").cy() self.add_layout_pin_segment_center(text="en", - layer="metal3", + layer="m3", start=vector(0,vdd_yloc), end=vector(self.width,vdd_yloc)) en_loc = self.en_inst.get_pin("A").center() en_rail = vector(en_loc.x, vdd_yloc) - self.add_via_stack("metal1", "metal2", en_loc) - self.add_path("metal2", [en_loc, en_rail]) - self.add_via_stack("metal2", "metal3", en_rail) + self.add_via_stack("m1", "m2", en_loc) + self.add_path("m2", [en_loc, en_rail]) + self.add_via_stack("m2", "m3", en_rail) # Start point in the track on the pin rail en_track = vector(track_xoff, vdd_yloc) - self.add_via_stack("metal3", "metal4", en_track) + self.add_via_stack("m3", "m4", en_track) # This is a U route to the right down then left bl_en_loc = self.bl_inst.get_pin("en").center() bl_en_track = vector(track_xoff, bl_en_loc.y) - self.add_via_stack("metal1", "metal3", bl_en_loc) + self.add_via_stack("m1", "m3", bl_en_loc) br_en_loc = self.br_inst.get_pin("en").center() br_en_track = vector(track_xoff, bl_en_loc.y) - self.add_via_stack("metal1", "metal3", br_en_loc) + self.add_via_stack("m1", "m3", br_en_loc) # U shape - self.add_wire(("metal3","via3","metal4"), + self.add_wire(self.m3_stack, [en_track, bl_en_track, bl_en_loc, bl_en_track, br_en_track, br_en_loc]) @@ -284,7 +284,7 @@ class pwrite_driver(design.design): # Continous vdd rail along with label. vdd_pin=inst.get_pin("vdd") self.add_layout_pin(text="vdd", - layer="metal1", + layer="m1", offset=vdd_pin.ll().scale(0,1), width=self.width, height=vdd_pin.height()) @@ -292,7 +292,7 @@ class pwrite_driver(design.design): # Continous gnd rail along with label. gnd_pin=inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="metal1", + layer="m1", offset=gnd_pin.ll().scale(0,1), width=self.width, height=vdd_pin.height()) diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 525c1680..18b4b10f 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -65,21 +65,21 @@ class single_level_column_mux(pgate.pgate): # bl and br self.add_layout_pin(text="bl", - layer="metal2", + layer="m2", offset=bl_pos + vector(0, self.height - self.pin_height), height=self.pin_height) self.add_layout_pin(text="br", - layer="metal2", + layer="m2", offset=br_pos + vector(0, self.height - self.pin_height), height=self.pin_height) # bl_out and br_out self.add_layout_pin(text="bl_out", - layer="metal2", + layer="m2", offset=bl_pos, height=self.pin_height) self.add_layout_pin(text="br_out", - layer="metal2", + layer="m2", offset=br_pos, height=self.pin_height) @@ -141,7 +141,7 @@ class single_level_column_mux(pgate.pgate): # bl -> nmos_upper/D on metal1 # bl_out -> nmos_upper/S on metal2 - self.add_path("metal1", + self.add_path("m1", [bl_pin.ll(), vector(nmos_upper_d_pin.cx(), bl_pin.by()), nmos_upper_d_pin.center()]) # halfway up, move over @@ -149,12 +149,12 @@ class single_level_column_mux(pgate.pgate): + nmos_upper_s_pin.bc().scale(0, 0.4) mid2 = bl_out_pin.uc().scale(0, 0.4) \ + nmos_upper_s_pin.bc().scale(1, 0.4) - self.add_path("metal2", + self.add_path("m2", [bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.bc()]) # br -> nmos_lower/D on metal2 # br_out -> nmos_lower/S on metal1 - self.add_path("metal1", + self.add_path("m1", [br_out_pin.uc(), vector(nmos_lower_s_pin.cx(), br_out_pin.uy()), nmos_lower_s_pin.center()]) @@ -163,7 +163,7 @@ class single_level_column_mux(pgate.pgate): + nmos_lower_d_pin.uc().scale(0,0.5) mid2 = br_pin.bc().scale(0,0.5) \ + nmos_lower_d_pin.uc().scale(1,0.5) - self.add_path("metal2", + self.add_path("m2", [br_pin.bc(), mid1, mid2, nmos_lower_d_pin.uc()]) def add_wells(self): @@ -186,7 +186,7 @@ class single_level_column_mux(pgate.pgate): self.add_via_center(layers=self.m2_stack, offset=active_pos) self.add_layout_pin_rect_center(text="gnd", - layer="metal3", + layer="m3", offset=active_pos) # Add well enclosure over all the tx and contact diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 6c887790..151c8a70 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -261,18 +261,18 @@ class sram_1bank(sram_base): # This is the steiner point where the net branches out clk_steiner_pos = vector(mid1_pos.x, control_clk_buf_pos.y) - self.add_path("metal1", [control_clk_buf_pos, clk_steiner_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), + self.add_path("m1", [control_clk_buf_pos, clk_steiner_pos]) + self.add_via_center(layers=self.m1_stack, offset=clk_steiner_pos) # Note, the via to the control logic is taken care of above - self.add_wire(("metal3","via2","metal2"),[row_addr_clk_pos, mid1_pos, clk_steiner_pos]) + self.add_wire(("m3","via2","m2"),[row_addr_clk_pos, mid1_pos, clk_steiner_pos]) if self.col_addr_dff: dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk") dff_clk_pos = dff_clk_pin.center() mid_pos = vector(clk_steiner_pos.x, dff_clk_pos.y) - self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, clk_steiner_pos]) + self.add_wire(("m3","via2","m2"),[dff_clk_pos, mid_pos, clk_steiner_pos]) if port in self.write_ports: data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk") @@ -280,8 +280,8 @@ class sram_1bank(sram_base): mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y) # In some designs, the steiner via will be too close to the mid_pos via # so make the wire as wide as the contacts - self.add_path("metal2",[mid_pos, clk_steiner_pos], width=max(m2m3.width,m2m3.height)) - self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos]) + self.add_path("m2",[mid_pos, clk_steiner_pos], width=max(m2m3.width,m2m3.height)) + self.add_wire(("m3","via2","m2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos]) if self.write_size: wmask_dff_clk_pin = self.wmask_dff_insts[port].get_pin("clk") @@ -289,8 +289,8 @@ class sram_1bank(sram_base): mid_pos = vector(clk_steiner_pos.x, wmask_dff_clk_pos.y) # In some designs, the steiner via will be too close to the mid_pos via # so make the wire as wide as the contacts - self.add_path("metal2", [mid_pos, clk_steiner_pos], width=max(m2m3.width, m2m3.height)) - self.add_wire(("metal3", "via2", "metal2"), [wmask_dff_clk_pos, mid_pos, clk_steiner_pos]) + self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2m3.width, m2m3.height)) + self.add_wire(("m3", "via2", "m2"), [wmask_dff_clk_pos, mid_pos, clk_steiner_pos]) def route_control_logic(self): @@ -323,8 +323,8 @@ class sram_1bank(sram_base): flop_pos = flop_pin.center() bank_pos = bank_pin.center() mid_pos = vector(bank_pos.x,flop_pos.y) - self.add_wire(("metal3","via2","metal2"),[flop_pos, mid_pos,bank_pos]) - self.add_via_center(layers=("metal2","via2","metal3"), + self.add_wire(("m3","via2","m2"),[flop_pos, mid_pos,bank_pos]) + self.add_via_center(layers=self.m2_stack, offset=flop_pos) def route_col_addr_dff(self): @@ -336,7 +336,7 @@ class sram_1bank(sram_base): offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) bus_names = ["addr_{}".format(x) for x in range(self.col_addr_size)] - col_addr_bus_offsets = self.create_horizontal_bus(layer="metal1", + col_addr_bus_offsets = self.create_horizontal_bus(layer="m1", pitch=self.m1_pitch, offset=offset, names=bus_names, diff --git a/compiler/sram/sram_2bank.py b/compiler/sram/sram_2bank.py index e1224795..dace1ed9 100644 --- a/compiler/sram/sram_2bank.py +++ b/compiler/sram/sram_2bank.py @@ -103,25 +103,25 @@ class sram_2bank(sram_base): for n in self.control_logic_outputs + ["vdd", "gnd"]: pins = self.control_logic_inst.get_pins(n) for pin in pins: - if pin.layer=="metal2": + if pin.layer=="m2": pin_pos = pin.bc() break rail_pos = vector(pin_pos.x,self.horz_control_bus_positions[n].y) - self.add_path("metal2",[pin_pos,rail_pos]) - self.add_via_center(("metal1","via1","metal2"),rail_pos) + self.add_path("m2",[pin_pos,rail_pos]) + self.add_via_center(self.m1_stack,rail_pos) # connect the control logic cross bar for n in self.control_logic_outputs: cross_pos = vector(self.vert_control_bus_positions[n].x,self.horz_control_bus_positions[n].y) - self.add_via_center(("metal1","via1","metal2"),cross_pos) + self.add_via_center(self.m1_stack,cross_pos) # connect the bank select signals to the vertical bus for i in range(self.num_banks): pin = self.bank_inst[i].get_pin("bank_sel") pin_pos = pin.rc() if i==0 else pin.lc() rail_pos = vector(self.vert_control_bus_positions["bank_sel[{}]".format(i)].x,pin_pos.y) - self.add_path("metal3",[pin_pos,rail_pos]) - self.add_via_center(("metal2","via2","metal3"),rail_pos) + self.add_path("m3",[pin_pos,rail_pos]) + self.add_via_center(self.m2_stack,rail_pos) def route_single_msb_address(self): """ Route one MSB address bit for 2-bank SRAM """ @@ -129,37 +129,37 @@ class sram_2bank(sram_base): # connect the bank MSB flop supplies vdd_pins = self.msb_address_inst.get_pins("vdd") for vdd_pin in vdd_pins: - if vdd_pin.layer != "metal1": continue + if vdd_pin.layer != "m1": continue vdd_pos = vdd_pin.bc() down_pos = vdd_pos - vector(0,self.m1_pitch) rail_pos = vector(vdd_pos.x,self.horz_control_bus_positions["vdd"].y) - self.add_path("metal1",[vdd_pos,down_pos]) - self.add_via_center(("metal1","via1","metal2"),down_pos,rotate=90) - self.add_path("metal2",[down_pos,rail_pos]) - self.add_via_center(("metal1","via1","metal2"),rail_pos) + self.add_path("m1",[vdd_pos,down_pos]) + self.add_via_center(self.m1_stack,down_pos,rotate=90) + self.add_path("m2",[down_pos,rail_pos]) + self.add_via_center(self.m1_stack,rail_pos) gnd_pins = self.msb_address_inst.get_pins("gnd") # Only add the ground connection to the lowest metal2 rail in the flop array # FIXME: SCMOS doesn't have a vertical rail in the cell, or we could use those lowest_y = None for gnd_pin in gnd_pins: - if gnd_pin.layer != "metal2": continue + if gnd_pin.layer != "m2": continue if lowest_y==None or gnd_pin.by() Date: Tue, 17 Dec 2019 11:23:59 -0800 Subject: [PATCH 076/521] Fix over-writing of active spacing rule. --- compiler/base/design.py | 44 ++++++++++++++++--------------- technology/freepdk45/tech/tech.py | 5 ++-- 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/compiler/base/design.py b/compiler/base/design.py index 3b6ae914..2b11111d 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -81,27 +81,29 @@ class design(hierarchy_design): setattr(self, match.group(0), drc(match.group(0))) # These are for debugging previous manual rules - # print("poly_width", self.poly_width) - # print("poly_space", self.poly_space) - # print("m1_width", self.m1_width) - # print("m1_space", self.m1_space) - # print("m2_width", self.m2_width) - # print("m2_space", self.m2_space) - # print("m3_width", self.m3_width) - # print("m3_space", self.m3_space) - # print("m4_width", self.m4_width) - # print("m4_space", self.m4_space) - # print("active_width", self.active_width) - # print("active_space", self.active_space) - # print("contact_width", self.contact_width) - # print("poly_to_active", self.poly_to_active) - # print("poly_extend_active", self.poly_extend_active) - # print("poly_to_contact", self.poly_to_contact) - # print("contact_to_gate", self.contact_to_gate) - # print("well_enclose_active", self.well_enclose_active) - # print("implant_enclose_active", self.implant_enclose_active) - # print("implant_space", self.implant_space) - + if False: + print("poly_width", self.poly_width) + print("poly_space", self.poly_space) + print("m1_width", self.m1_width) + print("m1_space", self.m1_space) + print("m2_width", self.m2_width) + print("m2_space", self.m2_space) + print("m3_width", self.m3_width) + print("m3_space", self.m3_space) + print("m4_width", self.m4_width) + print("m4_space", self.m4_space) + print("active_width", self.active_width) + print("active_space", self.active_space) + print("contact_width", self.contact_width) + print("poly_to_active", self.poly_to_active) + print("poly_extend_active", self.poly_extend_active) + print("poly_to_contact", self.poly_to_contact) + print("contact_to_gate", self.contact_to_gate) + print("well_enclose_active", self.well_enclose_active) + print("implant_enclose_active", self.implant_enclose_active) + print("implant_space", self.implant_space) + import sys; sys.exit(1) + def setup_multiport_constants(self): """ These are contants and lists that aid multiport design. diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 78b031c4..d87e98f1 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -152,12 +152,11 @@ drc["poly_to_field_poly"] = 0.075 # Not a rule drc["minarea_poly"] = 0.0 -# ACTIVE.2 Minimum spacing of active -drc["active_to_active"] = 0.08 # ACTIVE.1 Minimum width of active +# ACTIVE.2 Minimum spacing of active drc.add_layer("active", width = 0.09, - spacing = 0) + spacing = 0.08) # ACTIVE.3 Minimum enclosure/spacing of nwell/pwell to active drc.add_enclosure("well", layer = "active", From c025ce63563ee64b617fa054f28392ff7388fbc7 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 17 Dec 2019 14:06:23 -0800 Subject: [PATCH 077/521] Add li to preferred direction --- compiler/base/hierarchy_layout.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 7f23e942..95b27618 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -390,10 +390,10 @@ class layout(): """ Return the preferred routing directions """ if layer in ["m1", "m3", "m5"]: return "H" - elif layer in ["active", "poly", "m2", "m4"]: + elif layer in ["active", "poly", "li", "m2", "m4"]: return "V" else: - return "N" + debug.error("Unable to find preferred direction for {}".format(layer)) def add_via(self, layers, offset, size=[1,1], directions=None, implant_type=None, well_type=None): From 449b0a7c28d8b4be4c8b17e675214ebecfe66703 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Tue, 17 Dec 2019 22:36:38 +0000 Subject: [PATCH 078/521] Make wire test programmatic --- compiler/tests/03_wire_test.py | 121 +++++++-------------------------- 1 file changed, 23 insertions(+), 98 deletions(-) diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index ae4f8499..bd4b9345 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -22,107 +22,32 @@ class wire_test(openram_test): import wire import tech import design - - min_space = 2 * (tech.drc["minwidth_poly"] + - tech.drc["minwidth_m1"]) - layer_stack = tech.poly_stack - old_position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - position_list = [[x-min_space, y-min_space] for x,y in old_position_list] - w = design.design("wire_test1") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) - min_space = 2 * (tech.drc["minwidth_poly"] + - tech.drc["minwidth_m1"]) - layer_stack = tech.poly_stack - old_position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - position_list = [[x+min_space, y+min_space] for x,y in old_position_list] - w = design.design("wire_test2") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) + layer_stacks = [tech.poly_stack] + tech.beol_stacks - min_space = 2 * (tech.drc["minwidth_m2"] + - tech.drc["minwidth_m1"]) - layer_stack = tech.m1_stack - position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - w = design.design("wire_test3") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) + for reverse in [False, True]: + for stack in layer_stacks: + if reverse: + layer_stack = stack[::-1] + else: + layer_stack = stack + + min_space = 2 * (tech.drc["minwidth_{}".format(layer_stack[0])] + + tech.drc["minwidth_{}".format(layer_stack[2])]) - - min_space = 2 * (tech.drc["minwidth_m2"] + - tech.drc["minwidth_m1"]) - layer_stack = tech.m2_stack[::-1] - position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - w = design.design("wire_test4") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) - - min_space = 2 * (tech.drc["minwidth_m2"] + - tech.drc["minwidth_m3"]) - layer_stack = tech.m2_stack - position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - position_list.reverse() - w = design.design("wire_test5") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) - - min_space = 2 * (tech.drc["minwidth_m2"] + - tech.drc["minwidth_m3"]) - layer_stack = tech.m2_stack[::-1] - position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - position_list.reverse() - w = design.design("wire_test6") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) + position_list = [[0, 0], + [0, 3 * min_space], + [1 * min_space, 3 * min_space], + [4 * min_space, 3 * min_space], + [4 * min_space, 0], + [7 * min_space, 0], + [7 * min_space, 4 * min_space], + [-1 * min_space, 4 * min_space], + [-1 * min_space, 0]] + position_list = [[x - min_space, y - min_space] for x, y in position_list] + w = design.design("wire_test_{}".format("_".join(layer_stack))) + wire.wire(w, layer_stack, position_list) + self.local_drc_check(w) globals.end_openram() From fc4685c7f70214c6601ff0d44b328f47de4ced1b Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Tue, 17 Dec 2019 23:07:01 +0000 Subject: [PATCH 079/521] Cleanup. --- compiler/base/contact.py | 47 ++++++++++++++++++---------------- compiler/base/design.py | 42 +++++++++++++++++++----------- compiler/tests/03_wire_test.py | 9 ++++--- 3 files changed, 57 insertions(+), 41 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index c5b1ef9e..24b0e866 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -7,8 +7,10 @@ # import hierarchy_design import debug -from tech import * +from tech import drc +import tech from vector import vector +from sram_factory import factory class contact(hierarchy_design.hierarchy_design): @@ -65,7 +67,8 @@ class contact(hierarchy_design.hierarchy_design): if self.implant_type and self.well_type: self.create_implant_well_enclosures() elif self.implant_type or self.well_type: - debug.error(-1, "Must define both implant and well type or none at all.") + debug.error(-1, + "Must define both implant and well type or none.") def setup_layers(self): """ Locally assign the layer names. """ @@ -75,7 +78,7 @@ class contact(hierarchy_design.hierarchy_design): self.second_layer_name = second_layer # Contacts will have unique per first layer - if via_layer in layer.keys(): + if via_layer in tech.layer.keys(): self.via_layer_name = via_layer elif via_layer == "contact": if first_layer in ("active", "poly"): @@ -86,8 +89,6 @@ class contact(hierarchy_design.hierarchy_design): debug.error("Invalid via layer {}".format(via_layer), -1) else: debug.error("Invalid via layer {}".format(via_layer), -1) - - def setup_layout_constants(self): """ Determine the design rules for the enclosure layers """ @@ -127,7 +128,9 @@ class contact(hierarchy_design.hierarchy_design): else: debug.error("Invalid first layer direction.", -1) - # In some technologies, the minimum width may be larger than the overlap requirement around the via, so + # In some technologies, + # the minimum width may be larger than + # the overlap requirement around the via, so # check this for each dimension. if self.directions[1] == "V": self.second_layer_horizontal_enclosure = max(second_layer_enclosure, @@ -146,11 +149,14 @@ class contact(hierarchy_design.hierarchy_design): """ Create the contact array at the origin""" # offset for the via array self.via_layer_position = vector( - max(self.first_layer_horizontal_enclosure, self.second_layer_horizontal_enclosure), - max(self.first_layer_vertical_enclosure, self.second_layer_vertical_enclosure)) + max(self.first_layer_horizontal_enclosure, + self.second_layer_horizontal_enclosure), + max(self.first_layer_vertical_enclosure, + self.second_layer_vertical_enclosure)) for i in range(self.dimensions[1]): - offset = self.via_layer_position + vector(0, self.contact_pitch * i) + offset = self.via_layer_position + vector(0, + self.contact_pitch * i) for j in range(self.dimensions[0]): self.add_rect(layer=self.via_layer_name, offset=offset, @@ -161,7 +167,7 @@ class contact(hierarchy_design.hierarchy_design): def create_nitride_cut_enclosure(self): """ Special layer that encloses poly contacts in some processes """ # Check if there is a special poly nitride cut layer - if "npc" not in layer.keys(): + if "npc" not in tech.layer.keys(): return # Only add for poly layers @@ -175,7 +181,6 @@ class contact(hierarchy_design.hierarchy_design): offset=self.second_layer_position, width=self.second_layer_width, height=self.second_layer_height) - def create_first_layer_enclosure(self): # this is if the first and second layers are different @@ -224,35 +229,33 @@ class contact(hierarchy_design.hierarchy_design): return self.return_power() -from sram_factory import factory - # This is not instantiated and used for calculations only. # These are static 1x1 contacts to reuse in all the design modules. well = factory.create(module_type="contact", - layer_stack=active_stack, + layer_stack=tech.active_stack, directions=("H", "V")) active = factory.create(module_type="contact", - layer_stack=active_stack, + layer_stack=tech.active_stack, directions=("H", "V")) poly = factory.create(module_type="contact", - layer_stack=poly_stack, + layer_stack=tech.poly_stack, directions=("V", "H")) -if "li" in layer.keys(): +if "li" in tech.layer.keys(): lim1 = factory.create(module_type="contact", - layer_stack=li_stack, + layer_stack=tech.li_stack, directions=("V", "H")) else: lim1 = None m1m2 = factory.create(module_type="contact", - layer_stack=m1_stack, + layer_stack=tech.m1_stack, directions=("H", "V")) m2m3 = factory.create(module_type="contact", - layer_stack=m2_stack, + layer_stack=tech.m2_stack, directions=("V", "H")) -if "m4" in layer.keys(): +if "m4" in tech.layer.keys(): m3m4 = factory.create(module_type="contact", - layer_stack=m3_stack, + layer_stack=tech.m3_stack, directions=("H", "V")) else: m3m4 = None diff --git a/compiler/base/design.py b/compiler/base/design.py index 2b11111d..1066cbc0 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -10,6 +10,7 @@ import contact from globals import OPTS import re + class design(hierarchy_design): """ This is the same as the hierarchy_design class except it contains @@ -24,16 +25,23 @@ class design(hierarchy_design): self.setup_layer_constants() self.setup_multiport_constants() - def setup_layer_constants(self): - """ These are some layer constants used in many places in the compiler.""" + """ + These are some layer constants used + in many places in the compiler. + """ import tech - - self.m1_pitch = max(contact.m1m2.width, contact.m1m2.height) + max(self.m1_space, self.m2_space) - self.m2_pitch = max(contact.m2m3.width, contact.m2m3.height) + max(self.m2_space, self.m3_space) + + # This is contact direction independent pitch, + # i.e. we take the maximum contact dimension + max_m1m2_contact = max(contact.m1m2.width, contact.m1m2.height) + self.m1_pitch = max_m1m2_contact + max(self.m1_space, self.m2_space) + max_m2m3_contact = max(contact.m2m3.width, contact.m2m3.height) + self.m2_pitch = max_m2m3_contact + max(self.m2_space, self.m3_space) if "m4" in tech.layer: - self.m3_pitch = max(contact.m3m4.width, contact.m3m4.height) + max(self.m3_space, self.m4_space) + max_m3m4_contact = max(contact.m3m4.width, contact.m3m4.height) + self.m3_pitch = max_m3m4_contact + max(self.m3_space, self.m4_space) else: self.m3_pitch = self.m2_pitch @@ -44,15 +52,17 @@ class design(hierarchy_design): self.m3_stack = tech.m3_stack def setup_drc_constants(self): - """ These are some DRC constants used in many places in the compiler.""" - from tech import drc, layer - + """ + These are some DRC constants used in many places + in the compiler. + """ # Make some local rules for convenience + from tech import drc for rule in drc.keys(): # Single layer width rules match = re.search(r"minwidth_(.*)", rule) if match: - if match.group(1)=="active_contact": + if match.group(1) == "active_contact": setattr(self, "contact_width", drc(match.group(0))) else: setattr(self, match.group(1)+"_width", drc(match.group(0))) @@ -64,11 +74,12 @@ class design(hierarchy_design): # Single layer spacing rules match = re.search(r"(.*)_to_(.*)", rule) - if match and match.group(1)==match.group(2): + if match and match.group(1) == match.group(2): setattr(self, match.group(1)+"_space", drc(match.group(0))) - elif match and match.group(1)!=match.group(2): - if match.group(2)=="poly_active": - setattr(self, match.group(1)+"_to_contact", drc(match.group(0))) + elif match and match.group(1) != match.group(2): + if match.group(2) == "poly_active": + setattr(self, match.group(1)+"_to_contact", + drc(match.group(0))) else: setattr(self, match.group(0), drc(match.group(0))) @@ -102,7 +113,8 @@ class design(hierarchy_design): print("well_enclose_active", self.well_enclose_active) print("implant_enclose_active", self.implant_enclose_active) print("implant_space", self.implant_space) - import sys; sys.exit(1) + import sys + sys.exit(1) def setup_multiport_constants(self): """ diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index bd4b9345..61e21985 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -8,11 +8,11 @@ # import unittest from testutils import * -import sys,os +import sys +import os sys.path.append(os.getenv("OPENRAM_HOME")) import globals -from globals import OPTS -import debug + class wire_test(openram_test): @@ -31,7 +31,8 @@ class wire_test(openram_test): layer_stack = stack[::-1] else: layer_stack = stack - + + # Just make a conservative spacing. Make it wire pitch instead? min_space = 2 * (tech.drc["minwidth_{}".format(layer_stack[0])] + tech.drc["minwidth_{}".format(layer_stack[2])]) From 8e151553e43b1fd71ef20d7ff8c50eafeb0bc527 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Tue, 17 Dec 2019 23:45:07 +0000 Subject: [PATCH 080/521] Update contact types. Use preferred directions in tech files. Programmatically generate based on interconnect stacks. --- compiler/base/contact.py | 50 ++++++++++-------------------- compiler/base/design.py | 45 +++++++++++++++++---------- technology/freepdk45/tech/tech.py | 7 +++++ technology/scn4m_subm/tech/tech.py | 6 ++++ 4 files changed, 58 insertions(+), 50 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 24b0e866..0a7ace88 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -11,6 +11,7 @@ from tech import drc import tech from vector import vector from sram_factory import factory +import sys class contact(hierarchy_design.hierarchy_design): @@ -28,7 +29,7 @@ class contact(hierarchy_design.hierarchy_design): """ - def __init__(self, layer_stack, dimensions=(1, 1), directions=("V", "V"), + def __init__(self, layer_stack, dimensions=(1, 1), directions=None, implant_type=None, well_type=None, name=""): # This will ignore the name parameter since # we can guarantee a unique name here @@ -43,7 +44,11 @@ class contact(hierarchy_design.hierarchy_design): self.layer_stack = layer_stack self.dimensions = dimensions - self.directions = directions + if directions: + self.directions = directions + else: + self.directions = (tech.preferred_directions[layer_stack[0]], + tech.preferred_directions[layer_stack[2]]) self.offset = vector(0, 0) self.implant_type = implant_type self.well_type = well_type @@ -228,35 +233,14 @@ class contact(hierarchy_design.hierarchy_design): """ Get total power of a module """ return self.return_power() - -# This is not instantiated and used for calculations only. -# These are static 1x1 contacts to reuse in all the design modules. -well = factory.create(module_type="contact", - layer_stack=tech.active_stack, - directions=("H", "V")) -active = factory.create(module_type="contact", - layer_stack=tech.active_stack, - directions=("H", "V")) -poly = factory.create(module_type="contact", - layer_stack=tech.poly_stack, - directions=("V", "H")) -if "li" in tech.layer.keys(): - lim1 = factory.create(module_type="contact", - layer_stack=tech.li_stack, - directions=("V", "H")) -else: - lim1 = None - -m1m2 = factory.create(module_type="contact", - layer_stack=tech.m1_stack, - directions=("H", "V")) -m2m3 = factory.create(module_type="contact", - layer_stack=tech.m2_stack, - directions=("V", "H")) -if "m4" in tech.layer.keys(): - m3m4 = factory.create(module_type="contact", - layer_stack=tech.m3_stack, - directions=("H", "V")) -else: - m3m4 = None + +# Set up a static for each layer to be used for measurements +for layer_stack in tech.layer_stacks: + (layer1, via, layer2) = layer_stack + cont = factory.create(module_type="contact", + layer_stack=layer_stack) + module = sys.modules[__name__] + # Create the contact as just the concat of the layer names + setattr(module, layer1 + layer2, cont) + diff --git a/compiler/base/design.py b/compiler/base/design.py index 1066cbc0..2e1488f9 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -26,30 +26,41 @@ class design(hierarchy_design): self.setup_multiport_constants() def setup_layer_constants(self): - """ + """ These are some layer constants used in many places in the compiler. """ import tech + for key in dir(tech): + # Single layer width rules + match = re.match(r".*_stack$", key) + if match: + layer_stack = getattr(tech, key) - # This is contact direction independent pitch, - # i.e. we take the maximum contact dimension - max_m1m2_contact = max(contact.m1m2.width, contact.m1m2.height) - self.m1_pitch = max_m1m2_contact + max(self.m1_space, self.m2_space) - max_m2m3_contact = max(contact.m2m3.width, contact.m2m3.height) - self.m2_pitch = max_m2m3_contact + max(self.m2_space, self.m3_space) - if "m4" in tech.layer: - max_m3m4_contact = max(contact.m3m4.width, contact.m3m4.height) - self.m3_pitch = max_m3m4_contact + max(self.m3_space, self.m4_space) - else: - self.m3_pitch = self.m2_pitch + # Set the stack as a local helper + setattr(self, key, layer_stack) - self.poly_stack = tech.poly_stack - self.active_stack = tech.active_stack - self.m1_stack = tech.m1_stack - self.m2_stack = tech.m2_stack - self.m3_stack = tech.m3_stack + # Add the pitch + setattr(self, + "{}_pitch".format(layer_stack[0]), + self.compute_pitch(layer_stack)) + + def compute_pitch(self, layer_stack): + + """ + This is contact direction independent pitch, + i.e. we take the maximum contact dimension + """ + (layer1, via, layer2) = layer_stack + + contact1 = getattr(contact, layer1 + layer2) + max_contact = max(contact1.width, contact1.height) + layer1_space = getattr(self, layer1+"_space") + layer2_space = getattr(self, layer2+"_space") + pitch = max_contact + max(layer1_space, layer2_space) + + return pitch def setup_drc_constants(self): """ diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index d87e98f1..3eba1a58 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -56,6 +56,13 @@ beol_stacks = [m1_stack, layer_stacks = feol_stacks + beol_stacks +preferred_directions = {"poly": "V", + "active": "H", + "m1": "H", + "m2": "V", + "m3": "H", + "m4": "V"} + ################################################### # GDS Layer Map ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 349310f6..44ffe9be 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -56,6 +56,12 @@ beol_stacks = [m1_stack, layer_stacks = feol_stacks + beol_stacks +preferred_directions = {"poly": "V", + "active": "H", + "m1": "H", + "m2": "V", + "m3": "H", + "m4": "V"} ################################################### ##GDS Layer Map From aceaa9fb2178cd9b076926a22f752e583ecfca6b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 17 Dec 2019 15:55:20 -0800 Subject: [PATCH 081/521] Standardize contact names. --- compiler/bitcells/pbitcell.py | 24 ++++++++++++------------ compiler/pgates/pgate.py | 16 ++++++++-------- compiler/pgates/pinv.py | 4 ++-- compiler/pgates/pnand2.py | 4 ++-- compiler/pgates/pnand3.py | 4 ++-- compiler/pgates/pnor2.py | 2 +- compiler/pgates/precharge.py | 6 +++--- compiler/pgates/ptristate_inv.py | 6 +++--- 8 files changed, 33 insertions(+), 33 deletions(-) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index bdb9161b..6df230e9 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -213,7 +213,7 @@ class pbitcell(bitcell_base.bitcell_base): # y-offset for the access transistor's gate contact self.gate_contact_yoffset = max_contact_extension + self.m2_space \ - + 0.5 * max(contact.poly.height, contact.m1m2.height) + + 0.5 * max(contact.polym1.height, contact.m1m2.height) # y-position of access transistors self.port_ypos = self.m1_space + 0.5 * contact.m1m2.height + self.gate_contact_yoffset @@ -234,7 +234,7 @@ class pbitcell(bitcell_base.bitcell_base): self.read_port_spacing = self.bitline_offset + self.m2_space # spacing between cross coupled inverters - self.inverter_to_inverter_spacing = contact.poly.width + self.m1_space + self.inverter_to_inverter_spacing = contact.polym1.width + self.m1_space # calculations related to inverter connections inverter_pmos_contact_extension = 0.5 * \ @@ -243,19 +243,19 @@ class pbitcell(bitcell_base.bitcell_base): (self.inverter_nmos.active_contact.height - self.inverter_nmos.active_height) self.inverter_gap = max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + self.poly_to_contact + 2 * contact.poly.width \ + + self.poly_to_contact + 2 * contact.polym1.width \ + self.m1_space + inverter_pmos_contact_extension self.cross_couple_lower_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + 0.5 * contact.poly.width + + 0.5 * contact.polym1.width self.cross_couple_upper_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ + self.poly_to_contact \ - + 1.5 * contact.poly.width + + 1.5 * contact.polym1.width # spacing between wordlines (and gnd) self.m1_offset = -0.5 * self.m1_width @@ -263,7 +263,7 @@ class pbitcell(bitcell_base.bitcell_base): # spacing for vdd implant_constraint = max(inverter_pmos_contact_extension, 0) \ + 2 * self.implant_enclose_active \ - + 0.5 * (contact.well.width - self.m1_width) + + 0.5 * (contact.activem1.width - self.m1_width) metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space self.vdd_offset = max(implant_constraint, metal1_constraint) + 0.5*self.m1_width @@ -367,16 +367,16 @@ class pbitcell(bitcell_base.bitcell_base): self.add_path("m1", [self.inverter_nmos_left.get_pin("D").uc(), self.inverter_pmos_left.get_pin("D").bc()], - width=contact.active.second_layer_width) + width=contact.activem1.second_layer_width) self.add_path("m1", [self.inverter_nmos_right.get_pin("S").uc(), self.inverter_pmos_right.get_pin("S").bc()], - width=contact.active.second_layer_width) + width=contact.activem1.second_layer_width) # add contacts to connect gate poly to drain/source # metal1 (to connect Q to Q_bar) contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x \ - + 0.5 * contact.poly.height, + + 0.5 * contact.polym1.height, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=contact_offset_left, @@ -384,7 +384,7 @@ class pbitcell(bitcell_base.bitcell_base): contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x \ - - 0.5*contact.poly.height, + - 0.5*contact.polym1.height, self.cross_couple_lower_ypos) self.add_via_center(layers=self.poly_stack, offset=contact_offset_right, @@ -926,14 +926,14 @@ class pbitcell(bitcell_base.bitcell_base): """ # add poly to metal1 contacts for gates of the inverters left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x \ - - self.poly_to_contact - 0.5*contact.poly.width, + - self.poly_to_contact - 0.5*contact.polym1.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=left_storage_contact, directions=("H", "H")) right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \ - + self.poly_to_contact + 0.5*contact.poly.width, + + self.poly_to_contact + 0.5*contact.polym1.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=right_storage_contact, diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index d5f2395b..8f94ed07 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -88,14 +88,14 @@ class pgate(design.design): # Center is completely symmetric. if rotate: - contact_width = contact.poly.height - contact_m1_width = contact.poly.second_layer_height - contact_m1_height = contact.poly.second_layer_width + contact_width = contact.polym1.height + contact_m1_width = contact.polym1.second_layer_height + contact_m1_height = contact.polym1.second_layer_width directions = ("H", "V") else: - contact_width = contact.poly.width - contact_m1_width = contact.poly.second_layer_width - contact_m1_height = contact.poly.second_layer_height + contact_width = contact.polym1.width + contact_m1_width = contact.polym1.second_layer_width + contact_m1_height = contact.polym1.second_layer_height directions = ("V", "H") if position == "center": @@ -103,7 +103,7 @@ class pgate(design.design): + vector(0.5 * self.poly_width, 0) elif position == "farleft": contact_offset = left_gate_offset \ - - vector(0.5 * contact.poly.width, 0) + - vector(0.5 * contact.polym1.width, 0) elif position == "left": contact_offset = left_gate_offset \ - vector(0.5 * contact_width - 0.5 * self.poly_width, 0) @@ -131,7 +131,7 @@ class pgate(design.design): + left_gate_offset.scale(0.5, 0) self.add_rect_center(layer="poly", offset=mid_point, - height=contact.poly.first_layer_width, + height=contact.polym1.first_layer_width, width=left_gate_offset.x - contact_offset.x) def extend_wells(self, middle_position): diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 1ff5b67b..ce477a83 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -95,8 +95,8 @@ class pinv(pgate.pgate): tx_type="pmos") tx_height = nmos.poly_height + pmos.poly_height # rotated m1 pitch or poly to active spacing - min_channel = max(contact.poly.width + self.m1_space, - contact.poly.width + 2 * self.poly_to_active) + min_channel = max(contact.polym1.width + self.m1_space, + contact.polym1.width + 2 * self.poly_to_active) # This is the extra space needed to ensure DRC rules # to the active contacts diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 8acde2ce..c7f184b2 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -85,7 +85,7 @@ class pnand2(pgate.pgate): """ Pre-compute some handy layout parameters. """ # metal spacing to allow contacts on any layer - self.input_spacing = max(self.poly_space + contact.poly.first_layer_width, + self.input_spacing = max(self.poly_space + contact.polym1.first_layer_width, self.m1_space + contact.m1m2.first_layer_width, self.m2_space + contact.m2m3.first_layer_width, self.m3_space + contact.m2m3.second_layer_width) @@ -98,7 +98,7 @@ class pnand2(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.well_width = 2 * self.pmos.active_width + contact.active.width \ + self.well_width = 2 * self.pmos.active_width + contact.activem1.width \ + 2 * self.active_space \ + 2 * self.well_enclose_active diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 7a773497..8ccbff2c 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -202,10 +202,10 @@ class pnand3(pgate.pgate): # wire space or wire and one contact space metal_spacing = max(self.m1_space + self.m1_width, self.m2_space + self.m2_width, - self.m1_space + 0.5 *contact.poly.width + 0.5 * self.m1_width) + self.m1_space + 0.5 *contact.polym1.width + 0.5 * self.m1_width) active_spacing = max(self.m1_space, - 0.5 * contact.poly.first_layer_width + self.poly_to_active) + 0.5 * contact.polym1.first_layer_width + self.poly_to_active) inputC_yoffset = self.nmos3_pos.y + self.nmos.active_height + active_spacing self.route_input_gate(self.pmos3_inst, self.nmos3_inst, diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index d75df0a9..d24189ac 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -84,7 +84,7 @@ class pnor2(pgate.pgate): """ Pre-compute some handy layout parameters. """ # metal spacing to allow contacts on any layer - self.input_spacing = max(self.poly_space + contact.poly.first_layer_width, + self.input_spacing = max(self.poly_space + contact.polym1.first_layer_width, self.m1_space + contact.m1m2.first_layer_width, self.m2_space + contact.m2m3.first_layer_width, self.m3_space + contact.m2m3.second_layer_width) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 784bb418..f9e8ce87 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -121,7 +121,7 @@ class precharge(design.design): self.lower_pmos_inst.place(self.lower_pmos_position) # adds the upper pmos(s) to layout - ydiff = self.pmos.height + 2 * self.m1_space + contact.poly.width + ydiff = self.pmos.height + 2 * self.m1_space + contact.polym1.width self.upper_pmos1_pos = self.lower_pmos_position + vector(0, ydiff) self.upper_pmos1_inst.place(self.upper_pmos1_pos) @@ -175,7 +175,7 @@ class precharge(design.design): # adds the contact from active to metal1 well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \ - + vector(0, self.upper_pmos1_inst.uy() + contact.well.height / 2 \ + + vector(0, self.upper_pmos1_inst.uy() + contact.activem1.height / 2 \ + self.well_extend_active) self.add_via_center(layers=self.active_stack, offset=well_contact_pos, @@ -183,7 +183,7 @@ class precharge(design.design): well_type="n") # leave an extra pitch for the height - self.height = well_contact_pos.y + contact.well.height + self.m1_pitch + self.height = well_contact_pos.y + contact.activem1.height + self.m1_pitch # nwell should span the whole design since it is pmos only self.add_rect(layer="nwell", diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index 5c0028b2..d2965cde 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -80,7 +80,7 @@ class ptristate_inv(pgate.pgate): # Height is an input parameter, so it is not recomputed. # Make sure we can put a well above and below - self.top_bottom_space = max(contact.well.width, contact.well.height) + self.top_bottom_space = max(contact.activem1.width, contact.activem1.height) def add_ptx(self): @@ -138,8 +138,8 @@ class ptristate_inv(pgate.pgate): """ pmos_yoff = self.height - self.pmos.active_height \ - - self.top_bottom_space - 0.5 * contact.well.height - nmos_yoff = self.top_bottom_space + 0.5 * contact.well.height + - self.top_bottom_space - 0.5 * contact.activem1.height + nmos_yoff = self.top_bottom_space + 0.5 * contact.activem1.height # Tristate transistors pmos1_pos = vector(self.pmos.active_offset.x, pmos_yoff) From de6b207798cd8ac4ff0b9674999f6ae392778910 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 18 Dec 2019 11:33:21 +0100 Subject: [PATCH 082/521] hierachy_layout: Move number of via arg to add_power_pins() this allows custom modules to state how many vias they need for power rails. Signed-off-by: Bastian Koppelmann --- compiler/base/hierarchy_layout.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 7f23e942..4751000a 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1015,7 +1015,7 @@ class layout(): - def add_power_pin(self, name, loc, vertical=False, start_layer="m1"): + def add_power_pin(self, name, loc, size=[1,1], vertical=False, start_layer="m1"): """ Add a single power pin from M3 down to M1 at the given center location. The starting layer is specified to determine which vias are needed. @@ -1027,12 +1027,14 @@ class layout(): if start_layer=="m1": self.add_via_center(layers=self.m1_stack, + size=size, offset=loc, directions=direction) if start_layer=="m1" or start_layer=="m2": via=self.add_via_center(layers=self.m2_stack, + size=size, offset=loc, directions=direction) From 451ef4d8965e54131add58b62ede96a75f5061f4 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 18 Dec 2019 11:58:04 +0100 Subject: [PATCH 083/521] sram_factory: Allow a prefered module name Signed-off-by: Bastian Koppelmann --- compiler/sram_factory.py | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 6bb3578c..f323fbdc 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -31,7 +31,7 @@ class sram_factory: """ self.__init__() - def create(self, module_type, **kwargs): + def create(self, module_type, module_name=None, **kwargs): """ A generic function to create a module with a given module_type. The args are passed directly to the module constructor. @@ -72,16 +72,18 @@ class sram_factory: if obj_kwargs == kwargs: return obj_item - # Use the default name if there are default arguments - # This is especially for library cells so that the - # spice and gds files can be found. - if len(kwargs) > 0: - # Create a unique name and increment the index - module_name = "{0}_{1}".format(real_module_type, - self.module_indices[real_module_type]) - self.module_indices[real_module_type] += 1 - else: - module_name = real_module_type + # If no prefered module name is provided, we generate one. + if module_name is None: + # Use the default name if there are default arguments + # This is especially for library cells so that the + # spice and gds files can be found. + if len(kwargs) > 0: + # Create a unique name and increment the index + module_name = "{0}_{1}".format(real_module_type, + self.module_indices[real_module_type]) + self.module_indices[real_module_type] += 1 + else: + module_name = real_module_type # type_str = "type={}".format(real_module_type) # name_str = "name={}".format(module_name) From fab963701b8eb5fd1443fc8a16c18f2150314bf1 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 18 Dec 2019 12:00:02 +0100 Subject: [PATCH 084/521] sram_base: Instantiate "dff_array" and "bank" through sram_factory Signed-off-by: Bastian Koppelmann --- compiler/modules/module_type.py | 1 + compiler/sram/sram_base.py | 13 +++++-------- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/compiler/modules/module_type.py b/compiler/modules/module_type.py index 90e1fdbe..ee3e8eb2 100644 --- a/compiler/modules/module_type.py +++ b/compiler/modules/module_type.py @@ -62,6 +62,7 @@ class ModuleType(): self.names['pwrite_driver'] = 'pwrite_driver' self.names['ptristate_inv'] = 'ptristate_inv' self.names['ptristate_buf'] = 'ptristate_buf' + self.names['dff_array'] = 'dff_array' def __setitem__(self, b, c): self.names[b] = c diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index cfb5af71..65297889 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -271,28 +271,25 @@ class sram_base(design, verilog, lef): self.dff = factory.create(module_type="dff") # Create the address and control flops (but not the clk) - from dff_array import dff_array - self.row_addr_dff = dff_array(name="row_addr_dff", rows=self.row_addr_size, columns=1) + self.row_addr_dff = factory.create("dff_array", module_name="row_addr_dff", rows=self.row_addr_size, columns=1) self.add_mod(self.row_addr_dff) if self.col_addr_size > 0: - self.col_addr_dff = dff_array(name="col_addr_dff", rows=1, columns=self.col_addr_size) + self.col_addr_dff = factory.create("dff_array", module_name="col_addr_dff", rows=1, columns=self.col_addr_size) self.add_mod(self.col_addr_dff) else: self.col_addr_dff = None - self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size) + self.data_dff = factory.create("dff_array", module_name="data_dff", rows=1, columns=self.word_size) self.add_mod(self.data_dff) if self.write_size: - self.wmask_dff = dff_array(name="wmask_dff", rows=1, columns=self.num_wmasks) + self.wmask_dff = factory.create("dff_array", module_name="wmask_dff", rows=1, columns=self.num_wmasks) self.add_mod(self.wmask_dff) # Create the bank module (up to four are instantiated) - from bank import bank - self.bank = bank(self.sram_config, - name="bank") + self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") self.add_mod(self.bank) # Create bank decoder From 36cb675150f795c98ca9d42827d97891e635ff69 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 18 Dec 2019 09:30:00 -0800 Subject: [PATCH 085/521] Fix minwidth for multiple via bug. --- compiler/base/contact.py | 63 +++++++++++++++++++++------------------- compiler/base/design.py | 7 +++++ 2 files changed, 40 insertions(+), 30 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 0a7ace88..8def5bfd 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -109,44 +109,43 @@ class contact(hierarchy_design.hierarchy_design): # The extend rule applies to asymmetric enclosures in one direction. # The enclosure rule applies to symmetric enclosure component. - first_layer_minwidth = drc("minwidth_{0}".format(self.first_layer_name)) - first_layer_enclosure = drc("{0}_enclose_{1}".format(self.first_layer_name, self.via_layer_name)) - first_layer_extend = drc("{0}_extend_{1}".format(self.first_layer_name, self.via_layer_name)) + self.first_layer_minwidth = drc("minwidth_{0}".format(self.first_layer_name)) + self.first_layer_enclosure = drc("{0}_enclose_{1}".format(self.first_layer_name, self.via_layer_name)) + self.first_layer_extend = drc("{0}_extend_{1}".format(self.first_layer_name, self.via_layer_name)) - second_layer_minwidth = drc("minwidth_{0}".format(self.second_layer_name)) - second_layer_enclosure = drc("{0}_enclose_{1}".format(self.second_layer_name, self.via_layer_name)) - second_layer_extend = drc("{0}_extend_{1}".format(self.second_layer_name, self.via_layer_name)) + self.second_layer_minwidth = drc("minwidth_{0}".format(self.second_layer_name)) + self.second_layer_enclosure = drc("{0}_enclose_{1}".format(self.second_layer_name, self.via_layer_name)) + self.second_layer_extend = drc("{0}_extend_{1}".format(self.second_layer_name, self.via_layer_name)) # In some technologies, the minimum width may be larger # than the overlap requirement around the via, so # check this for each dimension. if self.directions[0] == "V": - self.first_layer_horizontal_enclosure = max(first_layer_enclosure, - (first_layer_minwidth - self.contact_array_width) / 2) - self.first_layer_vertical_enclosure = max(first_layer_extend, - (first_layer_minwidth - self.contact_array_height) / 2) + self.first_layer_horizontal_enclosure = max(self.first_layer_enclosure, + (self.first_layer_minwidth - self.contact_array_width) / 2) + self.first_layer_vertical_enclosure = max(self.first_layer_extend, + (self.first_layer_minwidth - self.contact_array_height) / 2) elif self.directions[0] == "H": - self.first_layer_horizontal_enclosure = max(first_layer_extend, - (first_layer_minwidth - self.contact_array_width) / 2) - self.first_layer_vertical_enclosure = max(first_layer_enclosure, - (first_layer_minwidth - self.contact_array_height) / 2) + self.first_layer_horizontal_enclosure = max(self.first_layer_extend, + (self.first_layer_minwidth - self.contact_array_width) / 2) + self.first_layer_vertical_enclosure = max(self.first_layer_enclosure, + (self.first_layer_minwidth - self.contact_array_height) / 2) else: debug.error("Invalid first layer direction.", -1) - # In some technologies, - # the minimum width may be larger than - # the overlap requirement around the via, so + # In some technologies, the minimum width may be larger + # than the overlap requirement around the via, so # check this for each dimension. if self.directions[1] == "V": - self.second_layer_horizontal_enclosure = max(second_layer_enclosure, - (second_layer_minwidth - self.contact_array_width) / 2) - self.second_layer_vertical_enclosure = max(second_layer_extend, - (second_layer_minwidth - self.contact_array_height) / 2) + self.second_layer_horizontal_enclosure = max(self.second_layer_enclosure, + (self.second_layer_minwidth - self.contact_array_width) / 2) + self.second_layer_vertical_enclosure = max(self.second_layer_extend, + (self.second_layer_minwidth - self.contact_array_height) / 2) elif self.directions[1] == "H": - self.second_layer_horizontal_enclosure = max(second_layer_extend, - (second_layer_minwidth - self.contact_array_height) / 2) - self.second_layer_vertical_enclosure = max(second_layer_enclosure, - (second_layer_minwidth - self.contact_array_width) / 2) + self.second_layer_horizontal_enclosure = max(self.second_layer_extend, + (self.second_layer_minwidth - self.contact_array_height) / 2) + self.second_layer_vertical_enclosure = max(self.second_layer_enclosure, + (self.second_layer_minwidth - self.contact_array_width) / 2) else: debug.error("Invalid second layer direction.", -1) @@ -193,8 +192,10 @@ class contact(hierarchy_design.hierarchy_design): max(self.second_layer_horizontal_enclosure - self.first_layer_horizontal_enclosure, 0), max(self.second_layer_vertical_enclosure - self.first_layer_vertical_enclosure, 0)) - self.first_layer_width = self.contact_array_width + 2 * self.first_layer_horizontal_enclosure - self.first_layer_height = self.contact_array_height + 2 * self.first_layer_vertical_enclosure + self.first_layer_width = max(self.contact_array_width + 2 * self.first_layer_horizontal_enclosure, + self.first_layer_minwidth) + self.first_layer_height = max(self.contact_array_height + 2 * self.first_layer_vertical_enclosure, + self.first_layer_minwidth) self.add_rect(layer=self.first_layer_name, offset=self.first_layer_position, width=self.first_layer_width, @@ -206,8 +207,10 @@ class contact(hierarchy_design.hierarchy_design): max(self.first_layer_horizontal_enclosure - self.second_layer_horizontal_enclosure, 0), max(self.first_layer_vertical_enclosure - self.second_layer_vertical_enclosure, 0)) - self.second_layer_width = self.contact_array_width + 2 * self.second_layer_horizontal_enclosure - self.second_layer_height = self.contact_array_height + 2 * self.second_layer_vertical_enclosure + self.second_layer_width = max(self.contact_array_width + 2 * self.second_layer_horizontal_enclosure, + self.second_layer_minwidth) + self.second_layer_height = max(self.contact_array_height + 2 * self.second_layer_vertical_enclosure, + self.second_layer_minwidth) self.add_rect(layer=self.second_layer_name, offset=self.second_layer_position, width=self.second_layer_width, @@ -242,5 +245,5 @@ for layer_stack in tech.layer_stacks: module = sys.modules[__name__] # Create the contact as just the concat of the layer names setattr(module, layer1 + layer2, cont) - + diff --git a/compiler/base/design.py b/compiler/base/design.py index 2e1488f9..59772a02 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -46,6 +46,13 @@ class design(hierarchy_design): "{}_pitch".format(layer_stack[0]), self.compute_pitch(layer_stack)) + if False: + print("m1_pitch", self.m1_pitch) + print("m2_pitch", self.m2_pitch) + print("m3_pitch", self.m3_pitch) + import sys + sys.exit(1) + def compute_pitch(self, layer_stack): """ From 1df16eceb60f2a50f78e18b5256cc3c318c9654a Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Thu, 19 Dec 2019 15:58:00 +0100 Subject: [PATCH 086/521] sram_factory: Give proper priority to overrides modules overridden by the user are the highest priority, then modules overridden by the technology. If nothing is overriden, use the defaults from OPTS (if they exist) or use the requested module_type. This fixes that custom tech_modules could not be used, if they had a default in OPTS even if the latter was not overridden by the user. We don't need extra defaults in the tech_modules, as we now only use them, if they have been overridden by the tech_module. Signed-off-by: Bastian Koppelmann --- compiler/globals.py | 2 ++ compiler/modules/module_type.py | 57 +++------------------------------ compiler/sram_factory.py | 43 +++++++++++++++++++++---- 3 files changed, 42 insertions(+), 60 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index 8bca4b3f..70e4b54b 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -304,6 +304,7 @@ def read_config(config_file, is_unit_test=True): except: debug.error("Unable to read configuration file: {0}".format(config_file),2) + OPTS.overridden = {} for k, v in config.__dict__.items(): # The command line will over-ride the config file # except in the case of the tech name! This is because the tech name @@ -311,6 +312,7 @@ def read_config(config_file, is_unit_test=True): # Note that if we re-read a config file, nothing will get read again! if k not in OPTS.__dict__ or k == "tech_name": OPTS.__dict__[k] = v + OPTS.overridden[k] = True # Massage the output path to be an absolute one if not OPTS.output_path.endswith('/'): diff --git a/compiler/modules/module_type.py b/compiler/modules/module_type.py index ee3e8eb2..1d8d0cba 100644 --- a/compiler/modules/module_type.py +++ b/compiler/modules/module_type.py @@ -12,64 +12,15 @@ class ModuleType(): """ def __init__(self): self.names = {} - self.names['contact'] = 'contact' - self.names['precharge'] = 'precharge' - self.names['pinv'] = 'pinv' - self.names['dff_buf'] = 'dff_buf' - self.names['sense_amp'] = 'sense_amp' - self.names['bitcell'] = 'bitcell' - self.names['port_data'] = 'port_data' - self.names['port_address'] = 'port_address' - self.names['replica_bitcell_array'] = 'replica_bitcell_array' - self.names['bank_select'] = 'bank_select' - self.names['dff'] = 'dff' - self.names['pinvbuf'] = 'pinvbuf' - self.names['hierarchical_predecode2x4'] = 'hierarchical_predecode2x4' - self.names['hierarchical_predecode3x8'] = 'hierarchical_predecode3x8' - self.names['replica_bitcell'] = 'replica_bitcell' - self.names['dummy_bitcell'] = 'dummy_bitcell' - self.names['bitcell'] = 'bitcell' - self.names['pnor2'] = 'pnor2' - self.names['pnand2'] = 'pnand2' - self.names['precharge_array'] = 'precharge_array' - self.names['sense_amp_array'] = 'sense_amp_array' - self.names['column_mux_array'] = 'column_mux_array' - self.names['write_driver_array'] = 'write_driver_array' - self.names['write_mask_and_array'] = 'write_mask_and_array' - self.names['pand2'] = 'pand2' - self.names['write_driver'] = 'write_driver' - self.names['dff_buf_array'] = 'dff_buf_array' - self.names['pdriver'] = 'pdriver' - self.names['pand3'] = 'pand3' - self.names['delay_chain'] = 'delay_chain' - self.names['decoder'] = 'decoder' - self.names['wordline_driver'] = 'wordline_driver' - self.names['tri_gate'] = 'tri_gate' - self.names['tri_gate_array'] = 'tri_gate_array' - self.names['bitcell_array'] = 'bitcell_array' - self.names['replica_column'] = 'replica_column' - self.names['dummy_array'] = 'dummy_array' - self.names['single_level_column_mux_array'] = 'single_level_column_mux_array' - self.names['single_level_column_mux'] = 'single_level_column_mux' - self.names['sram'] = 'sram' - self.names['ptx'] = 'ptx' - self.names['hierarchical_decoder'] = 'hierarchical_decoder' - self.names['pbuf'] = 'pbuf' - self.names['control_logic'] = 'control_logic' - self.names['bank'] = 'bank' - self.names['pbitcell'] = 'pbitcell' - self.names['pnand3'] = 'pnand3' - self.names['pwrite_driver'] = 'pwrite_driver' - self.names['ptristate_inv'] = 'ptristate_inv' - self.names['ptristate_buf'] = 'ptristate_buf' - self.names['dff_array'] = 'dff_array' def __setitem__(self, b, c): self.names[b] = c + def is_overridden(self, b): + return (b in self.names.keys()) + def __getitem__(self, b): if b not in self.names.keys(): raise KeyError - + return self.names[b] - diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index f323fbdc..2ba34b40 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -30,15 +30,16 @@ class sram_factory: Clear the factory instances for testing. """ self.__init__() - - def create(self, module_type, module_name=None, **kwargs): + + def get_techmodule_type(self, module_type): """ - A generic function to create a module with a given module_type. - The args are passed directly to the module constructor. + Try to load the custom tech module type. """ + overridden = False try: from tech import tech_modules real_module_type = tech_modules[module_type] + overridden = tech_modules.is_overridden(module_type) except ImportError: # If they didn't define these, then don't use the option types. # Primarily for backward compatibility and simplicity of tech files. @@ -46,12 +47,40 @@ class sram_factory: except KeyError: # If it wasn't a tech module type, we can ignore that too. real_module_type = module_type - + return (real_module_type, overridden) + + def get_usermodule_type(self, module_type): + """ + Try to load the custom user module type. If the user hasn't specified + anything, we use the default from 'options.py'. If we cannot find anything, we + fall back to the original 'module_type'. + """ + overridden = False if hasattr(OPTS, module_type): # Retrieve the name from OPTS if it exists, # otherwise just use the name - real_module_type = getattr(OPTS, module_type) - + module_type = getattr(OPTS, module_type) + overridden = module_type in OPTS.overridden.keys() + return (module_type, overridden) + + def create(self, module_type, module_name=None, **kwargs): + """ + A generic function to create a module with a given module_type. + The args are passed directly to the module constructor. + """ + tech_module_type, tm_overridden = self.get_techmodule_type(module_type) + user_module_type, um_overridden = self.get_usermodule_type(module_type) + + # overridden user modules have priority + if um_overridden: + real_module_type = user_module_type + # then overridden tech modules + elif tm_overridden: + real_module_type = tech_module_type + # if nothing else works use the name generated by get_usermodule_type() + else: + real_module_type = user_module_type + # Either retrieve the already loaded module or load it try: # Load a cached version from previous usage From 11760a999317fb7a56ab3b826424890a71a64463 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Thu, 19 Dec 2019 16:31:52 +0100 Subject: [PATCH 087/521] sram_factory: Add check for duplicate module name sram_factory cannot handle duplicate module name, thus we bail out and raise an error if a user attempts that. Signed-off-by: Bastian Koppelmann --- compiler/sram_factory.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 2ba34b40..110dbe15 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -63,6 +63,13 @@ class sram_factory: overridden = module_type in OPTS.overridden.keys() return (module_type, overridden) + def is_duplicate_name(self, name): + for mods in self.objects.values(): + for insts in mods: + if insts[1].name == name: + return True + return False + def create(self, module_type, module_name=None, **kwargs): """ A generic function to create a module with a given module_type. @@ -113,6 +120,10 @@ class sram_factory: self.module_indices[real_module_type] += 1 else: module_name = real_module_type + else: + if self.is_duplicate_name(module_name): + raise ValueError("Modules with duplicate name are not allowed." \ + " '{}'".format(module_name)) # type_str = "type={}".format(real_module_type) # name_str = "name={}".format(module_name) From b7d78ec2ec5193284765b67e69acb3d39863370d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 19 Dec 2019 12:54:10 -0800 Subject: [PATCH 088/521] Fix ptx active contact orientation to non-default M1 direction. --- compiler/base/hierarchy_layout.py | 15 ++++++--------- compiler/bitcells/pbitcell.py | 7 +++---- compiler/pgates/pgate.py | 22 +++++++--------------- compiler/pgates/ptx.py | 1 + compiler/tests/03_contact_test.py | 2 +- technology/freepdk45/tech/tech.py | 2 +- technology/scn4m_subm/tech/tech.py | 2 +- 7 files changed, 20 insertions(+), 31 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 95b27618..4baa8fc4 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -388,19 +388,15 @@ class layout(): def get_preferred_direction(self, layer): """ Return the preferred routing directions """ - if layer in ["m1", "m3", "m5"]: - return "H" - elif layer in ["active", "poly", "li", "m2", "m4"]: - return "V" - else: - debug.error("Unable to find preferred direction for {}".format(layer)) - + from tech import preferred_directions + return preferred_directions[layer] def add_via(self, layers, offset, size=[1,1], directions=None, implant_type=None, well_type=None): """ Add a three layer via structure. """ if directions==None: - directions = (self.get_preferred_direction(layers[0]), self.get_preferred_direction(layers[2])) + directions = (self.get_preferred_direction(layers[0]), + self.get_preferred_direction(layers[2])) from sram_factory import factory via = factory.create(module_type="contact", @@ -421,7 +417,8 @@ class layout(): """ Add a three layer via structure by the center coordinate accounting for mirroring and rotation. """ if directions==None: - directions = (self.get_preferred_direction(layers[0]), self.get_preferred_direction(layers[2])) + directions = (self.get_preferred_direction(layers[0]), + self.get_preferred_direction(layers[2])) from sram_factory import factory via = factory.create(module_type="contact", diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 6df230e9..2d9b4384 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -199,7 +199,6 @@ class pbitcell(bitcell_base.bitcell_base): def calculate_spacing(self): """ Calculate transistor spacings """ - # calculate metal contact extensions over transistor active readwrite_nmos_contact_extension = 0.5 * \ (self.readwrite_nmos.active_contact.height - self.readwrite_nmos.active_height) @@ -263,7 +262,7 @@ class pbitcell(bitcell_base.bitcell_base): # spacing for vdd implant_constraint = max(inverter_pmos_contact_extension, 0) \ + 2 * self.implant_enclose_active \ - + 0.5 * (contact.activem1.width - self.m1_width) + + 0.5*(self.inverter_pmos.active_contact.height - self.m1_width) metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space self.vdd_offset = max(implant_constraint, metal1_constraint) + 0.5*self.m1_width @@ -367,11 +366,11 @@ class pbitcell(bitcell_base.bitcell_base): self.add_path("m1", [self.inverter_nmos_left.get_pin("D").uc(), self.inverter_pmos_left.get_pin("D").bc()], - width=contact.activem1.second_layer_width) + width=self.inverter_nmos_left.get_pin("D").width()) self.add_path("m1", [self.inverter_nmos_right.get_pin("S").uc(), self.inverter_pmos_right.get_pin("S").bc()], - width=contact.activem1.second_layer_width) + width=self.inverter_nmos_right.get_pin("S").width()) # add contacts to connect gate poly to drain/source # metal1 (to connect Q to Q_bar) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 8f94ed07..5bf3e5e3 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -64,7 +64,7 @@ class pgate(design.design): height=height, width=source_pin.width()) - def route_input_gate(self, pmos_inst, nmos_inst, ypos, name, position="left", rotate=False): + def route_input_gate(self, pmos_inst, nmos_inst, ypos, name, position="left"): """ Route the input gate to the left side of the cell for access. Position specifies to place the contact the left, center, or @@ -87,16 +87,9 @@ class pgate(design.design): left_gate_offset = vector(nmos_gate_pin.lx(), ypos) # Center is completely symmetric. - if rotate: - contact_width = contact.polym1.height - contact_m1_width = contact.polym1.second_layer_height - contact_m1_height = contact.polym1.second_layer_width - directions = ("H", "V") - else: - contact_width = contact.polym1.width - contact_m1_width = contact.polym1.second_layer_width - contact_m1_height = contact.polym1.second_layer_height - directions = ("V", "H") + contact_width = contact.polym1.width + contact_m1_width = contact.polym1.second_layer_width + contact_m1_height = contact.polym1.second_layer_height if position == "center": contact_offset = left_gate_offset \ @@ -115,16 +108,15 @@ class pgate(design.design): # Non-preferred direction via - self.add_via_center(layers=self.poly_stack, - offset=contact_offset, - directions=directions) + v=self.add_via_center(layers=self.poly_stack, + offset=contact_offset, + directions = ("V", "H")) self.add_layout_pin_rect_center(text=name, layer="m1", offset=contact_offset, width=contact_m1_width, height=contact_m1_height) - # This is to ensure that the contact is # connected to the gate mid_point = contact_offset.scale(0.5, 1) \ diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 9907485f..5d4c015a 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -125,6 +125,7 @@ class ptx(design.design): # This is not actually instantiated but used for calculations self.active_contact = factory.create(module_type="contact", layer_stack=self.active_stack, + directions = ("V", "V"), dimensions=(1, self.num_contacts)) diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 18604213..f7a13118 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -30,7 +30,7 @@ class contact_test(openram_test): # Check single 1 x 1 contact" debug.info(2, "1 x 1 {} test".format(stack_name)) - c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 1)) + c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 1), directions=("H", "H")) self.local_drc_check(c) # Check single 1 x 1 contact" diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 3eba1a58..a76624d4 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -57,7 +57,7 @@ beol_stacks = [m1_stack, layer_stacks = feol_stacks + beol_stacks preferred_directions = {"poly": "V", - "active": "H", + "active": "V", "m1": "H", "m2": "V", "m3": "H", diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 44ffe9be..beb604c5 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -57,7 +57,7 @@ beol_stacks = [m1_stack, layer_stacks = feol_stacks + beol_stacks preferred_directions = {"poly": "V", - "active": "H", + "active": "V", "m1": "H", "m2": "V", "m3": "H", From 0da8164ea6391693c8d40c70c9eb7aab865eb5fc Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 19 Dec 2019 13:54:50 -0800 Subject: [PATCH 089/521] Remove some unnecessary via directions. --- compiler/bitcells/pbitcell.py | 18 ++++++------------ compiler/pgates/pgate.py | 5 +---- compiler/pgates/pnand2.py | 6 ++---- 3 files changed, 9 insertions(+), 20 deletions(-) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 2d9b4384..d809c6f1 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -378,16 +378,14 @@ class pbitcell(bitcell_base.bitcell_base): + 0.5 * contact.polym1.height, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, - offset=contact_offset_left, - directions=("H", "H")) + offset=contact_offset_left) contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x \ - 0.5*contact.polym1.height, self.cross_couple_lower_ypos) self.add_via_center(layers=self.poly_stack, - offset=contact_offset_right, - directions=("H", "H")) + offset=contact_offset_right) # connect contacts to gate poly (cross couple connections) gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").lc().x, @@ -784,8 +782,7 @@ class pbitcell(bitcell_base.bitcell_base): offset=port_contact_offset) self.add_via_center(layers=self.m1_stack, - offset=wl_contact_offset, - directions=("H", "H")) + offset=wl_contact_offset) self.add_path("poly", [gate_offset, port_contact_offset]) self.add_path("m2", @@ -862,8 +859,7 @@ class pbitcell(bitcell_base.bitcell_base): supply_offset = vector(position.x + contact_correct, self.gnd_position.y) self.add_via_center(layers=self.m1_stack, - offset=supply_offset, - directions=("H", "H")) + offset=supply_offset) self.add_path("m2", [position, supply_offset]) @@ -928,15 +924,13 @@ class pbitcell(bitcell_base.bitcell_base): - self.poly_to_contact - 0.5*contact.polym1.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, - offset=left_storage_contact, - directions=("H", "H")) + offset=left_storage_contact) right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \ + self.poly_to_contact + 0.5*contact.polym1.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, - offset=right_storage_contact, - directions=("H", "H")) + offset=right_storage_contact) inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_upper_ypos) self.add_path("poly", [left_storage_contact, inverter_gate_offset_left]) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 5bf3e5e3..9cb73542 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -106,11 +106,8 @@ class pgate(design.design): else: debug.error("Invalid contact placement option.", -1) - # Non-preferred direction via - v=self.add_via_center(layers=self.poly_stack, - offset=contact_offset, - directions = ("V", "H")) + offset=contact_offset) self.add_layout_pin_rect_center(text=name, layer="m1", diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index c7f184b2..bc520c7b 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -226,11 +226,9 @@ class pnand2(pgate.pgate): mid2_offset = vector(out_offset.x, bottom_pin_offset.y) self.add_via_center(layers=self.m1_stack, - offset=pmos_pin.center(), - directions=("V", "H")) + offset=pmos_pin.center()) self.add_via_center(layers=self.m1_stack, - offset=nmos_pin.center(), - directions=("V", "H")) + offset=nmos_pin.center()) self.add_via_center(layers=self.m1_stack, offset=out_offset) From d2461e5011a3dce9ce376746dc03f3125dabe10b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 19 Dec 2019 16:19:21 -0800 Subject: [PATCH 090/521] Supply indexing bug resolved. Recompute width/height basted on insts. --- compiler/modules/bank_select.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index 4b49750d..0c15401e 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -42,6 +42,10 @@ class bank_select(design.design): self.place_instances() self.route_instances() + self.height = max([x.uy() for x in self.inv_inst]) + self.m1_width + self.width = max([x.rx() for x in self.inv_inst]) + + self.add_boundary() self.DRC_LVS() @@ -96,14 +100,11 @@ class bank_select(design.design): self.xoffset_nand = self.inv4x.width + 2*self.m2_pitch + drc("pwell_to_nwell") self.xoffset_nor = self.inv4x.width + 2*self.m2_pitch + drc("pwell_to_nwell") - self.xoffset_inv = max(self.xoffset_nand + self.nand2.width, self.xoffset_nor + self.nor2.width) self.xoffset_bank_sel_inv = 0 self.xoffset_inputs = 0 self.yoffset_maxpoint = self.num_control_lines * self.inv4x.height - # Include the M1 pitches for the supply rails and spacing - self.height = self.yoffset_maxpoint + 2*self.m1_pitch - self.width = self.xoffset_inv + self.inv4x.width + def create_instances(self): @@ -197,7 +198,7 @@ class bank_select(design.design): mirror=mirror) # They all get inverters on the output - inv_inst.place(offset=[self.xoffset_inv, y_offset], + inv_inst.place(offset=[logic_inst.rx(), y_offset], mirror=mirror) @@ -312,14 +313,14 @@ class bank_select(design.design): offset=pin_pos) # Add vdd/gnd supply rails - gnd_pin = inv_inst.get_pin("gnd") + gnd_pin = self.inv_inst[num].get_pin("gnd") left_gnd_pos = vector(0, gnd_pin.cy()) self.add_layout_pin_segment_center(text="gnd", layer="m1", start=left_gnd_pos, end=gnd_pin.rc()) - vdd_pin = inv_inst.get_pin("vdd") + vdd_pin = self.inv_inst[num].get_pin("vdd") left_vdd_pos = vector(0, vdd_pin.cy()) self.add_layout_pin_segment_center(text="vdd", layer="m1", From 82496a66fe77b4ca3e1d9fd87cada9e6ee4866b9 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 20 Dec 2019 10:35:57 -0800 Subject: [PATCH 091/521] Simplify supply code. --- compiler/modules/write_mask_and_array.py | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 40f386d2..e6dcfff9 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -104,8 +104,6 @@ class write_mask_and_array(design.design): def add_layout_pins(self): - self.nand2 = factory.create(module_type="pnand2") - supply_pin=self.nand2.get_pin("vdd") # Create the enable pin that connects all write mask AND array's B pins beg_en_pin = self.and2_insts[0].get_pin("B") @@ -139,15 +137,16 @@ class write_mask_and_array(design.design): self.add_via_center(layers=self.m2_stack, offset=en_pin.center()) - self.add_power_pin("gnd", vector(supply_pin.width() + i * self.wmask_en_len, 0)) - self.add_power_pin("vdd", vector(supply_pin.width() + i * self.wmask_en_len, self.height)) - # Route power and ground rails together - if i < self.num_wmasks-1: - for n in ["gnd","vdd"]: - pin = self.and2_insts[i].get_pin(n) - next_pin = self.and2_insts[i+1].get_pin(n) - self.add_path("m1",[pin.center(),next_pin.center()]) + for supply in ["gnd", "vdd"]: + supply_pin=self.and2_insts[i].get_pin(supply) + self.add_power_pin(supply, supply_pin.rc()) + + for supply in ["gnd", "vdd"]: + supply_pin_left = self.and2_insts[0].get_pin(supply) + supply_pin_right = self.and2_insts[self.num_wmasks-1].get_pin(supply) + self.add_path("m1",[supply_pin_left.lc(), supply_pin_right.rc()]) + def get_cin(self): """Get the relative capacitance of all the input connections in the bank""" # The enable is connected to an and2 for every row. From 89396698ef69f8e8adcd33689ca38735812b24e6 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 20 Dec 2019 10:36:14 -0800 Subject: [PATCH 092/521] Non-preferred via in pnand active --- compiler/pgates/pnand2.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index bc520c7b..dda736d2 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -224,10 +224,14 @@ class pnand2(pgate.pgate): # Midpoints of the L routes go horizontal first then vertical mid1_offset = vector(out_offset.x, top_pin_offset.y) mid2_offset = vector(out_offset.x, bottom_pin_offset.y) - + + # Non-preferred active contacts self.add_via_center(layers=self.m1_stack, + directions=("V","H"), offset=pmos_pin.center()) + # Non-preferred active contacts self.add_via_center(layers=self.m1_stack, + directions=("V","H"), offset=nmos_pin.center()) self.add_via_center(layers=self.m1_stack, offset=out_offset) From 9ad06a77707ebf8108ac1d767d8a21a974faaf30 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 20 Dec 2019 11:48:27 -0800 Subject: [PATCH 093/521] Move write mask vias to center to avoid data pins. --- compiler/modules/write_mask_and_array.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index e6dcfff9..25acb324 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -139,7 +139,7 @@ class write_mask_and_array(design.design): for supply in ["gnd", "vdd"]: supply_pin=self.and2_insts[i].get_pin(supply) - self.add_power_pin(supply, supply_pin.rc()) + self.add_power_pin(supply, supply_pin.center()) for supply in ["gnd", "vdd"]: From a8d370ee8c733d29c2ce3eeee9c7012a1a888880 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 20 Dec 2019 16:35:31 -0800 Subject: [PATCH 094/521] Improved comments in tech files --- technology/freepdk45/tech/tech.py | 11 ++++++++++- technology/scn4m_subm/tech/tech.py | 12 +++++++++--- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index a76624d4..79773878 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -12,6 +12,11 @@ from module_type import * """ File containing the process technology parameters for FreePDK 45nm. """ + +################################################### +# Custom modules +################################################### + # This uses the default classes to instantiate module from # '$OPENRAM_HOME/compiler/modules'. # Using tech_modules['cellname'] you can override each class by providing a custom @@ -19,7 +24,11 @@ File containing the process technology parameters for FreePDK 45nm. # For example: tech_modules['contact'] = 'contact_freepdk45' tech_modules = ModuleType() -#GDS file info + +################################################### +# GDS file info +################################################### + GDS = {} # gds units # From http://www.cnf.cornell.edu/cnf_spie9.html: "The first diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index beb604c5..3fb7acc0 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -12,6 +12,11 @@ from module_type import * """ File containing the process technology parameters for SCMOS 4m, 0.35um """ + +################################################### +# Custom modules +################################################### + # This uses the default classes to instantiate module from # '$OPENRAM_HOME/compiler/modules'. # Using tech_modules['cellname'] you can override each class by providing a custom @@ -19,7 +24,10 @@ File containing the process technology parameters for SCMOS 4m, 0.35um # For example: tech_modules['contact'] = 'contact_scn4m' tech_modules = ModuleType() -#GDS file info + +################################################### +# GDS file info +################################################### GDS={} # gds units # From http://www.cnf.cornell.edu/cnf_spie9.html: "The first @@ -69,8 +77,6 @@ preferred_directions = {"poly": "V", # create the GDS layer map layer={} -layer["vtg"] = None -layer["vth"] = None layer["pwell"] = (41, 0) layer["nwell"] = (42, 0) layer["active"] = (43, 0) From 4ad920eaf7b098a9f21649ef7be41187a6407afa Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 23 Dec 2019 08:42:52 -0800 Subject: [PATCH 095/521] Small fixes to tech usage. --- compiler/base/contact.py | 22 +++++++++++++--------- compiler/pgates/ptx.py | 6 +++--- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 8def5bfd..64433633 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -83,7 +83,7 @@ class contact(hierarchy_design.hierarchy_design): self.second_layer_name = second_layer # Contacts will have unique per first layer - if via_layer in tech.layer.keys(): + if via_layer in tech.layer: self.via_layer_name = via_layer elif via_layer == "contact": if first_layer in ("active", "poly"): @@ -171,7 +171,7 @@ class contact(hierarchy_design.hierarchy_design): def create_nitride_cut_enclosure(self): """ Special layer that encloses poly contacts in some processes """ # Check if there is a special poly nitride cut layer - if "npc" not in tech.layer.keys(): + if "npc" not in tech.layer: return # Only add for poly layers @@ -224,13 +224,17 @@ class contact(hierarchy_design.hierarchy_design): offset=implant_position, width=implant_width, height=implant_height) - well_position = self.first_layer_position - [drc("well_enclose_active")] * 2 - well_width = self.first_layer_width + 2 * drc("well_enclose_active") - well_height = self.first_layer_height + 2 * drc("well_enclose_active") - self.add_rect(layer="{}well".format(self.well_type), - offset=well_position, - width=well_width, - height=well_height) + + # Optionally implant well if layer exists + well_layer = "{}well".format(self.well_type) + if well_layer in tech.layer: + well_position = self.first_layer_position - [drc("well_enclose_active")] * 2 + well_width = self.first_layer_width + 2 * drc("well_enclose_active") + well_height = self.first_layer_height + 2 * drc("well_enclose_active") + self.add_rect(layer=well_layer, + offset=well_position, + width=well_width, + height=well_height) def analytical_power(self, corner, load): """ Get total power of a module """ diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 5d4c015a..20c513bb 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -159,7 +159,7 @@ class ptx(design.design): # Well enclosure of active, ensure minwidth as well well_name = "{}well".format(self.well_type) - if layer[well_name]: + if well_name in layer: self.cell_well_width = max(self.active_width + 2 * self.well_enclose_active, self.well_width) self.cell_well_height = max(self.tx_width + 2 * self.well_enclose_active, @@ -326,12 +326,12 @@ class ptx(design.design): Add an (optional) well and implant for the type of transistor. """ well_name = "{}well".format(self.well_type) - if layer[well_name]: + if well_name in layer: self.add_rect(layer=well_name, offset=(0,0), width=self.cell_well_width, height=self.cell_well_height) - if layer["vtg"]: + if "vtg" in layer: self.add_rect(layer="vtg", offset=(0,0), width=self.cell_well_width, From bec12f5b94d8dbbe4300c3994c54aa6c5436258d Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Mon, 23 Dec 2019 21:16:08 +0000 Subject: [PATCH 096/521] Cleanup. --- compiler/base/hierarchy_layout.py | 674 ++++++++++++++++-------------- compiler/pgates/ptx.py | 50 +-- 2 files changed, 395 insertions(+), 329 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 27bf60eb..7b870ae7 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -5,7 +5,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import itertools import collections import geometry import gdsMill @@ -16,7 +15,7 @@ import os from globals import OPTS from vector import vector from pin_layout import pin_layout -import lef + class layout(): """ @@ -57,63 +56,65 @@ class layout(): """ if (inv_num % 2 == 0): - base_offset=vector(x_offset, inv_num * height) + base_offset = vector(x_offset, inv_num * height) y_dir = 1 else: - # we lose a rail after every 2 gates - base_offset=vector(x_offset, (inv_num+1) * height - (inv_num%2)*drc["minwidth_m1"]) + # we lose a rail after every 2 gates + base_offset = vector(x_offset, + (inv_num + 1) * height - \ + (inv_num % 2) * drc["minwidth_m1"]) y_dir = -1 - return (base_offset,y_dir) - + return (base_offset, y_dir) def find_lowest_coords(self): """Finds the lowest set of 2d cartesian coordinates within this layout""" - if len(self.objs)>0: - lowestx1 = min(obj.lx() for obj in self.objs if obj.name!="label") - lowesty1 = min(obj.by() for obj in self.objs if obj.name!="label") + if len(self.objs) > 0: + lowestx1 = min(obj.lx() for obj in self.objs if obj.name != "label") + lowesty1 = min(obj.by() for obj in self.objs if obj.name != "label") else: - lowestx1=lowesty1=None - if len(self.insts)>0: + lowestx1 = lowesty1 = None + if len(self.insts) > 0: lowestx2 = min(inst.lx() for inst in self.insts) lowesty2 = min(inst.by() for inst in self.insts) else: - lowestx2=lowesty2=None + lowestx2 = lowesty2 = None - if lowestx1==None and lowestx2==None: + if lowestx1 == None and lowestx2 == None: return None - elif lowestx1==None: - return vector(lowestx2,lowesty2) - elif lowestx2==None: - return vector(lowestx1,lowesty1) + elif lowestx1 == None: + return vector(lowestx2, lowesty2) + elif lowestx2 == None: + return vector(lowestx1, lowesty1) else: return vector(min(lowestx1, lowestx2), min(lowesty1, lowesty2)) def find_highest_coords(self): - """Finds the highest set of 2d cartesian coordinates within - this layout""" - - if len(self.objs)>0: - highestx1 = max(obj.rx() for obj in self.objs if obj.name!="label") - highesty1 = max(obj.uy() for obj in self.objs if obj.name!="label") + """ + Finds the highest set of 2d cartesian coordinates within + this layout + """ + if len(self.objs) > 0: + highestx1 = max(obj.rx() for obj in self.objs if obj.name != "label") + highesty1 = max(obj.uy() for obj in self.objs if obj.name != "label") else: - highestx1=highesty1=None - if len(self.insts)>0: + highestx1 = highesty1 = None + if len(self.insts) > 0: highestx2 = max(inst.rx() for inst in self.insts) highesty2 = max(inst.uy() for inst in self.insts) else: - highestx2=highesty2=None - if highestx1==None and highestx2==None: + highestx2 = highesty2 = None + if highestx1 == None and highestx2 == None: return None - elif highestx1==None: - return vector(highestx2,highesty2) - elif highestx2==None: - return vector(highestx1,highesty1) + elif highestx1 == None: + return vector(highestx2, highesty2) + elif highestx2 == None: + return vector(highestx1, highesty1) else: - return vector(max(highestx1, highestx2), max(highesty1, highesty2)) - + return vector(max(highestx1, highestx2), + max(highesty1, highesty2)) def translate_all(self, offset): """ @@ -132,8 +133,8 @@ class layout(): for pin in pin_list: pin.rect = [pin.ll() - offset, pin.ur() - offset] - def add_inst(self, name, mod, offset=[0,0], mirror="R0",rotate=0): - """Adds an instance of a mod to this module""" + def add_inst(self, name, mod, offset=[0, 0], mirror="R0", rotate=0): + """ Adds an instance of a mod to this module """ self.insts.append(geometry.instance(name, mod, offset, mirror, rotate)) debug.info(3, "adding instance {}".format(self.insts[-1])) # This is commented out for runtime reasons @@ -141,7 +142,7 @@ class layout(): return self.insts[-1] def get_inst(self, name): - """Retrieve an instance by name""" + """ Retrieve an instance by name """ for inst in self.insts: if inst.name == name: return inst @@ -152,9 +153,9 @@ class layout(): Adds a rectangle on a given layer,offset with width and height """ if not width: - width=drc["minwidth_{}".format(layer)] + width = drc["minwidth_{}".format(layer)] if not height: - height=drc["minwidth_{}".format(layer)] + height = drc["minwidth_{}".format(layer)] # negative layers indicate "unused" layers in a given technology lpp = techlayer[layer] if lpp[0] >= 0: @@ -164,58 +165,63 @@ class layout(): def add_rect_center(self, layer, offset, width=None, height=None): """ - Adds a rectangle on a given layer at the center point with width and height + Adds a rectangle on a given layer at the center + point with width and height """ if not width: - width=drc["minwidth_{}".format(layer)] + width = drc["minwidth_{}".format(layer)] if not height: - height=drc["minwidth_{}".format(layer)] + height = drc["minwidth_{}".format(layer)] # negative layers indicate "unused" layers in a given technology lpp = techlayer[layer] - corrected_offset = offset - vector(0.5*width,0.5*height) + corrected_offset = offset - vector(0.5 * width, 0.5 * height) if lpp[0] >= 0: - self.objs.append(geometry.rectangle(lpp, corrected_offset, width, height)) + self.objs.append(geometry.rectangle(lpp, + corrected_offset, + width, + height)) return self.objs[-1] return None - def add_segment_center(self, layer, start, end): - """ - Add a min-width rectanglular segment using center line on the start to end point """ - minwidth_layer = drc["minwidth_{}".format(layer)] - if start.x!=end.x and start.y!=end.y: - debug.error("Nonrectilinear center rect!",-1) - elif start.x!=end.x: - offset = vector(0,0.5*minwidth_layer) - return self.add_rect(layer,start-offset,end.x-start.x,minwidth_layer) + Add a min-width rectanglular segment using center + line on the start to end point + """ + minwidth_layer = drc["minwidth_{}".format(layer)] + if start.x != end.x and start.y != end.y: + debug.error("Nonrectilinear center rect!", -1) + elif start.x != end.x: + offset = vector(0, 0.5 * minwidth_layer) + return self.add_rect(layer, + start-offset, + end.x-start.x, + minwidth_layer) else: - offset = vector(0.5*minwidth_layer,0) - return self.add_rect(layer,start-offset,minwidth_layer,end.y-start.y) - - + offset = vector(0.5 * minwidth_layer, 0) + return self.add_rect(layer, + start-offset, + minwidth_layer, + end.y-start.y) def get_pin(self, text): - """ - Return the pin or list of pins + """ + Return the pin or list of pins """ try: - if len(self.pin_map[text])>1: + if len(self.pin_map[text]) > 1: debug.error("Should use a pin iterator since more than one pin {}".format(text),-1) # If we have one pin, return it and not the list. # Otherwise, should use get_pins() any_pin = next(iter(self.pin_map[text])) return any_pin - except Exception as e: - #print e + except Exception: self.gds_write("missing_pin.gds") debug.error("No pin found with name {0} on {1}. Saved as missing_pin.gds.".format(text,self.name),-1) - - def get_pins(self, text): - """ - Return a pin list (instead of a single pin) + """ + Return a pin list (instead of a single pin) """ if text in self.pin_map.keys(): return self.pin_map[text] @@ -223,87 +229,97 @@ class layout(): return set() def get_pin_names(self): - """ + """ Return a pin list of all pins """ return self.pin_map.keys() def copy_layout_pin(self, instance, pin_name, new_name=""): - """ - Create a copied version of the layout pin at the current level. - You can optionally rename the pin to a new name. """ - pins=instance.get_pins(pin_name) + Create a copied version of the layout pin at the current level. + You can optionally rename the pin to a new name. + """ + pins = instance.get_pins(pin_name) - debug.check(len(pins)>0,"Could not find pin {}".format(pin_name)) + debug.check(len(pins) > 0, + "Could not find pin {}".format(pin_name)) for pin in pins: - if new_name=="": + if new_name == "": new_name = pin.name - self.add_layout_pin(new_name, pin.layer, pin.ll(), pin.width(), pin.height()) + self.add_layout_pin(new_name, + pin.layer, + pin.ll(), + pin.width(), + pin.height()) def copy_layout_pins(self, instance, prefix=""): - """ + """ Create a copied version of the layout pin at the current level. - You can optionally rename the pin to a new name. + You can optionally rename the pin to a new name. """ for pin_name in self.pin_map.keys(): self.copy_layout_pin(instance, pin_name, prefix+pin_name) def add_layout_pin_segment_center(self, text, layer, start, end): - """ - Creates a path like pin with center-line convention + """ + Creates a path like pin with center-line convention """ - debug.check(start.x==end.x or start.y==end.y,"Cannot have a non-manhatten layout pin.") + debug.check(start.x == end.x or start.y == end.y, + "Cannot have a non-manhatten layout pin.") minwidth_layer = drc["minwidth_{}".format(layer)] # one of these will be zero - width = max(start.x,end.x) - min(start.x,end.x) - height = max(start.y,end.y) - min(start.y,end.y) - ll_offset = vector(min(start.x,end.x),min(start.y,end.y)) + width = max(start.x, end.x) - min(start.x, end.x) + height = max(start.y, end.y) - min(start.y, end.y) + ll_offset = vector(min(start.x, end.x), min(start.y, end.y)) # Shift it down 1/2 a width in the 0 dimension - if height==0: - ll_offset -= vector(0,0.5*minwidth_layer) - if width==0: - ll_offset -= vector(0.5*minwidth_layer,0) + if height == 0: + ll_offset -= vector(0, 0.5 * minwidth_layer) + if width == 0: + ll_offset -= vector(0.5 * minwidth_layer, 0) # This makes sure it is long enough, but also it is not 0 width! - height = max(minwidth_layer,height) - width = max(minwidth_layer,width) + height = max(minwidth_layer, height) + width = max(minwidth_layer, width) - - return self.add_layout_pin(text, layer, ll_offset, width, height) + return self.add_layout_pin(text, + layer, + ll_offset, + width, + height) def add_layout_pin_rect_center(self, text, layer, offset, width=None, height=None): """ Creates a path like pin with center-line convention """ if not width: - width=drc["minwidth_{0}".format(layer)] + width = drc["minwidth_{0}".format(layer)] if not height: - height=drc["minwidth_{0}".format(layer)] + height = drc["minwidth_{0}".format(layer)] - ll_offset = offset - vector(0.5*width,0.5*height) + ll_offset = offset - vector(0.5 * width, 0.5 * height) return self.add_layout_pin(text, layer, ll_offset, width, height) - def remove_layout_pin(self, text): """ Delete a labeled pin (or all pins of the same name) """ - self.pin_map[text]=set() + self.pin_map[text] = set() def add_layout_pin(self, text, layer, offset, width=None, height=None): """ - Create a labeled pin + Create a labeled pin """ if not width: - width=drc["minwidth_{0}".format(layer)] + width = drc["minwidth_{0}".format(layer)] if not height: - height=drc["minwidth_{0}".format(layer)] + height = drc["minwidth_{0}".format(layer)] - new_pin = pin_layout(text, [offset,offset+vector(width,height)], layer) + new_pin = pin_layout(text, + [offset, offset+vector(width, height)], + layer) try: # Check if there's a duplicate! @@ -324,42 +340,41 @@ class layout(): in LVS. """ if not width: - width=drc["minwidth_{0}".format(layer)] + width = drc["minwidth_{0}".format(layer)] if not height: - height=drc["minwidth_{0}".format(layer)] + height = drc["minwidth_{0}".format(layer)] self.add_rect(layer=layer, offset=offset, width=width, height=height) self.add_label(text=text, layer=layer, - offset=offset+vector(0.5*width,0.5*height)) + offset=offset + vector(0.5 * width, + 0.5 * height)) - - def add_label(self, text, layer, offset=[0,0],zoom=-1): + def add_label(self, text, layer, offset=[0, 0], zoom=-1): """Adds a text label on the given layer,offset, and zoom level""" # negative layers indicate "unused" layers in a given technology - debug.info(5,"add label " + str(text) + " " + layer + " " + str(offset)) + debug.info(5, "add label " + str(text) + " " + layer + " " + str(offset)) lpp = techlayer[layer] if lpp[0] >= 0: self.objs.append(geometry.label(text, lpp, offset, zoom)) return self.objs[-1] return None - def add_path(self, layer, coordinates, width=None): """Connects a routing path on given layer,coordinates,width.""" - debug.info(4,"add path " + str(layer) + " " + str(coordinates)) + debug.info(4, "add path " + str(layer) + " " + str(coordinates)) import wire_path # NOTE: (UNTESTED) add_path(...) is currently not used # negative layers indicate "unused" layers in a given technology - #lpp = techlayer[layer] - #if lpp[0] >= 0: - # self.objs.append(geometry.path(lpp, coordinates, width)) + # lpp = techlayer[layer] + # if lpp[0] >= 0: + # self.objs.append(geometry.path(lpp, coordinates, width)) wire_path.wire_path(obj=self, - layer=layer, - position_list=coordinates, + layer=layer, + position_list=coordinates, width=width) def add_route(self, layers, coordinates, layer_widths): @@ -369,21 +384,21 @@ class layout(): the coordinates. """ import route - debug.info(4,"add route " + str(layers) + " " + str(coordinates)) + debug.info(4, "add route " + str(layers) + " " + str(coordinates)) # add an instance of our path that breaks down into rectangles and contacts route.route(obj=self, - layer_stack=layers, + layer_stack=layers, path=coordinates, layer_widths=layer_widths) - def add_wire(self, layers, coordinates): """Connects a routing path on given layer,coordinates,width. The layers are the (horizontal, via, vertical). """ import wire - # add an instance of our path that breaks down into rectangles and contacts + # add an instance of our path that breaks down + # into rectangles and contacts wire.wire(obj=self, - layer_stack=layers, + layer_stack=layers, position_list=coordinates) def get_preferred_direction(self, layer): @@ -394,7 +409,7 @@ class layout(): def add_via(self, layers, offset, size=[1,1], directions=None, implant_type=None, well_type=None): """ Add a three layer via structure. """ - if directions==None: + if not directions: directions = (self.get_preferred_direction(layers[0]), self.get_preferred_direction(layers[2])) @@ -406,17 +421,20 @@ class layout(): implant_type=implant_type, well_type=well_type) self.add_mod(via) - inst=self.add_inst(name=via.name, - mod=via, - offset=offset) + inst = self.add_inst(name=via.name, + mod=via, + offset=offset) # We don't model the logical connectivity of wires/paths self.connect_inst([]) return inst def add_via_center(self, layers, offset, directions=None, size=[1,1], implant_type=None, well_type=None): - """ Add a three layer via structure by the center coordinate accounting for mirroring and rotation. """ + """ + Add a three layer via structure by the center coordinate + accounting for mirroring and rotation. + """ - if directions==None: + if not directions: directions = (self.get_preferred_direction(layers[0]), self.get_preferred_direction(layers[2])) @@ -430,12 +448,13 @@ class layout(): height = via.height width = via.width - corrected_offset = offset + vector(-0.5*width,-0.5*height) + corrected_offset = offset + vector(-0.5 * width, + -0.5 * height) self.add_mod(via) - inst=self.add_inst(name=via.name, - mod=via, - offset=corrected_offset) + inst = self.add_inst(name=via.name, + mod=via, + offset=corrected_offset) # We don't model the logical connectivity of wires/paths self.connect_inst([]) return inst @@ -447,22 +466,20 @@ class layout(): mults=mults, tx_type=tx_type) self.add_mod(mos) - inst=self.add_inst(name=mos.name, - mod=mos, - offset=offset, - mirror=mirror, - rotate=rotate) + inst = self.add_inst(name=mos.name, + mod=mos, + offset=offset, + mirror=mirror, + rotate=rotate) return inst - - def gds_read(self): """Reads a GDSII file in the library and checks if it exists Otherwise, start a new layout for dynamic generation.""" # This must be done for netlist only mode too if os.path.isfile(self.gds_file): - self.is_library_cell=True + self.is_library_cell = True if OPTS.netlist_only: self.gds = None @@ -480,7 +497,7 @@ class layout(): def print_gds(self, gds_file=None): """Print the gds file (not the vlsi class) to the terminal """ - if gds_file == None: + if not gds_file: gds_file = self.gds_file debug.info(4, "Printing {}".format(gds_file)) arrayCellLayout = gdsMill.VlsiLayout(units=GDS["unit"]) @@ -511,10 +528,12 @@ class layout(): # If there is a boundary layer, and we didn't create one, add one. if "stdc" in techlayer.keys(): boundary_layer = "stdc" - boundary = [self.find_lowest_coords(), self.find_highest_coords()] + boundary = [self.find_lowest_coords(), + self.find_highest_coords()] height = boundary[1][1] - boundary[0][1] width = boundary[1][0] - boundary[0][0] (layer_number, layer_purpose) = techlayer[boundary_layer] + print(self.name, boundary, height, width) gds_layout.addBox(layerNumber=layer_number, purposeNumber=layer_purpose, offsetInMicrons=boundary[0], @@ -522,7 +541,6 @@ class layout(): height=height, center=False) debug.info(2, "Adding {0} boundary {1}".format(self.name, boundary)) - self.visited.append(self.name) @@ -549,20 +567,21 @@ class layout(): # populates the xyTree data structure for gds # self.gds.prepareForWrite() writer.writeToFile(gds_name) - debug.info(3, "Done writing to {}".format(gds_name)) + debug.info(3, "Done writing to {}".format(gds_name)) def get_boundary(self): """ Return the lower-left and upper-right coordinates of boundary """ # This assumes nothing spans outside of the width and height! - return [vector(0,0), vector(self.width, self.height)] + return [vector(0, 0), vector(self.width, self.height)] #return [self.find_lowest_coords(), self.find_highest_coords()] def get_blockages(self, layer, top_level=False): - """ - Write all of the obstacles in the current (and children) modules to the lef file + """ + Write all of the obstacles in the current (and children) + modules to the lef file. Do not write the pins since they aren't obstructions. """ - if type(layer)==str: + if type(layer) == str: lpp = techlayer[layer] else: lpp = layer @@ -659,11 +678,13 @@ class layout(): self.add_rect(layer=layer, offset=line_offset, height=length) - # Make this the center of the rail - line_positions[names[i]]=line_offset+vector(half_minwidth,0.5*length) + # Make this the center of the rail + line_positions[names[i]] = line_offset + vector(half_minwidth, + 0.5 * length) else: for i in range(len(names)): - line_offset = offset + vector(0,i*pitch + half_minwidth) + line_offset = offset + vector(0, + i * pitch + half_minwidth) if make_pins: self.add_layout_pin(text=names[i], layer=layer, @@ -674,7 +695,8 @@ class layout(): offset=line_offset, width=length) # Make this the center of the rail - line_positions[names[i]]=line_offset+vector(0.5*length,half_minwidth) + line_positions[names[i]] = line_offset + vector(0.5 * length, + half_minwidth) return line_positions @@ -684,17 +706,18 @@ class layout(): self.connect_bus(mapping, inst, bus_offsets, layer_stack, True) def connect_vertical_bus(self, mapping, inst, bus_offsets, - layer_stack=("m1", "via1", "m2")): + layer_stack=("m1", "via1", "m2")): """ Vertical version of connect_bus. """ self.connect_bus(mapping, inst, bus_offsets, layer_stack, False) def connect_bus(self, mapping, inst, bus_offsets, layer_stack, horizontal): - """ - Connect a mapping of pin -> name for a bus. This could be - replaced with a channel router in the future. - NOTE: This has only really been tested with point-to-point connections (not multiple pins on a net). """ - (horizontal_layer, via_layer, vertical_layer)=layer_stack + Connect a mapping of pin -> name for a bus. This could be + replaced with a channel router in the future. + NOTE: This has only really been tested with point-to-point + connections (not multiple pins on a net). + """ + (horizontal_layer, via_layer, vertical_layer) = layer_stack if horizontal: route_layer = vertical_layer else: @@ -712,37 +735,48 @@ class layout(): # left/right then up/down mid_pos = vector(bus_pos.x, pin_pos.y) - self.add_wire(layer_stack,[bus_pos, mid_pos, pin_pos]) + self.add_wire(layer_stack, + [bus_pos, mid_pos, pin_pos]) # Connect to the pin on the instances with a via if it is # not on the right layer if pin.layer != route_layer: self.add_via_center(layers=layer_stack, offset=pin_pos) - # FIXME: output pins tend to not be rotate, but supply pins are. Make consistent? + # FIXME: output pins tend to not be rotate, + # but supply pins are. Make consistent? - - # We only need a via if they happened to align perfectly # so the add_wire didn't add a via if (horizontal and bus_pos.y == pin_pos.y) or (not horizontal and bus_pos.x == pin_pos.x): self.add_via_center(layers=layer_stack, offset=bus_pos, rotate=90) + def get_layer_pitch(self, layer): """ Return the track pitch on a given layer """ - if layer=="m1": - return (self.m1_pitch,self.m1_pitch-self.m1_space,self.m1_space) - elif layer=="m2": - return (self.m2_pitch,self.m2_pitch-self.m2_space,self.m2_space) - elif layer=="m3": - return (self.m3_pitch,self.m3_pitch-self.m3_space,self.m3_space) - elif layer=="m4": + if layer == "m1": + return (self.m1_pitch, + self.m1_pitch - self.m1_space, + self.m1_space) + elif layer == "m2": + return (self.m2_pitch, + self.m2_pitch - self.m2_space, + self.m2_space) + elif layer == "m3": + return (self.m3_pitch, + self.m3_pitch - self.m3_space, + self.m3_space) + elif layer == "m4": from tech import layer as tech_layer if "m4" in tech_layer: - return (self.m3_pitch,self.m3_pitch-self.m4_space,self.m4_space) + return (self.m3_pitch, + self.m3_pitch - self.m4_space, + self.m4_space) else: - return (self.m3_pitch,self.m3_pitch-self.m3_space,self.m3_space) + return (self.m3_pitch, + self.m3_pitch - self.m3_space, + self.m3_space) else: debug.error("Cannot find layer pitch.") @@ -752,18 +786,20 @@ class layout(): layer_stack, pitch): """ - Create a trunk route for all pins with the trunk located at the given y offset. + Create a trunk route for all pins with + the trunk located at the given y offset. """ max_x = max([pin.center().x for pin in pins]) min_x = min([pin.center().x for pin in pins]) # if we are less than a pitch, just create a non-preferred layer jog if max_x-min_x <= pitch: - - half_layer_width = 0.5*drc["minwidth_{0}".format(self.vertical_layer)] + half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)] # Add the horizontal trunk on the vertical layer! - self.add_path(self.vertical_layer,[vector(min_x-half_layer_width,trunk_offset.y), vector(max_x+half_layer_width,trunk_offset.y)]) + self.add_path(self.vertical_layer, + [vector(min_x - half_layer_width, trunk_offset.y), + vector(max_x + half_layer_width, trunk_offset.y)]) # Route each pin to the trunk for pin in pins: @@ -772,8 +808,9 @@ class layout(): self.add_path(self.vertical_layer, [pin.center(), mid]) else: # Add the horizontal trunk - self.add_path(self.horizontal_layer,[vector(min_x,trunk_offset.y), vector(max_x,trunk_offset.y)]) - trunk_mid = vector(0.5*(max_x+min_x),trunk_offset.y) + self.add_path(self.horizontal_layer, + [vector(min_x, trunk_offset.y), + vector(max_x, trunk_offset.y)]) # Route each pin to the trunk for pin in pins: @@ -788,7 +825,8 @@ class layout(): layer_stack, pitch): """ - Create a trunk route for all pins with the trunk located at the given x offset. + Create a trunk route for all pins with the + trunk located at the given x offset. """ max_y = max([pin.center().y for pin in pins]) min_y = min([pin.center().y for pin in pins]) @@ -796,10 +834,12 @@ class layout(): # if we are less than a pitch, just create a non-preferred layer jog if max_y-min_y <= pitch: - half_layer_width = 0.5*drc["minwidth_{0}".format(self.horizontal_layer)] + half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)] # Add the vertical trunk on the horizontal layer! - self.add_path(self.horizontal_layer,[vector(trunk_offset.x,min_y-half_layer_width), vector(trunk_offset.x,max_y+half_layer_width)]) + self.add_path(self.horizontal_layer, + [vector(trunk_offset.x, min_y - half_layer_width), + vector(trunk_offset.x,max_y + half_layer_width)]) # Route each pin to the trunk for pin in pins: @@ -808,8 +848,9 @@ class layout(): self.add_path(self.horizontal_layer, [pin.center(), mid]) else: # Add the vertical trunk - self.add_path(self.vertical_layer,[vector(trunk_offset.x,min_y), vector(trunk_offset.x,max_y)]) - trunk_mid = vector(trunk_offset.x,0.5*(max_y+min_y),) + self.add_path(self.vertical_layer, + [vector(trunk_offset.x, min_y), + vector(trunk_offset.x, max_y)]) # Route each pin to the trunk for pin in pins: @@ -817,10 +858,9 @@ class layout(): self.add_path(self.horizontal_layer, [pin.center(), mid]) self.add_via_center(layers=layer_stack, offset=mid) - def create_channel_route(self, netlist, - offset, + offset, layer_stack, vertical=False): """ @@ -835,7 +875,7 @@ class layout(): """ Remove the pin from the graph and all conflicts """ - g.pop(pin,None) + g.pop(pin, None) # Remove the pin from all conflicts # FIXME: This is O(n^2), so maybe optimize it. @@ -848,7 +888,7 @@ class layout(): def vcg_nets_overlap(net1, net2, vertical, pitch): """ Check all the pin pairs on two nets and return a pin - overlap if any pin overlaps + overlap if any pin overlaps. """ for pin1 in net1: @@ -861,7 +901,8 @@ class layout(): def vcg_pin_overlap(pin1, pin2, vertical, pitch): """ Check for vertical or horizontal overlap of the two pins """ # FIXME: If the pins are not in a row, this may break. - # However, a top pin shouldn't overlap another top pin, for example, so the + # However, a top pin shouldn't overlap another top pin, + # for example, so the # extra comparison *shouldn't* matter. # Pin 1 must be in the "BOTTOM" set @@ -872,80 +913,93 @@ class layout(): overlaps = (not vertical and x_overlap) or (vertical and y_overlap) return overlaps - if self.get_preferred_direction(layer_stack[0])=="V": + if self.get_preferred_direction(layer_stack[0]) == "V": self.vertical_layer = layer_stack[0] self.horizontal_layer = layer_stack[2] else: self.vertical_layer = layer_stack[2] self.horizontal_layer = layer_stack[0] - (self.vertical_pitch,self.vertical_width,self.vertical_space) = self.get_layer_pitch(self.vertical_layer) - (self.horizontal_pitch,self.horizontal_width,self.horizontal_space) = self.get_layer_pitch(self.horizontal_layer) + layer_stuff = self.get_layer_pitch(self.vertical_layer) + (self.vertical_pitch, self.vertical_width, self.vertical_space) = layer_stuff + layer_stuff = self.get_layer_pitch(self.horizontal_layer) + (self.horizontal_pitch, self.horizontal_width, self.horizontal_space) = layer_stuff - - # FIXME: Must extend this to a horizontal conflict graph too if we want to minimize the + # FIXME: Must extend this to a horizontal conflict graph + # too if we want to minimize the # number of tracks! - #hcg = {} + # hcg = {} - # Initialize the vertical conflict graph (vcg) and make a list of all pins + # Initialize the vertical conflict graph (vcg) + # and make a list of all pins vcg = collections.OrderedDict() # Create names for the nets for the graphs nets = collections.OrderedDict() index = 0 - #print(netlist) + # print(netlist) for pin_list in netlist: - net_name = "n{}".format(index) - index += 1 - nets[net_name] = pin_list + net_name = "n{}".format(index) + index += 1 + nets[net_name] = pin_list # Find the vertical pin conflicts # FIXME: O(n^2) but who cares for now for net_name1 in nets: if net_name1 not in vcg.keys(): - vcg[net_name1]=[] + vcg[net_name1] = [] for net_name2 in nets: if net_name2 not in vcg.keys(): - vcg[net_name2]=[] + vcg[net_name2] = [] # Skip yourself if net_name1 == net_name2: continue - if vertical and vcg_nets_overlap(nets[net_name1], nets[net_name2], vertical, self.vertical_pitch): + if vertical and vcg_nets_overlap(nets[net_name1], + nets[net_name2], + vertical, + self.vertical_pitch): vcg[net_name2].append(net_name1) - elif not vertical and vcg_nets_overlap(nets[net_name1], nets[net_name2], vertical, self.horizontal_pitch): + elif not vertical and vcg_nets_overlap(nets[net_name1], + nets[net_name2], + vertical, + self.horizontal_pitch): vcg[net_name2].append(net_name1) # list of routes to do while vcg: - #from pprint import pformat - #print("VCG:\n",pformat(vcg)) + # from pprint import pformat + # print("VCG:\n",pformat(vcg)) # get a route from conflict graph with empty fanout set - net_name=None - for net_name,conflicts in vcg.items(): - if len(conflicts)==0: - vcg=remove_net_from_graph(net_name,vcg) + net_name = None + for net_name, conflicts in vcg.items(): + if len(conflicts) == 0: + vcg = remove_net_from_graph(net_name, vcg) break else: # FIXME: We don't support cyclic VCGs right now. - debug.error("Cyclic VCG in channel router.",-1) - - + debug.error("Cyclic VCG in channel router.", -1) # These are the pins we'll have to connect pin_list = nets[net_name] - #print("Routing:",net_name,[x.name for x in pin_list]) + # print("Routing:", net_name, [x.name for x in pin_list]) # Remove the net from other constriants in the VCG - vcg=remove_net_from_graph(net_name, vcg) + vcg = remove_net_from_graph(net_name, vcg) - # Add the trunk routes from the bottom up for horizontal or the left to right for vertical + # Add the trunk routes from the bottom up for + # horizontal or the left to right for vertical if vertical: - self.add_vertical_trunk_route(pin_list, offset, layer_stack, self.vertical_pitch) - offset += vector(self.vertical_pitch,0) + self.add_vertical_trunk_route(pin_list, + offset, + layer_stack, + self.vertical_pitch) + offset += vector(self.vertical_pitch, 0) else: - self.add_horizontal_trunk_route(pin_list, offset, layer_stack, self.horizontal_pitch) - offset += vector(0,self.horizontal_pitch) - + self.add_horizontal_trunk_route(pin_list, + offset, + layer_stack, + self.horizontal_pitch) + offset += vector(0, self.horizontal_pitch) def create_vertical_channel_route(self, netlist, offset, layer_stack): """ @@ -959,7 +1013,7 @@ class layout(): """ self.create_channel_route(netlist, offset, layer_stack, vertical=False) - def add_boundary(self, ll=vector(0,0), ur=None): + def add_boundary(self, ll=vector(0, 0), ur=None): """ Add boundary for debugging dimensions """ if "stdc" in techlayer.keys(): boundary_layer = "stdc" @@ -981,10 +1035,10 @@ class layout(): for creating wells, for example. Doesn't check for minimum widths or spacings.""" - xmin=insts[0].lx() - ymin=insts[0].by() - xmax=insts[0].rx() - ymax=insts[0].uy() + xmin = insts[0].lx() + ymin = insts[0].by() + xmax = insts[0].rx() + ymax = insts[0].uy() for inst in insts: xmin = min(xmin, inst.lx()) ymin = min(ymin, inst.by()) @@ -992,50 +1046,52 @@ class layout(): ymax = max(ymax, inst.uy()) self.add_rect(layer=layer, - offset=vector(xmin,ymin), + offset=vector(xmin, ymin), width=xmax-xmin, height=ymax-ymin) - def copy_power_pins(self, inst, name): """ - This will copy a power pin if it is on M3. If it is on M1, it will add a power via too. + This will copy a power pin if it is on M3. + If it is on M1, it will add a power via too. """ - pins=inst.get_pins(name) + pins = inst.get_pins(name) for pin in pins: - if pin.layer=="m3": - self.add_layout_pin(name, pin.layer, pin.ll(), pin.width(), pin.height()) - elif pin.layer=="m1": + if pin.layer == "m3": + self.add_layout_pin(name, + pin.layer, + pin.ll(), + pin.width(), + pin.height()) + elif pin.layer == "m1": self.add_power_pin(name, pin.center()) else: debug.warning("{0} pins of {1} should be on metal3 or metal1 for supply router.".format(name,inst.name)) - def add_power_pin(self, name, loc, size=[1,1], vertical=False, start_layer="m1"): - """ + def add_power_pin(self, name, loc, size=[1, 1], vertical=False, start_layer="m1"): + """ Add a single power pin from M3 down to M1 at the given center location. The starting layer is specified to determine which vias are needed. """ if vertical: - direction=("V","V") + direction = ("V", "V") else: - direction=("H","H") + direction = ("H", "H") - if start_layer=="m1": + if start_layer == "m1": self.add_via_center(layers=self.m1_stack, size=size, offset=loc, directions=direction) - - if start_layer=="m1" or start_layer=="m2": - via=self.add_via_center(layers=self.m2_stack, - size=size, - offset=loc, - directions=direction) - - if start_layer=="m3": + if start_layer == "m1" or start_layer == "m2": + via = self.add_via_center(layers=self.m2_stack, + size=size, + offset=loc, + directions=direction) + if start_layer == "m3": self.add_layout_pin_rect_center(text=name, layer="m3", offset=loc) @@ -1048,10 +1104,11 @@ class layout(): def add_power_ring(self, bbox): """ - Create vdd and gnd power rings around an area of the bounding box argument. Must - have a supply_rail_width and supply_rail_pitch defined as a member variable. - Defines local variables of the left/right/top/bottom vdd/gnd center offsets - for use in other modules.. + Create vdd and gnd power rings around an area of the bounding box + argument. Must have a supply_rail_width and supply_rail_pitch + defined as a member variable. Defines local variables of the + left/right/top/bottom vdd/gnd center offsets for use in other + modules.. """ [ll, ur] = bbox @@ -1061,65 +1118,71 @@ class layout(): width = (ur.x-ll.x) + 3 * self.supply_rail_pitch - supply_rail_spacing # LEFT vertical rails - offset = ll + vector(-2*self.supply_rail_pitch, -2*self.supply_rail_pitch) - left_gnd_pin=self.add_layout_pin(text="gnd", - layer="m2", - offset=offset, - width=self.supply_rail_width, - height=height) + offset = ll + vector(-2 * self.supply_rail_pitch, + -2 * self.supply_rail_pitch) + left_gnd_pin = self.add_layout_pin(text="gnd", + layer="m2", + offset=offset, + width=self.supply_rail_width, + height=height) + offset = ll + vector(-1 * self.supply_rail_pitch, + -1 * self.supply_rail_pitch) + left_vdd_pin = self.add_layout_pin(text="vdd", + layer="m2", + offset=offset, + width=self.supply_rail_width, + height=height) - offset = ll + vector(-1*self.supply_rail_pitch, -1*self.supply_rail_pitch) - left_vdd_pin=self.add_layout_pin(text="vdd", - layer="m2", - offset=offset, - width=self.supply_rail_width, - height=height) - - # RIGHT vertical rails - offset = vector(ur.x,ll.y) + vector(0,-2*self.supply_rail_pitch) + # RIGHT vertical rails + offset = vector(ur.x, ll.y) + vector(0, -2 * self.supply_rail_pitch) right_gnd_pin = self.add_layout_pin(text="gnd", - layer="m2", + layer="m2", offset=offset, width=self.supply_rail_width, height=height) - offset = vector(ur.x,ll.y) + vector(self.supply_rail_pitch,-1*self.supply_rail_pitch) - right_vdd_pin=self.add_layout_pin(text="vdd", - layer="m2", - offset=offset, - width=self.supply_rail_width, - height=height) + offset = vector(ur.x, ll.y) + vector(self.supply_rail_pitch, + -1 * self.supply_rail_pitch) + right_vdd_pin = self.add_layout_pin(text="vdd", + layer="m2", + offset=offset, + width=self.supply_rail_width, + height=height) # BOTTOM horizontal rails - offset = ll + vector(-2*self.supply_rail_pitch, -2*self.supply_rail_pitch) - bottom_gnd_pin=self.add_layout_pin(text="gnd", - layer="m1", - offset=offset, - width=width, - height=self.supply_rail_width) + offset = ll + vector(-2 * self.supply_rail_pitch, + -2 * self.supply_rail_pitch) + bottom_gnd_pin = self.add_layout_pin(text="gnd", + layer="m1", + offset=offset, + width=width, + height=self.supply_rail_width) - offset = ll + vector(-1*self.supply_rail_pitch, -1*self.supply_rail_pitch) - bottom_vdd_pin=self.add_layout_pin(text="vdd", - layer="m1", - offset=offset, - width=width, - height=self.supply_rail_width) + offset = ll + vector(-1 * self.supply_rail_pitch, + -1 * self.supply_rail_pitch) + bottom_vdd_pin = self.add_layout_pin(text="vdd", + layer="m1", + offset=offset, + width=width, + height=self.supply_rail_width) - # TOP horizontal rails - offset = vector(ll.x, ur.y) + vector(-2*self.supply_rail_pitch,0) - top_gnd_pin=self.add_layout_pin(text="gnd", - layer="m1", - offset=offset, - width=width, - height=self.supply_rail_width) + # TOP horizontal rails + offset = vector(ll.x, ur.y) + vector(-2 * self.supply_rail_pitch, + 0) + top_gnd_pin = self.add_layout_pin(text="gnd", + layer="m1", + offset=offset, + width=width, + height=self.supply_rail_width) - offset = vector(ll.x, ur.y) + vector(-1*self.supply_rail_pitch, self.supply_rail_pitch) - top_vdd_pin=self.add_layout_pin(text="vdd", - layer="m1", - offset=offset, - width=width, - height=self.supply_rail_width) + offset = vector(ll.x, ur.y) + vector(-1 * self.supply_rail_pitch, + self.supply_rail_pitch) + top_vdd_pin = self.add_layout_pin(text="vdd", + layer="m1", + offset=offset, + width=width, + height=self.supply_rail_width) # Remember these for connecting things in the design self.left_gnd_x_center = left_gnd_pin.cx() @@ -1132,14 +1195,13 @@ class layout(): self.top_gnd_y_center = top_gnd_pin.cy() self.top_vdd_y_center = top_vdd_pin.cy() - # Find the number of vias for this pitch self.supply_vias = 1 from sram_factory import factory while True: - c=factory.create(module_type="contact", - layer_stack=self.m1_stack, - dimensions=(self.supply_vias, self.supply_vias)) + c = factory.create(module_type="contact", + layer_stack=self.m1_stack, + dimensions=(self.supply_vias, self.supply_vias)) if c.second_layer_width < self.supply_rail_width and c.second_layer_height < self.supply_rail_width: self.supply_vias += 1 else: @@ -1158,13 +1220,15 @@ class layout(): for pt in via_points: self.add_via_center(layers=self.m1_stack, offset=pt, - size = (self.supply_vias, self.supply_vias)) + size=(self.supply_vias, + self.supply_vias)) - - def pdf_write(self, pdf_name): - # NOTE: Currently does not work (Needs further research) - #self.pdf_name = self.name + ".pdf" + """ + Display the layout to a PDF file. + """ + debug.error("NOTE: Currently does not work (Needs further research)") + # self.pdf_name = self.name + ".pdf" debug.info(0, "Writing to {}".format(pdf_name)) pdf = gdsMill.pdfLayout(self.gds) @@ -1184,22 +1248,22 @@ class layout(): def print_attr(self): """Prints a list of attributes for the current layout object""" - debug.info(0, + debug.info(0, "|==============================================================================|") - debug.info(0, + debug.info(0, "|========= LIST OF OBJECTS (Rects) FOR: " + self.name) - debug.info(0, + debug.info(0, "|==============================================================================|") for obj in self.objs: debug.info(0, "layer={0} : offset={1} : size={2}".format(obj.layerNumber, obj.offset, obj.size)) - debug.info(0, + debug.info(0, "|==============================================================================|") - debug.info(0, + debug.info(0, "|========= LIST OF INSTANCES FOR: " + self.name) - debug.info(0, + debug.info(0, "|==============================================================================|") for inst in self.insts: debug.info(0, "name={0} : mod={1} : offset={2}".format(inst.name, diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 20c513bb..bfe03c7b 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -62,7 +62,7 @@ class ptx(design.design): #ur = self.find_highest_coords() #self.add_boundary(ll, ur) - # (0,0) will be the corner ofthe active area (not the larger well) + # (0,0) will be the corner of the active area (not the larger well) self.translate_all(self.active_offset) def create_layout(self): @@ -108,8 +108,8 @@ class ptx(design.design): Pre-compute some handy layout parameters. """ - if self.num_contacts==None: - self.num_contacts=self.calculate_num_contacts() + if not self.num_contacts: + self.num_contacts = self.calculate_num_contacts() # Determine layer types needed if self.tx_type == "nmos": @@ -119,8 +119,7 @@ class ptx(design.design): self.implant_type = "p" self.well_type = "n" else: - self.error("Invalid transitor type.",-1) - + self.error("Invalid transitor type.", -1) # This is not actually instantiated but used for calculations self.active_contact = factory.create(module_type="contact", @@ -128,28 +127,30 @@ class ptx(design.design): directions = ("V", "V"), dimensions=(1, self.num_contacts)) - # The contacted poly pitch (or uncontacted in an odd technology) self.poly_pitch = max(2 * self.contact_to_gate + self.contact_width + self.poly_width, self.poly_space) # The contacted poly pitch (or uncontacted in an odd technology) - self.contact_pitch = 2 * self.contact_to_gate + self.contact_width + self.poly_width + self.contact_pitch = 2 * self.contact_to_gate + \ + self.contact_width + self.poly_width # The enclosure of an active contact. Not sure about second term. active_enclose_contact = max(self.active_enclose_contact, (self.active_width - self.contact_width) / 2) - # This is the distance from the edge of poly to the contacted end of active - self.end_to_poly = active_enclose_contact + self.contact_width + self.contact_to_gate + # This is the distance from the edge of + # poly to the contacted end of active + self.end_to_poly = active_enclose_contact + \ + self.contact_width + self.contact_to_gate - # Active width is determined by enclosure on both ends and contacted pitch, # at least one poly and n-1 poly pitches - self.active_width = 2 * self.end_to_poly + self.poly_width + (self.mults - 1) * self.poly_pitch + self.ptx_active_width = 2 * self.end_to_poly + self.poly_width + \ + (self.mults - 1) * self.poly_pitch # Active height is just the transistor width - self.active_height = self.tx_width + self.ptx_active_height = self.tx_width # Poly height must include poly extension over active self.poly_height = self.tx_width + 2 * self.poly_extend_active @@ -177,11 +178,11 @@ class ptx(design.design): # This is the center of the first active contact offset (centered vertically) self.contact_offset = self.active_offset + vector(active_enclose_contact + 0.5 * self.contact_width, - 0.5 * self.active_height) + 0.5 * self.ptx_active_height) # Min area results are just flagged for now. - debug.check(self.active_width * self.active_height >= self.minarea_active, + debug.check(self.ptx_active_width * self.ptx_active_height >= self.minarea_active, "Minimum active area violated.") # We do not want to increase the poly dimensions to fix # an area problem as it would cause an LVS issue. @@ -215,14 +216,14 @@ class ptx(design.design): poly_offset = poly_positions[0] + vector(-0.5 * self.poly_width, distance_above_active) # Remove the old pin and add the new one - self.remove_layout_pin("G") # only keep the main pin + # only keep the main pin + self.remove_layout_pin("G") self.add_layout_pin(text="G", layer="poly", offset=poly_offset, width=poly_width, height=self.poly_width) - def connect_fingered_active(self, drain_positions, source_positions): """ Connect each contact up/down to a source or drain pin @@ -230,10 +231,10 @@ class ptx(design.design): # This is the distance that we must route up or down from the center # of the contacts to avoid DRC violations to the other contacts - pin_offset = vector(0, 0.5 * self.active_contact.second_layer_height \ + pin_offset = vector(0, 0.5 * self.active_contact.second_layer_height + self.m1_space + 0.5 * self.m1_width) # This is the width of a m1 extend the ends of the pin - end_offset = vector(self.m1_width/2,0) + end_offset = vector(self.m1_width / 2.0, 0) # drains always go to the MIDDLE of the cell, # so top of NMOS, bottom of PMOS @@ -246,8 +247,9 @@ class ptx(design.design): source_dir = -1 if len(source_positions) > 1: - source_offset = pin_offset.scale(source_dir,source_dir) - self.remove_layout_pin("S") # remove the individual connections + source_offset = pin_offset.scale(source_dir, source_dir) + # remove the individual connections + self.remove_layout_pin("S") # Add each vertical segment for a in source_positions: self.add_path(("m1"), @@ -310,16 +312,16 @@ class ptx(design.design): """ self.add_rect(layer="active", offset=self.active_offset, - width=self.active_width, - height=self.active_height) + width=self.ptx_active_width, + height=self.ptx_active_height) # If the implant must enclose the active, shift offset # and increase width/height enclose_width = self.implant_enclose_active enclose_offset = [enclose_width] * 2 self.add_rect(layer="{}implant".format(self.implant_type), offset=self.active_offset - enclose_offset, - width=self.active_width + 2 * enclose_width, - height=self.active_height + 2 * enclose_width) + width=self.ptx_active_width + 2 * enclose_width, + height=self.ptx_active_height + 2 * enclose_width) def add_well_implant(self): """ From 082f575e2a8fca9c347990bc4161a5be437f2401 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Mon, 23 Dec 2019 21:45:09 +0000 Subject: [PATCH 097/521] Use active_width in ptx again despite colliding with DRC rule --- compiler/pgates/ptx.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index bfe03c7b..282e17d8 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -146,11 +146,11 @@ class ptx(design.design): # Active width is determined by enclosure on both ends and contacted pitch, # at least one poly and n-1 poly pitches - self.ptx_active_width = 2 * self.end_to_poly + self.poly_width + \ + self.active_width = 2 * self.end_to_poly + self.poly_width + \ (self.mults - 1) * self.poly_pitch # Active height is just the transistor width - self.ptx_active_height = self.tx_width + self.active_height = self.tx_width # Poly height must include poly extension over active self.poly_height = self.tx_width + 2 * self.poly_extend_active @@ -178,11 +178,11 @@ class ptx(design.design): # This is the center of the first active contact offset (centered vertically) self.contact_offset = self.active_offset + vector(active_enclose_contact + 0.5 * self.contact_width, - 0.5 * self.ptx_active_height) + 0.5 * self.active_height) # Min area results are just flagged for now. - debug.check(self.ptx_active_width * self.ptx_active_height >= self.minarea_active, + debug.check(self.active_width * self.active_height >= self.minarea_active, "Minimum active area violated.") # We do not want to increase the poly dimensions to fix # an area problem as it would cause an LVS issue. @@ -312,16 +312,16 @@ class ptx(design.design): """ self.add_rect(layer="active", offset=self.active_offset, - width=self.ptx_active_width, - height=self.ptx_active_height) + width=self.active_width, + height=self.active_height) # If the implant must enclose the active, shift offset # and increase width/height enclose_width = self.implant_enclose_active enclose_offset = [enclose_width] * 2 self.add_rect(layer="{}implant".format(self.implant_type), offset=self.active_offset - enclose_offset, - width=self.ptx_active_width + 2 * enclose_width, - height=self.ptx_active_height + 2 * enclose_width) + width=self.active_width + 2 * enclose_width, + height=self.active_height + 2 * enclose_width) def add_well_implant(self): """ From a6f5e59e186984a936e3e82c4d2dab66b22817d5 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Mon, 23 Dec 2019 21:49:47 +0000 Subject: [PATCH 098/521] Remove unused layers and simplify layer check to work without it. --- compiler/pgates/pgate.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 9cb73542..7e1fc87f 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -130,12 +130,12 @@ class pgate(design.design): max_y_offset = self.height + 0.5 * self.m1_width self.nwell_position = middle_position nwell_height = max_y_offset - middle_position.y - if layer["nwell"]: + if "nwell" in layer: self.add_rect(layer="nwell", offset=middle_position, width=self.well_width, height=nwell_height) - if layer["vtg"]: + if "vtg" in layer: self.add_rect(layer="vtg", offset=self.nwell_position, width=self.well_width, @@ -143,12 +143,12 @@ class pgate(design.design): pwell_position = vector(0, -0.5 * self.m1_width) pwell_height = middle_position.y - pwell_position.y - if layer["pwell"]: + if "pwell" in layer: self.add_rect(layer="pwell", offset=pwell_position, width=self.well_width, height=pwell_height) - if layer["vtg"]: + if "vtg" in layer: self.add_rect(layer="vtg", offset=pwell_position, width=self.well_width, From 14e8a26246d9ff0f70a94970ab527a26389255b5 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 3 Jan 2020 11:33:34 +0100 Subject: [PATCH 099/521] base/pin_layout: Make rect and layer properties only rect and layer are used to compute the hash for a pin. Having those as properties allows us to cache the hash value and only update it if either rect or layer are written. Signed-off-by: Bastian Koppelmann --- compiler/base/pin_layout.py | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index ea114ac6..451bb1ed 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -22,31 +22,47 @@ class pin_layout: self.name = name # repack the rect as a vector, just in case if type(rect[0]) == vector: - self.rect = rect + self._rect = rect else: - self.rect = [vector(rect[0]), vector(rect[1])] + self._rect = [vector(rect[0]), vector(rect[1])] # snap the rect to the grid - self.rect = [x.snap_to_grid() for x in self.rect] + self._rect = [x.snap_to_grid() for x in self.rect] debug.check(self.width() > 0, "Zero width pin.") debug.check(self.height() > 0, "Zero height pin.") # if it's a string, use the name if type(layer_name_pp) == str: - self.layer = layer_name_pp + self._layer = layer_name_pp # else it is required to be a lpp else: for (layer_name, lpp) in layer.items(): if not lpp: continue if self.same_lpp(layer_name_pp, lpp): - self.layer = layer_name + self._layer = layer_name break else: debug.error("Couldn't find layer {}".format(layer_name_pp), -1) self.lpp = layer[self.layer] + @property + def layer(self): + return self._layer + + @layer.setter + def layer(self, l): + self._layer = l + + @property + def rect(self): + return self._rect + + @rect.setter + def rect(self, r): + self._rect = r + def __str__(self): """ override print function output """ return "({} layer={} ll={} ur={})".format(self.name, From 7ff5121d8ce33ba7ae45d0914e493da13da5d515 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 3 Jan 2020 11:39:59 +0100 Subject: [PATCH 100/521] base/pin_layout: Implement hash cache the hash value only depends of the properties 'rect' and 'layer' so we only compute the hash if those values are changed. Otherwise we just return the precomputed value. This gives us a major speedup (~10x) if the hash is used as a key in a dict. During the grouping of pins in analyze_pins() this gives the best improvements. For example for FreePDK45 with num_bits=8, num_words=256 Improved **** Analyzing pins: 20.9 seconds ** Routing: 293.8 seconds ** SRAM creation: 349.8 seconds Non-improved **** Analyzing pins: 267.9 seconds ** Routing: 537.5 seconds ** SRAM creation: 592.9 seconds Signed-off-by: Bastian Koppelmann --- compiler/base/pin_layout.py | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index 451bb1ed..d7f6c49e 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -46,6 +46,7 @@ class pin_layout: debug.error("Couldn't find layer {}".format(layer_name_pp), -1) self.lpp = layer[self.layer] + self._recompute_hash() @property def layer(self): @@ -54,6 +55,7 @@ class pin_layout: @layer.setter def layer(self, l): self._layer = l + self._recompute_hash() @property def rect(self): @@ -62,6 +64,11 @@ class pin_layout: @rect.setter def rect(self, r): self._rect = r + self._recompute_hash() + + def _recompute_hash(self): + """ Recompute the hash for our hash cache """ + self._hash = hash(repr(self)) def __str__(self): """ override print function output """ @@ -80,8 +87,12 @@ class pin_layout: self.rect[1]) def __hash__(self): - """ Implement the hash function for sets etc. """ - return hash(repr(self)) + """ + Implement the hash function for sets etc. We only return a cached + value, that is updated when either 'rect' or 'layer' are changed. This + is a major speedup, if pin_layout is used as a key for dicts. + """ + return self._hash def __lt__(self, other): """ Provide a function for ordering items by the ll point """ From c0c89e465a191d676c8a8f2f16a4ea2939046616 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 3 Jan 2020 11:49:51 +0100 Subject: [PATCH 101/521] vector: Implement hash cache for vector3d and vector this gives us a small runtime improvement in the router. For FreePDK45 word_size=8, num_words=256 Improved *** Maze routing supplies: 89.8 seconds ** Routing: 279.3 seconds Non-improved *** Maze routing supplies: 105.1 seconds ** Routing: 293.5 seconds Signed-off-by: Bastian Koppelmann --- compiler/base/vector.py | 3 ++- compiler/router/vector3d.py | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/compiler/base/vector.py b/compiler/base/vector.py index 8bf09f7d..6688462d 100644 --- a/compiler/base/vector.py +++ b/compiler/base/vector.py @@ -28,6 +28,7 @@ class vector(): else: self.x = float(x) self.y = float(y) + self._hash = hash((self.x,self.y)) def __str__(self): """ override print function output """ @@ -97,7 +98,7 @@ class vector(): Note: This assumes that you DON'T CHANGE THE VECTOR or it will break things. """ - return hash((self.x,self.y)) + return self._hash def snap_to_grid(self): self.x = self.snap_offset_to_grid(self.x) diff --git a/compiler/router/vector3d.py b/compiler/router/vector3d.py index 0d183021..066f843f 100644 --- a/compiler/router/vector3d.py +++ b/compiler/router/vector3d.py @@ -27,7 +27,7 @@ class vector3d(): self.x = x self.y = y self.z = z - + self._hash = hash((self.x,self.y,self.z)) def __str__(self): """ override print function output """ @@ -96,7 +96,7 @@ class vector3d(): Note: This assumes that you DON'T CHANGE THE VECTOR or it will break things. """ - return hash((self.x,self.y,self.z)) + return self._hash def __rsub__(self, other): From 2c610036b2ee00d10286353c2e758e3778ed56b5 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 3 Jan 2020 12:24:14 +0100 Subject: [PATCH 102/521] router/supply_grid_router: Print init time to the user this can take considerable amount of time, so the user knows that useful work is done. Signed-off-by: Bastian Koppelmann --- compiler/router/supply_grid_router.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/router/supply_grid_router.py b/compiler/router/supply_grid_router.py index 881e87b2..b28f875e 100644 --- a/compiler/router/supply_grid_router.py +++ b/compiler/router/supply_grid_router.py @@ -31,6 +31,8 @@ class supply_grid_router(router): This will route on layers in design. It will get the blockages from either the gds file name or the design itself (by saving to a gds file). """ + start_time = datetime.now() + # Power rail width in minimum wire widths self.rail_track_width = 3 @@ -40,8 +42,8 @@ class supply_grid_router(router): self.supply_rails = {} # This is the same as above but as a sigle set for the all the rails self.supply_rail_tracks = {} - + print_time("Init supply router", datetime.now(), start_time, 3) def create_routing_grid(self): From ea00258be9b7474c5aa4b6f6781c28d8a32426c9 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Jan 2020 19:26:43 +0000 Subject: [PATCH 103/521] Cleanup contact --- compiler/base/contact.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 64433633..1a5785aa 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -55,7 +55,7 @@ class contact(hierarchy_design.hierarchy_design): # Module does not have pins, but has empty pin list. self.pins = [] self.create_layout() - + def create_layout(self): self.setup_layers() @@ -65,8 +65,10 @@ class contact(hierarchy_design.hierarchy_design): self.create_second_layer_enclosure() self.create_nitride_cut_enclosure() - self.height = max(obj.offset.y + obj.height for obj in self.objs) - self.width = max(obj.offset.x + obj.width for obj in self.objs) + self.height = max(self.first_layer_position.y + self.first_layer_height, + self.second_layer_position.y + self.second_layer_height) + self.width = max(self.first_layer_position.x + self.first_layer_width, + self.second_layer_position.x + self.second_layer_width) # Do not include the select layer in the height/width if self.implant_type and self.well_type: @@ -228,9 +230,10 @@ class contact(hierarchy_design.hierarchy_design): # Optionally implant well if layer exists well_layer = "{}well".format(self.well_type) if well_layer in tech.layer: - well_position = self.first_layer_position - [drc("well_enclose_active")] * 2 - well_width = self.first_layer_width + 2 * drc("well_enclose_active") - well_height = self.first_layer_height + 2 * drc("well_enclose_active") + well_enclose_active = drc(well_layer + "_enclose_active") + well_position = self.first_layer_position - [well_enclose_active] * 2 + well_width = self.first_layer_width + 2 * well_enclose_active + well_height = self.first_layer_height + 2 * well_enclose_active self.add_rect(layer=well_layer, offset=well_position, width=well_width, From a2387da29d48d9064991f7726bf8c448c9053c51 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Jan 2020 19:26:57 +0000 Subject: [PATCH 104/521] PEP format design --- compiler/base/design.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/base/design.py b/compiler/base/design.py index 59772a02..9b595b5f 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -63,8 +63,8 @@ class design(hierarchy_design): contact1 = getattr(contact, layer1 + layer2) max_contact = max(contact1.width, contact1.height) - layer1_space = getattr(self, layer1+"_space") - layer2_space = getattr(self, layer2+"_space") + layer1_space = getattr(self, layer1 + "_space") + layer2_space = getattr(self, layer2 + "_space") pitch = max_contact + max(layer1_space, layer2_space) return pitch @@ -83,7 +83,7 @@ class design(hierarchy_design): if match.group(1) == "active_contact": setattr(self, "contact_width", drc(match.group(0))) else: - setattr(self, match.group(1)+"_width", drc(match.group(0))) + setattr(self, match.group(1) + "_width", drc(match.group(0))) # Single layer area rules match = re.search(r"minarea_(.*)", rule) @@ -93,10 +93,10 @@ class design(hierarchy_design): # Single layer spacing rules match = re.search(r"(.*)_to_(.*)", rule) if match and match.group(1) == match.group(2): - setattr(self, match.group(1)+"_space", drc(match.group(0))) + setattr(self, match.group(1) + "_space", drc(match.group(0))) elif match and match.group(1) != match.group(2): if match.group(2) == "poly_active": - setattr(self, match.group(1)+"_to_contact", + setattr(self, match.group(1) + "_to_contact", drc(match.group(0))) else: setattr(self, match.group(0), drc(match.group(0))) From 262782cba09b1c3167239d5876c83e1c3253262a Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Jan 2020 19:27:39 +0000 Subject: [PATCH 105/521] Remove print, fix compare --- compiler/base/hierarchy_layout.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 7b870ae7..caf8d02b 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -533,7 +533,6 @@ class layout(): height = boundary[1][1] - boundary[0][1] width = boundary[1][0] - boundary[0][0] (layer_number, layer_purpose) = techlayer[boundary_layer] - print(self.name, boundary, height, width) gds_layout.addBox(layerNumber=layer_number, purposeNumber=layer_purpose, offsetInMicrons=boundary[0], @@ -1019,7 +1018,7 @@ class layout(): boundary_layer = "stdc" else: boundary_layer = "boundary" - if ur == None: + if not ur: self.boundary = self.add_rect(layer=boundary_layer, offset=ll, height=self.height, From 306740f0f3cd21e4615e7732f58246e1fc38d307 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Jan 2020 19:27:59 +0000 Subject: [PATCH 106/521] Add empty minarea function --- compiler/base/pin_layout.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index ea114ac6..a600d474 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -101,7 +101,14 @@ class pin_layout: max_y = max(max_y, pin.ur().y) self.rect = [vector(min_x, min_y), vector(max_x, max_y)] - + + def fix_minarea(self): + """ + Try to fix minimum area rule. + """ + min_area = drc("{}_minarea".format(self.layer)) + pass + def inflate(self, spacing=None): """ Inflate the rectangle by the spacing (or other rule) From 9beb0f4ece894618e65f0c9528639c50a5e0c61a Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 23 Jan 2020 19:43:41 +0000 Subject: [PATCH 107/521] Add separate well design rules. Needed to fix various pgates with wells. Did some cleanup of these gates as well. --- compiler/base/hierarchy_layout.py | 67 +++++++++++++++--- compiler/bitcells/pbitcell.py | 18 ++--- compiler/modules/bank.py | 2 +- compiler/modules/port_address.py | 2 +- compiler/modules/port_data.py | 2 +- compiler/pgates/pgate.py | 20 +++--- compiler/pgates/pinv.py | 4 +- compiler/pgates/pnand2.py | 4 +- compiler/pgates/pnand3.py | 12 ++-- compiler/pgates/pnor2.py | 5 +- compiler/pgates/precharge.py | 4 +- compiler/pgates/ptristate_inv.py | 7 +- compiler/pgates/ptx.py | 105 ++++++++++++++++------------- compiler/pgates/pwrite_driver.py | 16 ++--- technology/freepdk45/tech/tech.py | 10 ++- technology/scn4m_subm/tech/tech.py | 14 ++-- 16 files changed, 181 insertions(+), 111 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index caf8d02b..bfb1c2d2 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -68,8 +68,10 @@ class layout(): return (base_offset, y_dir) def find_lowest_coords(self): - """Finds the lowest set of 2d cartesian coordinates within - this layout""" + """ + Finds the lowest set of 2d cartesian coordinates within + this layout + """ if len(self.objs) > 0: lowestx1 = min(obj.lx() for obj in self.objs if obj.name != "label") @@ -116,6 +118,54 @@ class layout(): return vector(max(highestx1, highestx2), max(highesty1, highesty2)) + def find_highest_layer_coords(self, layer): + """ + Finds the highest set of 2d cartesian coordinates within + this layout on a layer + """ + # Only consider the layer not the purpose for now + layerNumber = techlayer[layer][0] + try: + highestx = max(obj.rx() for obj in self.objs if obj.layerNumber == layerNumber) + except ValueError: + highestx =0 + try: + highesty = max(obj.uy() for obj in self.objs if obj.layerNumber == layerNumber) + except ValueError: + highesty = 0 + + for inst in self.insts: + # This really should be rotated/mirrored etc... + subcoord = inst.mod.find_highest_layer_coords(layer) + inst.offset + highestx = max(highestx, subcoord.x) + highesty = max(highesty, subcoord.y) + + return vector(highestx, highesty) + + def find_lowest_layer_coords(self, layer): + """ + Finds the highest set of 2d cartesian coordinates within + this layout on a layer + """ + # Only consider the layer not the purpose for now + layerNumber = techlayer[layer][0] + try: + lowestx = min(obj.lx() for obj in self.objs if obj.layerNumber == layerNumber) + except ValueError: + lowestx = 0 + try: + lowesty = min(obj.by() for obj in self.objs if obj.layerNumber == layerNumber) + except ValueError: + lowesty = 0 + + for inst in self.insts: + # This really should be rotated/mirrored etc... + subcoord = inst.mod.find_lowest_layer_coords(layer) + inst.offset + lowestx = min(lowestx, subcoord.x) + lowesty = min(lowesty, subcoord.y) + + return vector(lowestx, lowesty) + def translate_all(self, offset): """ Translates all objects, instances, and pins by the given (x,y) offset @@ -429,7 +479,7 @@ class layout(): return inst def add_via_center(self, layers, offset, directions=None, size=[1,1], implant_type=None, well_type=None): - """ + """ Add a three layer via structure by the center coordinate accounting for mirroring and rotation. """ @@ -466,7 +516,7 @@ class layout(): mults=mults, tx_type=tx_type) self.add_mod(mos) - inst = self.add_inst(name=mos.name, + inst = self.add_inst(name=mos.name, mod=mos, offset=offset, mirror=mirror, @@ -652,22 +702,21 @@ class layout(): vertical=False, make_pins=False) - def create_bus(self, layer, pitch, offset, names, length, vertical, make_pins): """ Create a horizontal or vertical bus. It can be either just rectangles, or actual - layout pins. It returns an map of line center line positions indexed by name. + layout pins. It returns an map of line center line positions indexed by name. The other coordinate is a 0 since the bus provides a range. TODO: combine with channel router. """ # half minwidth so we can return the center line offsets - half_minwidth = 0.5*drc["minwidth_{}".format(layer)] + half_minwidth = 0.5 * drc["minwidth_{}".format(layer)] line_positions = {} if vertical: for i in range(len(names)): - line_offset = offset + vector(i*pitch,0) + line_offset = offset + vector(i * pitch, 0) if make_pins: self.add_layout_pin(text=names[i], layer=layer, @@ -885,7 +934,7 @@ class layout(): return g def vcg_nets_overlap(net1, net2, vertical, pitch): - """ + """ Check all the pin pairs on two nets and return a pin overlap if any pin overlaps. """ diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index d809c6f1..6de87507 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -977,12 +977,12 @@ class pbitcell(bitcell_base.bitcell_base): """ # extend pwell to encompass entire nmos region of the cell up to the # height of the tallest nmos transistor - max_nmos_well_height = max(self.inverter_nmos.cell_well_height, - self.readwrite_nmos.cell_well_height, - self.write_nmos.cell_well_height, - self.read_nmos.cell_well_height) + max_nmos_well_height = max(self.inverter_nmos.well_height, + self.readwrite_nmos.well_height, + self.write_nmos.well_height, + self.read_nmos.well_height) well_height = max_nmos_well_height + self.port_ypos \ - - self.well_enclose_active - self.gnd_position.y + - self.nwell_enclose_active - self.gnd_position.y offset = vector(self.leftmost_xpos, self.botmost_ypos) self.add_rect(layer="pwell", offset=offset, @@ -992,16 +992,16 @@ class pbitcell(bitcell_base.bitcell_base): # extend nwell to encompass inverter_pmos # calculate offset of the left pmos well inverter_well_xpos = -(self.inverter_nmos.active_width + 0.5 * self.inverter_to_inverter_spacing) \ - - self.well_enclose_active + - self.nwell_enclose_active inverter_well_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \ - + self.inverter_gap - self.well_enclose_active + + self.inverter_gap - self.nwell_enclose_active # calculate width of the two combined nwells # calculate height to encompass nimplant connected to vdd well_width = 2 * (self.inverter_nmos.active_width + 0.5 * self.inverter_to_inverter_spacing) \ - + 2 * self.well_enclose_active + + 2 * self.nwell_enclose_active well_height = self.vdd_position.y - inverter_well_ypos \ - + self.well_enclose_active + drc["minwidth_tx"] + + self.nwell_enclose_active + drc["minwidth_tx"] offset = [inverter_well_xpos, inverter_well_ypos] self.add_rect(layer="nwell", diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 4527044c..7ed0c9a3 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -333,7 +333,7 @@ class bank(design.design): self.col_addr_bus_width = self.m2_pitch*self.num_col_addr_lines # A space for wells or jogging m2 - self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"), + self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"), 3*self.m2_pitch) diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 7f1fdd49..44b0d5a5 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -149,7 +149,7 @@ class port_address(design.design): """ # A space for wells or jogging m2 - self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"), + self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"), 3*self.m2_pitch) row_decoder_offset = vector(0,0) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 33ecdd01..9e7f4048 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -212,7 +212,7 @@ class port_data(design.design): # A space for wells or jogging m2 between modules - self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"), + self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"), 3*self.m2_pitch) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 7e1fc87f..a964cbe4 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -8,7 +8,7 @@ import contact import design import debug -from tech import layer, drc +from tech import layer from vector import vector from globals import OPTS from sram_factory import factory @@ -127,9 +127,10 @@ class pgate(design.design): """ Extend the n/p wells to cover whole cell """ # Add a rail width to extend the well to the top of the rail - max_y_offset = self.height + 0.5 * self.m1_width - self.nwell_position = middle_position - nwell_height = max_y_offset - middle_position.y + nwell_max_offset = max(self.find_highest_layer_coords("nwell").y, + self.height + 0.5 * self.m1_width) + nwell_position = middle_position + nwell_height = nwell_max_offset - middle_position.y if "nwell" in layer: self.add_rect(layer="nwell", offset=middle_position, @@ -137,11 +138,14 @@ class pgate(design.design): height=nwell_height) if "vtg" in layer: self.add_rect(layer="vtg", - offset=self.nwell_position, + offset=nwell_position, width=self.well_width, height=nwell_height) - pwell_position = vector(0, -0.5 * self.m1_width) + # Start this half a rail width below the cell + pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y, + -0.5 * self.m1_width) + pwell_position = vector(0, pwell_min_offset) pwell_height = middle_position.y - pwell_position.y if "pwell" in layer: self.add_rect(layer="pwell", @@ -168,7 +172,7 @@ class pgate(design.design): # OR align the active with the top of PMOS active. max_y_offset = self.height + 0.5 * self.m1_width contact_yoffset = min(pmos_pos.y + pmos.active_height - pmos.active_contact.first_layer_height, - max_y_offset - pmos.active_contact.first_layer_height / 2 - self.well_enclose_active) + max_y_offset - pmos.active_contact.first_layer_height / 2 - self.nwell_enclose_active) contact_offset = vector(contact_xoffset, contact_yoffset) # Offset by half a contact in x and y contact_offset += vector(0.5 * pmos.active_contact.first_layer_width, @@ -220,7 +224,7 @@ class pgate(design.design): # Must be at least an well enclosure of active up # from the bottom of the well contact_yoffset = max(nmos_pos.y, - self.well_enclose_active \ + self.nwell_enclose_active \ - nmos.active_contact.first_layer_height / 2) contact_offset = vector(contact_xoffset, contact_yoffset) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index ce477a83..8a3a8326 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -153,7 +153,7 @@ class pinv(pgate.pgate): # the well width is determined the multi-finger PMOS device width plus # the well contact width and half well enclosure on both sides self.well_width = self.pmos.active_width + self.pmos.active_contact.width \ - + self.active_space + 2*self.well_enclose_active + + self.active_space + 2*self.nwell_enclose_active self.width = self.well_width # Height is an input parameter, so it is not recomputed. @@ -223,7 +223,7 @@ class pinv(pgate.pgate): self.output_pos = vector(0, 0.5 * (pmos_drain_pos.y + nmos_drain_pos.y)) # This will help with the wells - self.well_pos = vector(0, self.nmos_inst.uy()) + self.well_pos = self.output_pos def route_outputs(self): """ diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index dda736d2..8d3605a2 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -100,7 +100,7 @@ class pnand2(pgate.pgate): # Enclosure space on the sides. self.well_width = 2 * self.pmos.active_width + contact.activem1.width \ + 2 * self.active_space \ - + 2 * self.well_enclose_active + + 2 * self.nwell_enclose_active self.width = self.well_width # Height is an input parameter, so it is not recomputed. @@ -171,7 +171,7 @@ class pnand2(pgate.pgate): 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height)) # This will help with the wells - self.well_pos = vector(0, self.nmos1_inst.uy()) + self.well_pos = self.output_pos def add_well_contacts(self): """ diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 8ccbff2c..bb379db7 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -92,14 +92,11 @@ class pnand3(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. self.well_width = 3 * self.pmos.active_width + self.pmos.active_contact.width \ - + 2 * self.active_space + 2 * self.well_enclose_active \ + + 2 * self.active_space + 2 * self.nwell_enclose_active \ - self.overlap_offset.x self.width = self.well_width # Height is an input parameter, so it is not recomputed. - # This will help with the wells and the input/output placement - self.output_pos = vector(0, 0.5*self.height) - # This is the extra space needed to ensure DRC rules # to the active contacts nmos = factory.create(module_type="ptx", tx_type="nmos") @@ -178,9 +175,12 @@ class pnand3(pgate.pgate): self.nmos3_pos = nmos2_pos + self.overlap_offset self.nmos3_inst.place(self.nmos3_pos) - + + # This will help with the wells and the input/output placement + self.output_pos = vector(0, 0.5*self.height) + # This should be placed at the top of the NMOS well - self.well_pos = vector(0, self.nmos1_inst.uy()) + self.well_pos = self.output_pos def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index d24189ac..9895e9d9 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -98,7 +98,7 @@ class pnor2(pgate.pgate): self.well_width = 2 * self.pmos.active_width \ + self.pmos.active_contact.width \ + 2 * self.active_space \ - + 2 * self.well_enclose_active + + 2 * self.nwell_enclose_active self.width = self.well_width # Height is an input parameter, so it is not recomputed. @@ -136,7 +136,6 @@ class pnor2(pgate.pgate): mod=self.pmos) self.connect_inst(["net1", "B", "Z", "vdd"]) - self.nmos1_inst = self.add_inst(name="pnor2_nmos1", mod=self.nmos) self.connect_inst(["Z", "A", "gnd", "gnd"]) @@ -170,7 +169,7 @@ class pnor2(pgate.pgate): 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height)) # This will help with the wells - self.well_pos = vector(0, self.nmos1_inst.uy()) + self.well_pos = self.output_pos def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index f9e8ce87..d1e2f3af 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -116,7 +116,7 @@ class precharge(design.design): # adds the lower pmos to layout bl_xoffset = self.bitcell.get_pin(self.bitcell_bl).lx() self.lower_pmos_position = vector(max(bl_xoffset - contact_xdiff, - self.well_enclose_active), + self.nwell_enclose_active), self.pmos.active_offset.y) self.lower_pmos_inst.place(self.lower_pmos_position) @@ -176,7 +176,7 @@ class precharge(design.design): # adds the contact from active to metal1 well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \ + vector(0, self.upper_pmos1_inst.uy() + contact.activem1.height / 2 \ - + self.well_extend_active) + + self.nwell_extend_active) self.add_via_center(layers=self.active_stack, offset=well_contact_pos, implant_type="n", diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index d2965cde..764b87c0 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -44,7 +44,7 @@ class ptristate_inv(pgate.pgate): """ Calls all functions related to the generation of the netlist """ self.add_pins() self.add_ptx() - self.create_ptx() + self.create_ptx() def create_layout(self): """ Calls all functions related to the generation of the layout """ @@ -61,7 +61,6 @@ class ptristate_inv(pgate.pgate): """ Adds pins for spice netlist """ self.add_pin_list(["in", "out", "en", "en_bar", "vdd", "gnd"]) - def setup_layout_constants(self): """ Pre-compute some handy layout parameters. @@ -73,7 +72,7 @@ class ptristate_inv(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.well_width = 2 * self.pmos.active_width + self.well_enclose_active + self.well_width = 2 * self.pmos.active_width + self.nwell_enclose_active # Add an extra space because we route the output on the right of the S/D self.width = self.well_width + 0.5 * self.m1_space @@ -81,7 +80,6 @@ class ptristate_inv(pgate.pgate): # Make sure we can put a well above and below self.top_bottom_space = max(contact.activem1.width, contact.activem1.height) - def add_ptx(self): """ Create the PMOS and NMOS transistors. """ @@ -95,7 +93,6 @@ class ptristate_inv(pgate.pgate): width=self.pmos_width, mults=1, tx_type="pmos") - self.add_mod(self.pmos) def route_supply_rails(self): diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 282e17d8..32bbeefe 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -58,9 +58,9 @@ class ptx(design.design): # some transistor sizes in other netlist depend on pbitcell self.create_layout() - #ll = self.find_lowest_coords() - #ur = self.find_highest_coords() - #self.add_boundary(ll, ur) + ll = self.find_lowest_coords() + ur = self.find_highest_coords() + self.add_boundary(ll, ur) # (0,0) will be the corner of the active area (not the larger well) self.translate_all(self.active_offset) @@ -99,7 +99,7 @@ class ptx(design.design): drc("minwidth_poly")) area_str = "pd={0:.2f}u ps={0:.2f}u as={1:.2f}p ad={1:.2f}p".format(perimeter_sd, area_sd) - self.spice_device= main_str + area_str + self.spice_device = main_str + area_str self.spice.append("\n* ptx " + self.spice_device) # self.spice.append(".ENDS {0}".format(self.name)) @@ -124,30 +124,30 @@ class ptx(design.design): # This is not actually instantiated but used for calculations self.active_contact = factory.create(module_type="contact", layer_stack=self.active_stack, - directions = ("V", "V"), + directions=("V", "V"), dimensions=(1, self.num_contacts)) - # The contacted poly pitch (or uncontacted in an odd technology) + # The contacted poly pitch self.poly_pitch = max(2 * self.contact_to_gate + self.contact_width + self.poly_width, self.poly_space) - # The contacted poly pitch (or uncontacted in an odd technology) - self.contact_pitch = 2 * self.contact_to_gate + \ - self.contact_width + self.poly_width + # The contacted poly pitch + self.contact_spacing = 2 * self.contact_to_gate + \ + self.contact_width + self.poly_width + + # This is measured because of asymmetric enclosure rules + active_enclose_contact = 0.5*(self.active_contact.width - self.contact_width) - # The enclosure of an active contact. Not sure about second term. - active_enclose_contact = max(self.active_enclose_contact, - (self.active_width - self.contact_width) / 2) - - # This is the distance from the edge of - # poly to the contacted end of active - self.end_to_poly = active_enclose_contact + \ - self.contact_width + self.contact_to_gate + # This is the distance from the side of + # poly gate to the contacted end of active + # (i.e. the "outside" contacted diffusion sizes) + self.end_to_poly = self.active_contact.width - active_enclose_contact + \ + self.contact_to_gate # Active width is determined by enclosure on both ends and contacted pitch, # at least one poly and n-1 poly pitches self.active_width = 2 * self.end_to_poly + self.poly_width + \ - (self.mults - 1) * self.poly_pitch + (self.mults - 1) * self.poly_pitch # Active height is just the transistor width self.active_height = self.tx_width @@ -155,32 +155,35 @@ class ptx(design.design): # Poly height must include poly extension over active self.poly_height = self.tx_width + 2 * self.poly_extend_active + well_name = "{}well".format(self.well_type) + # The active offset is due to the well extension - self.active_offset = vector([self.well_enclose_active] * 2) + if well_name in layer: + well_enclose_active = drc(well_name + "_enclose_active") + self.active_offset = vector([well_enclose_active] * 2) + else: + self.active_offset = vector(0, 0) # Well enclosure of active, ensure minwidth as well - well_name = "{}well".format(self.well_type) if well_name in layer: - self.cell_well_width = max(self.active_width + 2 * self.well_enclose_active, - self.well_width) - self.cell_well_height = max(self.tx_width + 2 * self.well_enclose_active, - self.well_width) + well_width_rule = drc("minwidth_" + well_name) + well_enclose_active = drc(well_name + "_enclose_active") + self.well_width = max(self.active_width + 2 * well_enclose_active, + well_width_rule) + self.well_height = max(self.active_height + 2 * well_enclose_active, + well_width_rule) # We are going to shift the 0,0, so include that in the width and height - self.height = self.cell_well_height - self.active_offset.y - self.width = self.cell_well_width - self.active_offset.x + self.height = self.well_height - self.active_offset.y + self.width = self.well_width - self.active_offset.x else: - # If no well, use the boundary of the active and poly + # The well is not included in the height and width self.height = self.poly_height self.width = self.active_width - # The active offset is due to the well extension - self.active_offset = vector([self.well_enclose_active] * 2) - # This is the center of the first active contact offset (centered vertically) - self.contact_offset = self.active_offset + vector(active_enclose_contact + 0.5 * self.contact_width, + self.contact_offset = self.active_offset + vector(0.5 * self.active_contact.width, 0.5 * self.active_height) - # Min area results are just flagged for now. debug.check(self.active_width * self.active_height >= self.minarea_active, "Minimum active area violated.") @@ -231,8 +234,8 @@ class ptx(design.design): # This is the distance that we must route up or down from the center # of the contacts to avoid DRC violations to the other contacts - pin_offset = vector(0, 0.5 * self.active_contact.second_layer_height - + self.m1_space + 0.5 * self.m1_width) + pin_offset = vector(0, + 0.5 * self.active_contact.second_layer_height + self.m1_space + 0.5 * self.m1_width) # This is the width of a m1 extend the ends of the pin end_offset = vector(self.m1_width / 2.0, 0) @@ -328,26 +331,34 @@ class ptx(design.design): Add an (optional) well and implant for the type of transistor. """ well_name = "{}well".format(self.well_type) + if not (well_name in layer or "vtg" in layer): + return + + center_pos = self.active_offset + vector(self.width / 2.0, + self.height / 2.0) + well_ll = center_pos - vector(self.well_width / 2.0, + self.well_height / 2.0) + well_ll = well_ll - vector(0, + self.poly_extend_active) + if well_name in layer: self.add_rect(layer=well_name, - offset=(0,0), - width=self.cell_well_width, - height=self.cell_well_height) + offset=well_ll, + width=self.well_width, + height=self.well_height) if "vtg" in layer: self.add_rect(layer="vtg", - offset=(0,0), - width=self.cell_well_width, - height=self.cell_well_height) - + offset=well_ll, + width=self.well_width, + height=self.well_height) def calculate_num_contacts(self): - """ + """ Calculates the possible number of source/drain contacts in a finger. For now, it is hard set as 1. """ return 1 - def get_contact_positions(self): """ Create a list of the centers of drain and source contact positions. @@ -361,10 +372,10 @@ class ptx(design.design): for i in range(self.mults): if i%2: # It's a source... so offset from previous drain. - source_positions.append(drain_positions[-1] + vector(self.contact_pitch, 0)) + source_positions.append(drain_positions[-1] + vector(self.contact_spacing, 0)) else: # It's a drain... so offset from previous source. - drain_positions.append(source_positions[-1] + vector(self.contact_pitch, 0)) + drain_positions.append(source_positions[-1] + vector(self.contact_spacing, 0)) return [source_positions,drain_positions] @@ -379,7 +390,7 @@ class ptx(design.design): contact=self.add_via_center(layers=self.active_stack, offset=pos, size=(1, self.num_contacts), - directions=("H","V"), + directions=("V","V"), implant_type=self.implant_type, well_type=self.well_type) self.add_layout_pin_rect_center(text="S", @@ -393,7 +404,7 @@ class ptx(design.design): contact=self.add_via_center(layers=self.active_stack, offset=pos, size=(1, self.num_contacts), - directions=("H","V"), + directions=("V","V"), implant_type=self.implant_type, well_type=self.well_type) self.add_layout_pin_rect_center(text="D", diff --git a/compiler/pgates/pwrite_driver.py b/compiler/pgates/pwrite_driver.py index 2dc356c3..ed970f9b 100644 --- a/compiler/pgates/pwrite_driver.py +++ b/compiler/pgates/pwrite_driver.py @@ -40,12 +40,10 @@ class pwrite_driver(design.design): # Creates the netlist and layout # Since it has variable height, it is not a pgate. self.create_netlist() - if not OPTS.netlist_only: + if not OPTS.netlist_only: self.create_layout() self.DRC_LVS() - - def create_netlist(self): self.add_pins() self.add_modules() @@ -55,8 +53,6 @@ class pwrite_driver(design.design): self.place_modules() self.route_wires() self.route_supplies() - - def add_pins(self): self.add_pin("din", "INPUT") @@ -66,17 +62,19 @@ class pwrite_driver(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - def add_modules(self): # Tristate inverter self.tri = factory.create(module_type="ptristate_inv", height="min") self.add_mod(self.tri) - debug.check(self.tri.width Date: Fri, 24 Jan 2020 17:45:24 +0000 Subject: [PATCH 108/521] Add fudge factor to pbitcell wells --- compiler/bitcells/pbitcell.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 6de87507..4f19c489 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -983,10 +983,12 @@ class pbitcell(bitcell_base.bitcell_base): self.read_nmos.well_height) well_height = max_nmos_well_height + self.port_ypos \ - self.nwell_enclose_active - self.gnd_position.y - offset = vector(self.leftmost_xpos, self.botmost_ypos) + # FIXME fudge factor xpos + well_width = self.width + 2*self.nwell_enclose_active + offset = vector(self.leftmost_xpos - self.nwell_enclose_active, self.botmost_ypos) self.add_rect(layer="pwell", offset=offset, - width=self.width, + width=well_width, height=well_height) # extend nwell to encompass inverter_pmos @@ -1003,7 +1005,8 @@ class pbitcell(bitcell_base.bitcell_base): well_height = self.vdd_position.y - inverter_well_ypos \ + self.nwell_enclose_active + drc["minwidth_tx"] - offset = [inverter_well_xpos, inverter_well_ypos] + # FIXME fudge factor xpos + offset = [inverter_well_xpos + 2*self.nwell_enclose_active, inverter_well_ypos] self.add_rect(layer="nwell", offset=offset, width=well_width, From 71cbe7401788736119e6827bede68c98b9f82e92 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 24 Jan 2020 18:00:28 +0000 Subject: [PATCH 109/521] Round middle position fix --- compiler/base/vector.py | 2 +- compiler/pgates/pgate.py | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/base/vector.py b/compiler/base/vector.py index 8bf09f7d..c9304f42 100644 --- a/compiler/base/vector.py +++ b/compiler/base/vector.py @@ -49,7 +49,7 @@ class vector(): else: self.x=float(value[0]) self.y=float(value[1]) - + def __getitem__(self, index): """ override getitem function diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index a964cbe4..e009d1bb 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -126,6 +126,8 @@ class pgate(design.design): def extend_wells(self, middle_position): """ Extend the n/p wells to cover whole cell """ + # FIXME: float rounding problem + middle_position = middle_position.snap_to_grid() # Add a rail width to extend the well to the top of the rail nwell_max_offset = max(self.find_highest_layer_coords("nwell").y, self.height + 0.5 * self.m1_width) From 877ea53b7f82c44b387e593659a591b1f7dd1ea3 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 24 Jan 2020 21:24:44 +0000 Subject: [PATCH 110/521] Fix conflicting boundary name --- compiler/base/geometry.py | 2 ++ compiler/base/hierarchy_layout.py | 23 +++++++++++++---------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 46cfe7c7..f354cf02 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -69,7 +69,9 @@ class geometry: """ Transform with offset, mirror and rotation to get the absolute pin location. We must then re-find the ll and ur. The master is the cell instance. """ if OPTS.netlist_only: + self.boundary = [vector(0,0), vector(0,0)] return + (ll, ur) = [vector(0, 0), vector(self.width, self.height)] if mirror == "MX": diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index bfb1c2d2..a1b18ef3 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -31,7 +31,7 @@ class layout(): self.name = name self.width = None self.height = None - self.boundary = None + self.bounding_box = None self.insts = [] # Holds module/cell layout instances self.objs = [] # Holds all other objects (labels, geometries, etc) self.pin_map = {} # Holds name->pin_layout map for all pins @@ -574,7 +574,7 @@ class layout(): # If it's not a premade cell # and we didn't add our own boundary, # we should add a boundary just for DRC in some technologies - if not self.is_library_cell and not self.boundary: + if not self.is_library_cell and not self.bounding_box: # If there is a boundary layer, and we didn't create one, add one. if "stdc" in techlayer.keys(): boundary_layer = "stdc" @@ -1063,20 +1063,23 @@ class layout(): def add_boundary(self, ll=vector(0, 0), ur=None): """ Add boundary for debugging dimensions """ + if OPTS.netlist_only: + return + if "stdc" in techlayer.keys(): boundary_layer = "stdc" else: boundary_layer = "boundary" if not ur: - self.boundary = self.add_rect(layer=boundary_layer, - offset=ll, - height=self.height, - width=self.width) + self.bounding_box = self.add_rect(layer=boundary_layer, + offset=ll, + height=self.height, + width=self.width) else: - self.boundary = self.add_rect(layer=boundary_layer, - offset=ll, - height=ur.y-ll.y, - width=ur.x-ll.x) + self.bounding_box = self.add_rect(layer=boundary_layer, + offset=ll, + height=ur.y-ll.y, + width=ur.x-ll.x) def add_enclosure(self, insts, layer="nwell"): """ Add a layer that surrounds the given instances. Useful From 3fb2b9c1c36bd27a7dd157c9dfad759ff64e9d0c Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 27 Jan 2020 11:53:29 +0100 Subject: [PATCH 111/521] Bitcell arrays: Create abstract base class a lot of functions of dummy- and bitcell-array are either copy-pasted or have just slight differences. Merge all of those into an abstract base class such that we don't have too much duplicate code. Signed-off-by: Bastian Koppelmann --- compiler/modules/base_array.py | 107 ++++++++++++++++++++++++++++++ compiler/modules/bitcell_array.py | 91 ++----------------------- compiler/modules/dummy_array.py | 94 ++------------------------ 3 files changed, 115 insertions(+), 177 deletions(-) create mode 100644 compiler/modules/base_array.py diff --git a/compiler/modules/base_array.py b/compiler/modules/base_array.py new file mode 100644 index 00000000..db2b1be6 --- /dev/null +++ b/compiler/modules/base_array.py @@ -0,0 +1,107 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +import design + +class bitcell_base_array(design.design): + """ + Abstract base class for bitcell-arrays -- bitcell, dummy + """ + def __init__(self, cols, rows, name): + design.design.__init__(self, name) + debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) + self.add_comment("rows: {0} cols: {1}".format(rows, cols)) + + self.column_size = cols + self.row_size = rows + + def add_pins(self): + row_list = self.cell.get_all_wl_names() + column_list = self.cell.get_all_bitline_names() + for col in range(self.column_size): + for cell_column in column_list: + self.add_pin(cell_column+"_{0}".format(col), "INOUT") + for row in range(self.row_size): + for cell_row in row_list: + self.add_pin(cell_row+"_{0}".format(row), "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def get_bitcell_pins(self, col, row): + """ Creates a list of connections in the bitcell, + indexed by column and row, for instance use in bitcell_array """ + + bitcell_pins = [] + + pin_names = self.cell.get_all_bitline_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(col)) + pin_names = self.cell.get_all_wl_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(row)) + bitcell_pins.append("vdd") + bitcell_pins.append("gnd") + + return bitcell_pins + + def add_layout_pins(self): + """ Add the layout pins """ + + row_list = self.cell.get_all_wl_names() + column_list = self.cell.get_all_bitline_names() + + for col in range(self.column_size): + for cell_column in column_list: + bl_pin = self.cell_inst[0,col].get_pin(cell_column) + self.add_layout_pin(text=cell_column+"_{0}".format(col), + layer=bl_pin.layer, + offset=bl_pin.ll().scale(1,0), + width=bl_pin.width(), + height=self.height) + + for row in range(self.row_size): + for cell_row in row_list: + wl_pin = self.cell_inst[row,0].get_pin(cell_row) + self.add_layout_pin(text=cell_row+"_{0}".format(row), + layer=wl_pin.layer, + offset=wl_pin.ll().scale(0,1), + width=self.width, + height=wl_pin.height()) + + # For every second row and column, add a via for gnd and vdd + for row in range(self.row_size): + for col in range(self.column_size): + inst = self.cell_inst[row,col] + for pin_name in ["vdd", "gnd"]: + for pin in inst.get_pins(pin_name): + self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer) + + + + def place_array(self, name_template, row_offset=0): + # We increase it by a well enclosure so the precharges don't overlap our wells + self.height = self.row_size*self.cell.height + self.width = self.column_size*self.cell.width + + xoffset = 0.0 + for col in range(self.column_size): + yoffset = 0.0 + for row in range(self.row_size): + name = name_template.format(row, col) + + if (row + row_offset) % 2: + tempy = yoffset + self.cell.height + dir_key = "MX" + else: + tempy = yoffset + dir_key = "" + + self.cell_inst[row,col].place(offset=[xoffset, tempy], + mirror=dir_key) + yoffset += self.cell.height + xoffset += self.cell.width diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index bf43736b..4c1c798b 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -7,25 +7,21 @@ # import debug import design +from base_array import bitcell_base_array from tech import drc, spice from vector import vector from globals import OPTS from sram_factory import factory import logical_effort -class bitcell_array(design.design): +class bitcell_array(bitcell_base_array): """ Creates a rows x cols array of memory cells. Assumes bit-lines and word line is connected by abutment. Connects the word lines and bit lines. """ def __init__(self, cols, rows, name): - design.design.__init__(self, name) - debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) - self.add_comment("rows: {0} cols: {1}".format(rows, cols)) - - self.column_size = cols - self.row_size = rows + super().__init__(cols, rows, name) self.create_netlist() if not OPTS.netlist_only: @@ -44,27 +40,7 @@ class bitcell_array(design.design): def create_layout(self): - # We increase it by a well enclosure so the precharges don't overlap our wells - self.height = self.row_size*self.cell.height - self.width = self.column_size*self.cell.width - - xoffset = 0.0 - for col in range(self.column_size): - yoffset = 0.0 - for row in range(self.row_size): - name = "bit_r{0}_c{1}".format(row, col) - - if row % 2: - tempy = yoffset + self.cell.height - dir_key = "MX" - else: - tempy = yoffset - dir_key = "" - - self.cell_inst[row,col].place(offset=[xoffset, tempy], - mirror=dir_key) - yoffset += self.cell.height - xoffset += self.cell.width + self.place_array("bit_r{0}_c{1}") self.add_layout_pins() @@ -72,41 +48,13 @@ class bitcell_array(design.design): self.DRC_LVS() - def add_pins(self): - row_list = self.cell.get_all_wl_names() - column_list = self.cell.get_all_bitline_names() - for col in range(self.column_size): - for cell_column in column_list: - self.add_pin(cell_column+"_{0}".format(col), "INOUT") - for row in range(self.row_size): - for cell_row in row_list: - self.add_pin(cell_row+"_{0}".format(row), "INPUT") - self.add_pin("vdd", "POWER") - self.add_pin("gnd", "GROUND") def add_modules(self): """ Add the modules used in this design """ self.cell = factory.create(module_type="bitcell") self.add_mod(self.cell) - def get_bitcell_pins(self, col, row): - """ Creates a list of connections in the bitcell, - indexed by column and row, for instance use in bitcell_array """ - - bitcell_pins = [] - - pin_names = self.cell.get_all_bitline_names() - for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(col)) - pin_names = self.cell.get_all_wl_names() - for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(row)) - bitcell_pins.append("vdd") - bitcell_pins.append("gnd") - - return bitcell_pins - def create_instances(self): """ Create the module instances used in this design """ self.cell_inst = {} @@ -117,37 +65,6 @@ class bitcell_array(design.design): mod=self.cell) self.connect_inst(self.get_bitcell_pins(col, row)) - def add_layout_pins(self): - """ Add the layout pins """ - - row_list = self.cell.get_all_wl_names() - column_list = self.cell.get_all_bitline_names() - - for col in range(self.column_size): - for cell_column in column_list: - bl_pin = self.cell_inst[0,col].get_pin(cell_column) - self.add_layout_pin(text=cell_column+"_{0}".format(col), - layer=bl_pin.layer, - offset=bl_pin.ll().scale(1,0), - width=bl_pin.width(), - height=self.height) - - for row in range(self.row_size): - for cell_row in row_list: - wl_pin = self.cell_inst[row,0].get_pin(cell_row) - self.add_layout_pin(text=cell_row+"_{0}".format(row), - layer=wl_pin.layer, - offset=wl_pin.ll().scale(0,1), - width=self.width, - height=wl_pin.height()) - - # For every second row and column, add a via for gnd and vdd - for row in range(self.row_size): - for col in range(self.column_size): - inst = self.cell_inst[row,col] - for pin_name in ["vdd", "gnd"]: - for pin in inst.get_pins(pin_name): - self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer) def analytical_power(self, corner, load): """Power of Bitcell array and bitline in nW.""" diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 1e5a2121..88717b56 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -5,23 +5,19 @@ # import debug import design +from base_array import bitcell_base_array from tech import drc import contact from sram_factory import factory from vector import vector from globals import OPTS -class dummy_array(design.design): +class dummy_array(bitcell_base_array): """ Generate a dummy row/column for the replica array. """ def __init__(self, cols, rows, mirror=0, name=""): - design.design.__init__(self, name) - debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) - self.add_comment("rows: {0} cols: {1}".format(rows, cols)) - - self.column_size = cols - self.row_size = rows + super().__init__(cols, rows, name) self.mirror = mirror self.create_netlist() @@ -37,27 +33,7 @@ class dummy_array(design.design): def create_layout(self): - # We increase it by a well enclosure so the precharges don't overlap our wells - self.height = self.row_size*self.dummy_cell.height - self.width = self.column_size*self.dummy_cell.width - - xoffset = 0.0 - for col in range(self.column_size): - yoffset = 0.0 - for row in range(self.row_size): - name = "dummy_r{0}_c{1}".format(row, col) - - if (row+self.mirror) % 2: - tempy = yoffset + self.dummy_cell.height - dir_key = "MX" - else: - tempy = yoffset - dir_key = "" - - self.cell_inst[row,col].place(offset=[xoffset, tempy], - mirror=dir_key) - yoffset += self.dummy_cell.height - xoffset += self.dummy_cell.width + self.place_array("dummy_r{0}_c{1}", self.mirror) self.add_layout_pins() @@ -65,18 +41,6 @@ class dummy_array(design.design): self.DRC_LVS() - def add_pins(self): - row_list = self.cell.get_all_wl_names() - column_list = self.cell.get_all_bitline_names() - for col in range(self.column_size): - for cell_column in column_list: - self.add_pin(cell_column+"_{0}".format(col), "INOUT") - for row in range(self.row_size): - for cell_row in row_list: - self.add_pin(cell_row+"_{0}".format(row), "INPUT") - self.add_pin("vdd", "POWER") - self.add_pin("gnd", "GROUND") - def add_modules(self): """ Add the modules used in this design """ self.dummy_cell = factory.create(module_type="dummy_bitcell") @@ -84,23 +48,6 @@ class dummy_array(design.design): self.cell = factory.create(module_type="bitcell") - def get_bitcell_pins(self, col, row): - """ Creates a list of connections in the bitcell, - indexed by column and row, for instance use in bitcell_array """ - - bitcell_pins = [] - - pin_names = self.cell.get_all_bitline_names() - for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(col)) - pin_names = self.cell.get_all_wl_names() - for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(row)) - bitcell_pins.append("vdd") - bitcell_pins.append("gnd") - - return bitcell_pins - def create_instances(self): """ Create the module instances used in this design """ @@ -111,39 +58,6 @@ class dummy_array(design.design): self.cell_inst[row,col]=self.add_inst(name=name, mod=self.dummy_cell) self.connect_inst(self.get_bitcell_pins(col, row)) - - def add_layout_pins(self): - """ Add the layout pins """ - - row_list = self.cell.get_all_wl_names() - column_list = self.cell.get_all_bitline_names() - - for col in range(self.column_size): - for cell_column in column_list: - bl_pin = self.cell_inst[0,col].get_pin(cell_column) - self.add_layout_pin(text=cell_column+"_{0}".format(col), - layer="m2", - offset=bl_pin.ll(), - width=bl_pin.width(), - height=self.height) - - for row in range(self.row_size): - for cell_row in row_list: - wl_pin = self.cell_inst[row,0].get_pin(cell_row) - self.add_layout_pin(text=cell_row+"_{0}".format(row), - layer="m1", - offset=wl_pin.ll(), - width=self.width, - height=wl_pin.height()) - - # For every second row and column, add a via for gnd and vdd - for row in range(self.row_size): - for col in range(self.column_size): - inst = self.cell_inst[row,col] - for pin_name in ["vdd", "gnd"]: - for pin in inst.get_pins(pin_name): - self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer) - def input_load(self): wl_wire = self.gen_wl_wire() From 988df8ebb919d1147b7c09901db32fe73c7e9d89 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Tue, 28 Jan 2020 11:47:32 +0100 Subject: [PATCH 112/521] hierarchy_layout: Add methods to create via stacks this allows us to simplify add_power_pin() and gives a clean API to create vias through multiple layers. Signed-off-by: Bastian Koppelmann --- compiler/base/hierarchy_layout.py | 81 +++++++++++++++++++++++++++---- 1 file changed, 71 insertions(+), 10 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index a1b18ef3..4dedd9a9 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -11,6 +11,7 @@ import gdsMill import debug from tech import drc, GDS from tech import layer as techlayer +from tech import layer_stacks import os from globals import OPTS from vector import vector @@ -508,6 +509,71 @@ class layout(): # We don't model the logical connectivity of wires/paths self.connect_inst([]) return inst + + def add_via_stack(self, offset, direction, from_layer, to_layer, + size=[1,1]): + """ + Punch a stack of vias from a start layer to a target layer. + """ + + return self.__add_via_stack_internal(offset=offset, + direction=direction, + from_layer=from_layer, + to_layer=to_layer, + via_func=self.add_via, + last_via=None, + size=size) + + def add_via_stack_center(self, offset, direction, from_layer, to_layer, + size=[1,1]): + """ + Punch a stack of vias from a start layer to a target layer by the center + coordinate accounting for mirroring and rotation. + """ + return self.__add_via_stack_internal(offset=offset, + direction=direction, + from_layer=from_layer, + to_layer=to_layer, + via_func=self.add_via_center, + last_via=None, + size=size) + + + def __add_via_stack_internal(self, offset, direction, from_layer, to_layer, + via_func, last_via, size): + """ + Punch a stack of vias from a start layer to a target layer. Here we + figure out whether to punch it up or down the stack. + """ + + if from_layer == to_layer: + return last_via + + from_id = int(from_layer[1]) + to_id = int(to_layer[1]) + + if from_id < to_id: # grow the stack up + search_id = 0 + next_id = 2 + else: # grow the stack down + search_id = 2 + next_id = 0 + + curr_stack = next(filter(lambda stack: stack[search_id] == from_layer, layer_stacks), None) + if curr_stack is None: + raise ValueError("Cannot create via from '{0}' to '{1}'." \ + "Layer '{0}' not defined" + .format(from_layer, to_layer)) + + via = via_func(layers=curr_stack, size=size, offset=offset, directions=direction) + return self.__add_via_stack_internal(offset=offset, + direction=direction, + from_layer=curr_stack[next_id], + to_layer=to_layer, + via_func=via_func, + last_via=via, + size=size) + def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"): """Adds a ptx module to the design.""" @@ -1131,17 +1197,12 @@ class layout(): else: direction = ("H", "H") - if start_layer == "m1": - self.add_via_center(layers=self.m1_stack, - size=size, - offset=loc, - directions=direction) + via = self.add_via_stack_center(from_layer=start_layer, + to_layer="m3", + size=size, + offset=loc, + direction=direction) - if start_layer == "m1" or start_layer == "m2": - via = self.add_via_center(layers=self.m2_stack, - size=size, - offset=loc, - directions=direction) if start_layer == "m3": self.add_layout_pin_rect_center(text=name, layer="m3", From 90a4a72bba2b50cb1cf1d79b79d78b450b01ba13 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 23 Dec 2019 16:37:16 +0100 Subject: [PATCH 113/521] modules: Use add_power_pin API for all modules sense_amp_array, write_driver_array, and single_column_mux were the only offenders. Signed-off-by: Bastian Koppelmann --- compiler/modules/sense_amp_array.py | 21 +++++++++------------ compiler/modules/write_driver_array.py | 11 ++++------- compiler/pgates/single_level_column_mux.py | 12 ++++-------- 3 files changed, 17 insertions(+), 27 deletions(-) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 2447e4b8..ca5afc47 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -98,18 +98,15 @@ class sense_amp_array(design.design): for i in range(len(self.local_insts)): inst = self.local_insts[i] - gnd_pos = inst.get_pin("gnd").center() - self.add_via_center(layers=self.m2_stack, - offset=gnd_pos) - self.add_layout_pin_rect_center(text="gnd", - layer="m3", - offset=gnd_pos) - vdd_pos = inst.get_pin("vdd").center() - self.add_via_center(layers=self.m2_stack, - offset=vdd_pos) - self.add_layout_pin_rect_center(text="vdd", - layer="m3", - offset=vdd_pos) + self.add_power_pin(name = "gnd", + loc = inst.get_pin("gnd").center(), + start_layer="m2", + vertical=True) + + self.add_power_pin(name = "vdd", + loc = inst.get_pin("vdd").center(), + start_layer="m2", + vertical=True) bl_pin = inst.get_pin("bl") br_pin = inst.get_pin("br") diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index ac4dab00..900a8294 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -141,13 +141,10 @@ class write_driver_array(design.design): for n in ["vdd", "gnd"]: pin_list = self.driver_insts[i].get_pins(n) for pin in pin_list: - pin_pos = pin.center() - # Add the M2->M3 stack - self.add_via_center(layers=self.m2_stack, - offset=pin_pos) - self.add_layout_pin_rect_center(text=n, - layer="m3", - offset=pin_pos) + self.add_power_pin(name = n, + loc = pin.center(), + vertical=True, + start_layer = "m2") if self.write_size: for bit in range(self.num_wmasks): en_pin = self.driver_insts[bit*self.write_size].get_pin("en") diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 18b4b10f..66faf1da 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -180,14 +180,10 @@ class single_level_column_mux(pgate.pgate): implant_type="p", well_type="p") - # Add the M1->M2->M3 stack - self.add_via_center(layers=self.m1_stack, - offset=active_pos) - self.add_via_center(layers=self.m2_stack, - offset=active_pos) - self.add_layout_pin_rect_center(text="gnd", - layer="m3", - offset=active_pos) + # Add the M1->..->power_grid_layer stack + self.add_power_pin(name = "gnd", + loc = active_pos, + start_layer="m1") # Add well enclosure over all the tx and contact self.add_rect(layer="pwell", From 9749c522d1cc0e5003f9fc8a80dcf4601d368b18 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Tue, 28 Jan 2020 11:53:36 +0100 Subject: [PATCH 114/521] tech: Make power_grid configurable this is the first step to allow engineers, porting technologies, more room for routing their handmade cells. For now, we don't allow the specification of power_grids where the lower layer prefers to be routed vertically. This is due to the router not connecting some pins properly in that case. Signed-off-by: Bastian Koppelmann --- compiler/base/hierarchy_layout.py | 27 ++++++++++++++++++--------- compiler/router/router_tech.py | 17 +++++++++++++++-- compiler/sram/sram_base.py | 21 ++++++++++++++------- 3 files changed, 47 insertions(+), 18 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 4dedd9a9..451d1356 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -39,6 +39,12 @@ class layout(): self.visited = [] # List of modules we have already visited self.is_library_cell = False # Flag for library cells self.gds_read() + try: + from tech import power_grid + self.pwr_grid_layer = power_grid[0] + except ImportError: + self.pwr_grid_layer = "m3" + ############################################################ # GDS layout @@ -1169,12 +1175,12 @@ class layout(): def copy_power_pins(self, inst, name): """ - This will copy a power pin if it is on M3. + This will copy a power pin if it is on the lowest power_grid layer. If it is on M1, it will add a power via too. """ pins = inst.get_pins(name) for pin in pins: - if pin.layer == "m3": + if pin.layer == self.pwr_grid_layer: self.add_layout_pin(name, pin.layer, pin.ll(), @@ -1183,14 +1189,17 @@ class layout(): elif pin.layer == "m1": self.add_power_pin(name, pin.center()) else: - debug.warning("{0} pins of {1} should be on metal3 or metal1 for supply router.".format(name,inst.name)) + debug.warning("{0} pins of {1} should be on {2} or metal1 for "\ + "supply router." + .format(name,inst.name,self.pwr_grid_layer)) def add_power_pin(self, name, loc, size=[1, 1], vertical=False, start_layer="m1"): """ - Add a single power pin from M3 down to M1 at the given center location. - The starting layer is specified to determine which vias are needed. + Add a single power pin from the lowest power_grid layer down to M1 at + the given center location. The starting layer is specified to determine + which vias are needed. """ if vertical: direction = ("V", "V") @@ -1198,18 +1207,18 @@ class layout(): direction = ("H", "H") via = self.add_via_stack_center(from_layer=start_layer, - to_layer="m3", + to_layer=self.pwr_grid_layer, size=size, offset=loc, direction=direction) - if start_layer == "m3": + if start_layer == self.pwr_grid_layer: self.add_layout_pin_rect_center(text=name, - layer="m3", + layer=self.pwr_grid_layer, offset=loc) else: self.add_layout_pin_rect_center(text=name, - layer="m3", + layer=self.pwr_grid_layer, offset=loc, width=via.width, height=via.height) diff --git a/compiler/router/router_tech.py b/compiler/router/router_tech.py index efae2708..e0f277e9 100644 --- a/compiler/router/router_tech.py +++ b/compiler/router/router_tech.py @@ -5,7 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from tech import drc, layer +from tech import drc, layer, preferred_directions from contact import contact from vector import vector import debug @@ -26,6 +26,9 @@ class router_tech: self.rail_track_width = rail_track_width if len(self.layers) == 1: + if preferred_directions[self.layers[0]] != "H": + debug.warning("Using '{}' for horizontal routing, but it " \ + "prefers vertical routing".format(self.layers[0])) self.horiz_layer_name = self.vert_layer_name = self.layers[0] self.horiz_lpp = self.vert_lpp = layer[self.layers[0]] @@ -35,7 +38,17 @@ class router_tech: self.horiz_track_width = self.horiz_layer_minwidth + self.horiz_layer_spacing self.vert_track_width = self.vert_layer_minwidth + self.vert_layer_spacing else: - (self.horiz_layer_name, self.via_layer_name, self.vert_layer_name) = self.layers + (try_horiz_layer, self.via_layer_name, try_vert_layer) = self.layers + + # figure out wich of the two layers prefers horizontal/vertical + # routing + if preferred_directions[try_horiz_layer] == "H" and preferred_directions[try_vert_layer] == "V": + self.horiz_layer_name = try_horiz_layer + self.vert_layer_name = try_vert_layer + else: + raise ValueError("Layer '{}' and '{}' are using the wrong " \ + "preferred_directions '{}' and '{}'. Only "\ + "('H', 'V') are supported") via_connect = contact(self.layers, (1, 1)) max_via_size = max(via_connect.width,via_connect.height) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 65297889..c7c91e90 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -148,14 +148,21 @@ class sram_base(design, verilog, lef): if not OPTS.route_supplies: # Do not route the power supply (leave as must-connect pins) return - elif "m4" in tech.layer: - # Route a M3/M4 grid - from supply_grid_router import supply_grid_router as router - rtr=router(self.m3_stack, self) - elif "m3" in tech.layer: - from supply_tree_router import supply_tree_router as router - rtr=router(("m3",), self) + grid_stack = set() + try: + from tech import power_grid + grid_stack = power_grid + except ImportError: + # if no power_grid is specified by tech we use sensible defaults + if "m4" in tech.layer: + # Route a M3/M4 grid + grid_stack = self.m3_stack + elif "m3" in tech.layer: + grid_stack =("m3",) + + from supply_grid_router import supply_grid_router as router + rtr=router(grid_stack, self) rtr.route() From 407bd026ee0a3ef64c53bb01c689fe4cf07185db Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 23 Dec 2019 17:36:57 +0100 Subject: [PATCH 115/521] tech: Make m3_stack the power_grid stack for FreePDK45/scn4m explicitly stating the power_grid makes people porting a new technology aware of this option. Signed-off-by: Bastian Koppelmann --- technology/freepdk45/tech/tech.py | 5 +++++ technology/scn4m_subm/tech/tech.py | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 8b769af9..00ab4b9b 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -71,6 +71,11 @@ preferred_directions = {"poly": "V", "m2": "V", "m3": "H", "m4": "V"} +################################################### +# Power grid +################################################### +# Use M3/M4 +power_grid = m3_stack ################################################### # GDS Layer Map diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 3000dc99..87c1d830 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -71,6 +71,12 @@ preferred_directions = {"poly": "V", "m3": "H", "m4": "V"} +################################################### +# Power grid +################################################### +# Use M3/M4 +power_grid = m3_stack + ################################################### ##GDS Layer Map ################################################### From df9f351a915d1af4bb77322c98514dbc5a59b5f1 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Tue, 28 Jan 2020 11:03:08 +0100 Subject: [PATCH 116/521] Add custom cell properties to technologies this is technology specific database to store data about the custom design cells. For now it only contains on which axis the bitcells are mirrored. This is a first step to support thin cells that need to be mirrored on the x and y axis. Signed-off-by: Bastian Koppelmann --- compiler/modules/base_array.py | 4 ++-- compiler/modules/custom_cell_properties.py | 28 ++++++++++++++++++++++ compiler/modules/replica_column.py | 4 ++-- technology/freepdk45/tech/tech.py | 7 ++++++ technology/scn3me_subm/tech/tech.py | 8 +++++++ technology/scn4m_subm/tech/tech.py | 7 ++++++ 6 files changed, 54 insertions(+), 4 deletions(-) create mode 100644 compiler/modules/custom_cell_properties.py diff --git a/compiler/modules/base_array.py b/compiler/modules/base_array.py index db2b1be6..40481c59 100644 --- a/compiler/modules/base_array.py +++ b/compiler/modules/base_array.py @@ -7,6 +7,7 @@ # import debug import design +from tech import cell_properties class bitcell_base_array(design.design): """ @@ -93,8 +94,7 @@ class bitcell_base_array(design.design): yoffset = 0.0 for row in range(self.row_size): name = name_template.format(row, col) - - if (row + row_offset) % 2: + if cell_properties.bitcell.mirror.x and (row + row_offset) % 2: tempy = yoffset + self.cell.height dir_key = "MX" else: diff --git a/compiler/modules/custom_cell_properties.py b/compiler/modules/custom_cell_properties.py new file mode 100644 index 00000000..085527fc --- /dev/null +++ b/compiler/modules/custom_cell_properties.py @@ -0,0 +1,28 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2020 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# + +class _MirrorAxis: + def __init__(self, x, y): + self.x = x + self.y = y + +class _Bitcell: + def __init__(self, mirror): + self.mirror = mirror + +class CellProperties(): + """ + TODO + """ + def __init__(self): + self.names = {} + self._bitcell = _Bitcell(_MirrorAxis(True, False)) + + @property + def bitcell(self): + return self._bitcell diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 5552ed55..283787c2 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -92,7 +92,7 @@ class replica_column(design.design): self.connect_inst(self.get_bitcell_pins(0, row)) def place_instances(self): - + from tech import cell_properties # Flip the mirrors if we have an odd number of replica+dummy rows at the bottom # so that we will start with mirroring rather than not mirroring rbl_offset = (self.left_rbl+1)%2 @@ -100,7 +100,7 @@ class replica_column(design.design): for row in range(self.total_size): name = "bit_r{0}_{1}".format(row,"rbl") offset = vector(0,self.cell.height*(row+(row+rbl_offset)%2)) - if (row+rbl_offset)%2: + if cell_properties.bitcell.mirror.x and (row+rbl_offset)%2: dir_key = "MX" else: dir_key = "R0" diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 8b769af9..c21b1f97 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -8,6 +8,7 @@ import os from design_rules import * from module_type import * +from custom_cell_properties import CellProperties """ File containing the process technology parameters for FreePDK 45nm. @@ -24,6 +25,12 @@ File containing the process technology parameters for FreePDK 45nm. # For example: tech_modules['contact'] = 'contact_freepdk45' tech_modules = ModuleType() +################################################### +# Custom cell properties +################################################### +cell_properties = CellProperties() +cell_properties.bitcell.mirror.x = True +cell_properties.bitcell.mirror.y = False ################################################### # GDS file info diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index cb476df5..9e6f370b 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -1,6 +1,7 @@ import os from design_rules import * from module_type import * +from custom_cell_properties import CellProperties """ File containing the process technology parameters for SCMOS 3me, subm, 180nm. @@ -12,6 +13,13 @@ File containing the process technology parameters for SCMOS 3me, subm, 180nm. # For example: tech_modules['contact'] = 'contact_scn3me' tech_modules = ModuleType() +################################################### +# Custom cell properties +################################################### +cell_properties = CellProperties() +cell_properties.bitcell.mirror.x = True +cell_properties.bitcell.mirror.y = False + #GDS file info GDS={} # gds units diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 3000dc99..ce89e5af 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -8,6 +8,7 @@ import os from design_rules import * from module_type import * +from custom_cell_properties import CellProperties """ File containing the process technology parameters for SCMOS 4m, 0.35um @@ -24,6 +25,12 @@ File containing the process technology parameters for SCMOS 4m, 0.35um # For example: tech_modules['contact'] = 'contact_scn4m' tech_modules = ModuleType() +################################################### +# Custom cell properties +################################################### +cell_properties = CellProperties() +cell_properties.bitcell.mirror.x = True +cell_properties.bitcell.mirror.y = False ################################################### # GDS file info From dd1afe03133d70254711574152ff519e8a8f67a6 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 27 Jan 2020 17:17:06 +0100 Subject: [PATCH 117/521] Bitcell arrays: Allow mirroring on the y axis this allows for bitcells that need to be mirrored on the y axis, like thin cells. However, the portdata elements also need to be mirrored on the y axis. Otherwise the router will fail horribly when connecting bitlines. Signed-off-by: Bastian Koppelmann --- compiler/modules/base_array.py | 34 +++++++++++++++++---- compiler/modules/bitcell_array.py | 4 +-- compiler/modules/dummy_array.py | 4 +-- compiler/modules/replica_bitcell_array.py | 36 ++++++++++++++++++----- compiler/modules/replica_column.py | 27 ++++++++++++++--- 5 files changed, 84 insertions(+), 21 deletions(-) diff --git a/compiler/modules/base_array.py b/compiler/modules/base_array.py index 40481c59..08a52c21 100644 --- a/compiler/modules/base_array.py +++ b/compiler/modules/base_array.py @@ -13,13 +13,14 @@ class bitcell_base_array(design.design): """ Abstract base class for bitcell-arrays -- bitcell, dummy """ - def __init__(self, cols, rows, name): + def __init__(self, cols, rows, name, column_offset): design.design.__init__(self, name) debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) self.add_comment("rows: {0} cols: {1}".format(rows, cols)) self.column_size = cols self.row_size = rows + self.column_offset = column_offset def add_pins(self): row_list = self.cell.get_all_wl_names() @@ -82,6 +83,23 @@ class bitcell_base_array(design.design): for pin in inst.get_pins(pin_name): self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer) + def _adjust_x_offset(self, xoffset, col, col_offset): + tempx = xoffset + dir_y = False + # If we mirror the current cell on the y axis adjust the x position + if cell_properties.bitcell.mirror.y and (col + col_offset) % 2: + tempx = xoffset + self.cell.width + dir_y = True + return (tempx, dir_y) + + def _adjust_y_offset(self, yoffset, row, row_offset): + tempy = yoffset + dir_x = False + # If we mirror the current cell on the x axis adjust the y position + if cell_properties.bitcell.mirror.x and (row + row_offset) % 2: + tempy = yoffset + self.cell.height + dir_x = True + return (tempy, dir_x) def place_array(self, name_template, row_offset=0): @@ -92,16 +110,22 @@ class bitcell_base_array(design.design): xoffset = 0.0 for col in range(self.column_size): yoffset = 0.0 + tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset) + for row in range(self.row_size): name = name_template.format(row, col) - if cell_properties.bitcell.mirror.x and (row + row_offset) % 2: - tempy = yoffset + self.cell.height + tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset) + + if dir_x and dir_y: + dir_key = "XY" + elif dir_x: dir_key = "MX" + elif dir_y: + dir_key = "MY" else: - tempy = yoffset dir_key = "" - self.cell_inst[row,col].place(offset=[xoffset, tempy], + self.cell_inst[row,col].place(offset=[tempx, tempy], mirror=dir_key) yoffset += self.cell.height xoffset += self.cell.width diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 4c1c798b..636408df 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -20,8 +20,8 @@ class bitcell_array(bitcell_base_array): and word line is connected by abutment. Connects the word lines and bit lines. """ - def __init__(self, cols, rows, name): - super().__init__(cols, rows, name) + def __init__(self, cols, rows, name, column_offset=0): + super().__init__(cols, rows, name, column_offset) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 88717b56..997330e1 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -16,8 +16,8 @@ class dummy_array(bitcell_base_array): """ Generate a dummy row/column for the replica array. """ - def __init__(self, cols, rows, mirror=0, name=""): - super().__init__(cols, rows, name) + def __init__(self, cols, rows, column_offset=0, mirror=0, name=""): + super().__init__(cols, rows, name, column_offset) self.mirror = mirror self.create_netlist() diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 74962ba2..9cf5c5a2 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -86,6 +86,7 @@ class replica_bitcell_array(design.design): # Bitcell array self.bitcell_array = factory.create(module_type="bitcell_array", + column_offset=1 + self.left_rbl, cols=self.column_size, rows=self.row_size) self.add_mod(self.bitcell_array) @@ -95,12 +96,17 @@ class replica_bitcell_array(design.design): for bit in range(self.left_rbl+self.right_rbl): if bit=self.total_size-right_rbl-1, @@ -96,14 +98,31 @@ class replica_column(design.design): # Flip the mirrors if we have an odd number of replica+dummy rows at the bottom # so that we will start with mirroring rather than not mirroring rbl_offset = (self.left_rbl+1)%2 - + + # if our bitcells are mirrored on the y axis, check if we are in global + # column that needs to be flipped. + dir_y = False + xoffset = 0 + if cell_properties.bitcell.mirror.y and self.column_offset % 2: + dir_y = True + xoffset = self.replica_cell.width + for row in range(self.total_size): + dir_x = False name = "bit_r{0}_{1}".format(row,"rbl") - offset = vector(0,self.cell.height*(row+(row+rbl_offset)%2)) if cell_properties.bitcell.mirror.x and (row+rbl_offset)%2: + dir_x = True + + offset = vector(xoffset,self.cell.height*(row+(row+rbl_offset)%2)) + + if dir_x and dir_y: + dir_key = "XY" + elif dir_x: dir_key = "MX" + elif dir_y: + dir_key = "MY" else: - dir_key = "R0" + dir_key = "" self.cell_inst[row].place(offset=offset, mirror=dir_key) From ed66fca031d0af78883b0348e845dac20e1e0b25 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 27 Jan 2020 17:20:48 +0100 Subject: [PATCH 118/521] write_driver/sense_amp/precharge arrays: Allow y axis mirroring since the bitlines alternate in the bitcell array we also need to mirror the port_data elements. Signed-off-by: Bastian Koppelmann --- compiler/modules/precharge_array.py | 14 ++++++++++++-- compiler/modules/sense_amp_array.py | 19 ++++++++++++++++--- compiler/modules/write_driver_array.py | 13 +++++++++++-- 3 files changed, 39 insertions(+), 7 deletions(-) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index c2617f50..54ed2690 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -107,9 +107,19 @@ class precharge_array(design.design): def place_insts(self): """ Places precharge array by horizontally tiling the precharge cell""" + from tech import cell_properties + xoffset = 0 for i in range(self.columns): - offset = vector(self.pc_cell.width * i, 0) - self.local_insts[i].place(offset) + tempx = xoffset + if cell_properties.bitcell.mirror.y and (i + 1) % 2: + mirror = "MY" + tempx = tempx + self.pc_cell.width + else: + mirror = "" + + offset = vector(tempx, 0) + self.local_insts[i].place(offset=offset, mirror=mirror) + xoffset = xoffset + self.pc_cell.width def get_en_cin(self): """Get the relative capacitance of all the clk connections in the precharge array""" diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 2447e4b8..fcb68792 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -84,14 +84,27 @@ class sense_amp_array(design.design): "en", "vdd", "gnd"]) def place_sense_amp_array(self): - + from tech import cell_properties if self.bitcell.width > self.amp.width: amp_spacing = self.bitcell.width * self.words_per_row else: amp_spacing = self.amp.width * self.words_per_row + for i in range(0,self.word_size): - amp_position = vector(amp_spacing * i, 0) - self.local_insts[i].place(amp_position) + xoffset = amp_spacing * i + + # align the xoffset to the grid of bitcells. This way we + # know when to do the mirroring. + grid_x = int(xoffset / self.amp.width) + + if cell_properties.bitcell.mirror.y and grid_x % 2: + mirror = "MY" + xoffset = xoffset + self.amp.width + else: + mirror = "" + + amp_position = vector(xoffset, 0) + self.local_insts[i].place(offset=amp_position,mirror=mirror) def add_layout_pins(self): diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index ac4dab00..cac9b396 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -106,14 +106,23 @@ class write_driver_array(design.design): def place_write_array(self): + from tech import cell_properties if self.bitcell.width > self.driver.width: self.driver_spacing = self.bitcell.width else: self.driver_spacing = self.driver.width for i in range(0,self.columns,self.words_per_row): index = int(i/self.words_per_row) - base = vector(i * self.driver_spacing, 0) - self.driver_insts[index].place(base) + xoffset = i * self.driver_spacing + + if cell_properties.bitcell.mirror.y and i % 2: + mirror = "MY" + xoffset = xoffset + self.driver.width + else: + mirror = "" + + base = vector(xoffset, 0) + self.driver_insts[index].place(offset=base, mirror=mirror) def add_layout_pins(self): From b5701af8645118aefb58195079d57379dd72d664 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 27 Jan 2020 17:23:01 +0100 Subject: [PATCH 119/521] column_mux: Allow y axis mirroring since the bitlines alternate in the bitcell array we also need to mirror the port_data elements. Signed-off-by: Bastian Koppelmann --- .../modules/single_level_column_mux_array.py | 40 +++++++++++++++---- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 09f21cfa..24510015 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -99,11 +99,19 @@ class single_level_column_mux_array(design.design): "gnd"]) def place_array(self): + from tech import cell_properties # For every column, add a pass gate for col_num in range(self.columns): + xoffset = col_num * self.mux.width + if cell_properties.bitcell.mirror.y and col_num % 2: + mirror = "MY" + xoffset = xoffset + self.mux.width + else: + mirror = "" + name = "XMUX{0}".format(col_num) - x_off = vector(col_num * self.mux.width, self.route_height) - self.mux_inst[col_num].place(x_off) + offset = vector(xoffset, self.route_height) + self.mux_inst[col_num].place(offset=offset, mirror=mirror) def add_layout_pins(self): @@ -161,6 +169,7 @@ class single_level_column_mux_array(design.design): def route_bitlines(self): """ Connect the output bit-lines to form the appropriate width mux """ + from tech import cell_properties for j in range(self.columns): bl_offset = self.mux_inst[j].get_pin("bl_out").bc() br_offset = self.mux_inst[j].get_pin("br_out").bc() @@ -171,23 +180,38 @@ class single_level_column_mux_array(design.design): bl_out_offset_end = bl_out_offset + vector(0,self.route_height) br_out_offset_end = br_out_offset + vector(0,self.route_height) + if cell_properties.bitcell.mirror.y and j % 2: + tmp_bl_out_end = br_out_offset_end + tmp_br_out_end = bl_out_offset_end + else: + tmp_bl_out_end = bl_out_offset_end + tmp_br_out_end = br_out_offset_end + if (j % self.words_per_row) == 0: # Create the metal1 to connect the n-way mux output from the pass gate # These will be located below the select lines. Yes, these are M2 width # to ensure vias are enclosed and M1 min width rules. width = self.m2_width + self.mux.width * (self.words_per_row - 1) - self.add_path("m1", [bl_out_offset, bl_out_offset+vector(width,0)]) - self.add_path("m1", [br_out_offset, br_out_offset+vector(width,0)]) + + if cell_properties.bitcell.mirror.y and (j % 2) == 0: + bl = self.mux.get_pin("bl") + br = self.mux.get_pin("br") + dist = abs(bl.ll().x - br.ll().x) + else: + dist = 0 + + self.add_path("m1", [bl_out_offset, bl_out_offset+vector(width+dist,0)]) + self.add_path("m1", [br_out_offset, br_out_offset+vector(width-dist,0)]) # Extend the bitline output rails and gnd downward on the first bit of each n-way mux self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j/self.words_per_row)), layer="m2", start=bl_out_offset, - end=bl_out_offset_end) + end=tmp_bl_out_end) self.add_layout_pin_segment_center(text="br_out_{}".format(int(j/self.words_per_row)), layer="m2", start=br_out_offset, - end=br_out_offset_end) + end=tmp_br_out_end) # This via is on the right of the wire @@ -200,8 +224,8 @@ class single_level_column_mux_array(design.design): else: - self.add_path("m2", [ bl_out_offset, bl_out_offset_end]) - self.add_path("m2", [ br_out_offset, br_out_offset_end]) + self.add_path("m2", [ bl_out_offset, tmp_bl_out_end]) + self.add_path("m2", [ br_out_offset, tmp_br_out_end]) # This via is on the right of the wire self.add_via_center(layers=self.m1_stack, From 79391b84da278637106cd04843e4747fb5aa4889 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 30 Jan 2020 01:45:33 +0000 Subject: [PATCH 120/521] Cleanup and rename vias. --- compiler/base/contact.py | 12 +++++-- compiler/base/design.py | 6 +++- compiler/bitcells/bitcell.py | 17 ++++++++-- .../custom_cell_properties.py | 12 ++++--- compiler/bitcells/pbitcell.py | 34 +++++++++---------- compiler/modules/bank_select.py | 2 +- compiler/modules/bitcell_array.py | 16 +++------ .../{base_array.py => bitcell_base_array.py} | 0 compiler/modules/hierarchical_predecode.py | 2 +- compiler/modules/module_type.py | 2 +- compiler/modules/multibank.py | 4 +-- compiler/modules/wordline_driver.py | 4 +-- compiler/pgates/pgate.py | 10 +++--- compiler/pgates/pinv.py | 7 ++-- compiler/pgates/pnand2.py | 14 ++++---- compiler/pgates/pnand3.py | 8 ++--- compiler/pgates/pnor2.py | 12 +++---- compiler/pgates/precharge.py | 6 ++-- compiler/pgates/ptristate_inv.py | 6 ++-- compiler/sram/sram_1bank.py | 6 ++-- technology/freepdk45/tech/tech.py | 7 ++-- technology/scn4m_subm/tech/tech.py | 6 ++-- 22 files changed, 106 insertions(+), 87 deletions(-) rename compiler/{modules => bitcells}/custom_cell_properties.py (66%) rename compiler/modules/{base_array.py => bitcell_base_array.py} (100%) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 1a5785aa..51efc498 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -36,6 +36,7 @@ class contact(hierarchy_design.hierarchy_design): hierarchy_design.hierarchy_design.__init__(self, name) debug.info(4, "create contact object {0}".format(name)) + self.add_comment("layers: {0}".format(layer_stack)) self.add_comment("dimensions: {0}".format(dimensions)) if implant_type or well_type: @@ -243,14 +244,19 @@ class contact(hierarchy_design.hierarchy_design): """ Get total power of a module """ return self.return_power() - + # Set up a static for each layer to be used for measurements for layer_stack in tech.layer_stacks: (layer1, via, layer2) = layer_stack cont = factory.create(module_type="contact", layer_stack=layer_stack) module = sys.modules[__name__] - # Create the contact as just the concat of the layer names - setattr(module, layer1 + layer2, cont) + # Also create a contact that is just the first layer + if layer1 == "poly" or layer1 == "active": + setattr(module, layer1 + "_contact", cont) + else: + setattr(module, layer1 + "_via", cont) + + diff --git a/compiler/base/design.py b/compiler/base/design.py index 9b595b5f..9db68877 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -61,8 +61,12 @@ class design(hierarchy_design): """ (layer1, via, layer2) = layer_stack - contact1 = getattr(contact, layer1 + layer2) + if layer1 == "poly" or layer1 == "active": + contact1 = getattr(contact, layer1 + "_contact") + else: + contact1 = getattr(contact, layer1 + "_via") max_contact = max(contact1.width, contact1.height) + layer1_space = getattr(self, layer1 + "_space") layer2_space = getattr(self, layer2 + "_space") pitch = max_contact + max(layer1_space, layer2_space) diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index b22c9a46..5b552832 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -7,7 +7,8 @@ # import debug import utils -from tech import GDS, layer +from tech import GDS, layer, parameter +from tech import cell_properties import bitcell_base @@ -19,7 +20,14 @@ class bitcell(bitcell_base.bitcell_base): library. """ - pin_names = ["bl", "br", "wl", "vdd", "gnd"] + # If we have a split WL bitcell, if not be backwards + # compatible in the tech file + + if cell_properties.bitcell.split_wl: + pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] + else: + pin_names = ["bl", "br", "wl", "vdd", "gnd"] + storage_nets = ['Q', 'Qbar'] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] (width, height) = utils.get_libcell_size("cell_6t", @@ -40,7 +48,10 @@ class bitcell(bitcell_base.bitcell_base): def get_all_wl_names(self): """ Creates a list of all wordline pin names """ - row_pins = ["wl"] + if cell_properties.bitcell.split_wl: + row_pins = ["wl0", "wl1"] + else: + row_pins = ["wl"] return row_pins def get_all_bitline_names(self): diff --git a/compiler/modules/custom_cell_properties.py b/compiler/bitcells/custom_cell_properties.py similarity index 66% rename from compiler/modules/custom_cell_properties.py rename to compiler/bitcells/custom_cell_properties.py index 085527fc..e795f6d7 100644 --- a/compiler/modules/custom_cell_properties.py +++ b/compiler/bitcells/custom_cell_properties.py @@ -6,22 +6,24 @@ # All rights reserved. # -class _MirrorAxis: +class _mirror_axis: def __init__(self, x, y): self.x = x self.y = y -class _Bitcell: - def __init__(self, mirror): +class _bitcell: + def __init__(self, mirror, split_wl): self.mirror = mirror + self.split_wl = split_wl -class CellProperties(): +class cell_properties(): """ TODO """ def __init__(self): self.names = {} - self._bitcell = _Bitcell(_MirrorAxis(True, False)) + self._bitcell = _bitcell(mirror = _mirror_axis(True, False), + split_wl = False) @property def bitcell(self): diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 4f19c489..61bd9710 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -212,20 +212,20 @@ class pbitcell(bitcell_base.bitcell_base): # y-offset for the access transistor's gate contact self.gate_contact_yoffset = max_contact_extension + self.m2_space \ - + 0.5 * max(contact.polym1.height, contact.m1m2.height) + + 0.5 * max(contact.poly_contact.height, contact.m1_via.height) # y-position of access transistors - self.port_ypos = self.m1_space + 0.5 * contact.m1m2.height + self.gate_contact_yoffset + self.port_ypos = self.m1_space + 0.5 * contact.m1_via.height + self.gate_contact_yoffset # y-position of inverter nmos self.inverter_nmos_ypos = self.port_ypos # spacing between ports (same for read/write and write ports) self.bitline_offset = -0.5 * self.readwrite_nmos.active_width \ - + 0.5 * contact.m1m2.height \ + + 0.5 * contact.m1_via.height \ + self.m2_space + self.m2_width m2_constraint = self.bitline_offset + self.m2_space \ - + 0.5 * contact.m1m2.height \ + + 0.5 * contact.m1_via.height \ - 0.5 * self.readwrite_nmos.active_width self.write_port_spacing = max(self.active_space, self.m1_space, @@ -233,7 +233,7 @@ class pbitcell(bitcell_base.bitcell_base): self.read_port_spacing = self.bitline_offset + self.m2_space # spacing between cross coupled inverters - self.inverter_to_inverter_spacing = contact.polym1.width + self.m1_space + self.inverter_to_inverter_spacing = contact.poly_contact.width + self.m1_space # calculations related to inverter connections inverter_pmos_contact_extension = 0.5 * \ @@ -242,19 +242,19 @@ class pbitcell(bitcell_base.bitcell_base): (self.inverter_nmos.active_contact.height - self.inverter_nmos.active_height) self.inverter_gap = max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + self.poly_to_contact + 2 * contact.polym1.width \ + + self.poly_to_contact + 2 * contact.poly_contact.width \ + self.m1_space + inverter_pmos_contact_extension self.cross_couple_lower_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + 0.5 * contact.polym1.width + + 0.5 * contact.poly_contact.width self.cross_couple_upper_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ + self.poly_to_contact \ - + 1.5 * contact.polym1.width + + 1.5 * contact.poly_contact.width # spacing between wordlines (and gnd) self.m1_offset = -0.5 * self.m1_width @@ -290,7 +290,7 @@ class pbitcell(bitcell_base.bitcell_base): (self.write_nmos.active_width + self.write_port_spacing) \ - self.num_r_ports * \ (self.read_port_width + self.read_port_spacing) \ - - self.bitline_offset - 0.5 * contact.m1m2.width + - self.bitline_offset - 0.5 * contact.m1_via.width self.width = -2 * self.leftmost_xpos self.height = self.topmost_ypos - self.botmost_ypos @@ -375,14 +375,14 @@ class pbitcell(bitcell_base.bitcell_base): # add contacts to connect gate poly to drain/source # metal1 (to connect Q to Q_bar) contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x \ - + 0.5 * contact.polym1.height, + + 0.5 * contact.poly_contact.height, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=contact_offset_left) contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x \ - - 0.5*contact.polym1.height, + - 0.5*contact.poly_contact.height, self.cross_couple_lower_ypos) self.add_via_center(layers=self.poly_stack, offset=contact_offset_right) @@ -824,7 +824,7 @@ class pbitcell(bitcell_base.bitcell_base): offset=port_contact_offest) self.add_path("m2", - [port_contact_offest, bl_offset], width=contact.m1m2.height) + [port_contact_offest, bl_offset], width=contact.m1_via.height) for k in range(self.total_ports): port_contact_offest = right_port_transistors[k].get_pin("D").center() @@ -836,7 +836,7 @@ class pbitcell(bitcell_base.bitcell_base): offset=port_contact_offest) self.add_path("m2", - [port_contact_offest, br_offset], width=contact.m1m2.height) + [port_contact_offest, br_offset], width=contact.m1_via.height) def route_supply(self): """ Route inverter nmos and read-access nmos to gnd. Route inverter pmos to vdd. """ @@ -853,9 +853,9 @@ class pbitcell(bitcell_base.bitcell_base): offset=position) if position.x > 0: - contact_correct = 0.5 * contact.m1m2.height + contact_correct = 0.5 * contact.m1_via.height else: - contact_correct = -0.5 * contact.m1m2.height + contact_correct = -0.5 * contact.m1_via.height supply_offset = vector(position.x + contact_correct, self.gnd_position.y) self.add_via_center(layers=self.m1_stack, @@ -921,13 +921,13 @@ class pbitcell(bitcell_base.bitcell_base): """ # add poly to metal1 contacts for gates of the inverters left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x \ - - self.poly_to_contact - 0.5*contact.polym1.width, + - self.poly_to_contact - 0.5*contact.poly_contact.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=left_storage_contact) right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \ - + self.poly_to_contact + 0.5*contact.polym1.width, + + self.poly_to_contact + 0.5*contact.poly_contact.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=right_storage_contact) diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index 0c15401e..c3307ece 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -256,7 +256,7 @@ class bank_select(design.design): # Connect the logic B input to bank_sel/bank_sel_bar - logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1m2.height,0) + logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1_via.height,0) input_pos = vector(xoffset_bank_signal, logic_pos.y) self.add_path("m2",[logic_pos, input_pos]) self.add_via_center(layers=self.m1_stack, diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 636408df..60461724 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -5,14 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -import design -from base_array import bitcell_base_array +from bitcell_base_array import bitcell_base_array from tech import drc, spice -from vector import vector from globals import OPTS from sram_factory import factory -import logical_effort + class bitcell_array(bitcell_base_array): """ @@ -29,7 +26,7 @@ class bitcell_array(bitcell_base_array): # We don't offset this because we need to align # the replica bitcell in the control logic - #self.offset_all_coordinates() + # self.offset_all_coordinates() def create_netlist(self): @@ -48,13 +45,11 @@ class bitcell_array(bitcell_base_array): self.DRC_LVS() - def add_modules(self): """ Add the modules used in this design """ self.cell = factory.create(module_type="bitcell") self.add_mod(self.cell) - def create_instances(self): """ Create the module instances used in this design """ self.cell_inst = {} @@ -65,7 +60,6 @@ class bitcell_array(bitcell_base_array): mod=self.cell) self.connect_inst(self.get_bitcell_pins(col, row)) - def analytical_power(self, corner, load): """Power of Bitcell array and bitline in nW.""" from tech import drc, parameter @@ -77,10 +71,10 @@ class bitcell_array(bitcell_base_array): freq = spice["default_event_frequency"] bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing) - #Calculate the bitcell power which currently only includes leakage + # Calculate the bitcell power which currently only includes leakage cell_power = self.cell.analytical_power(corner, load) - #Leakage power grows with entire array and bitlines. + # Leakage power grows with entire array and bitlines. total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size, cell_power.leakage * self.column_size * self.row_size) return total_power diff --git a/compiler/modules/base_array.py b/compiler/modules/bitcell_base_array.py similarity index 100% rename from compiler/modules/base_array.py rename to compiler/modules/bitcell_base_array.py diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index dec04073..78e9af7f 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -178,7 +178,7 @@ class hierarchical_predecode(design.design): # route one signal next to each vdd/gnd rail since this is # typically where the p/n devices are and there are no # pins in the nand gates. - y_offset = (num+self.number_of_inputs) * self.inv.height + contact.m1m2.width + self.m1_space + y_offset = (num+self.number_of_inputs) * self.inv.height + contact.m1_via.width + self.m1_space in_pin = "in_{}".format(num) a_pin = "A_{}".format(num) in_pos = vector(self.input_rails[in_pin].x,y_offset) diff --git a/compiler/modules/module_type.py b/compiler/modules/module_type.py index 1d8d0cba..419e6041 100644 --- a/compiler/modules/module_type.py +++ b/compiler/modules/module_type.py @@ -6,7 +6,7 @@ # All rights reserved. # -class ModuleType(): +class module_type(): """ This is a class that maps cell names to python classes implementing them. """ diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index 33076bfb..bf19954b 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -810,7 +810,7 @@ class multibank(design.design): self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) # Bring it up to M2 for M2/M3 routing self.add_via(layers=self.m1_stack, - offset=in_pin + contact.m1m2.offset, + offset=in_pin + contact.m1_via.offset, rotate=90) self.add_via(layers=self.m2_stack, offset=in_pin + self.m2m3_via_offset, @@ -823,7 +823,7 @@ class multibank(design.design): rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y) self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) self.add_via(layers=self.m1_stack, - offset=in_pin + contact.m1m2.offset, + offset=in_pin + contact.m1_via.offset, rotate=90) self.add_via(layers=self.m2_stack, offset=in_pin + self.m2m3_via_offset, diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 2af2c8c9..cac2eea5 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -177,7 +177,7 @@ class wordline_driver(design.design): up_or_down = self.m2_space if row % 2 else -self.m2_space input_offset = vector(0, b_pos.y + up_or_down) base_offset = vector(clk_offset.x, input_offset.y) - contact_offset = vector(0.5 * self.m2_width + self.m2_space + 0.5 * contact.m1m2.width, 0) + contact_offset = vector(0.5 * self.m2_width + self.m2_space + 0.5 * contact.m1_via.width, 0) mid_via_offset = base_offset + contact_offset # must under the clk line in M1 @@ -191,7 +191,7 @@ class wordline_driver(design.design): # now connect to the nand2 B self.add_path("m2", [mid_via_offset, b_pos]) - contact_offset = b_pos - vector(0.5 * contact.m1m2.height, 0) + contact_offset = b_pos - vector(0.5 * contact.m1_via.height, 0) self.add_via_center(layers=self.m1_stack, offset=contact_offset, directions=("H", "H")) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index e009d1bb..43fc1c8c 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -87,16 +87,16 @@ class pgate(design.design): left_gate_offset = vector(nmos_gate_pin.lx(), ypos) # Center is completely symmetric. - contact_width = contact.polym1.width - contact_m1_width = contact.polym1.second_layer_width - contact_m1_height = contact.polym1.second_layer_height + contact_width = contact.poly_contact.width + contact_m1_width = contact.poly_contact.second_layer_width + contact_m1_height = contact.poly_contact.second_layer_height if position == "center": contact_offset = left_gate_offset \ + vector(0.5 * self.poly_width, 0) elif position == "farleft": contact_offset = left_gate_offset \ - - vector(0.5 * contact.polym1.width, 0) + - vector(0.5 * contact.poly_contact.width, 0) elif position == "left": contact_offset = left_gate_offset \ - vector(0.5 * contact_width - 0.5 * self.poly_width, 0) @@ -120,7 +120,7 @@ class pgate(design.design): + left_gate_offset.scale(0.5, 0) self.add_rect_center(layer="poly", offset=mid_point, - height=contact.polym1.first_layer_width, + height=contact.poly_contact.first_layer_width, width=left_gate_offset.x - contact_offset.x) def extend_wells(self, middle_position): diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 8a3a8326..8da648b0 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -89,14 +89,15 @@ class pinv(pgate.pgate): # Assume we need 3 metal 1 pitches (2 power rails, one # between the tx for the drain) # plus the tx height - nmos = factory.create(module_type="ptx", tx_type="nmos") + nmos = factory.create(module_type="ptx", + tx_type="nmos") pmos = factory.create(module_type="ptx", width=drc("minwidth_tx"), tx_type="pmos") tx_height = nmos.poly_height + pmos.poly_height # rotated m1 pitch or poly to active spacing - min_channel = max(contact.polym1.width + self.m1_space, - contact.polym1.width + 2 * self.poly_to_active) + min_channel = max(contact.poly_contact.width + self.m1_space, + contact.poly_contact.width + 2 * self.poly_to_active) # This is the extra space needed to ensure DRC rules # to the active contacts diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 8d3605a2..f5abdaaa 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -85,10 +85,10 @@ class pnand2(pgate.pgate): """ Pre-compute some handy layout parameters. """ # metal spacing to allow contacts on any layer - self.input_spacing = max(self.poly_space + contact.polym1.first_layer_width, - self.m1_space + contact.m1m2.first_layer_width, - self.m2_space + contact.m2m3.first_layer_width, - self.m3_space + contact.m2m3.second_layer_width) + self.input_spacing = max(self.poly_space + contact.poly_contact.first_layer_width, + self.m1_space + contact.m1_via.first_layer_width, + self.m2_space + contact.m2_via.first_layer_width, + self.m3_space + contact.m2_via.second_layer_width) # Compute the other pmos2 location, @@ -98,7 +98,7 @@ class pnand2(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.well_width = 2 * self.pmos.active_width + contact.activem1.width \ + self.well_width = 2 * self.pmos.active_width + contact.active_contact.width \ + 2 * self.active_space \ + 2 * self.nwell_enclose_active @@ -245,8 +245,8 @@ class pnand2(pgate.pgate): self.add_layout_pin_rect_center(text="Z", layer="m1", offset=out_offset, - width=contact.m1m2.first_layer_height, - height=contact.m1m2.first_layer_width) + width=contact.m1_via.first_layer_height, + height=contact.m1_via.first_layer_width) def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index bb379db7..5c1e0db5 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -202,10 +202,10 @@ class pnand3(pgate.pgate): # wire space or wire and one contact space metal_spacing = max(self.m1_space + self.m1_width, self.m2_space + self.m2_width, - self.m1_space + 0.5 *contact.polym1.width + 0.5 * self.m1_width) + self.m1_space + 0.5 *contact.poly_contact.width + 0.5 * self.m1_width) active_spacing = max(self.m1_space, - 0.5 * contact.polym1.first_layer_width + self.poly_to_active) + 0.5 * contact.poly_contact.first_layer_width + self.poly_to_active) inputC_yoffset = self.nmos3_pos.y + self.nmos.active_height + active_spacing self.route_input_gate(self.pmos3_inst, self.nmos3_inst, @@ -256,8 +256,8 @@ class pnand3(pgate.pgate): self.add_layout_pin_rect_center(text="Z", layer="m1", offset=mid_offset, - width=contact.m1m2.first_layer_width, - height=contact.m1m2.first_layer_height) + width=contact.m1_via.first_layer_width, + height=contact.m1_via.first_layer_height) def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 9895e9d9..e28b6fc8 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -84,10 +84,10 @@ class pnor2(pgate.pgate): """ Pre-compute some handy layout parameters. """ # metal spacing to allow contacts on any layer - self.input_spacing = max(self.poly_space + contact.polym1.first_layer_width, - self.m1_space + contact.m1m2.first_layer_width, - self.m2_space + contact.m2m3.first_layer_width, - self.m3_space + contact.m2m3.second_layer_width) + self.input_spacing = max(self.poly_space + contact.poly_contact.first_layer_width, + self.m1_space + contact.m1_via.first_layer_width, + self.m2_space + contact.m2_via.first_layer_width, + self.m3_space + contact.m2_via.second_layer_width) # Compute the other pmos2 location, but determining # offset to overlap the source and drain pins @@ -234,8 +234,8 @@ class pnor2(pgate.pgate): self.add_layout_pin_rect_center(text="Z", layer="m1", offset=mid3_offset, - width=contact.m1m2.first_layer_height, - height=contact.m1m2.first_layer_width) + width=contact.m1_via.first_layer_height, + height=contact.m1_via.first_layer_width) def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index d1e2f3af..888304ce 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -121,7 +121,7 @@ class precharge(design.design): self.lower_pmos_inst.place(self.lower_pmos_position) # adds the upper pmos(s) to layout - ydiff = self.pmos.height + 2 * self.m1_space + contact.polym1.width + ydiff = self.pmos.height + 2 * self.m1_space + contact.poly_contact.width self.upper_pmos1_pos = self.lower_pmos_position + vector(0, ydiff) self.upper_pmos1_inst.place(self.upper_pmos1_pos) @@ -175,7 +175,7 @@ class precharge(design.design): # adds the contact from active to metal1 well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \ - + vector(0, self.upper_pmos1_inst.uy() + contact.activem1.height / 2 \ + + vector(0, self.upper_pmos1_inst.uy() + contact.active_contact.height / 2 \ + self.nwell_extend_active) self.add_via_center(layers=self.active_stack, offset=well_contact_pos, @@ -183,7 +183,7 @@ class precharge(design.design): well_type="n") # leave an extra pitch for the height - self.height = well_contact_pos.y + contact.activem1.height + self.m1_pitch + self.height = well_contact_pos.y + contact.active_contact.height + self.m1_pitch # nwell should span the whole design since it is pmos only self.add_rect(layer="nwell", diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index 764b87c0..9586e72b 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -79,7 +79,7 @@ class ptristate_inv(pgate.pgate): # Height is an input parameter, so it is not recomputed. # Make sure we can put a well above and below - self.top_bottom_space = max(contact.activem1.width, contact.activem1.height) + self.top_bottom_space = max(contact.active_contact.width, contact.active_contact.height) def add_ptx(self): """ Create the PMOS and NMOS transistors. """ @@ -135,8 +135,8 @@ class ptristate_inv(pgate.pgate): """ pmos_yoff = self.height - self.pmos.active_height \ - - self.top_bottom_space - 0.5 * contact.activem1.height - nmos_yoff = self.top_bottom_space + 0.5 * contact.activem1.height + - self.top_bottom_space - 0.5 * contact.active_contact.height + nmos_yoff = self.top_bottom_space + 0.5 * contact.active_contact.height # Tristate transistors pmos1_pos = vector(self.pmos.active_offset.x, pmos_yoff) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 151c8a70..93247fc1 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -17,7 +17,7 @@ from globals import OPTS, print_time from sram_base import sram_base from bank import bank -from contact import m2m3 +from contact import m2_via from dff_buf_array import dff_buf_array from dff_array import dff_array @@ -280,7 +280,7 @@ class sram_1bank(sram_base): mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y) # In some designs, the steiner via will be too close to the mid_pos via # so make the wire as wide as the contacts - self.add_path("m2",[mid_pos, clk_steiner_pos], width=max(m2m3.width,m2m3.height)) + self.add_path("m2",[mid_pos, clk_steiner_pos], width=max(m2_via.width,m2_via.height)) self.add_wire(("m3","via2","m2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos]) if self.write_size: @@ -289,7 +289,7 @@ class sram_1bank(sram_base): mid_pos = vector(clk_steiner_pos.x, wmask_dff_clk_pos.y) # In some designs, the steiner via will be too close to the mid_pos via # so make the wire as wide as the contacts - self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2m3.width, m2m3.height)) + self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height)) self.add_wire(("m3", "via2", "m2"), [wmask_dff_clk_pos, mid_pos, clk_steiner_pos]) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index ffc981b8..c60abeb5 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -8,7 +8,7 @@ import os from design_rules import * from module_type import * -from custom_cell_properties import CellProperties +from custom_cell_properties import cell_properties """ File containing the process technology parameters for FreePDK 45nm. @@ -23,15 +23,16 @@ File containing the process technology parameters for FreePDK 45nm. # Using tech_modules['cellname'] you can override each class by providing a custom # implementation in '$OPENRAM_TECHDIR/modules/' # For example: tech_modules['contact'] = 'contact_freepdk45' -tech_modules = ModuleType() +tech_modules = module_type() ################################################### # Custom cell properties ################################################### -cell_properties = CellProperties() +cell_properties = cell_properties() cell_properties.bitcell.mirror.x = True cell_properties.bitcell.mirror.y = False + ################################################### # GDS file info ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 965306a3..7c360d38 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -8,7 +8,7 @@ import os from design_rules import * from module_type import * -from custom_cell_properties import CellProperties +from custom_cell_properties import cell_properties """ File containing the process technology parameters for SCMOS 4m, 0.35um @@ -23,12 +23,12 @@ File containing the process technology parameters for SCMOS 4m, 0.35um # Using tech_modules['cellname'] you can override each class by providing a custom # implementation in '$OPENRAM_TECHDIR/modules/' # For example: tech_modules['contact'] = 'contact_scn4m' -tech_modules = ModuleType() +tech_modules = module_type() ################################################### # Custom cell properties ################################################### -cell_properties = CellProperties() +cell_properties = cell_properties() cell_properties.bitcell.mirror.x = True cell_properties.bitcell.mirror.y = False From 0880c393fda4fbfd2a9a4dc43f1eb7b945db5304 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 30 Jan 2020 01:58:30 +0000 Subject: [PATCH 121/521] Fix base bitcell syntax error. Remove some unused imports. --- compiler/modules/dummy_array.py | 9 ++------- compiler/modules/replica_bitcell_array.py | 5 +---- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 997330e1..de15d0ce 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -3,15 +3,11 @@ # Copyright (c) 2016-2019 Regents of the University of California # All rights reserved. # -import debug -import design -from base_array import bitcell_base_array -from tech import drc -import contact +from bitcell_base_array import bitcell_base_array from sram_factory import factory -from vector import vector from globals import OPTS + class dummy_array(bitcell_base_array): """ Generate a dummy row/column for the replica array. @@ -23,7 +19,6 @@ class dummy_array(bitcell_base_array): self.create_netlist() if not OPTS.netlist_only: self.create_layout() - def create_netlist(self): """ Create and connect the netlist """ diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 9cf5c5a2..178c2f91 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -10,10 +10,7 @@ from tech import drc, spice from vector import vector from globals import OPTS from sram_factory import factory -import logical_effort -import bitcell_array -import replica_column -import dummy_array + class replica_bitcell_array(design.design): """ From 400cf0333aef3ef153ad42e4e4e98b7727ffe6ee Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 30 Jan 2020 03:34:04 +0000 Subject: [PATCH 122/521] Pgates are 8 M1 high by default. Port data is bitcell height. --- compiler/modules/hierarchical_decoder.py | 5 +-- compiler/modules/wordline_driver.py | 8 +++-- compiler/pgates/pgate.py | 42 ++++++++++++------------ 3 files changed, 30 insertions(+), 25 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index bb637ed1..f83035ce 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -21,7 +21,7 @@ class hierarchical_decoder(design.design): """ Dynamically generated hierarchical decoder. """ - def __init__(self, name, rows, height=None): + def __init__(self, name, rows): design.design.__init__(self, name) self.NAND_FORMAT = "DEC_NAND_{0}" @@ -30,7 +30,8 @@ class hierarchical_decoder(design.design): self.pre2x4_inst = [] self.pre3x8_inst = [] - self.cell_height = height + b = factory.create(module_type="bitcell") + self.cell_height = b.height self.rows = rows self.num_inputs = math.ceil(math.log(self.rows, 2)) (self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index cac2eea5..27671fd2 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -56,12 +56,16 @@ class wordline_driver(design.design): self.add_pin("gnd", "GROUND") def add_modules(self): + b = factory.create(module_type="bitcell") + self.inv = factory.create(module_type="pdriver", fanout=self.cols, - neg_polarity=True) + neg_polarity=True, + height=b.height) self.add_mod(self.inv) - self.nand2 = factory.create(module_type="pnand2") + self.nand2 = factory.create(module_type="pnand2", + height=b.height) self.add_mod(self.nand2) def route_vdd_gnd(self): diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 43fc1c8c..cac2ee9d 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -27,8 +27,8 @@ class pgate(design.design): if height: self.height = height elif not height: - b = factory.create(module_type="bitcell") - self.height = b.height + # By default, we make it 8 M1 pitch tall + self.height = 8*self.m1_pitch self.create_netlist() if not OPTS.netlist_only: @@ -128,37 +128,37 @@ class pgate(design.design): # FIXME: float rounding problem middle_position = middle_position.snap_to_grid() - # Add a rail width to extend the well to the top of the rail - nwell_max_offset = max(self.find_highest_layer_coords("nwell").y, - self.height + 0.5 * self.m1_width) - nwell_position = middle_position - nwell_height = nwell_max_offset - middle_position.y if "nwell" in layer: + # Add a rail width to extend the well to the top of the rail + nwell_max_offset = max(self.find_highest_layer_coords("nwell").y, + self.height + 0.5 * self.m1_width) + nwell_position = middle_position + nwell_height = nwell_max_offset - middle_position.y self.add_rect(layer="nwell", offset=middle_position, width=self.well_width, height=nwell_height) - if "vtg" in layer: - self.add_rect(layer="vtg", - offset=nwell_position, - width=self.well_width, - height=nwell_height) + if "vtg" in layer: + self.add_rect(layer="vtg", + offset=nwell_position, + width=self.well_width, + height=nwell_height) # Start this half a rail width below the cell - pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y, - -0.5 * self.m1_width) - pwell_position = vector(0, pwell_min_offset) - pwell_height = middle_position.y - pwell_position.y if "pwell" in layer: + pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y, + -0.5 * self.m1_width) + pwell_position = vector(0, pwell_min_offset) + pwell_height = middle_position.y - pwell_position.y self.add_rect(layer="pwell", offset=pwell_position, width=self.well_width, height=pwell_height) - if "vtg" in layer: - self.add_rect(layer="vtg", - offset=pwell_position, - width=self.well_width, - height=pwell_height) + if "vtg" in layer: + self.add_rect(layer="vtg", + offset=pwell_position, + width=self.well_width, + height=pwell_height) def add_nwell_contact(self, pmos, pmos_pos): """ Add an nwell contact next to the given pmos device. """ From 6cf20a03538bb318e7325e65d37a15ae6b23c376 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 30 Jan 2020 19:44:24 +0000 Subject: [PATCH 123/521] add technology based module customization --- compiler/modules/custom_module_properties.py | 27 ++++++++++++++++++++ compiler/modules/dff.py | 9 +++++-- 2 files changed, 34 insertions(+), 2 deletions(-) create mode 100644 compiler/modules/custom_module_properties.py diff --git a/compiler/modules/custom_module_properties.py b/compiler/modules/custom_module_properties.py new file mode 100644 index 00000000..43c140b0 --- /dev/null +++ b/compiler/modules/custom_module_properties.py @@ -0,0 +1,27 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2020 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# + +class _dff: + def __init__(self, use_custom_ports, custom_port_list, custom_type_list): + self.use_custom_ports = use_custom_ports + self.custom_port_list = custom_port_list + self.custom_type_list = custom_type_list + +class module_properties(): + """ + TODO + """ + def __init__(self): + self.names = {} + self._dff = _dff(use_custom_ports = False, + custom_port_list = [], + custom_type_list = []) + + @property + def dff(self): + return self._dff diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 8871872d..1078088e 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -7,6 +7,7 @@ # import design from tech import GDS, layer, spice, parameter +from tech import module_properties import utils @@ -14,9 +15,13 @@ class dff(design.design): """ Memory address flip-flop """ + if not module_properties.dff.use_custom_ports: + pin_names = ["D", "Q", "clk", "vdd", "gnd"] + type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] + else: + pin_names = module_properties.dff.custom_port_list + type_list = module_properties.dff.custom_type_list - pin_names = ["D", "Q", "clk", "vdd", "gnd"] - type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] (width, height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"]) From 34c9b3a0a552edc4d7bd9c9ef3031a5bfe351b1c Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 3 Feb 2020 17:37:53 +0000 Subject: [PATCH 124/521] Fix well offset computation for PMOS --- compiler/pgates/ptx.py | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 32bbeefe..3af456e0 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -154,17 +154,19 @@ class ptx(design.design): # Poly height must include poly extension over active self.poly_height = self.tx_width + 2 * self.poly_extend_active - - well_name = "{}well".format(self.well_type) # The active offset is due to the well extension - if well_name in layer: - well_enclose_active = drc(well_name + "_enclose_active") - self.active_offset = vector([well_enclose_active] * 2) - else: - self.active_offset = vector(0, 0) + # but we need to do the active offset for the other tx type too + # so that they align in pgates. + well_enclose_active = 0 + if self.well_type=="p" and "pwell" in layer: + well_enclose_active = max(drc("pwell_enclose_active"), well_enclose_active) + if self.well_type=="n" and "nwell" in layer: + well_enclose_active = max(drc("nwell_enclose_active"), well_enclose_active) + self.active_offset = vector([well_enclose_active] * 2) # Well enclosure of active, ensure minwidth as well + well_name = "{}well".format(self.well_type) if well_name in layer: well_width_rule = drc("minwidth_" + well_name) well_enclose_active = drc(well_name + "_enclose_active") @@ -179,7 +181,7 @@ class ptx(design.design): # The well is not included in the height and width self.height = self.poly_height self.width = self.active_width - + # This is the center of the first active contact offset (centered vertically) self.contact_offset = self.active_offset + vector(0.5 * self.active_contact.width, 0.5 * self.active_height) @@ -334,13 +336,10 @@ class ptx(design.design): if not (well_name in layer or "vtg" in layer): return - center_pos = self.active_offset + vector(self.width / 2.0, - self.height / 2.0) - well_ll = center_pos - vector(self.well_width / 2.0, - self.well_height / 2.0) - well_ll = well_ll - vector(0, - self.poly_extend_active) - + center_pos = self.active_offset + vector(0.5*self.active_width, + 0.5*self.active_height) + well_ll = center_pos - vector(0.5*self.well_width, + 0.5*self.well_height) if well_name in layer: self.add_rect(layer=well_name, offset=well_ll, From 5aed893725d9809688437f3c4e1245c38982af63 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 3 Feb 2020 18:41:06 +0000 Subject: [PATCH 125/521] Add nwell/pwell tap test --- compiler/tests/03_contact_test.py | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index f7a13118..d2f0c7f6 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -21,7 +21,7 @@ class contact_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from tech import poly_stack, beol_stacks + from tech import active_stack, poly_stack, beol_stacks # Don't do active because of nwell contact rules # Don't do metal3 because of min area rules @@ -67,6 +67,25 @@ class contact_test(openram_test): c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(3, 3)) self.local_drc_check(c) + # Test the well taps + # check vertical array with one in the middle and two ends + layer_stack = active_stack + stack_name = ":".join(map(str, layer_stack)) + + debug.info(2, "1 x 1 {} nwell".format(stack_name)) + c = factory.create(module_type="contact", + layer_stack=layer_stack, + implant_type="n", + well_type="n") + self.local_drc_check(c) + + debug.info(2, "1 x 1 {} pwell".format(stack_name)) + c = factory.create(module_type="contact", + layer_stack=layer_stack, + implant_type="p", + well_type="p") + self.local_drc_check(c) + globals.end_openram() From 53217e4030a0af582f3440a70440ea71c22b0ee2 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 4 Feb 2020 17:37:58 +0000 Subject: [PATCH 126/521] Check min well width in contact and redo position --- compiler/base/contact.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 51efc498..141ed979 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -231,10 +231,14 @@ class contact(hierarchy_design.hierarchy_design): # Optionally implant well if layer exists well_layer = "{}well".format(self.well_type) if well_layer in tech.layer: + well_width_rule = drc("minwidth_" + well_layer) well_enclose_active = drc(well_layer + "_enclose_active") - well_position = self.first_layer_position - [well_enclose_active] * 2 - well_width = self.first_layer_width + 2 * well_enclose_active - well_height = self.first_layer_height + 2 * well_enclose_active + well_width = max(self.first_layer_width + 2 * well_enclose_active, + well_width_rule) + well_height = max(self.first_layer_height + 2 * well_enclose_active, + well_width_rule) + center_pos = vector(0.5*self.width, 0.5*self.height) + well_position = center_pos - vector(0.5*well_width, 0.5*well_height) self.add_rect(layer=well_layer, offset=well_position, width=well_width, From 304971ff6086982d14a638439dd5407ba3da56ab Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 4 Feb 2020 17:38:35 +0000 Subject: [PATCH 127/521] Fix ptx so nmos and pmos have same active offset and gates align --- compiler/pgates/pgate.py | 4 +++- compiler/pgates/ptx.py | 18 +++++++++++------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index cac2ee9d..ab30a0d0 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -75,8 +75,10 @@ class pgate(design.design): pmos_gate_pin = pmos_inst.get_pin("G") # Check if the gates are aligned and give an error if they aren't! + if nmos_gate_pin.ll().x != pmos_gate_pin.ll().x: + self.gds_write("unaliged_gates.gds") debug.check(nmos_gate_pin.ll().x == pmos_gate_pin.ll().x, - "Connecting unaligned gates not supported.") + "Connecting unaligned gates not supported. See unaligned_gates.gds.") # Pick point on the left of NMOS and connect down to PMOS nmos_gate_pos = nmos_gate_pin.ll() + vector(0.5 * self.poly_width, 0) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 3af456e0..f331dc28 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -156,13 +156,17 @@ class ptx(design.design): self.poly_height = self.tx_width + 2 * self.poly_extend_active # The active offset is due to the well extension - # but we need to do the active offset for the other tx type too - # so that they align in pgates. - well_enclose_active = 0 - if self.well_type=="p" and "pwell" in layer: - well_enclose_active = max(drc("pwell_enclose_active"), well_enclose_active) - if self.well_type=="n" and "nwell" in layer: - well_enclose_active = max(drc("nwell_enclose_active"), well_enclose_active) + if "pwell" in layer: + pwell_enclose_active = drc("pwell_enclose_active") + else: + pwell_enclose_active = 0 + if "nwell" in layer: + nwell_enclose_active = drc("nwell_enclose_active") + else: + nwell_enclose_active = 0 + # Use the max of either so that the poly gates will align properly + well_enclose_active = max(pwell_enclose_active, + nwell_enclose_active) self.active_offset = vector([well_enclose_active] * 2) # Well enclosure of active, ensure minwidth as well From ed11145ca49a365cd46641d288fb1ef64b55b91b Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 4 Feb 2020 23:35:06 -0800 Subject: [PATCH 128/521] add custom module file, make dff clk pin dynamic --- compiler/modules/custom_module_properties.py | 8 +++++--- compiler/modules/dff.py | 2 ++ compiler/modules/dff_array.py | 15 ++++++++------- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/compiler/modules/custom_module_properties.py b/compiler/modules/custom_module_properties.py index 43c140b0..e27741ea 100644 --- a/compiler/modules/custom_module_properties.py +++ b/compiler/modules/custom_module_properties.py @@ -7,10 +7,11 @@ # class _dff: - def __init__(self, use_custom_ports, custom_port_list, custom_type_list): + def __init__(self, use_custom_ports, custom_port_list, custom_type_list, clk_pin): self.use_custom_ports = use_custom_ports self.custom_port_list = custom_port_list self.custom_type_list = custom_type_list + self.clk_pin = clk_pin class module_properties(): """ @@ -19,8 +20,9 @@ class module_properties(): def __init__(self): self.names = {} self._dff = _dff(use_custom_ports = False, - custom_port_list = [], - custom_type_list = []) + custom_port_list = ["D", "Q", "clk", "vdd", "gnd"], + custom_type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"], + clk_pin= "clk") @property def dff(self): diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 1078088e..45d20a62 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -18,9 +18,11 @@ class dff(design.design): if not module_properties.dff.use_custom_ports: pin_names = ["D", "Q", "clk", "vdd", "gnd"] type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] + clk_pin = "clk" else: pin_names = module_properties.dff.custom_port_list type_list = module_properties.dff.custom_type_list + clk_pin = module_properties.dff.clk_pin (width, height) = utils.get_libcell_size("dff", GDS["unit"], diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 6ba020c7..62464834 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -69,11 +69,12 @@ class dff_array(design.design): name = "dff_r{0}_c{1}".format(row,col) self.dff_insts[row,col]=self.add_inst(name=name, mod=self.dff) - self.connect_inst([self.get_din_name(row,col), - self.get_dout_name(row,col), - "clk", - "vdd", - "gnd"]) + instance_ports = [self.get_din_name(row,col), + self.get_dout_name(row,col)] + for port in self.dff.pin_names: + if port != 'D' and port != 'Q': + instance_ports.append(port) + self.connect_inst(instance_ports) def place_dff_array(self): for row in range(self.rows): @@ -142,7 +143,7 @@ class dff_array(design.design): # Create vertical spines to a single horizontal rail - clk_pin = self.dff_insts[0,0].get_pin("clk") + clk_pin = self.dff_insts[0,0].get_pin(self.dff.clk_pin) clk_ypos = 2*self.m3_pitch+self.m3_width debug.check(clk_pin.layer=="m2","DFF clk pin not on metal2") self.add_layout_pin_segment_center(text="clk", @@ -150,7 +151,7 @@ class dff_array(design.design): start=vector(0,clk_ypos), end=vector(self.width,clk_ypos)) for col in range(self.columns): - clk_pin = self.dff_insts[0,col].get_pin("clk") + clk_pin = self.dff_insts[0,col].get_pin(self.dff.clk_pin) # Make a vertical strip for each column self.add_rect(layer="m2", offset=clk_pin.ll().scale(1,0), From 4526986de3bd0384a6b0d076a29e069fc0c15b20 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 5 Feb 2020 18:21:01 +0000 Subject: [PATCH 129/521] Update contact well support. Add asymmetric tap overlap support in DRC rules. Add static nwell and pwell contact in class for measurements. --- compiler/base/contact.py | 42 ++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 141ed979..1ffdc7bf 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -42,6 +42,8 @@ class contact(hierarchy_design.hierarchy_design): if implant_type or well_type: self.add_comment("implant type: {}\n".format(implant_type)) self.add_comment("well_type: {}\n".format(well_type)) + + self.is_well_contact = implant_type == well_type self.layer_stack = layer_stack self.dimensions = dimensions @@ -114,7 +116,12 @@ class contact(hierarchy_design.hierarchy_design): self.first_layer_minwidth = drc("minwidth_{0}".format(self.first_layer_name)) self.first_layer_enclosure = drc("{0}_enclose_{1}".format(self.first_layer_name, self.via_layer_name)) - self.first_layer_extend = drc("{0}_extend_{1}".format(self.first_layer_name, self.via_layer_name)) + # If there's a different rule for active + # FIXME: Make this more elegant + if self.is_well_contact and self.first_layer_name == "active" and "tap_extend_contact" in drc.keys(): + self.first_layer_extend = drc("tap_extend_contact") + else: + self.first_layer_extend = drc("{0}_extend_{1}".format(self.first_layer_name, self.via_layer_name)) self.second_layer_minwidth = drc("minwidth_{0}".format(self.second_layer_name)) self.second_layer_enclosure = drc("{0}_enclose_{1}".format(self.second_layer_name, self.via_layer_name)) @@ -232,17 +239,17 @@ class contact(hierarchy_design.hierarchy_design): well_layer = "{}well".format(self.well_type) if well_layer in tech.layer: well_width_rule = drc("minwidth_" + well_layer) - well_enclose_active = drc(well_layer + "_enclose_active") - well_width = max(self.first_layer_width + 2 * well_enclose_active, - well_width_rule) - well_height = max(self.first_layer_height + 2 * well_enclose_active, - well_width_rule) + self.well_enclose_active = drc(well_layer + "_enclose_active") + self.well_width = max(self.first_layer_width + 2 * self.well_enclose_active, + well_width_rule) + self.well_height = max(self.first_layer_height + 2 * self.well_enclose_active, + well_width_rule) center_pos = vector(0.5*self.width, 0.5*self.height) - well_position = center_pos - vector(0.5*well_width, 0.5*well_height) + well_position = center_pos - vector(0.5*self.well_width, 0.5*self.well_height) self.add_rect(layer=well_layer, offset=well_position, - width=well_width, - height=well_height) + width=self.well_width, + height=self.well_height) def analytical_power(self, corner, load): """ Get total power of a module """ @@ -261,6 +268,21 @@ for layer_stack in tech.layer_stacks: else: setattr(module, layer1 + "_via", cont) - +# Set up a static for each well contact for measurements +if "nwell" in tech.layer: + cont = factory.create(module_type="contact", + layer_stack=tech.active_stack, + implant_type="n", + well_type="n") + module = sys.modules[__name__] + setattr(module, "nwell_contact", cont) + +if "pwell" in tech.layer: + cont = factory.create(module_type="contact", + layer_stack=tech.active_stack, + implant_type="p", + well_type="p") + module = sys.modules[__name__] + setattr(module, "pwell_contact", cont) From 04d254542dde8004f363a2a113ee253cc98dfb1b Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 5 Feb 2020 18:22:22 +0000 Subject: [PATCH 130/521] Add general well_extend_active DRC in design class. --- compiler/base/design.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/compiler/base/design.py b/compiler/base/design.py index 9db68877..c2ef8340 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -113,6 +113,15 @@ class design(hierarchy_design): if match: setattr(self, match.group(0), drc(match.group(0))) + # Create the maximum well extend active that gets used + # by cells to extend the wells for interaction with other cells + from tech import layer + self.well_extend_active = 0 + if "nwell" in layer: + self.well_extend_active = max(self.well_extend_active, self.nwell_extend_active) + if "pwell" in layer: + self.well_extend_active = max(self.well_extend_active, self.pwell_extend_active) + # These are for debugging previous manual rules if False: print("poly_width", self.poly_width) From 596302d9a927743ba929b358cecdf8f32b0deb09 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 5 Feb 2020 18:22:45 +0000 Subject: [PATCH 131/521] Update pgate well and well contacts. Extend well left and right past a cell boundary. Use asymmetric well contacts. --- compiler/pgates/pgate.py | 8 +++----- compiler/pgates/pinv.py | 18 ++++++++++-------- compiler/pgates/pnand2.py | 6 +++--- compiler/pgates/pnand3.py | 10 +++++----- compiler/pgates/pnor2.py | 8 ++++---- 5 files changed, 25 insertions(+), 25 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index ab30a0d0..c13939f1 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -134,10 +134,10 @@ class pgate(design.design): # Add a rail width to extend the well to the top of the rail nwell_max_offset = max(self.find_highest_layer_coords("nwell").y, self.height + 0.5 * self.m1_width) - nwell_position = middle_position + nwell_position = middle_position - vector(self.well_extend_active, 0) nwell_height = nwell_max_offset - middle_position.y self.add_rect(layer="nwell", - offset=middle_position, + offset=nwell_position, width=self.well_width, height=nwell_height) if "vtg" in layer: @@ -150,7 +150,7 @@ class pgate(design.design): if "pwell" in layer: pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y, -0.5 * self.m1_width) - pwell_position = vector(0, pwell_min_offset) + pwell_position = vector(-self.well_extend_active, pwell_min_offset) pwell_height = middle_position.y - pwell_position.y self.add_rect(layer="pwell", offset=pwell_position, @@ -183,7 +183,6 @@ class pgate(design.design): 0.5 * pmos.active_contact.first_layer_height) self.nwell_contact = self.add_via_center(layers=layer_stack, offset=contact_offset, - directions=("H", "V"), implant_type="n", well_type="n") self.add_rect_center(layer="m1", @@ -237,7 +236,6 @@ class pgate(design.design): 0.5 * nmos.active_contact.first_layer_height) self.pwell_contact= self.add_via_center(layers=layer_stack, offset=contact_offset, - directions=("H", "V"), implant_type="p", well_type="p") self.add_rect_center(layer="m1", diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 8da648b0..c0336956 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -52,10 +52,10 @@ class pinv(pgate.pgate): def create_layout(self): """ Calls all functions related to the generation of the layout """ self.setup_layout_constants() - self.route_supply_rails() self.place_ptx() self.add_well_contacts() self.extend_wells(self.well_pos) + self.route_supply_rails() self.connect_rails() self.route_input_gate(self.pmos_inst, self.nmos_inst, @@ -104,8 +104,9 @@ class pinv(pgate.pgate): extra_contact_space = max(-nmos.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space, - self.poly_extend_active, self.poly_space) + self.poly_extend_active + self.poly_space) total_height = tx_height + min_channel + 2 * self.top_bottom_space + debug.check(self.height > total_height, "Cell height {0} too small for simple min height {1}.".format(self.height, total_height)) @@ -148,14 +149,15 @@ class pinv(pgate.pgate): def setup_layout_constants(self): """ - Pre-compute some handy layout parameters. + Compute the width and height """ - # the well width is determined the multi-finger PMOS device width plus - # the well contact width and half well enclosure on both sides - self.well_width = self.pmos.active_width + self.pmos.active_contact.width \ - + self.active_space + 2*self.nwell_enclose_active - self.width = self.well_width + # the width is determined the multi-finger PMOS device width plus + # the well contact width, spacing between them + self.width = self.pmos.active_offset.x + self.pmos.active_width \ + + contact.nwell_contact.width + self.active_space + 0.5 * self.nwell_enclose_active + # This includes full enclosures on each end + self.well_width = self.width + 2*self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. def add_ptx(self): diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index f5abdaaa..2f539c16 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -98,11 +98,11 @@ class pnand2(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.well_width = 2 * self.pmos.active_width + contact.active_contact.width \ + self.width = 2 * self.pmos.active_width + contact.active_contact.width \ + 2 * self.active_space \ - + 2 * self.nwell_enclose_active + + 0.5 * self.nwell_enclose_active - self.width = self.well_width + self.well_width = self.width + 2 * self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. # This is the extra space needed to ensure DRC rules diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 5c1e0db5..d5b07069 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -91,10 +91,10 @@ class pnand3(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.well_width = 3 * self.pmos.active_width + self.pmos.active_contact.width \ - + 2 * self.active_space + 2 * self.nwell_enclose_active \ + self.width = 3 * self.pmos.active_width + self.pmos.active_contact.width \ + + 2 * self.active_space + 0.5 * self.nwell_enclose_active \ - self.overlap_offset.x - self.width = self.well_width + self.well_width = self.width + 2 * self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. # This is the extra space needed to ensure DRC rules @@ -245,10 +245,10 @@ class pnand3(pgate.pgate): offset=nmos3_pin.center()) # PMOS3 and NMOS3 are drain aligned - self.add_path("m2", [pmos3_pin.bc(), nmos3_pin.uc()]) + self.add_path("m2", [pmos3_pin.center(), nmos3_pin.uc()]) # Route in the A input track (top track) mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset) - self.add_path("m2", [pmos1_pin.bc(), mid_offset, nmos3_pin.uc()]) + self.add_path("m2", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()]) # This extends the output to the edge of the cell self.add_via_center(layers=self.m1_stack, diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index e28b6fc8..7ceab71a 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -95,11 +95,11 @@ class pnor2(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.well_width = 2 * self.pmos.active_width \ + self.width = 2 * self.pmos.active_width \ + self.pmos.active_contact.width \ + 2 * self.active_space \ - + 2 * self.nwell_enclose_active - self.width = self.well_width + + 0.5 * self.nwell_enclose_active + self.well_width = self.width + 2 * self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. # This is the extra space needed to ensure DRC rules @@ -225,7 +225,7 @@ class pnor2(pgate.pgate): # PMOS1 to mid-drain to NMOS2 drain self.add_path("m2", - [pmos_pin.bc(), mid2_offset, mid3_offset]) + [pmos_pin.center(), mid2_offset, mid3_offset]) self.add_path("m2", [nmos_pin.rc(), mid1_offset, mid2_offset]) # This extends the output to the edge of the cell From 18573c0e42c4b48ff24716d230fb1c454b6304dc Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 5 Feb 2020 22:25:35 +0000 Subject: [PATCH 132/521] add module properties to other technologies --- technology/freepdk45/tech/tech.py | 3 ++- technology/scn4m_subm/tech/tech.py | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index c60abeb5..f91be16c 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -9,7 +9,7 @@ import os from design_rules import * from module_type import * from custom_cell_properties import cell_properties - +from custom_module_properties import module_properties """ File containing the process technology parameters for FreePDK 45nm. """ @@ -25,6 +25,7 @@ File containing the process technology parameters for FreePDK 45nm. # For example: tech_modules['contact'] = 'contact_freepdk45' tech_modules = module_type() +module_properties = module_properties() ################################################### # Custom cell properties ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 7c360d38..bb379478 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -9,6 +9,7 @@ import os from design_rules import * from module_type import * from custom_cell_properties import cell_properties +from custom_module_properties import module_properties """ File containing the process technology parameters for SCMOS 4m, 0.35um @@ -24,6 +25,7 @@ File containing the process technology parameters for SCMOS 4m, 0.35um # implementation in '$OPENRAM_TECHDIR/modules/' # For example: tech_modules['contact'] = 'contact_scn4m' tech_modules = module_type() +module_properties = module_properties() ################################################### # Custom cell properties From 3a06141030c2f247d8184cef1db3955d16fbf01f Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 6 Feb 2020 12:10:49 +0000 Subject: [PATCH 133/521] add simple sram sizing for netlist only --- compiler/base/utils.py | 13 +++++++++---- compiler/modules/bank.py | 1 + compiler/sram/sram_config.py | 15 +++++++++++++-- 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/compiler/base/utils.py b/compiler/base/utils.py index f02b2b85..16fbc51f 100644 --- a/compiler/base/utils.py +++ b/compiler/base/utils.py @@ -96,8 +96,10 @@ def get_libcell_size(name, units, lpp): Open a GDS file and return the library cell size from either the bounding box or a border layer. """ - cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" - return(get_gds_size(name, cell_gds, units, lpp)) + if not OPTS.netlist_only: + cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" + return(get_gds_size(name, cell_gds, units, lpp)) + return (0,0,) def get_gds_pins(pin_names, name, gds_filename, units): @@ -128,8 +130,11 @@ def get_libcell_pins(pin_list, name, units): Open a GDS file and find the pins in pin_list as text on a given layer. Return these as a rectangle layer pair for each pin. """ - cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" - return(get_gds_pins(pin_list, name, cell_gds, units)) + if not OPTS.netlist_only: + cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" + return(get_gds_pins(pin_list, name, cell_gds, units)) + else: + return diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 7ed0c9a3..4a674c23 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -57,6 +57,7 @@ class bank(design.design): def create_netlist(self): + self.compute_sizes() self.add_modules() self.add_pins() # Must create the replica bitcell array first diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index 376bf42b..c086a57a 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -23,9 +23,12 @@ class sram_config: # This will get over-written when we determine the organization self.words_per_row = words_per_row + if not OPTS.netlist_only: + self.compute_sizes() + else: + self.compute_simple_sram_sizes() - self.compute_sizes() - + def set_local_config(self, module): """ Copy all of the member variables to the given module for convenience """ @@ -35,6 +38,14 @@ class sram_config: # Copy all the variables to the local module for member in members: setattr(module,member,getattr(self,member)) + def compute_simple_sram_sizes(self): + self.row_addr_size = int(log(OPTS.num_words, 2)) + self.col_addr_size = int(log(OPTS.word_size, 2)) + self.words_per_row = 1 + self.num_rows = OPTS.num_words + self.num_cols = OPTS.word_size + self.bank_addr_size = self.col_addr_size + self.row_addr_size + self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2)) def compute_sizes(self): """ Computes the organization of the memory using bitcell size by trying to make it square.""" From b1079346726ae5f4028bba0f0d5272488d972f82 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 6 Feb 2020 12:15:52 +0000 Subject: [PATCH 134/521] fix styling --- compiler/example_configs/example_config_scn4m_subm.py | 1 + compiler/sram/sram_config.py | 1 + 2 files changed, 2 insertions(+) diff --git a/compiler/example_configs/example_config_scn4m_subm.py b/compiler/example_configs/example_config_scn4m_subm.py index 71ef328b..a55122a2 100644 --- a/compiler/example_configs/example_config_scn4m_subm.py +++ b/compiler/example_configs/example_config_scn4m_subm.py @@ -9,6 +9,7 @@ temperatures = [25] route_supplies = True check_lvsdrc = True +netlist_only = True output_path = "temp" output_name = "sram_{0}_{1}_{2}".format(word_size, diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index c086a57a..20c8299e 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -38,6 +38,7 @@ class sram_config: # Copy all the variables to the local module for member in members: setattr(module,member,getattr(self,member)) + def compute_simple_sram_sizes(self): self.row_addr_size = int(log(OPTS.num_words, 2)) self.col_addr_size = int(log(OPTS.word_size, 2)) From f0ecf385e883420ddea567543f308de041e9a4c0 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 6 Feb 2020 16:20:09 +0000 Subject: [PATCH 135/521] Nwell fixes in pgates. Fix minor PEP8 format fixes. Fix nwell to be 55% of cell height. Move contact in hierarchical decoder for DRC error. --- compiler/modules/hierarchical_decoder.py | 14 +++----------- compiler/modules/hierarchical_predecode.py | 10 ++++------ compiler/pgates/pgate.py | 18 ++++++++++-------- compiler/pgates/pinv.py | 10 +++++----- compiler/pgates/pnand2.py | 7 ++----- compiler/pgates/pnand3.py | 11 +++-------- compiler/pgates/pnor2.py | 5 +---- compiler/pgates/precharge.py | 2 +- compiler/pgates/pwrite_driver.py | 5 ++--- 9 files changed, 31 insertions(+), 51 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index f83035ce..242ef476 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -5,18 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from tech import drc import debug import design -from math import log -from math import sqrt -from math import ceil import math -import contact from sram_factory import factory from vector import vector from globals import OPTS + class hierarchical_decoder(design.design): """ Dynamically generated hierarchical decoder. @@ -34,13 +30,12 @@ class hierarchical_decoder(design.design): self.cell_height = b.height self.rows = rows self.num_inputs = math.ceil(math.log(self.rows, 2)) - (self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) + (self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) self.create_netlist() if not OPTS.netlist_only: self.create_layout() - def create_netlist(self): self.add_modules() self.setup_netlist_constants() @@ -308,7 +303,6 @@ class hierarchical_decoder(design.design): base= vector(-self.pre2_4.width, num * self.pre2_4.height) self.pre2x4_inst[num].place(base) - def place_pre3x8(self,num): """ Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """ @@ -321,7 +315,6 @@ class hierarchical_decoder(design.design): self.pre3x8_inst[num].place(offset) - def create_row_decoder(self): """ Create the row-decoder by placing NAND2/NAND3 and Inverters and add the primary decoder output pins. """ @@ -329,7 +322,6 @@ class hierarchical_decoder(design.design): self.create_decoder_nand_array() self.create_decoder_inv_array() - def create_decoder_nand_array(self): """ Add a column of NAND gates for final decode """ @@ -556,7 +548,7 @@ class hierarchical_decoder(design.design): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ # The vias will be placed in the center and right of the cells, respectively. - xoffset = self.nand_inst[0].cx() + xoffset = self.nand_inst[0].rx() for num in range(0,self.rows): for pin_name in ["vdd", "gnd"]: # The nand and inv are the same height rows... diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 78e9af7f..88bae534 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -8,12 +8,11 @@ import debug import design import math -from tech import drc import contact from vector import vector -from globals import OPTS from sram_factory import factory + class hierarchical_predecode(design.design): """ Pre 2x4 and 3x8 decoder shared code. @@ -42,7 +41,7 @@ class hierarchical_predecode(design.design): self.add_nand(self.number_of_inputs) self.add_mod(self.nand) - def add_nand(self,inputs): + def add_nand(self, inputs): """ Create the NAND for the predecode input stage """ if inputs==2: self.nand = factory.create(module_type="pnand2", @@ -51,7 +50,7 @@ class hierarchical_predecode(design.design): self.nand = factory.create(module_type="pnand3", height=self.cell_height) else: - debug.error("Invalid number of predecode inputs: {}".format(inputs),-1) + debug.error("Invalid number of predecode inputs: {}".format(inputs), -1) def setup_layout_constraints(self): @@ -89,7 +88,6 @@ class hierarchical_predecode(design.design): names=decode_names, length=self.height - 2*self.m1_width) - def create_input_inverters(self): """ Create the input inverters to invert input signals for the decode stage. """ self.in_inst = [] @@ -266,7 +264,7 @@ class hierarchical_predecode(design.design): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ # Find the x offsets for where the vias/pins should be placed - in_xoffset = self.in_inst[0].rx() + in_xoffset = self.in_inst[0].rx() + self.m1_space out_xoffset = self.inv_inst[0].lx() - self.m1_space for num in range(0,self.number_of_outputs): # this will result in duplicate polygons for rails, but who cares diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index c13939f1..e0401726 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -11,7 +11,6 @@ import debug from tech import layer from vector import vector from globals import OPTS -from sram_factory import factory class pgate(design.design): @@ -29,7 +28,7 @@ class pgate(design.design): elif not height: # By default, we make it 8 M1 pitch tall self.height = 8*self.m1_pitch - + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -125,17 +124,20 @@ class pgate(design.design): height=contact.poly_contact.first_layer_width, width=left_gate_offset.x - contact_offset.x) - def extend_wells(self, middle_position): + def extend_wells(self): """ Extend the n/p wells to cover whole cell """ + # This should match the cells in the cell library + nwell_y_offset = 0.48 * self.height + full_height = self.height + 0.5*self.m1_width + # FIXME: float rounding problem - middle_position = middle_position.snap_to_grid() if "nwell" in layer: # Add a rail width to extend the well to the top of the rail nwell_max_offset = max(self.find_highest_layer_coords("nwell").y, - self.height + 0.5 * self.m1_width) - nwell_position = middle_position - vector(self.well_extend_active, 0) - nwell_height = nwell_max_offset - middle_position.y + full_height) + nwell_position = vector(0, nwell_y_offset) - vector(self.well_extend_active, 0) + nwell_height = nwell_max_offset - nwell_y_offset self.add_rect(layer="nwell", offset=nwell_position, width=self.well_width, @@ -151,7 +153,7 @@ class pgate(design.design): pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y, -0.5 * self.m1_width) pwell_position = vector(-self.well_extend_active, pwell_min_offset) - pwell_height = middle_position.y - pwell_position.y + pwell_height = nwell_y_offset - pwell_position.y self.add_rect(layer="pwell", offset=pwell_position, width=self.well_width, diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index c0336956..c0f1f955 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -54,7 +54,7 @@ class pinv(pgate.pgate): self.setup_layout_constants() self.place_ptx() self.add_well_contacts() - self.extend_wells(self.well_pos) + self.extend_wells() self.route_supply_rails() self.connect_rails() self.route_input_gate(self.pmos_inst, @@ -154,8 +154,11 @@ class pinv(pgate.pgate): # the width is determined the multi-finger PMOS device width plus # the well contact width, spacing between them + # space is for power supply contact to nwell m1 spacing self.width = self.pmos.active_offset.x + self.pmos.active_width \ - + contact.nwell_contact.width + self.active_space + 0.5 * self.nwell_enclose_active + + self.active_space + contact.nwell_contact.width \ + + 0.5 * self.nwell_enclose_active \ + + self.m1_space # This includes full enclosures on each end self.well_width = self.width + 2*self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. @@ -225,9 +228,6 @@ class pinv(pgate.pgate): nmos_drain_pos = self.nmos_inst.get_pin("D").ul() self.output_pos = vector(0, 0.5 * (pmos_drain_pos.y + nmos_drain_pos.y)) - # This will help with the wells - self.well_pos = self.output_pos - def route_outputs(self): """ Route the output (drains) together. diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 2f539c16..8d3e0582 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -53,7 +53,7 @@ class pnand2(pgate.pgate): self.place_ptx() self.connect_rails() self.add_well_contacts() - self.extend_wells(self.well_pos) + self.extend_wells() self.route_inputs() self.route_output() @@ -110,7 +110,7 @@ class pnand2(pgate.pgate): extra_contact_space = max(-self.nmos.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, - self.poly_extend_active, self.poly_space) + self.poly_extend_active + self.poly_space) def route_supply_rails(self): """ Add vdd/gnd rails to the top and bottom. """ @@ -170,9 +170,6 @@ class pnand2(pgate.pgate): self.output_pos = vector(0, 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height)) - # This will help with the wells - self.well_pos = self.output_pos - def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index d5b07069..88b02d92 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -61,7 +61,7 @@ class pnand3(pgate.pgate): self.place_ptx() self.connect_rails() self.add_well_contacts() - self.extend_wells(self.well_pos) + self.extend_wells() self.route_inputs() self.route_output() @@ -102,10 +102,8 @@ class pnand3(pgate.pgate): nmos = factory.create(module_type="ptx", tx_type="nmos") extra_contact_space = max(-nmos.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell - self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space \ - + extra_contact_space, - self.poly_extend_active, - self.poly_space) + self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, + self.poly_extend_active + self.poly_space) def route_supply_rails(self): """ Add vdd/gnd rails to the top and bottom. """ @@ -179,9 +177,6 @@ class pnand3(pgate.pgate): # This will help with the wells and the input/output placement self.output_pos = vector(0, 0.5*self.height) - # This should be placed at the top of the NMOS well - self.well_pos = self.output_pos - def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 7ceab71a..d6605d68 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -52,7 +52,7 @@ class pnor2(pgate.pgate): self.place_ptx() self.connect_rails() self.add_well_contacts() - self.extend_wells(self.well_pos) + self.extend_wells() self.route_inputs() self.route_output() @@ -168,9 +168,6 @@ class pnor2(pgate.pgate): self.output_pos = vector(0, 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height)) - # This will help with the wells - self.well_pos = self.output_pos - def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 888304ce..28b4d85a 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -8,7 +8,7 @@ import contact import design import debug -from tech import drc, parameter +from tech import parameter from vector import vector from globals import OPTS from sram_factory import factory diff --git a/compiler/pgates/pwrite_driver.py b/compiler/pgates/pwrite_driver.py index ed970f9b..16830e62 100644 --- a/compiler/pgates/pwrite_driver.py +++ b/compiler/pgates/pwrite_driver.py @@ -6,14 +6,13 @@ #All rights reserved. # import design -from tech import drc, parameter, spice +from tech import parameter import debug -import math -from tech import drc from vector import vector from globals import OPTS from sram_factory import factory + class pwrite_driver(design.design): """ The pwrite_driver is two tristate inverters that drive the bitlines. From 5e514215d5dad40b977bcea6ef3c2ebfa6b0daeb Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 6 Feb 2020 16:44:19 +0000 Subject: [PATCH 136/521] Force vertical vias on pnand3 --- compiler/pgates/pnand3.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 88b02d92..9ec9ff60 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -233,11 +233,14 @@ class pnand3(pgate.pgate): # Go up to metal2 for ease on all output pins self.add_via_center(layers=self.m1_stack, - offset=pmos1_pin.center()) + offset=pmos1_pin.center(), + directions=("V", "V")) self.add_via_center(layers=self.m1_stack, - offset=pmos3_pin.center()) + offset=pmos3_pin.center(), + directions=("V", "V")) self.add_via_center(layers=self.m1_stack, - offset=nmos3_pin.center()) + offset=nmos3_pin.center(), + directions=("V", "V")) # PMOS3 and NMOS3 are drain aligned self.add_path("m2", [pmos3_pin.center(), nmos3_pin.uc()]) From 4b06ab9eafa24dcd6589fb8caaffcda465ddbad1 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 6 Feb 2020 19:46:10 +0000 Subject: [PATCH 137/521] Move port 2 column address bus down. PEP 8 cleanup. --- compiler/pgates/pnand2.py | 4 ++-- compiler/sram/sram_1bank.py | 15 ++------------- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 8d3e0582..dd04ccb9 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -224,11 +224,11 @@ class pnand2(pgate.pgate): # Non-preferred active contacts self.add_via_center(layers=self.m1_stack, - directions=("V","H"), + directions=("V", "H"), offset=pmos_pin.center()) # Non-preferred active contacts self.add_via_center(layers=self.m1_stack, - directions=("V","H"), + directions=("V", "H"), offset=nmos_pin.center()) self.add_via_center(layers=self.m1_stack, offset=out_offset) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 93247fc1..2b02923f 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -5,21 +5,10 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import sys -from tech import drc, spice import debug -from math import log,sqrt,ceil -import datetime -import getpass -import numpy as np from vector import vector -from globals import OPTS, print_time - from sram_base import sram_base -from bank import bank from contact import m2_via -from dff_buf_array import dff_buf_array -from dff_array import dff_array class sram_1bank(sram_base): @@ -328,10 +317,10 @@ class sram_1bank(sram_base): offset=flop_pos) def route_col_addr_dff(self): - """ Connect the output of the row flops to the bank pins """ + """ Connect the output of the col flops to the bank pins """ for port in self.all_ports: if port%2: - offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch) + offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+4)*self.m1_pitch) else: offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) From 2ff058f5d563a1a8a1fcbda30fe4b1a3e64871bc Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 6 Feb 2020 22:59:30 +0000 Subject: [PATCH 138/521] PEP8 Cleanup and reverse pitch offset of col addr routing --- compiler/modules/bank.py | 34 ++++++++++++++++------------------ compiler/sram/sram_1bank.py | 2 +- 2 files changed, 17 insertions(+), 19 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 7ed0c9a3..915aa064 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -5,19 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import sys -from tech import drc, parameter import debug import design -import math -from math import log,sqrt,ceil -import contact -import pgates from sram_factory import factory +from math import log +from tech import drc from vector import vector - from globals import OPTS + class bank(design.design): """ Dynamically generated a single bank including bitcell array, @@ -499,6 +495,8 @@ class bank(design.design): Create a 2:4 or 3:8 column address decoder. """ + # Height is a multiple of DFF so that it can be staggered + # and rows do not align with the control logic module self.dff = factory.create(module_type="dff") if self.col_addr_size == 0: @@ -867,7 +865,6 @@ class bank(design.design): route_map = list(zip(decode_pins, column_mux_pins)) self.create_vertical_channel_route(route_map, offset, self.m1_stack) - def add_lvs_correspondence_points(self): """ This adds some points for easier debugging if LVS goes wrong. These should probably be turned off by default though, since extraction @@ -912,7 +909,6 @@ class bank(design.design): layer="m1", offset=data_pin.center()) - def route_control_lines(self, port): """ Route the control lines of the entire bank """ @@ -920,23 +916,25 @@ class bank(design.design): # From control signal to the module pin # Connection from the central bus to the main control block crosses # pre-decoder and this connection is in metal3 - write_inst = 0 - read_inst = 0 - connection = [] - connection.append((self.prefix+"p_en_bar{}".format(port), self.port_data_inst[port].get_pin("p_en_bar").lc())) + connection.append((self.prefix + "p_en_bar{}".format(port), + self.port_data_inst[port].get_pin("p_en_bar").lc())) rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]) - connection.append((self.prefix+"wl_en{}".format(port), self.bitcell_array_inst.get_pin(rbl_wl_name).lc())) + connection.append((self.prefix + "wl_en{}".format(port), + self.bitcell_array_inst.get_pin(rbl_wl_name).lc())) if port in self.write_ports: if port % 2: - connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").rc())) + connection.append((self.prefix + "w_en{}".format(port), + self.port_data_inst[port].get_pin("w_en").rc())) else: - connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").lc())) + connection.append((self.prefix + "w_en{}".format(port), + self.port_data_inst[port].get_pin("w_en").lc())) if port in self.read_ports: - connection.append((self.prefix+"s_en{}".format(port), self.port_data_inst[port].get_pin("s_en").lc())) + connection.append((self.prefix + "s_en{}".format(port), + self.port_data_inst[port].get_pin("s_en").lc())) for (control_signal, pin_pos) in connection: control_mid_pos = self.bus_xoffset[port][control_signal] @@ -960,7 +958,7 @@ class bank(design.design): self.add_via_center(layers=self.m1_stack, offset=control_pos) - def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): + def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): """Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline""" #Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption stage_effort_list = [] diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 2b02923f..3b8d969c 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -320,7 +320,7 @@ class sram_1bank(sram_base): """ Connect the output of the col flops to the bank pins """ for port in self.all_ports: if port%2: - offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+4)*self.m1_pitch) + offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch) else: offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) From 4d85640a0025154b511ee6be0a8d094c546b746a Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 7 Feb 2020 22:20:16 +0000 Subject: [PATCH 139/521] Change col addr spacing to col addr size --- compiler/sram/sram_1bank.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 3b8d969c..2f37d927 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -320,7 +320,7 @@ class sram_1bank(sram_base): """ Connect the output of the col flops to the bank pins """ for port in self.all_ports: if port%2: - offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch) + offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.col_addr_size+2)*self.m1_pitch) else: offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) From b212b3e85a31b279fe2265c8889a8fb3cb330586 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sun, 9 Feb 2020 21:37:09 -0800 Subject: [PATCH 140/521] s8 gdsless netlist only working up to dff array --- compiler/base/utils.py | 16 +++++++--------- compiler/bitcells/bitcell.py | 7 +++++-- compiler/bitcells/replica_bitcell.py | 18 ++++++++++++++---- compiler/modules/replica_bitcell_array.py | 4 ++-- compiler/modules/sense_amp.py | 9 +++++++-- compiler/modules/write_driver.py | 9 +++++++-- compiler/sram/sram_config.py | 14 +------------- 7 files changed, 43 insertions(+), 34 deletions(-) diff --git a/compiler/base/utils.py b/compiler/base/utils.py index 16fbc51f..b6a62788 100644 --- a/compiler/base/utils.py +++ b/compiler/base/utils.py @@ -96,10 +96,10 @@ def get_libcell_size(name, units, lpp): Open a GDS file and return the library cell size from either the bounding box or a border layer. """ - if not OPTS.netlist_only: - cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" - return(get_gds_size(name, cell_gds, units, lpp)) - return (0,0,) + + cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" + return(get_gds_size(name, cell_gds, units, lpp)) + def get_gds_pins(pin_names, name, gds_filename, units): @@ -130,11 +130,9 @@ def get_libcell_pins(pin_list, name, units): Open a GDS file and find the pins in pin_list as text on a given layer. Return these as a rectangle layer pair for each pin. """ - if not OPTS.netlist_only: - cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" - return(get_gds_pins(pin_list, name, cell_gds, units)) - else: - return + + cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" + return(get_gds_pins(pin_list, name, cell_gds, units)) diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index 5b552832..a2ae66bf 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -81,8 +81,11 @@ class bitcell(bitcell_base.bitcell_base): def get_wl_name(self, port=0): """Get wl name""" - debug.check(port == 0, "One port for bitcell only.") - return "wl" + if cell_properties.bitcell.split_wl: + return "wl{}".format(port) + else: + debug.check(port == 0, "One port for bitcell only.") + return "wl" def build_graph(self, graph, inst_name, port_nets): """ diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py index 2f804bf0..e67ce118 100644 --- a/compiler/bitcells/replica_bitcell.py +++ b/compiler/bitcells/replica_bitcell.py @@ -8,7 +8,8 @@ import design import debug import utils -from tech import GDS,layer,drc,parameter +from tech import GDS,layer,drc,parameter,cell_properties +from globals import OPTS class replica_bitcell(design.design): """ @@ -17,10 +18,19 @@ class replica_bitcell(design.design): is a hand-made cell, so the layout and netlist should be available in the technology library. """ - pin_names = ["bl", "br", "wl", "vdd", "gnd"] + if cell_properties.bitcell.split_wl: + pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] + else: + pin_names = ["bl", "br", "wl", "vdd", "gnd"] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] - (width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"]) - pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"]) + + if not OPTS.netlist_only: + (width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"]) + else: + (width,height) = (0,0) + pin_map = [] def __init__(self, name=""): # Ignore the name argument diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 178c2f91..a8b3ec30 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -158,7 +158,7 @@ class replica_bitcell_array(design.design): # Left port WLs (one dummy for each port when we allow >1 port) for port in range(self.left_rbl): # Make names for all RBLs - wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.all_ports))] + wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))] # Keep track of the pin that is the RBL self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]] self.replica_col_wl_names.extend(wl_names) @@ -167,7 +167,7 @@ class replica_bitcell_array(design.design): # Right port WLs (one dummy for each port when we allow >1 port) for port in range(self.left_rbl,self.left_rbl+self.right_rbl): # Make names for all RBLs - wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.all_ports))] + wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))] # Keep track of the pin that is the RBL self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]] self.replica_col_wl_names.extend(wl_names) diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index e77d577f..ac3a859c 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -9,6 +9,7 @@ import design import debug import utils from tech import GDS,layer, parameter,drc +from globals import OPTS import logical_effort class sense_amp(design.design): @@ -21,8 +22,12 @@ class sense_amp(design.design): pin_names = ["bl", "br", "dout", "en", "vdd", "gnd"] type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] - (width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"]) - pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"]) + if not OPTS.netlist_only: + (width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"]) + else: + (width, height) = (0,0) + pin_map = [] def __init__(self, name): design.design.__init__(self, name) diff --git a/compiler/modules/write_driver.py b/compiler/modules/write_driver.py index 85a58fd5..11b14f00 100644 --- a/compiler/modules/write_driver.py +++ b/compiler/modules/write_driver.py @@ -8,6 +8,7 @@ import debug import design import utils +from globals import OPTS from tech import GDS,layer class write_driver(design.design): @@ -20,8 +21,12 @@ class write_driver(design.design): pin_names = ["din", "bl", "br", "en", "vdd", "gnd"] type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] - (width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"]) - pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"]) + if not OPTS.netlist_only: + (width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"]) + else: + (width,height) = (0,0) + pin_map = [] def __init__(self, name): design.design.__init__(self, name) diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index 20c8299e..3a7e6d39 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -23,10 +23,7 @@ class sram_config: # This will get over-written when we determine the organization self.words_per_row = words_per_row - if not OPTS.netlist_only: - self.compute_sizes() - else: - self.compute_simple_sram_sizes() + self.compute_sizes() @@ -38,15 +35,6 @@ class sram_config: # Copy all the variables to the local module for member in members: setattr(module,member,getattr(self,member)) - - def compute_simple_sram_sizes(self): - self.row_addr_size = int(log(OPTS.num_words, 2)) - self.col_addr_size = int(log(OPTS.word_size, 2)) - self.words_per_row = 1 - self.num_rows = OPTS.num_words - self.num_cols = OPTS.word_size - self.bank_addr_size = self.col_addr_size + self.row_addr_size - self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2)) def compute_sizes(self): """ Computes the organization of the memory using bitcell size by trying to make it square.""" From 7038fad9301e3229364feb084233bb074cafdd91 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sun, 9 Feb 2020 23:10:33 -0800 Subject: [PATCH 141/521] s8 gdsless netlist only working up to pdriver --- compiler/modules/custom_module_properties.py | 27 ++++++++++++++++++++ compiler/modules/dff_buf.py | 9 +++++-- compiler/modules/dff_buf_array.py | 14 +++++++--- 3 files changed, 45 insertions(+), 5 deletions(-) diff --git a/compiler/modules/custom_module_properties.py b/compiler/modules/custom_module_properties.py index e27741ea..768a8c18 100644 --- a/compiler/modules/custom_module_properties.py +++ b/compiler/modules/custom_module_properties.py @@ -13,17 +13,44 @@ class _dff: self.custom_type_list = custom_type_list self.clk_pin = clk_pin +class _dff_buff: + def __init__(self, use_custom_ports, custom_buff_ports, add_body_contacts): + self.use_custom_ports = use_custom_ports + self.buf_ports = custom_buff_ports + self.add_body_contacts = add_body_contacts + +class _dff_buff_array: + def __init__(self, use_custom_ports, add_body_contacts): + self.use_custom_ports = use_custom_ports + self.add_body_contacts = add_body_contacts + class module_properties(): """ TODO """ def __init__(self): self.names = {} + self._dff = _dff(use_custom_ports = False, custom_port_list = ["D", "Q", "clk", "vdd", "gnd"], custom_type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"], clk_pin= "clk") + + self._dff_buff = _dff_buff(use_custom_ports = False, + custom_buff_ports = ["D", "qint", "clk", "vdd", "gnd"], + add_body_contacts = False) + + self._dff_buff_array = _dff_buff_array(use_custom_ports = False, + add_body_contacts = False) @property def dff(self): return self._dff + + @property + def dff_buff(self): + return self._dff_buff + + @property + def dff_buff_array(self): + return self._dff_buff_array \ No newline at end of file diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 9e2ff0aa..d2698b34 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -7,7 +7,7 @@ # import debug import design -from tech import drc,parameter +from tech import drc,parameter,module_properties from math import log from vector import vector from globals import OPTS @@ -82,10 +82,15 @@ class dff_buf(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") + if module_properties.dff_buff.add_body_contacts: + self.add_pin("vpb", "INPUT") + self.add_pin("vpn", "INPUT") + def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) + self.connect_inst(module_properties.dff_buff.buf_ports) + #self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1", mod=self.inv1) diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 8b8e21dc..326fdda1 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -7,7 +7,7 @@ # import debug import design -from tech import drc +from tech import drc, module_properties from math import log from vector import vector from globals import OPTS @@ -64,6 +64,10 @@ class dff_buf_array(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") + if module_properties.dff_buff_array.add_body_contacts: + self.add_pin("vpb", "INPUT") + self.add_pin("vnb", "INPUT") + def add_modules(self): self.dff = factory.create(module_type="dff_buf", inv1_size=self.inv1_size, @@ -77,12 +81,16 @@ class dff_buf_array(design.design): name = "dff_r{0}_c{1}".format(row,col) self.dff_insts[row,col]=self.add_inst(name=name, mod=self.dff) - self.connect_inst([self.get_din_name(row,col), + inst_ports = [self.get_din_name(row,col), self.get_dout_name(row,col), self.get_dout_bar_name(row,col), "clk", "vdd", - "gnd"]) + "gnd"] + if module_properties.dff_buff_array.add_body_contacts: + inst_ports.append("vpb") + inst_ports.append("vnb") + self.connect_inst(inst_ports) def place_dff_array(self): for row in range(self.rows): From 27eced1fbe0729c764117379c992cae405d14ada Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sun, 9 Feb 2020 23:51:01 -0800 Subject: [PATCH 142/521] netlist_only done --- compiler/bitcells/bitcell.py | 5 +++-- compiler/bitcells/replica_bitcell.py | 4 ++-- compiler/modules/control_logic.py | 8 ++++++-- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index a2ae66bf..49fdf19f 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -25,11 +25,12 @@ class bitcell(bitcell_base.bitcell_base): if cell_properties.bitcell.split_wl: pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] else: pin_names = ["bl", "br", "wl", "vdd", "gnd"] - + type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Qbar'] - type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] + (width, height) = utils.get_libcell_size("cell_6t", GDS["unit"], layer["boundary"]) diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py index e67ce118..a869e4b7 100644 --- a/compiler/bitcells/replica_bitcell.py +++ b/compiler/bitcells/replica_bitcell.py @@ -20,10 +20,10 @@ class replica_bitcell(design.design): if cell_properties.bitcell.split_wl: pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"] else: pin_names = ["bl", "br", "wl", "vdd", "gnd"] - - type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] if not OPTS.netlist_only: (width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"]) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index dbb7c3b7..fa11e30b 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -7,7 +7,7 @@ # from math import log import design -from tech import drc, parameter +from tech import drc, parameter, module_properties import debug import contact from sram_factory import factory @@ -742,7 +742,11 @@ class control_logic(design.design): def create_dffs(self): self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", mod=self.ctrl_dff_array) - self.connect_inst(self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list) + inst_pins = self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list + if module_properties.dff_buff_array.add_body_contacts: + inst_pins.append("vpb") + inst_pins.append("vnb") + self.connect_inst(inst_pins) def place_dffs(self): self.ctrl_dff_inst.place(vector(0,0)) From 101eb281126f6dd3fd1897ed0a4ebb3ac2f6372b Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sun, 9 Feb 2020 23:52:11 -0800 Subject: [PATCH 143/521] revert example scn4m to non netlist only --- compiler/example_configs/example_config_scn4m_subm.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/example_configs/example_config_scn4m_subm.py b/compiler/example_configs/example_config_scn4m_subm.py index a55122a2..71ef328b 100644 --- a/compiler/example_configs/example_config_scn4m_subm.py +++ b/compiler/example_configs/example_config_scn4m_subm.py @@ -9,7 +9,6 @@ temperatures = [25] route_supplies = True check_lvsdrc = True -netlist_only = True output_path = "temp" output_name = "sram_{0}_{1}_{2}".format(word_size, From f7915ec55e687adade51973fd22576563c2c3639 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 10 Feb 2020 17:12:39 +0000 Subject: [PATCH 144/521] Route to top of NMOS to prevent poly overlap nmos --- compiler/pgates/pgate.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index e0401726..6d385d09 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -79,8 +79,8 @@ class pgate(design.design): debug.check(nmos_gate_pin.ll().x == pmos_gate_pin.ll().x, "Connecting unaligned gates not supported. See unaligned_gates.gds.") - # Pick point on the left of NMOS and connect down to PMOS - nmos_gate_pos = nmos_gate_pin.ll() + vector(0.5 * self.poly_width, 0) + # Pick point on the left of NMOS and up to PMOS + nmos_gate_pos = nmos_gate_pin.ul() + vector(0.5 * self.poly_width, 0) pmos_gate_pos = vector(nmos_gate_pos.x, pmos_gate_pin.bc().y) self.add_path("poly", [nmos_gate_pos, pmos_gate_pos]) From 6bf33a980fd357f94516dd446f19e2239a21ed4b Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 10 Feb 2020 19:28:30 +0000 Subject: [PATCH 145/521] Add conservative well spacing between library FF and our pgates. --- compiler/modules/dff_buf.py | 10 +++++++--- compiler/modules/dff_buf_array.py | 10 ++++++++-- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 9e2ff0aa..82f567e6 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -49,10 +49,11 @@ class dff_buf(design.design): self.create_instances() def create_layout(self): - self.width = self.dff.width + self.inv1.width + self.inv2.width + self.place_instances() + self.width = self.inv2_inst.rx() self.height = self.dff.height - self.place_instances() + self.route_wires() self.add_layout_pins() self.add_boundary() @@ -100,7 +101,10 @@ class dff_buf(design.design): self.dff_inst.place(vector(0,0)) # Add INV1 to the right - self.inv1_inst.place(vector(self.dff_inst.rx(),0)) + well_spacing = max(self.nwell_space, + self.pwell_space, + self.pwell_to_nwell) + self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing + self.well_extend_active,0)) # Add INV2 to the right self.inv2_inst.place(vector(self.inv1_inst.rx(),0)) diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 8b8e21dc..67c7522f 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -70,6 +70,12 @@ class dff_buf_array(design.design): inv2_size=self.inv2_size) self.add_mod(self.dff) + well_spacing = max(self.nwell_space, + self.pwell_space, + self.pwell_to_nwell) + + self.dff_pitch = self.dff.width + well_spacing + self.well_extend_active + def create_dff_array(self): self.dff_insts={} for row in range(self.rows): @@ -89,10 +95,10 @@ class dff_buf_array(design.design): for col in range(self.columns): name = "Xdff_r{0}_c{1}".format(row,col) if (row % 2 == 0): - base = vector(col*self.dff.width,row*self.dff.height) + base = vector(col*self.dff_pitch,row*self.dff.height) mirror = "R0" else: - base = vector(col*self.dff.width,(row+1)*self.dff.height) + base = vector(col*self.dff_pitch,(row+1)*self.dff.height) mirror = "MX" self.dff_insts[row,col].place(offset=base, mirror=mirror) From 0ef06ec1e14c07948c54d5012d050988e1ce6f3f Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 10 Feb 2020 20:06:34 +0000 Subject: [PATCH 146/521] Fix dff_buf width in netlist_only mode --- compiler/modules/dff_buf_array.py | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 67c7522f..4f2140c4 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -70,11 +70,6 @@ class dff_buf_array(design.design): inv2_size=self.inv2_size) self.add_mod(self.dff) - well_spacing = max(self.nwell_space, - self.pwell_space, - self.pwell_to_nwell) - - self.dff_pitch = self.dff.width + well_spacing + self.well_extend_active def create_dff_array(self): self.dff_insts={} @@ -91,14 +86,21 @@ class dff_buf_array(design.design): "gnd"]) def place_dff_array(self): + + well_spacing = max(self.nwell_space, + self.pwell_space, + self.pwell_to_nwell) + + dff_pitch = self.dff.width + well_spacing + self.well_extend_active + for row in range(self.rows): for col in range(self.columns): name = "Xdff_r{0}_c{1}".format(row,col) if (row % 2 == 0): - base = vector(col*self.dff_pitch,row*self.dff.height) + base = vector(col*dff_pitch,row*self.dff.height) mirror = "R0" else: - base = vector(col*self.dff_pitch,(row+1)*self.dff.height) + base = vector(col*dff_pitch,(row+1)*self.dff.height) mirror = "MX" self.dff_insts[row,col].place(offset=base, mirror=mirror) From aedbc5f9689ba1b8fd4577b77f4f41b9a04b67d9 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 12 Feb 2020 04:09:40 +0000 Subject: [PATCH 147/521] merge custom cell and module properties --- .../custom_cell_properties.py} | 23 ++++++++++++-- compiler/bitcells/custom_cell_properties.py | 30 ------------------- compiler/modules/control_logic.py | 5 ++-- compiler/modules/dff.py | 10 +++---- compiler/modules/dff_buf.py | 7 +++-- compiler/modules/dff_buf_array.py | 7 +++-- technology/freepdk45/tech/tech.py | 4 +-- technology/scn4m_subm/tech/tech.py | 2 -- 8 files changed, 38 insertions(+), 50 deletions(-) rename compiler/{modules/custom_module_properties.py => base/custom_cell_properties.py} (79%) delete mode 100644 compiler/bitcells/custom_cell_properties.py diff --git a/compiler/modules/custom_module_properties.py b/compiler/base/custom_cell_properties.py similarity index 79% rename from compiler/modules/custom_module_properties.py rename to compiler/base/custom_cell_properties.py index 768a8c18..ed00d443 100644 --- a/compiler/modules/custom_module_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -5,6 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +class _mirror_axis: + def __init__(self, x, y): + self.x = x + self.y = y + +class _bitcell: + def __init__(self, mirror, split_wl): + self.mirror = mirror + self.split_wl = split_wl class _dff: def __init__(self, use_custom_ports, custom_port_list, custom_type_list, clk_pin): @@ -24,13 +33,16 @@ class _dff_buff_array: self.use_custom_ports = use_custom_ports self.add_body_contacts = add_body_contacts -class module_properties(): +class cell_properties(): """ TODO """ def __init__(self): self.names = {} - + + self._bitcell = _bitcell(mirror = _mirror_axis(True, False), + split_wl = False) + self._dff = _dff(use_custom_ports = False, custom_port_list = ["D", "Q", "clk", "vdd", "gnd"], custom_type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"], @@ -43,6 +55,10 @@ class module_properties(): self._dff_buff_array = _dff_buff_array(use_custom_ports = False, add_body_contacts = False) + @property + def bitcell(self): + return self._bitcell + @property def dff(self): return self._dff @@ -53,4 +69,5 @@ class module_properties(): @property def dff_buff_array(self): - return self._dff_buff_array \ No newline at end of file + return self._dff_buff_array + diff --git a/compiler/bitcells/custom_cell_properties.py b/compiler/bitcells/custom_cell_properties.py deleted file mode 100644 index e795f6d7..00000000 --- a/compiler/bitcells/custom_cell_properties.py +++ /dev/null @@ -1,30 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2020 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# - -class _mirror_axis: - def __init__(self, x, y): - self.x = x - self.y = y - -class _bitcell: - def __init__(self, mirror, split_wl): - self.mirror = mirror - self.split_wl = split_wl - -class cell_properties(): - """ - TODO - """ - def __init__(self): - self.names = {} - self._bitcell = _bitcell(mirror = _mirror_axis(True, False), - split_wl = False) - - @property - def bitcell(self): - return self._bitcell diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index fa11e30b..e22d05b3 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -7,7 +7,8 @@ # from math import log import design -from tech import drc, parameter, module_properties +from tech import drc, parameter +from tech import cell_properties as props import debug import contact from sram_factory import factory @@ -743,7 +744,7 @@ class control_logic(design.design): self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", mod=self.ctrl_dff_array) inst_pins = self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list - if module_properties.dff_buff_array.add_body_contacts: + if props.dff_buff_array.add_body_contacts: inst_pins.append("vpb") inst_pins.append("vnb") self.connect_inst(inst_pins) diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 45d20a62..e319459e 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -7,7 +7,7 @@ # import design from tech import GDS, layer, spice, parameter -from tech import module_properties +from tech import cell_properties as props import utils @@ -15,14 +15,14 @@ class dff(design.design): """ Memory address flip-flop """ - if not module_properties.dff.use_custom_ports: + if not props.dff.use_custom_ports: pin_names = ["D", "Q", "clk", "vdd", "gnd"] type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] clk_pin = "clk" else: - pin_names = module_properties.dff.custom_port_list - type_list = module_properties.dff.custom_type_list - clk_pin = module_properties.dff.clk_pin + pin_names = props.dff.custom_port_list + type_list = props.dff.custom_type_list + clk_pin = props.dff.clk_pin (width, height) = utils.get_libcell_size("dff", GDS["unit"], diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index d2698b34..1fba563b 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -7,7 +7,8 @@ # import debug import design -from tech import drc,parameter,module_properties +from tech import drc,parameter +from tech import cell_properties as props from math import log from vector import vector from globals import OPTS @@ -82,14 +83,14 @@ class dff_buf(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - if module_properties.dff_buff.add_body_contacts: + if props.dff_buff.add_body_contacts: self.add_pin("vpb", "INPUT") self.add_pin("vpn", "INPUT") def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - self.connect_inst(module_properties.dff_buff.buf_ports) + self.connect_inst(props.dff_buff.buf_ports) #self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1", diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 326fdda1..770675bf 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -7,7 +7,8 @@ # import debug import design -from tech import drc, module_properties +from tech import drc +from tech import cell_properties as props from math import log from vector import vector from globals import OPTS @@ -64,7 +65,7 @@ class dff_buf_array(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - if module_properties.dff_buff_array.add_body_contacts: + if props.dff_buff_array.add_body_contacts: self.add_pin("vpb", "INPUT") self.add_pin("vnb", "INPUT") @@ -87,7 +88,7 @@ class dff_buf_array(design.design): "clk", "vdd", "gnd"] - if module_properties.dff_buff_array.add_body_contacts: + if props.dff_buff_array.add_body_contacts: inst_ports.append("vpb") inst_ports.append("vnb") self.connect_inst(inst_ports) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index f91be16c..c2bf135f 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -9,7 +9,7 @@ import os from design_rules import * from module_type import * from custom_cell_properties import cell_properties -from custom_module_properties import module_properties + """ File containing the process technology parameters for FreePDK 45nm. """ @@ -25,7 +25,7 @@ File containing the process technology parameters for FreePDK 45nm. # For example: tech_modules['contact'] = 'contact_freepdk45' tech_modules = module_type() -module_properties = module_properties() + ################################################### # Custom cell properties ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index bb379478..7c360d38 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -9,7 +9,6 @@ import os from design_rules import * from module_type import * from custom_cell_properties import cell_properties -from custom_module_properties import module_properties """ File containing the process technology parameters for SCMOS 4m, 0.35um @@ -25,7 +24,6 @@ File containing the process technology parameters for SCMOS 4m, 0.35um # implementation in '$OPENRAM_TECHDIR/modules/' # For example: tech_modules['contact'] = 'contact_scn4m' tech_modules = module_type() -module_properties = module_properties() ################################################### # Custom cell properties From 64bf93e4e584fc4590eb63e23198961ee3cc6546 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 12 Feb 2020 13:19:41 +0100 Subject: [PATCH 148/521] bank: Connect instances by their individual bl/br names each module should be able to state how their bl/br lines are named. Here we always connect port_data with the bitcell_array, so port_data needs function that return the names of bl/br. Signed-off-by: Bastian Koppelmann --- compiler/modules/bank.py | 10 +++++++--- compiler/modules/port_data.py | 14 ++++++++++++++ compiler/pgates/precharge.py | 6 ++++++ 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 133a66c2..f5f3feb6 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -679,9 +679,13 @@ class bank(design.design): inst1 = self.bitcell_array_inst inst1_bl_name = self.bl_names[port]+"_{}" inst1_br_name = self.br_names[port]+"_{}" + + inst2_bl_name = inst2.mod.get_bl_names()+"_{}" + inst2_br_name = inst2.mod.get_br_names()+"_{}" self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols, - inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name) + inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, + inst2_bl_name=inst2_bl_name, inst2_br_name=inst2_br_name) # Connect the replica bitlines rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) @@ -786,8 +790,8 @@ class bank(design.design): def connect_bitlines(self, inst1, inst2, num_bits, - inst1_bl_name="bl_{}", inst1_br_name="br_{}", - inst2_bl_name="bl_{}", inst2_br_name="br_{}"): + inst1_bl_name, inst1_br_name, + inst2_bl_name, inst2_br_name): """ Connect the bl and br of two modules. """ diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 9e7f4048..0355fd3c 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -38,6 +38,15 @@ class port_data(design.design): self.create_layout() self.add_boundary() + def get_bl_names(self): + # bl lines are connect from the precharger + return self.precharge.get_bl_names() + + def get_br_names(self): + # br lines are connect from the precharger + return self.precharge.get_br_names() + + def create_netlist(self): self.precompute_constants() @@ -221,6 +230,11 @@ class port_data(design.design): self.bl_names = self.bitcell.get_all_bl_names() self.br_names = self.bitcell.get_all_br_names() self.wl_names = self.bitcell.get_all_wl_names() + # used for bl/br names + self.precharge = factory.create(module_type="precharge", + bitcell_bl = self.bl_names[0], + bitcell_br = self.br_names[0]) + def create_precharge_array(self): """ Creating Precharge """ diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 28b4d85a..acb2062f 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -38,6 +38,12 @@ class precharge(design.design): self.create_layout() self.DRC_LVS() + def get_bl_names(self): + return "bl" + + def get_br_names(self): + return "br" + def create_netlist(self): self.add_pins() self.add_ptx() From f9babcf6667aafda662c51447b2a83b9a42ab9ea Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 12 Feb 2020 14:04:05 +0100 Subject: [PATCH 149/521] port_data: Each submodule now specifies their bl/br names before the names of bl/br from the bitcell were assumed. If we want to allow renaming of bl/br from bitcells, we have to seperate the other modules from that. Note, that we don't touch every occurence of bl/br, but only the once necessary that pin renaming of the bitcell works. Signed-off-by: Bastian Koppelmann --- compiler/modules/port_data.py | 53 +++++++++++++------ compiler/modules/precharge_array.py | 15 ++++++ compiler/modules/sense_amp.py | 6 +++ compiler/modules/sense_amp_array.py | 14 +++++ .../modules/single_level_column_mux_array.py | 15 ++++++ compiler/modules/write_driver.py | 6 +++ compiler/modules/write_driver_array.py | 13 +++++ compiler/pgates/single_level_column_mux.py | 6 +++ 8 files changed, 112 insertions(+), 16 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 0355fd3c..d1c2c671 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -94,8 +94,10 @@ class port_data(design.design): self.add_pin("rbl_bl","INOUT") self.add_pin("rbl_br","INOUT") for bit in range(self.num_cols): - self.add_pin("{0}_{1}".format(self.bl_names[self.port], bit),"INOUT") - self.add_pin("{0}_{1}".format(self.br_names[self.port], bit),"INOUT") + bl_name = self.precharge_array.get_bl_name(self.port) + br_name = self.precharge_array.get_br_name(self.port) + self.add_pin("{0}_{1}".format(bl_name, bit),"INOUT") + self.add_pin("{0}_{1}".format(br_name, bit),"INOUT") if self.port in self.read_ports: for bit in range(self.word_size): self.add_pin("dout_{}".format(bit),"OUTPUT") @@ -234,6 +236,13 @@ class port_data(design.design): self.precharge = factory.create(module_type="precharge", bitcell_bl = self.bl_names[0], bitcell_br = self.br_names[0]) + # We create a dummy here to get bl/br names to add those pins to this + # module, which happens before we create the real precharge_array + self.precharge_array = factory.create(module_type="precharge_array", + columns=self.num_cols + 1, + bitcell_bl=self.bl_names[self.port], + bitcell_br=self.br_names[self.port]) + def create_precharge_array(self): @@ -244,6 +253,8 @@ class port_data(design.design): self.precharge_array_inst = self.add_inst(name="precharge_array{}".format(self.port), mod=self.precharge_array) + bl_name = self.precharge_array.get_bl_name(self.port) + br_name = self.precharge_array.get_br_name(self.port) temp = [] # Use left BLs for RBL @@ -251,8 +262,9 @@ class port_data(design.design): temp.append("rbl_bl") temp.append("rbl_br") for bit in range(self.num_cols): - temp.append(self.bl_names[self.port]+"_{0}".format(bit)) - temp.append(self.br_names[self.port]+"_{0}".format(bit)) + temp.append("{0}_{1}".format(bl_name, bit)) + temp.append("{0}_{1}".format(br_name, bit)) + # Use right BLs for RBL if self.port==1: temp.append("rbl_bl") @@ -273,15 +285,19 @@ class port_data(design.design): self.column_mux_array_inst = self.add_inst(name="column_mux_array{}".format(self.port), mod=self.column_mux_array) + bl_name = self.column_mux_array.get_bl_name(self.port) + br_name = self.column_mux_array.get_br_name(self.port) temp = [] for col in range(self.num_cols): - temp.append(self.bl_names[self.port]+"_{0}".format(col)) - temp.append(self.br_names[self.port]+"_{0}".format(col)) + temp.append("{0}_{1}".format(bl_name, col)) + temp.append("{0}_{1}".format(br_name, col)) + for word in range(self.words_per_row): temp.append("sel_{}".format(word)) for bit in range(self.word_size): - temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) - temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) + temp.append("{0}_out_{1}".format(bl_name, bit)) + temp.append("{0}_out_{1}".format(br_name, bit)) + temp.append("gnd") self.connect_inst(temp) @@ -299,15 +315,18 @@ class port_data(design.design): self.sense_amp_array_inst = self.add_inst(name="sense_amp_array{}".format(self.port), mod=self.sense_amp_array) + bl_name = self.sense_amp_array.get_bl_name(self.port) + br_name = self.sense_amp_array.get_br_name(self.port) temp = [] for bit in range(self.word_size): temp.append("dout_{}".format(bit)) if self.words_per_row == 1: - temp.append(self.bl_names[self.port]+"_{0}".format(bit)) - temp.append(self.br_names[self.port]+"_{0}".format(bit)) + temp.append("{0}_{1}".format(bl_name, bit)) + temp.append("{0}_{1}".format(br_name, bit)) else: - temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) - temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) + temp.append("{0}_out_{1}".format(bl_name, bit)) + temp.append("{0}_out_{1}".format(br_name, bit)) + temp.extend(["s_en", "vdd", "gnd"]) self.connect_inst(temp) @@ -322,6 +341,8 @@ class port_data(design.design): """ Creating Write Driver """ self.write_driver_array_inst = self.add_inst(name="write_driver_array{}".format(self.port), mod=self.write_driver_array) + bl_name = self.write_driver_array.get_bl_name(self.port) + br_name = self.write_driver_array.get_br_name(self.port) temp = [] for bit in range(self.word_size): @@ -329,11 +350,11 @@ class port_data(design.design): for bit in range(self.word_size): if (self.words_per_row == 1): - temp.append(self.bl_names[self.port] + "_{0}".format(bit)) - temp.append(self.br_names[self.port] + "_{0}".format(bit)) + temp.append("{0}_{1}".format(bl_name, bit)) + temp.append("{0}_{1}".format(br_name, bit)) else: - temp.append(self.bl_names[self.port] + "_out_{0}".format(bit)) - temp.append(self.br_names[self.port] + "_out_{0}".format(bit)) + temp.append("{0}_out_{1}".format(bl_name, bit)) + temp.append("{0}_out_{1}".format(br_name, bit)) if self.write_size is not None: for i in range(self.num_wmasks): diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 54ed2690..5ac97b4d 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -32,6 +32,21 @@ class precharge_array(design.design): if not OPTS.netlist_only: self.create_layout() + def get_bl_name(self, port=0): + bl_name = self.pc_cell.get_bl_names() + if len(self.all_ports) == 1: + return bl_name + else: + return bl_name + "{}".format(port) + + def get_br_name(self, port=0): + br_name = self.pc_cell.get_br_names() + if len(self.all_ports) == 1: + return br_name + else: + return br_name + "{}".format(port) + + def add_pins(self): """Adds pins for spice file""" for i in range(self.columns): diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index ac3a859c..eb624111 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -29,6 +29,12 @@ class sense_amp(design.design): (width, height) = (0,0) pin_map = [] + def get_bl_names(self): + return "bl" + + def get_br_names(self): + return "br" + def __init__(self, name): design.design.__init__(self, name) debug.info(2, "Create sense_amp") diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 44639017..8ac5146c 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -34,6 +34,20 @@ class sense_amp_array(design.design): self.create_layout() + def get_bl_name(self, port=0): + bl_name = self.amp.get_bl_names() + if len(self.all_ports) == 1: + return bl_name + else: + return bl_name + "{}".format(port) + + def get_br_name(self, port=0): + br_name = self.amp.get_br_names() + if len(self.all_ports) == 1: + return br_name + else: + return br_name + "{}".format(port) + def create_netlist(self): self.add_modules() self.add_pins() diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 24510015..1c181574 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -37,6 +37,21 @@ class single_level_column_mux_array(design.design): if not OPTS.netlist_only: self.create_layout() + def get_bl_name(self, port=0): + bl_name = self.mux.get_bl_names() + if len(self.all_ports) == 1: + return bl_name + else: + return bl_name + "{}".format(port) + + def get_br_name(self, port=0): + br_name = self.mux.get_br_names() + if len(self.all_ports) == 1: + return br_name + else: + return br_name + "{}".format(port) + + def create_netlist(self): self.add_modules() self.add_pins() diff --git a/compiler/modules/write_driver.py b/compiler/modules/write_driver.py index 11b14f00..db08bcf4 100644 --- a/compiler/modules/write_driver.py +++ b/compiler/modules/write_driver.py @@ -37,6 +37,12 @@ class write_driver(design.design): self.pin_map = write_driver.pin_map self.add_pin_types(self.type_list) + def get_bl_names(self): + return "bl" + + def get_br_names(self): + return "br" + def get_w_en_cin(self): """Get the relative capacitance of a single input""" # This is approximated from SCMOS. It has roughly 5 3x transistor gates. diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index e9b0ac1b..dd7430a9 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -37,6 +37,19 @@ class write_driver_array(design.design): if not OPTS.netlist_only: self.create_layout() + def get_bl_name(self, port=0): + bl_name = self.driver.get_bl_names() + if len(self.all_ports) == 1: + return bl_name + else: + return bl_name + "{}".format(port) + + def get_br_name(self, port=0): + br_name = self.driver.get_br_names() + if len(self.all_ports) == 1: + return br_name + else: + return br_name + "{}".format(port) def create_netlist(self): self.add_modules() diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 66faf1da..90645326 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -31,6 +31,12 @@ class single_level_column_mux(pgate.pgate): pgate.pgate.__init__(self, name) + def get_bl_names(self): + return "bl" + + def get_br_names(self): + return "br" + def create_netlist(self): self.add_modules() self.add_pins() From f6302caeac85bcaf8b332cdc007363d093d60f57 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 12 Feb 2020 14:17:29 +0100 Subject: [PATCH 150/521] replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names this allows us to override the bl/br/wl names of each bitcell. Signed-off-by: Bastian Koppelmann --- compiler/modules/bitcell_base_array.py | 26 ++++++++++++++ compiler/modules/replica_bitcell_array.py | 41 ++++++++++++----------- 2 files changed, 47 insertions(+), 20 deletions(-) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 08a52c21..45bcfe0c 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -22,6 +22,32 @@ class bitcell_base_array(design.design): self.row_size = rows self.column_offset = column_offset + def get_all_bitline_names(self): + + res = list() + bitline_names = self.cell.get_all_bitline_names() + + # We have to keep the order of self.pins, otherwise we connect + # it wrong in the spice netlist + for pin in self.pins: + for bl_name in bitline_names: + if bl_name in pin: + res.append(pin) + return res + + def get_all_wordline_names(self): + + res = list() + wordline_names = self.cell.get_all_wl_names() + + # We have to keep the order of self.pins, otherwise we connect + # it wrong in the spice netlist + for pin in self.pins: + for wl_name in wordline_names: + if wl_name in pin: + res.append(pin) + return res + def add_pins(self): row_list = self.cell.get_all_wl_names() column_list = self.cell.get_all_bitline_names() diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index a8b3ec30..d5865658 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -138,11 +138,10 @@ class replica_bitcell_array(design.design): def add_pins(self): + self.bitcell_array_wl_names = self.bitcell_array.get_all_wordline_names() + self.bitcell_array_bl_names = self.bitcell_array.get_all_bitline_names() - self.bitcell_array_wl_names = [x for x in self.bitcell_array.pins if x.startswith("w")] - self.bitcell_array_bl_names = [x for x in self.bitcell_array.pins if x.startswith("b")] - - # These are the non-indexed names + # These are the non-indexed names self.dummy_cell_wl_names = ["dummy_"+x for x in self.cell.get_all_wl_names()] self.dummy_cell_bl_names = ["dummy_"+x for x in self.cell.get_all_bitline_names()] self.dummy_row_bl_names = self.bitcell_array_bl_names @@ -316,22 +315,24 @@ class replica_bitcell_array(design.design): # Main array wl and bl/br pin_names = self.bitcell_array.get_pin_names() for pin_name in pin_names: - if pin_name.startswith("wl"): - pin_list = self.bitcell_array_inst.get_pins(pin_name) - for pin in pin_list: - self.add_layout_pin(text=pin_name, - layer=pin.layer, - offset=pin.ll().scale(0,1), - width=self.width, - height=pin.height()) - elif pin_name.startswith("bl") or pin_name.startswith("br"): - pin_list = self.bitcell_array_inst.get_pins(pin_name) - for pin in pin_list: - self.add_layout_pin(text=pin_name, - layer=pin.layer, - offset=pin.ll().scale(1,0), - width=pin.width(), - height=self.height) + for wl in self.bitcell_array_wl_names: + if wl in pin_name: + pin_list = self.bitcell_array_inst.get_pins(pin_name) + for pin in pin_list: + self.add_layout_pin(text=pin_name, + layer=pin.layer, + offset=pin.ll().scale(0,1), + width=self.width, + height=pin.height()) + for bitline in self.bitcell_array_bl_names: + if bitline in pin_name: + pin_list = self.bitcell_array_inst.get_pins(pin_name) + for pin in pin_list: + self.add_layout_pin(text=pin_name, + layer=pin.layer, + offset=pin.ll().scale(1,0), + width=pin.width(), + height=self.height) # Replica wordlines From c97bad72db9522f1fc624ea1249a63ea9fef4ca5 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 12 Feb 2020 15:03:47 +0100 Subject: [PATCH 151/521] custom_cell_properties: Add bitcell pin name API this allows users to overrride the pin names to match the names of their GDS. Signed-off-by: Bastian Koppelmann --- compiler/base/custom_cell_properties.py | 69 +++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 4 deletions(-) diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index ed00d443..45887561 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -5,15 +5,75 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # + +class _pins: + def __init__(self, pin_dict): + # make the pins elements of the class to allow "." access. + # For example: props.bitcell.cell_6t.pin.bl = "foobar" + for k,v in pin_dict.items(): + self.__dict__[k] = v + +class _cell: + def __init__(self, pin_dict): + pin_dict.update(self._default_power_pins()) + self._pins = _pins(pin_dict) + + @property + def pin(self): + return self._pins + + def _default_power_pins(self): + return { 'vdd' : 'vdd', 'gnd' : 'gnd' } + class _mirror_axis: def __init__(self, x, y): self.x = x self.y = y class _bitcell: - def __init__(self, mirror, split_wl): + def __init__(self, mirror, split_wl, cell_6t, cell_1rw1r, cell_1w1r): self.mirror = mirror self.split_wl = split_wl + self._6t = cell_6t + self._1rw1r = cell_1rw1r + self._1w1r = cell_1w1r + + def _default(): + axis = _mirror_axis(True, False) + cell_6t = _cell({'bl' : 'bl', + 'br' : 'br', + 'wl' : 'wl'}) + + cell_1rw1r = _cell({'bl0' : 'bl0', + 'br0' : 'br0', + 'bl1' : 'bl1', + 'br1' : 'br1', + 'wl0' : 'wl0', + 'wl1' : 'wl1'}) + cell_1w1r = _cell({'bl0' : 'bl0', + 'br0' : 'br0', + 'bl1' : 'bl1', + 'br1' : 'br1', + 'wl0' : 'wl0', + 'wl1' : 'wl1'}) + return _bitcell(cell_6t=cell_6t, + cell_1rw1r=cell_1rw1r, + cell_1w1r=cell_1w1r, + split_wl = False, + mirror=axis) + + @property + def cell_6t(self): + return self._6t + + @property + def cell_1rw1r(self): + return self._1rw1r + + @property + def cell_1w1r(self): + return self._1w1r + class _dff: def __init__(self, use_custom_ports, custom_port_list, custom_type_list, clk_pin): @@ -35,13 +95,14 @@ class _dff_buff_array: class cell_properties(): """ - TODO + This contains meta information about the custom designed cells. For + instance, pin names, or the axis on which they need to be mirrored. These + can be overriden in the tech.py file. """ def __init__(self): self.names = {} - self._bitcell = _bitcell(mirror = _mirror_axis(True, False), - split_wl = False) + self._bitcell = _bitcell._default() self._dff = _dff(use_custom_ports = False, custom_port_list = ["D", "Q", "clk", "vdd", "gnd"], From 87b5a48f9ecc52d2862e6e68933731aa83b832f7 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 12 Feb 2020 14:48:58 +0100 Subject: [PATCH 152/521] bitcell: Remove hardcoded signal pins use names provided by the tech file, which can be overriden by the technology. Signed-off-by: Bastian Koppelmann --- compiler/bitcells/bitcell.py | 49 +++++----- compiler/bitcells/bitcell_1rw_1r.py | 100 ++++++++++++-------- compiler/bitcells/bitcell_1w_1r.py | 96 +++++++++++-------- compiler/bitcells/dummy_bitcell.py | 7 +- compiler/bitcells/dummy_bitcell_1rw_1r.py | 11 ++- compiler/bitcells/dummy_bitcell_1w_1r.py | 10 +- compiler/bitcells/replica_bitcell.py | 11 ++- compiler/bitcells/replica_bitcell_1rw_1r.py | 24 +++-- compiler/bitcells/replica_bitcell_1w_1r.py | 22 +++-- 9 files changed, 207 insertions(+), 123 deletions(-) diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index 49fdf19f..68e70e7e 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -8,7 +8,7 @@ import debug import utils from tech import GDS, layer, parameter -from tech import cell_properties +from tech import cell_properties as props import bitcell_base @@ -22,15 +22,19 @@ class bitcell(bitcell_base.bitcell_base): # If we have a split WL bitcell, if not be backwards # compatible in the tech file - - if cell_properties.bitcell.split_wl: + + if props.bitcell.split_wl: pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] else: - pin_names = ["bl", "br", "wl", "vdd", "gnd"] + pin_names = [props.bitcell.cell_6t.pin.bl, + props.bitcell.cell_6t.pin.br, + props.bitcell.cell_6t.pin.wl, + props.bitcell.cell_6t.pin.vdd, + props.bitcell.cell_6t.pin.gnd] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Qbar'] - + (width, height) = utils.get_libcell_size("cell_6t", GDS["unit"], layer["boundary"]) @@ -46,48 +50,47 @@ class bitcell(bitcell_base.bitcell_base): self.pin_map = bitcell.pin_map self.add_pin_types(self.type_list) self.nets_match = self.do_nets_exist(self.storage_nets) - + def get_all_wl_names(self): """ Creates a list of all wordline pin names """ - if cell_properties.bitcell.split_wl: + if props.bitcell.split_wl: row_pins = ["wl0", "wl1"] else: - row_pins = ["wl"] + row_pins = [props.bitcell.cell_6t.pin.wl] return row_pins - + def get_all_bitline_names(self): """ Creates a list of all bitline pin names (both bl and br) """ - column_pins = ["bl", "br"] + pin = props.bitcell.cell_6t.pin + column_pins = [pin.bl, pin.br] return column_pins - + def get_all_bl_names(self): """ Creates a list of all bl pins names """ - column_pins = ["bl"] - return column_pins - + return [props.bitcell.cell_6t.pin.bl] + def get_all_br_names(self): """ Creates a list of all br pins names """ - column_pins = ["br"] - return column_pins - + return [props.bitcell.cell_6t.pin.br] + def get_bl_name(self, port=0): """Get bl name""" debug.check(port == 0, "One port for bitcell only.") - return "bl" - + return props.bitcell.cell_6t.pin.bl + def get_br_name(self, port=0): """Get bl name""" debug.check(port == 0, "One port for bitcell only.") - return "br" + return props.bitcell.cell_6t.pin.br def get_wl_name(self, port=0): """Get wl name""" - if cell_properties.bitcell.split_wl: + if props.bitcell.split_wl: return "wl{}".format(port) else: debug.check(port == 0, "One port for bitcell only.") - return "wl" - + return props.bitcell.cell_6t.pin.wl + def build_graph(self, graph, inst_name, port_nets): """ Adds edges based on inputs/outputs. diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py index 0280f3cb..e5eb3043 100644 --- a/compiler/bitcells/bitcell_1rw_1r.py +++ b/compiler/bitcells/bitcell_1rw_1r.py @@ -8,6 +8,7 @@ import debug import utils from tech import GDS, layer, parameter, drc +from tech import cell_properties as props import logical_effort import bitcell_base @@ -20,7 +21,15 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base): library. """ - pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"] + pin_names = [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.bl1, + props.bitcell.cell_1rw1r.pin.br1, + props.bitcell.cell_1rw1r.pin.wl0, + props.bitcell.cell_1rw1r.pin.wl1, + props.bitcell.cell_1rw1r.pin.vdd, + props.bitcell.cell_1rw1r.pin.gnd] + type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Q_bar'] @@ -39,85 +48,92 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base): self.pin_map = bitcell_1rw_1r.pin_map self.add_pin_types(self.type_list) self.nets_match = self.do_nets_exist(self.storage_nets) - + + pin_names = bitcell_1rw_1r.pin_names + self.bl_names = [pin_names[0], pin_names[2]] + self.br_names = [pin_names[1], pin_names[3]] + self.wl_names = [pin_names[4], pin_names[5]] + def get_bitcell_pins(self, col, row): """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ - bitcell_pins = ["bl0_{0}".format(col), - "br0_{0}".format(col), - "bl1_{0}".format(col), - "br1_{0}".format(col), - "wl0_{0}".format(row), - "wl1_{0}".format(row), + pin_name = props.bitcell.cell_1rw1r.pin + bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col), + "{0}_{1}".format(pin_name.br0, col), + "{0}_{1}".format(pin_name.bl1, col), + "{0}_{1}".format(pin_name.br1, col), + "{0}_{1}".format(pin_name.wl0, row), + "{0}_{1}".format(pin_name.wl1, row), "vdd", "gnd"] return bitcell_pins - + def get_all_wl_names(self): """ Creates a list of all wordline pin names """ - row_pins = ["wl0", "wl1"] - return row_pins - + return [props.bitcell.cell_1rw1r.pin.wl0, + props.bitcell.cell_1rw1r.pin.wl1] + def get_all_bitline_names(self): """ Creates a list of all bitline pin names (both bl and br) """ - column_pins = ["bl0", "br0", "bl1", "br1"] - return column_pins - + return [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.bl1, + props.bitcell.cell_1rw1r.pin.br1] + def get_all_bl_names(self): """ Creates a list of all bl pins names """ - column_pins = ["bl0", "bl1"] - return column_pins - + return [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.bl1] + def get_all_br_names(self): """ Creates a list of all br pins names """ - column_pins = ["br0", "br1"] - return column_pins - + return [props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.br1] + def get_read_bl_names(self): """ Creates a list of bl pin names associated with read ports """ - column_pins = ["bl0", "bl1"] - return column_pins - + return [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.bl1] + def get_read_br_names(self): """ Creates a list of br pin names associated with read ports """ - column_pins = ["br0", "br1"] - return column_pins - + return [props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.br1] + def get_write_bl_names(self): """ Creates a list of bl pin names associated with write ports """ - column_pins = ["bl0"] - return column_pins - + return [props.bitcell.cell_1rw1r.pin.bl0] + def get_write_br_names(self): """ Creates a list of br pin names asscociated with write ports""" - column_pins = ["br0"] - return column_pins - + return [props.bitcell.cell_1rw1r.pin.br1] + def get_bl_name(self, port=0): """Get bl name by port""" debug.check(port < 2, "Two ports for bitcell_1rw_1r only.") - return "bl{}".format(port) - + return self.bl_names[port] + def get_br_name(self, port=0): """Get bl name by port""" debug.check(port < 2, "Two ports for bitcell_1rw_1r only.") - return "br{}".format(port) + return self.br_names[port] def get_wl_name(self, port=0): """Get wl name by port""" debug.check(port < 2, "Two ports for bitcell_1rw_1r only.") - return "wl{}".format(port) - + return self.wl_names[port] + def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} # Edges hardcoded here. Essentially wl->bl/br for both ports. # Port 0 edges - graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self) - graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self) + pins = props.bitcell.cell_1rw1r.pin + graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self) + graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self) # Port 1 edges - graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self) - graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self) + graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self) + graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self) diff --git a/compiler/bitcells/bitcell_1w_1r.py b/compiler/bitcells/bitcell_1w_1r.py index a92dc75d..56bd0b45 100644 --- a/compiler/bitcells/bitcell_1w_1r.py +++ b/compiler/bitcells/bitcell_1w_1r.py @@ -8,6 +8,7 @@ import debug import utils from tech import GDS, layer +from tech import cell_properties as props import bitcell_base @@ -19,7 +20,14 @@ class bitcell_1w_1r(bitcell_base.bitcell_base): library. """ - pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"] + pin_names = [props.bitcell.cell_1w1r.pin.bl0, + props.bitcell.cell_1w1r.pin.br0, + props.bitcell.cell_1w1r.pin.bl1, + props.bitcell.cell_1w1r.pin.br1, + props.bitcell.cell_1w1r.pin.wl0, + props.bitcell.cell_1w1r.pin.wl1, + props.bitcell.cell_1w1r.pin.vdd, + props.bitcell.cell_1w1r.pin.gnd] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Q_bar'] @@ -39,80 +47,88 @@ class bitcell_1w_1r(bitcell_base.bitcell_base): self.add_pin_types(self.type_list) self.nets_match = self.do_nets_exist(self.storage_nets) + pin_names = bitcell_1w_1r.pin_names + self.bl_names = [pin_names[0], pin_names[2]] + self.br_names = [pin_names[1], pin_names[3]] + self.wl_names = [pin_names[4], pin_names[5]] + + def get_bitcell_pins(self, col, row): """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ - bitcell_pins = ["bl0_{0}".format(col), - "br0_{0}".format(col), - "bl1_{0}".format(col), - "br1_{0}".format(col), - "wl0_{0}".format(row), - "wl1_{0}".format(row), + pin_name = props.bitcell.cell_1w1r.pin + bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col), + "{0}_{1}".format(pin_name.br0, col), + "{0}_{1}".format(pin_name.bl1, col), + "{0}_{1}".format(pin_name.br1, col), + "{0}_{1}".format(pin_name.wl0, row), + "{0}_{1}".format(pin_name.wl1, row), "vdd", "gnd"] return bitcell_pins - + def get_all_wl_names(self): """ Creates a list of all wordline pin names """ - row_pins = ["wl0", "wl1"] - return row_pins - + return [props.bitcell.cell_1w1r.pin.wl0, + props.bitcell.cell_1w1r.pin.wl1] + def get_all_bitline_names(self): """ Creates a list of all bitline pin names (both bl and br) """ - column_pins = ["bl0", "br0", "bl1", "br1"] - return column_pins - + return [props.bitcell.cell_1w1r.pin.bl0, + props.bitcell.cell_1w1r.pin.br0, + props.bitcell.cell_1w1r.pin.bl1, + props.bitcell.cell_1w1r.pin.br1] + def get_all_bl_names(self): """ Creates a list of all bl pins names """ - column_pins = ["bl0", "bl1"] - return column_pins - + return [props.bitcell.cell_1w1r.pin.bl0, + props.bitcell.cell_1w1r.pin.bl1] + def get_all_br_names(self): """ Creates a list of all br pins names """ - column_pins = ["br0", "br1"] - return column_pins - + return [props.bitcell.cell_1w1r.pin.br0, + props.bitcell.cell_1w1r.pin.br1] + def get_read_bl_names(self): """ Creates a list of bl pin names associated with read ports """ - column_pins = ["bl0", "bl1"] - return column_pins - + return [props.bitcell.cell_1w1r.pin.bl0, + props.bitcell.cell_1w1r.pin.bl1] + def get_read_br_names(self): """ Creates a list of br pin names associated with read ports """ - column_pins = ["br0", "br1"] - return column_pins - + return [props.bitcell.cell_1w1r.pin.br0, + props.bitcell.cell_1w1r.pin.br1] + def get_write_bl_names(self): """ Creates a list of bl pin names associated with write ports """ - column_pins = ["bl0"] - return column_pins - + return [props.bitcell.cell_1w1r.pin.bl0] + def get_write_br_names(self): """ Creates a list of br pin names asscociated with write ports""" - column_pins = ["br0"] - return column_pins - + return [props.bitcell.cell_1w1r.pin.br1] + def get_bl_name(self, port=0): """Get bl name by port""" - return "bl{}".format(port) - + return self.bl_names[port] + def get_br_name(self, port=0): """Get bl name by port""" - return "br{}".format(port) - + return self.br_names[port] + def get_wl_name(self, port=0): """Get wl name by port""" debug.check(port < 2, "Two ports for bitcell_1rw_1r only.") - return "wl{}".format(port) - + return self.wl_names[port] + def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} + pins = props.bitcell.cell_1w1r.pin # Edges hardcoded here. Essentially wl->bl/br for both ports. # Port 0 edges - graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self) - graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self) + graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self) + graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self) # Port 1 is a write port, so its timing is not considered here. diff --git a/compiler/bitcells/dummy_bitcell.py b/compiler/bitcells/dummy_bitcell.py index 98da96e2..116ea3ed 100644 --- a/compiler/bitcells/dummy_bitcell.py +++ b/compiler/bitcells/dummy_bitcell.py @@ -8,6 +8,7 @@ import debug import utils from tech import GDS, layer +from tech import cell_properties as props import bitcell_base @@ -18,8 +19,12 @@ class dummy_bitcell(bitcell_base.bitcell_base): the layout and netlist should be available in the technology library. """ + pin_names = [props.bitcell.cell_6t.pin.bl, + props.bitcell.cell_6t.pin.br, + props.bitcell.cell_6t.pin.wl, + props.bitcell.cell_6t.pin.vdd, + props.bitcell.cell_6t.pin.gnd] - pin_names = ["bl", "br", "wl", "vdd", "gnd"] (width, height) = utils.get_libcell_size("dummy_cell_6t", GDS["unit"], layer["boundary"]) diff --git a/compiler/bitcells/dummy_bitcell_1rw_1r.py b/compiler/bitcells/dummy_bitcell_1rw_1r.py index 401e9f85..d29c804f 100644 --- a/compiler/bitcells/dummy_bitcell_1rw_1r.py +++ b/compiler/bitcells/dummy_bitcell_1rw_1r.py @@ -8,6 +8,7 @@ import debug import utils from tech import GDS, layer +from tech import cell_properties as props import bitcell_base @@ -18,7 +19,15 @@ class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base): is a hand-made cell, so the layout and netlist should be available in the technology library. """ - pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"] + pin_names = [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.bl1, + props.bitcell.cell_1rw1r.pin.br1, + props.bitcell.cell_1rw1r.pin.wl0, + props.bitcell.cell_1rw1r.pin.wl1, + props.bitcell.cell_1rw1r.pin.vdd, + props.bitcell.cell_1rw1r.pin.gnd] + type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] (width, height) = utils.get_libcell_size("dummy_cell_1rw_1r", diff --git a/compiler/bitcells/dummy_bitcell_1w_1r.py b/compiler/bitcells/dummy_bitcell_1w_1r.py index 54192f71..758a5b16 100644 --- a/compiler/bitcells/dummy_bitcell_1w_1r.py +++ b/compiler/bitcells/dummy_bitcell_1w_1r.py @@ -8,6 +8,7 @@ import debug import utils from tech import GDS, layer +from tech import cell_properties as props import bitcell_base @@ -18,7 +19,14 @@ class dummy_bitcell_1w_1r(bitcell_base.bitcell_base): is a hand-made cell, so the layout and netlist should be available in the technology library. """ - pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"] + pin_names = [props.bitcell.cell_1w1r.pin.bl0, + props.bitcell.cell_1w1r.pin.br0, + props.bitcell.cell_1w1r.pin.bl1, + props.bitcell.cell_1w1r.pin.br1, + props.bitcell.cell_1w1r.pin.wl0, + props.bitcell.cell_1w1r.pin.wl1, + props.bitcell.cell_1w1r.pin.vdd, + props.bitcell.cell_1w1r.pin.gnd] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"] (width, height) = utils.get_libcell_size("dummy_cell_1w_1r", diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py index a869e4b7..479883d9 100644 --- a/compiler/bitcells/replica_bitcell.py +++ b/compiler/bitcells/replica_bitcell.py @@ -9,6 +9,8 @@ import design import debug import utils from tech import GDS,layer,drc,parameter,cell_properties +from tech import cell_properties as props + from globals import OPTS class replica_bitcell(design.design): @@ -22,7 +24,12 @@ class replica_bitcell(design.design): pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"] else: - pin_names = ["bl", "br", "wl", "vdd", "gnd"] + pin_names = [props.bitcell.cell_6t.pin.bl, + props.bitcell.cell_6t.pin.br, + props.bitcell.cell_6t.pin.wl, + props.bitcell.cell_6t.pin.vdd, + props.bitcell.cell_6t.pin.gnd] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] if not OPTS.netlist_only: @@ -66,4 +73,4 @@ class replica_bitcell(design.design): def build_graph(self, graph, inst_name, port_nets): """Adds edges based on inputs/outputs. Overrides base class function.""" - self.add_graph_edges(graph, port_nets) \ No newline at end of file + self.add_graph_edges(graph, port_nets) diff --git a/compiler/bitcells/replica_bitcell_1rw_1r.py b/compiler/bitcells/replica_bitcell_1rw_1r.py index 0f56319e..79f16a47 100644 --- a/compiler/bitcells/replica_bitcell_1rw_1r.py +++ b/compiler/bitcells/replica_bitcell_1rw_1r.py @@ -9,6 +9,7 @@ import design import debug import utils from tech import GDS,layer,drc,parameter +from tech import cell_properties as props class replica_bitcell_1rw_1r(design.design): """ @@ -17,7 +18,15 @@ class replica_bitcell_1rw_1r(design.design): is a hand-made cell, so the layout and netlist should be available in the technology library. """ - pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"] + pin_names = [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.bl1, + props.bitcell.cell_1rw1r.pin.br1, + props.bitcell.cell_1rw1r.pin.wl0, + props.bitcell.cell_1rw1r.pin.wl1, + props.bitcell.cell_1rw1r.pin.vdd, + props.bitcell.cell_1rw1r.pin.gnd] + type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] (width,height) = utils.get_libcell_size("replica_cell_1rw_1r", GDS["unit"], layer["boundary"]) pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1rw_1r", GDS["unit"]) @@ -47,14 +56,15 @@ class replica_bitcell_1rw_1r(design.design): access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] return 2*access_tx_cin - def build_graph(self, graph, inst_name, port_nets): + def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" - pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} + pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} + pins = props.bitcell.cell_1rw1r.pin #Edges hardcoded here. Essentially wl->bl/br for both ports. # Port 0 edges - graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self) - graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self) + graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self) + graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self) # Port 1 edges - graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self) - graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self) \ No newline at end of file + graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self) + graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self) diff --git a/compiler/bitcells/replica_bitcell_1w_1r.py b/compiler/bitcells/replica_bitcell_1w_1r.py index b903e0ad..52bea519 100644 --- a/compiler/bitcells/replica_bitcell_1w_1r.py +++ b/compiler/bitcells/replica_bitcell_1w_1r.py @@ -9,6 +9,7 @@ import design import debug import utils from tech import GDS,layer,drc,parameter +from tech import cell_properties as props class replica_bitcell_1w_1r(design.design): """ @@ -17,7 +18,15 @@ class replica_bitcell_1w_1r(design.design): is a hand-made cell, so the layout and netlist should be available in the technology library. """ - pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"] + pin_names = [props.bitcell.cell_1w1r.pin.bl0, + props.bitcell.cell_1w1r.pin.br0, + props.bitcell.cell_1w1r.pin.bl1, + props.bitcell.cell_1w1r.pin.br1, + props.bitcell.cell_1w1r.pin.wl0, + props.bitcell.cell_1w1r.pin.wl1, + props.bitcell.cell_1w1r.pin.vdd, + props.bitcell.cell_1w1r.pin.gnd] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"] (width,height) = utils.get_libcell_size("replica_cell_1w_1r", GDS["unit"], layer["boundary"]) pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1w_1r", GDS["unit"]) @@ -47,13 +56,14 @@ class replica_bitcell_1w_1r(design.design): access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] return 2*access_tx_cin - def build_graph(self, graph, inst_name, port_nets): + def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" debug.info(1,'Adding edges for {}'.format(inst_name)) - pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} + pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} + pins = props.bitcell.cell_1w1r.pin #Edges hardcoded here. Essentially wl->bl/br for the read port. # Port 1 edges - graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self) - graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self) - # Port 0 is a write port, so its timing is not considered here. \ No newline at end of file + graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self) + graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self) + # Port 0 is a write port, so its timing is not considered here. From 125bcafb3edd6ffba578ca529632b9ae51fec3ae Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Sat, 15 Feb 2020 15:00:30 -0800 Subject: [PATCH 153/521] fixed purposes for gdsMill --- compiler/gdsMill/gdsMill/gds2reader.py | 101 +++++++++++----------- compiler/gdsMill/gdsMill/gds2writer.py | 95 ++++++++++---------- compiler/gdsMill/gdsMill/gdsPrimitives.py | 27 +++--- 3 files changed, 114 insertions(+), 109 deletions(-) diff --git a/compiler/gdsMill/gdsMill/gds2reader.py b/compiler/gdsMill/gdsMill/gds2reader.py index b4a40c35..2f9976a5 100644 --- a/compiler/gdsMill/gdsMill/gds2reader.py +++ b/compiler/gdsMill/gdsMill/gds2reader.py @@ -12,14 +12,14 @@ class Gds2reader: self.fileHandle = None self.layoutObject = layoutObject self.debugToTerminal=debugToTerminal - + #do we dump debug data to the screen - + def print64AsBinary(self,number): for index in range(0,64): print((number>>(63-index))&0x1,eol='') print("\n") - + def stripNonASCII(self,bytestring): string = bytestring.decode('utf-8') return string @@ -29,20 +29,20 @@ class Gds2reader: #(1)sign (7)exponent (56)mantissa #exponent is excess 64, mantissa has no implied 1 #a normal IEEE double is like this: - #(1)sign (11)exponent (52)mantissa + #(1)sign (11)exponent (52)mantissa data = struct.unpack('>q',ibmData)[0] sign = (data >> 63)&0x01 exponent = (data >> 56) & 0x7f mantissa = data<<8 #chop off sign and exponent - + if mantissa == 0: newFloat = 0.0 - else: + else: exponent = ((exponent-64)*4)+1023 #convert to double exponent #re normalize - while mantissa & 0x8000000000000000 == 0: + while mantissa & 0x8000000000000000 == 0: mantissa<<=1 - exponent-=1 + exponent-=1 mantissa<<=1 #remove the assumed high bit exponent-=1 #check for underflow error -- should handle these properly! @@ -56,7 +56,7 @@ class Gds2reader: #convert back to double newFloat = struct.unpack('>d',asciiDouble)[0] return newFloat - + def ieeeFloatCheck(self,aFloat): asciiDouble = struct.pack('>d',aFloat) data = struct.unpack('>q',asciiDouble)[0] @@ -70,12 +70,12 @@ class Gds2reader: asciiDouble = struct.pack('>q',(sign<<63)|(exponent+1023<<52)|(mantissa>>12)) newFloat = struct.unpack('>d',asciiDouble)[0] print("Check:"+str(newFloat)) - + def readNextRecord(self): global offset recordLengthAscii = self.fileHandle.read(2) #first 2 bytes tell us the length of the record if len(recordLengthAscii)==0: - return + return recordLength = struct.unpack(">h",recordLengthAscii) #gives us a tuple with a short int inside offset_int = int(recordLength[0]) # extract length offset += offset_int # count offset @@ -96,20 +96,20 @@ class Gds2reader: else: print("Invalid GDSII Header") return -1 - + #read records until we hit the UNITS section... this is the last part of the header while 1: record = self.readNextRecord() idBits = record[0:2] ## Modified Date if idBits==b'\x01\x02' and len(record)==26: - modYear = struct.unpack(">h",record[2:4])[0] + modYear = struct.unpack(">h",record[2:4])[0] modMonth = struct.unpack(">h",record[4:6])[0] modDay = struct.unpack(">h",record[6:8])[0] modHour = struct.unpack(">h",record[8:10])[0] modMinute = struct.unpack(">h",record[10:12])[0] modSecond = struct.unpack(">h",record[12:14])[0] - lastAccessYear = struct.unpack(">h",record[14:16])[0] + lastAccessYear = struct.unpack(">h",record[14:16])[0] lastAccessMonth = struct.unpack(">h",record[16:18])[0] lastAccessDay = struct.unpack(">h",record[18:20])[0] lastAccessHour = struct.unpack(">h",record[20:22])[0] @@ -169,14 +169,14 @@ class Gds2reader: if(self.debugToTerminal==1): print("Units: 1 user unit="+str(userUnits)+" database units, 1 database unit="+str(dbUnits)+" meters.") break; - if(self.debugToTerminal==1): + if(self.debugToTerminal==1): print("End of GDSII Header Found") return 1 - + def readBoundary(self): ##reads in a boundary type structure = a filled polygon if(self.debugToTerminal==1): - print("\t\t\tBeginBoundary") + print("\t\t\tBeginBoundary") thisBoundary=GdsBoundary() while 1: record = self.readNextRecord() @@ -198,9 +198,9 @@ class Gds2reader: self.layoutObject.layerNumbersInUse += [drawingLayer] if(self.debugToTerminal==1): print("\t\tDrawing Layer: "+str(drawingLayer)) - elif(idBits==b'\x16\x02'): #Purpose + elif(idBits==b'\x0E\x02'): #Purpose DATATYPE purposeLayer = struct.unpack(">h",record[2:4])[0] - thisBoundary.purposeLayer=purposeLayer + thisBoundary.purposeLayer=purposeLayer if(self.debugToTerminal==1): print("\t\tPurpose Layer: "+str(purposeLayer)) elif(idBits==b'\x10\x03'): #XY Data Points @@ -217,11 +217,11 @@ class Gds2reader: print("\t\t\tEndBoundary") break; return thisBoundary - + def readPath(self): #reads in a path structure if(self.debugToTerminal==1): print("\t\t\tBeginPath") - + thisPath=GdsPath() while 1: record = self.readNextRecord() @@ -245,7 +245,7 @@ class Gds2reader: print("\t\t\tDrawing Layer: "+str(drawingLayer)) elif(idBits==b'\x16\x02'): #Purpose purposeLayer = struct.unpack(">h",record[2:4])[0] - thisPath.purposeLayer=purposeLayer + thisPath.purposeLayer=purposeLayer if(self.debugToTerminal==1): print("\t\tPurpose Layer: "+str(purposeLayer)) elif(idBits==b'\x21\x02'): #Path type @@ -277,7 +277,7 @@ class Gds2reader: print("\t\t\tEndPath") break; return thisPath - + def readSref(self): #reads in a reference to another structure if(self.debugToTerminal==1): print("\t\t\tBeginSref") @@ -318,7 +318,7 @@ class Gds2reader: print("\t\t\tMagnification:"+str(magFactor)) elif(idBits==b'\x1C\x05'): #Rotate Angle rotateAngle=self.ieeeDoubleFromIbmData(record[2:10]) - thisSref.rotateAngle=rotateAngle + thisSref.rotateAngle=rotateAngle if(self.debugToTerminal==1): print("\t\t\tRotate Angle (CCW):"+str(rotateAngle)) elif(idBits==b'\x10\x03'): #XY Data Points @@ -333,11 +333,11 @@ class Gds2reader: print("\t\t\tEndSref") break; return thisSref - + def readAref(self): #an array of references if(self.debugToTerminal==1): print("\t\t\tBeginAref") - + thisAref = GdsAref() while 1: record = self.readNextRecord() @@ -374,7 +374,7 @@ class Gds2reader: print("\t\t\tMagnification:"+str(magFactor)) elif(idBits==b'\x1C\x05'): #Rotate Angle rotateAngle=self.ieeeDoubleFromIbmData(record[2:10]) - thisAref.rotateAngle=rotateAngle + thisAref.rotateAngle=rotateAngle if(self.debugToTerminal==1): print("\t\t\tRotate Angle (CCW):"+str(rotateAngle)) elif(idBits==b'\x10\x03'): #XY Data Points @@ -393,11 +393,11 @@ class Gds2reader: print("\t\t\tEndAref") break; return thisAref - + def readText(self): if(self.debugToTerminal==1): print("\t\t\tBeginText") - + thisText=GdsText() while 1: record = self.readNextRecord() @@ -419,9 +419,9 @@ class Gds2reader: self.layoutObject.layerNumbersInUse += [drawingLayer] if(self.debugToTerminal==1): print("\t\tDrawing Layer: "+str(drawingLayer)) - elif(idBits==b'\x16\x02'): #Purpose + elif(idBits==b'\x16\x02'): #Purpose TEXTTYPE purposeLayer = struct.unpack(">h",record[2:4])[0] - thisText.purposeLayer=purposeLayer + thisText.purposeLayer=purposeLayer if(self.debugToTerminal==1): print("\t\tPurpose Layer: "+str(purposeLayer)) elif(idBits==b'\x1A\x01'): #Transformation @@ -497,11 +497,11 @@ class Gds2reader: print("\t\t\tEndText") break; return thisText - + def readNode(self): if(self.debugToTerminal==1): print("\t\t\tBeginNode") - + ##reads in a node type structure = an electrical net thisNode = GdsNode() while 1: @@ -543,11 +543,11 @@ class Gds2reader: print("\t\t\tEndNode") break; return thisNode - + def readBox(self): if(self.debugToTerminal==1): print("\t\t\tBeginBox") - + ##reads in a gds BOX structure thisBox = GdsBox() while 1: @@ -570,9 +570,9 @@ class Gds2reader: self.layoutObject.layerNumbersInUse += [drawingLayer] if(self.debugToTerminal==1): print("\t\tDrawing Layer: "+str(drawingLayer)) - elif(idBits==b'\x16\x02'): #Purpose + elif(idBits==b'\x16\x02'): #Purpose TEXTYPE purposeLayer = struct.unpack(">h",record[2:4])[0] - thisBox.purposeLayer=purposeLayer + thisBox.purposeLayer=purposeLayer if(self.debugToTerminal==1): print("\t\tPurpose Layer: "+str(purposeLayer)) elif(idBits==b'\x2D\x00'): #Box @@ -594,14 +594,14 @@ class Gds2reader: print("\t\t\tEndBox") break; return thisBox - + def readNextStructure(self): - thisStructure = GdsStructure() + thisStructure = GdsStructure() record = self.readNextRecord() idBits = record[0:2] # Begin structure if(idBits==b'\x05\x02' and len(record)==26): - createYear = struct.unpack(">h",record[2:4])[0] + createYear = struct.unpack(">h",record[2:4])[0] createMonth = struct.unpack(">h",record[4:6])[0] createDay = struct.unpack(">h",record[6:8])[0] createHour = struct.unpack(">h",record[8:10])[0] @@ -628,7 +628,7 @@ class Gds2reader: idBits = record[0:2] if idBits==b'\x07\x00': break; #we've reached the end of the structure elif(idBits==b'\x06\x06'): - structName = self.stripNonASCII(record[2::]) + structName = self.stripNonASCII(record[2::]) thisStructure.name = structName if(self.debugToTerminal==1): print("\tStructure Name: "+structName) @@ -646,11 +646,11 @@ class Gds2reader: thisStructure.nodes+=[self.readNode()] elif(idBits==b'\x2E\x02'): thisStructure.boxes+=[self.readBox()] - if(self.debugToTerminal==1): + if(self.debugToTerminal==1): print("\tEnd of Structure.") self.layoutObject.structures[structName]=thisStructure #add this structure to the layout object return 1 - + def readGds2(self): if(self.readHeader()): #did the header read ok? record = self.readNextStructure() @@ -667,7 +667,7 @@ class Gds2reader: print("There was an error reading the structure list.") else: print("There was an error parsing the GDS header. Aborting...") - + def loadFromFile(self, fileName): self.fileHandle = open(fileName,"rb") self.readGds2() @@ -695,11 +695,11 @@ class Gds2reader: def findStruct_readNextStruct(self,findStructName): self.debugToTerminal=0 - thisStructure = GdsStructure() + thisStructure = GdsStructure() record = self.readNextRecord() idBits = record[0:2] if(idBits==('\x05','\x02') and len(record)==26): - createYear = struct.unpack(">h",record[2]+record[3])[0] + createYear = struct.unpack(">h",record[2]+record[3])[0] createMonth = struct.unpack(">h",record[4]+record[5])[0] createDay = struct.unpack(">h",record[6]+record[7])[0] createHour = struct.unpack(">h",record[8]+record[9])[0] @@ -743,7 +743,7 @@ class Gds2reader: thisStructure.nodes+=[self.readNode()] elif(idBits==('\x2E','\x02')): thisStructure.boxes+=[self.readBox()] - if(self.debugToTerminal==1): + if(self.debugToTerminal==1): print("\tEnd of Structure.") self.layoutObject.structures[structName]=thisStructure #add this structure to the layout object if(wantedStruct == 0): @@ -771,11 +771,11 @@ class Gds2reader: def findLabel_readNextStruct(self,findLabelName): self.debugToTerminal=0 - thisStructure = GdsStructure() + thisStructure = GdsStructure() record = self.readNextRecord() idBits = record[0:2] if(idBits==('\x05','\x02') and len(record)==26): - createYear = struct.unpack(">h",record[2]+record[3])[0] + createYear = struct.unpack(">h",record[2]+record[3])[0] createMonth = struct.unpack(">h",record[4]+record[5])[0] createDay = struct.unpack(">h",record[6]+record[7])[0] createHour = struct.unpack(">h",record[8]+record[9])[0] @@ -825,7 +825,7 @@ class Gds2reader: thisStructure.nodes+=[self.readNode()] elif(idBits==('\x2E','\x02')): thisStructure.boxes+=[self.readBox()] - if(self.debugToTerminal==1): + if(self.debugToTerminal==1): print("\tEnd of Structure.") self.layoutObject.structures[structName]=thisStructure #add this structure to the layout object if(wantedLabel == 0): @@ -833,4 +833,3 @@ class Gds2reader: else: #print("\tDone with collectting bound. Return") return [0,wantedtexts] - diff --git a/compiler/gdsMill/gdsMill/gds2writer.py b/compiler/gdsMill/gdsMill/gds2writer.py index 6e63533b..875de831 100644 --- a/compiler/gdsMill/gdsMill/gds2writer.py +++ b/compiler/gdsMill/gdsMill/gds2writer.py @@ -5,37 +5,37 @@ from .gdsPrimitives import * class Gds2writer: """Class to take a populated layout class and write it to a file in GDSII format""" ## Based on info from http://www.rulabinsky.com/cavd/text/chapc.html - + def __init__(self,layoutObject): self.fileHandle = 0 self.layoutObject = layoutObject self.debugToTerminal=0 #do we dump debug data to the screen - + def print64AsBinary(self,number): #debugging method for binary inspection for index in range(0,64): print((number>>(63-index))&0x1,eol='') print("\n") - + def ieeeDoubleFromIbmData(self,ibmData): #the GDS double is in IBM 370 format like this: #(1)sign (7)exponent (56)mantissa #exponent is excess 64, mantissa has no implied 1 #a normal IEEE double is like this: - #(1)sign (11)exponent (52)mantissa + #(1)sign (11)exponent (52)mantissa data = struct.unpack('>q',ibmData)[0] sign = (data >> 63)&0x01 exponent = (data >> 56) & 0x7f mantissa = data<<8 #chop off sign and exponent - + if mantissa == 0: newFloat = 0.0 else: exponent = ((exponent-64)*4)+1023 #convert to double exponent #re normalize - while mantissa & 0x8000000000000000 == 0: + while mantissa & 0x8000000000000000 == 0: mantissa<<=1 - exponent-=1 + exponent-=1 mantissa<<=1 #remove the assumed high bit exponent-=1 #check for underflow error -- should handle these properly! @@ -49,12 +49,12 @@ class Gds2writer: #convert back to double newFloat = struct.unpack('>d',asciiDouble)[0] return newFloat - + def ibmDataFromIeeeDouble(self,ieeeDouble): asciiDouble = struct.pack('>d',ieeeDouble) data = struct.unpack('>q',asciiDouble)[0] sign = (data >> 63) & 0x01 - exponent = ((data >> 52) & 0x7ff)-1023 + exponent = ((data >> 52) & 0x7ff)-1023 mantissa = data << 12 #chop off sign and exponent if(ieeeDouble == 0): mantissa = 0 @@ -70,14 +70,14 @@ class Gds2writer: for index in range (0,-exponent&3): mantissa >>= 1 mantissa = mantissa & 0x7fffffffffffffff - - exponent = (exponent+3) >> 2 + + exponent = (exponent+3) >> 2 exponent+=64 - - newFloat =(sign<<63)|(exponent<<56)|((mantissa>>8)&0xffffffffffffff) - asciiDouble = struct.pack('>q',newFloat) + + newFloat =(sign<<63)|(exponent<<56)|((mantissa>>8)&0xffffffffffffff) + asciiDouble = struct.pack('>q',newFloat) return asciiDouble - + def ieeeFloatCheck(self,aFloat): #debugging method for float construction asciiDouble = struct.pack('>d',aFloat) @@ -90,7 +90,7 @@ class Gds2writer: asciiDouble = struct.pack('>q',(sign<<63)|(exponent+1023<<52)|(mantissa>>12)) newFloat = struct.unpack('>d',asciiDouble)[0] print("Check:"+str(newFloat)) - + def writeRecord(self,record): recordLength = len(record)+2 #make sure to include this in the length recordLengthAscii=struct.pack(">h",recordLength) @@ -127,7 +127,7 @@ class Gds2writer: libraryName = self.layoutObject.info["libraryName"].encode() + "\0" else: libraryName = self.layoutObject.info["libraryName"].encode() - self.writeRecord(idBits+libraryName) + self.writeRecord(idBits+libraryName) ## reference libraries if("referenceLibraries" in self.layoutObject.info): idBits=b'\x1F\x06' @@ -158,11 +158,11 @@ class Gds2writer: mask = self.layoutObject.info["mask"] self.writeRecord(idBits+mask) if("units" in self.layoutObject.info): - idBits=b'\x03\x05' + idBits=b'\x03\x05' userUnits=self.ibmDataFromIeeeDouble(self.layoutObject.info["units"][0]) dbUnits=self.ibmDataFromIeeeDouble((self.layoutObject.info["units"][0]*1e-6/self.layoutObject.info["units"][1])*self.layoutObject.info["units"][1]) - #User Units are hardcoded, since the floating point implementation of gdsMill is not adequate, + #User Units are hardcoded, since the floating point implementation of gdsMill is not adequate, #resulting in a different value being written in output stream. Hardcoded to sram compiler's outputed gds units. #db="39225c17d04dad2a" #uu="3e20c49ba5e353f8" @@ -172,17 +172,17 @@ class Gds2writer: #dbUnits="39225c17d04dad2a".decode("hex") #db=39225c17d04dad2a - - + + self.writeRecord(idBits+userUnits+dbUnits) - if(self.debugToTerminal==1): + if(self.debugToTerminal==1): print("writer: userUnits %s"%(userUnits.encode("hex"))) print("writer: dbUnits %s"%(dbUnits.encode("hex"))) #self.ieeeFloatCheck(1.3e-6) - + print("End of GDSII Header Written") return 1 - + def writeBoundary(self,thisBoundary): idBits=b'\x08\x00' #record Type self.writeRecord(idBits) @@ -216,7 +216,7 @@ class Gds2writer: idBits=b'\x11\x00' #End Of Element coordinateRecord = idBits self.writeRecord(coordinateRecord) - + def writePath(self,thisPath): #writes out a path structure idBits=b'\x09\x00' #record Type self.writeRecord(idBits) @@ -260,7 +260,7 @@ class Gds2writer: idBits=b'\x11\x00' #End Of Element coordinateRecord = idBits self.writeRecord(coordinateRecord) - + def writeSref(self,thisSref): #reads in a reference to another structure idBits=b'\x0A\x00' #record Type self.writeRecord(idBits) @@ -296,7 +296,7 @@ class Gds2writer: magFactor=self.ibmDataFromIeeeDouble(thisSref.magFactor) self.writeRecord(idBits+magFactor) if(thisSref.rotateAngle!=""): - idBits=b'\x1C\x05' + idBits=b'\x1C\x05' rotateAngle=self.ibmDataFromIeeeDouble(thisSref.rotateAngle) self.writeRecord(idBits+rotateAngle) if(thisSref.coordinates!=""): @@ -312,7 +312,7 @@ class Gds2writer: idBits=b'\x11\x00' #End Of Element coordinateRecord = idBits self.writeRecord(coordinateRecord) - + def writeAref(self,thisAref): #an array of references idBits=b'\x0B\x00' #record Type self.writeRecord(idBits) @@ -348,7 +348,7 @@ class Gds2writer: magFactor=self.ibmDataFromIeeeDouble(thisAref.magFactor) self.writeRecord(idBits+magFactor) if(thisAref.rotateAngle!=""): - idBits=b'\x1C\x05' + idBits=b'\x1C\x05' rotateAngle=self.ibmDataFromIeeeDouble(thisAref.rotateAngle) self.writeRecord(idBits+rotateAngle) if(thisAref.coordinates): @@ -363,7 +363,7 @@ class Gds2writer: idBits=b'\x11\x00' #End Of Element coordinateRecord = idBits self.writeRecord(coordinateRecord) - + def writeText(self,thisText): idBits=b'\x0C\x00' #record Type self.writeRecord(idBits) @@ -379,9 +379,8 @@ class Gds2writer: idBits=b'\x0D\x02' #drawing layer drawingLayer = struct.pack(">h",thisText.drawingLayer) self.writeRecord(idBits+drawingLayer) - # TextType is always a 0 per GDS specification - idBits=b'\x16\x02' #purpose layer - purposeLayer = struct.pack(">h",0) + idBits=b'\x16\x02' #purpose layer TEXTTYPE + purposeLayer = struct.pack(">h",thisText.purposeLayer) self.writeRecord(idBits+purposeLayer) if(thisText.transFlags != ""): idBits=b'\x1A\x01' @@ -400,7 +399,7 @@ class Gds2writer: magFactor=self.ibmDataFromIeeeDouble(thisText.magFactor) self.writeRecord(idBits+magFactor) if(thisText.rotateAngle!=""): - idBits=b'\x1C\x05' + idBits=b'\x1C\x05' rotateAngle=self.ibmDataFromIeeeDouble(thisText.rotateAngle) self.writeRecord(idBits+rotateAngle) if(thisText.pathType !=""): @@ -412,12 +411,12 @@ class Gds2writer: pathWidth = struct.pack(">i",thisText.pathWidth) self.writeRecord(idBits+pathWidth) if(thisText.presentationFlags!=""): - idBits=b'\x1A\x01' + idBits=b'\x1A\x01' font = thisText.presentationFlags[0]<<4 verticalFlags = int(thisText.presentationFlags[1])<<2 horizontalFlags = int(thisText.presentationFlags[2]) presentationFlags = struct.pack(">H",font|verticalFlags|horizontalFlags) - self.writeRecord(idBits+transFlags) + self.writeRecord(idBits+transFlags) if(thisText.coordinates!=""): idBits=b'\x10\x03' #XY Data Points coordinateRecord = idBits @@ -431,11 +430,11 @@ class Gds2writer: idBits=b'\x19\x06' textString = thisText.textString self.writeRecord(idBits+textString.encode()) - + idBits=b'\x11\x00' #End Of Element coordinateRecord = idBits self.writeRecord(coordinateRecord) - + def writeNode(self,thisNode): idBits=b'\x15\x00' #record Type self.writeRecord(idBits) @@ -450,11 +449,11 @@ class Gds2writer: if(thisNode.drawingLayer!=""): idBits=b'\x0D\x02' #drawig layer drawingLayer = struct.pack(">h",thisNode.drawingLayer) - self.writeRecord(idBits+drawingLayer) + self.writeRecord(idBits+drawingLayer) if(thisNode.nodeType!=""): idBits=b'\x2A\x02' nodeType = struct.pack(">h",thisNode.nodeType) - self.writeRecord(idBits+nodeType) + self.writeRecord(idBits+nodeType) if(thisText.coordinates!=""): idBits=b'\x10\x03' #XY Data Points coordinateRecord = idBits @@ -464,11 +463,11 @@ class Gds2writer: coordinateRecord+=x coordinateRecord+=y self.writeRecord(coordinateRecord) - + idBits=b'\x11\x00' #End Of Element coordinateRecord = idBits self.writeRecord(coordinateRecord) - + def writeBox(self,thisBox): idBits=b'\x2E\x02' #record Type self.writeRecord(idBits) @@ -491,7 +490,7 @@ class Gds2writer: if(thisBox.boxValue!=""): idBits=b'\x2D\x00' boxValue = struct.pack(">h",thisBox.boxValue) - self.writeRecord(idBits+boxValue) + self.writeRecord(idBits+boxValue) if(thisBox.coordinates!=""): idBits=b'\x10\x03' #XY Data Points coordinateRecord = idBits @@ -501,11 +500,11 @@ class Gds2writer: coordinateRecord+=x coordinateRecord+=y self.writeRecord(coordinateRecord) - + idBits=b'\x11\x00' #End Of Element coordinateRecord = idBits self.writeRecord(coordinateRecord) - + def writeNextStructure(self,structureName): #first put in the structure head thisStructure = self.layoutObject.structures[structureName] @@ -532,7 +531,7 @@ class Gds2writer: structureName = structureName + '\x00' self.writeRecord(idBits+structureName.encode()) #now go through all the structure elements and write them in - + for boundary in thisStructure.boundaries: self.writeBoundary(boundary) for path in thisStructure.paths: @@ -550,7 +549,7 @@ class Gds2writer: #put in the structure tail idBits=b'\x07\x00' self.writeRecord(idBits) - + def writeGds2(self): self.writeHeader(); #first, put the header in #go through each structure in the layout and write it to the file @@ -559,7 +558,7 @@ class Gds2writer: #at the end, put in the END LIB record idBits=b'\x04\x00' self.writeRecord(idBits) - + def writeToFile(self,fileName): self.fileHandle = open(fileName,"wb") self.writeGds2() diff --git a/compiler/gdsMill/gdsMill/gdsPrimitives.py b/compiler/gdsMill/gdsMill/gdsPrimitives.py index 886f9c13..13b8acf9 100644 --- a/compiler/gdsMill/gdsMill/gdsPrimitives.py +++ b/compiler/gdsMill/gdsMill/gdsPrimitives.py @@ -1,5 +1,12 @@ import math +from globals import OPTS +# default purpose layer is used for addText() in vlsiLayout.py +if OPTS.tech_name == "s8": + purposeLayer=20 +else: + purposeLayer=0 + class GdsStructure: """Class represent a GDS Structure Object""" def __init__(self): @@ -9,7 +16,7 @@ class GdsStructure: #these are the primitives defined in GDS2, and we will maintain lists of them all self.boundaries=[] self.paths=[] - self.srefs=[] + self.srefs=[] self.arefs=[] self.texts=[] self.nodes=[] @@ -23,7 +30,7 @@ class GdsBoundary: self.drawingLayer="" self.purposeLayer=0 self.coordinates="" - + class GdsPath: """Class represent a GDS Path Object""" def __init__(self): @@ -35,7 +42,7 @@ class GdsPath: self.dataType=None self.pathWidth="" self.coordinates="" - + def equivalentBoundaryCoordinates(self): """Convert the path to a set of boundary coordinates that define it""" halfWidth = (self.pathWidth/2) @@ -62,7 +69,7 @@ class GdsPath: nextX = None; nextY = None; if lastX==None: #start of the path - if nextX>x:#moving right + if nextX>x:#moving right boundaryEquivalent+=[(x,y+halfWidth)] if nextX nextX): boundaryEquivalent+=[(x+halfWidth,y-halfWidth)] - - if nextX == None: #end of path, put in the last 2 points - if lastXx:#moving left boundaryEquivalent+=[(x,y-halfWidth)] @@ -140,7 +147,7 @@ class GdsText: self.elementFlags="" self.plex="" self.drawingLayer="" - self.purposeLayer=0 + self.purposeLayer=purposeLayer self.transFlags=[0,0,0] self.magFactor="" self.rotateAngle="" @@ -149,7 +156,7 @@ class GdsText: self.presentationFlags="" self.coordinates="" self.textString = "" - + class GdsNode: """Class represent a GDS Node Object""" def __init__(self): @@ -158,7 +165,7 @@ class GdsNode: self.drawingLayer="" self.nodeType="" self.coordinates="" - + class GdsBox: """Class represent a GDS Box Object""" def __init__(self): From 5e1f64c8f94972c122c0d165a1fb3339ca29f2c9 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 17 Feb 2020 14:09:50 +0100 Subject: [PATCH 154/521] modules/port_data: Add get_bl/br_name method if we rely on the names of the submodules (sense_amp_array, write_driver_array, etc.) for port_data's pins, we get into trouble on multiport SRAMs. To avoid this we use explicit names for br/bl depending on the port number in port_data. Now each submodule does no longer need to figure out the right name depending on the port number. Signed-off-by: Bastian Koppelmann --- compiler/modules/port_data.py | 32 +++++++++++++------ compiler/modules/precharge_array.py | 15 +++------ compiler/modules/sense_amp_array.py | 15 +++------ .../modules/single_level_column_mux_array.py | 13 ++------ compiler/modules/write_driver_array.py | 14 +++----- 5 files changed, 37 insertions(+), 52 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index d1c2c671..7776c045 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -46,7 +46,19 @@ class port_data(design.design): # br lines are connect from the precharger return self.precharge.get_br_names() + def get_bl_name(self, port=0): + bl_name = "bl" + if len(self.all_ports) == 1: + return bl_name + else: + return bl_name + "{}".format(port) + def get_br_name(self, port=0): + br_name = "br" + if len(self.all_ports) == 1: + return br_name + else: + return br_name + "{}".format(port) def create_netlist(self): self.precompute_constants() @@ -94,8 +106,8 @@ class port_data(design.design): self.add_pin("rbl_bl","INOUT") self.add_pin("rbl_br","INOUT") for bit in range(self.num_cols): - bl_name = self.precharge_array.get_bl_name(self.port) - br_name = self.precharge_array.get_br_name(self.port) + bl_name = self.get_bl_name(self.port) + br_name = self.get_br_name(self.port) self.add_pin("{0}_{1}".format(bl_name, bit),"INOUT") self.add_pin("{0}_{1}".format(br_name, bit),"INOUT") if self.port in self.read_ports: @@ -253,8 +265,8 @@ class port_data(design.design): self.precharge_array_inst = self.add_inst(name="precharge_array{}".format(self.port), mod=self.precharge_array) - bl_name = self.precharge_array.get_bl_name(self.port) - br_name = self.precharge_array.get_br_name(self.port) + bl_name = self.get_bl_name(self.port) + br_name = self.get_br_name(self.port) temp = [] # Use left BLs for RBL @@ -285,8 +297,8 @@ class port_data(design.design): self.column_mux_array_inst = self.add_inst(name="column_mux_array{}".format(self.port), mod=self.column_mux_array) - bl_name = self.column_mux_array.get_bl_name(self.port) - br_name = self.column_mux_array.get_br_name(self.port) + bl_name = self.get_bl_name(self.port) + br_name = self.get_br_name(self.port) temp = [] for col in range(self.num_cols): temp.append("{0}_{1}".format(bl_name, col)) @@ -315,8 +327,8 @@ class port_data(design.design): self.sense_amp_array_inst = self.add_inst(name="sense_amp_array{}".format(self.port), mod=self.sense_amp_array) - bl_name = self.sense_amp_array.get_bl_name(self.port) - br_name = self.sense_amp_array.get_br_name(self.port) + bl_name = self.get_bl_name(self.port) + br_name = self.get_br_name(self.port) temp = [] for bit in range(self.word_size): temp.append("dout_{}".format(bit)) @@ -341,8 +353,8 @@ class port_data(design.design): """ Creating Write Driver """ self.write_driver_array_inst = self.add_inst(name="write_driver_array{}".format(self.port), mod=self.write_driver_array) - bl_name = self.write_driver_array.get_bl_name(self.port) - br_name = self.write_driver_array.get_br_name(self.port) + bl_name = self.get_bl_name(self.port) + br_name = self.get_br_name(self.port) temp = [] for bit in range(self.word_size): diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 5ac97b4d..efc9c4a3 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -32,20 +32,13 @@ class precharge_array(design.design): if not OPTS.netlist_only: self.create_layout() - def get_bl_name(self, port=0): + def get_bl_name(self): bl_name = self.pc_cell.get_bl_names() - if len(self.all_ports) == 1: - return bl_name - else: - return bl_name + "{}".format(port) + return bl_name - def get_br_name(self, port=0): + def get_br_name(self): br_name = self.pc_cell.get_br_names() - if len(self.all_ports) == 1: - return br_name - else: - return br_name + "{}".format(port) - + return br_name def add_pins(self): """Adds pins for spice file""" diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 8ac5146c..f62b7a1d 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -33,20 +33,13 @@ class sense_amp_array(design.design): if not OPTS.netlist_only: self.create_layout() - - def get_bl_name(self, port=0): + def get_bl_name(self): bl_name = self.amp.get_bl_names() - if len(self.all_ports) == 1: - return bl_name - else: - return bl_name + "{}".format(port) + return bl_name - def get_br_name(self, port=0): + def get_br_name(self): br_name = self.amp.get_br_names() - if len(self.all_ports) == 1: - return br_name - else: - return br_name + "{}".format(port) + return br_name def create_netlist(self): self.add_modules() diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 1c181574..324b7415 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -37,20 +37,13 @@ class single_level_column_mux_array(design.design): if not OPTS.netlist_only: self.create_layout() - def get_bl_name(self, port=0): + def get_bl_name(self): bl_name = self.mux.get_bl_names() - if len(self.all_ports) == 1: - return bl_name - else: - return bl_name + "{}".format(port) + return bl_name def get_br_name(self, port=0): br_name = self.mux.get_br_names() - if len(self.all_ports) == 1: - return br_name - else: - return br_name + "{}".format(port) - + return br_name def create_netlist(self): self.add_modules() diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index dd7430a9..e6aaa118 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -37,19 +37,13 @@ class write_driver_array(design.design): if not OPTS.netlist_only: self.create_layout() - def get_bl_name(self, port=0): + def get_bl_name(self): bl_name = self.driver.get_bl_names() - if len(self.all_ports) == 1: - return bl_name - else: - return bl_name + "{}".format(port) + return bl_name - def get_br_name(self, port=0): + def get_br_name(self): br_name = self.driver.get_br_names() - if len(self.all_ports) == 1: - return br_name - else: - return br_name + "{}".format(port) + return br_name def create_netlist(self): self.add_modules() From 656fdd10083c5567be96a5cf2e53d08c353c784c Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 14 Feb 2020 14:00:43 +0100 Subject: [PATCH 155/521] port_data: Refactor channel_route/connect_bitlines() both functions share a lot of code and are passing around a lot of data under similar names (inst1, inst1_start_bit, inst1_bl_name, ...). Thus we group all these elements in a named tuple to ease passing around these elements. All callers of channel_route/connect_bitlines() either pass in the bl/br names or rely on "br_{}"/"bl_{}" as defaults. These hard coded values should be determined by the instances. Thus we get the bitline names based on the instances passed in. The callers only provide a template string, to take care of the case that bitlines are called "bl_out_{}". Signed-off-by: Bastian Koppelmann --- compiler/modules/port_data.py | 159 ++++++++++++++++++++++------------ 1 file changed, 106 insertions(+), 53 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 7776c045..7c37d670 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -8,6 +8,7 @@ from tech import drc, parameter import debug import design from sram_factory import factory +from collections import namedtuple from vector import vector from globals import OPTS @@ -535,13 +536,16 @@ class port_data(design.design): # Only do this if we have a column mux! if self.col_addr_size==0: return - + inst1 = self.column_mux_array_inst inst2 = self.precharge_array_inst - if self.port==0: - self.connect_bitlines(inst1, inst2, self.num_cols, inst2_start_bit=1) - else: - self.connect_bitlines(inst1, inst2, self.num_cols) + + insn2_start_bit = 1 if self.port == 0 else 0 + + self.connect_bitlines(inst1=inst1, + inst2=inst2, + num_bits=self.num_cols, + inst2_start_bit=insn2_start_bit) def route_sense_amp_to_column_mux_or_precharge_array(self, port): @@ -551,46 +555,49 @@ class port_data(design.design): if self.col_addr_size>0: # Sense amp is connected to the col mux inst1 = self.column_mux_array_inst - inst1_bl_name = "bl_out_{}" - inst1_br_name = "br_out_{}" + inst1_bls_templ = "{inst}_out_{bit}" start_bit = 0 else: # Sense amp is directly connected to the precharge array inst1 = self.precharge_array_inst - inst1_bl_name = "bl_{}" - inst1_br_name = "br_{}" + inst1_bls_templ="{inst}_{bit}" + if self.port==0: start_bit=1 else: start_bit=0 - - self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size, - inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst1_start_bit=start_bit) + self.channel_route_bitlines(inst1=inst1, + inst1_bls_template=inst1_bls_templ, + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) def route_write_driver_to_column_mux_or_precharge_array(self, port): """ Routing of BL and BR between sense_amp and column mux or precharge array """ inst2 = self.write_driver_array_inst - + inst2_bl_name = inst2.mod.get_bl_name() + inst2_br_name = inst2.mod.get_br_name() + if self.col_addr_size>0: # Write driver is connected to the col mux inst1 = self.column_mux_array_inst - inst1_bl_name = "bl_out_{}" - inst1_br_name = "br_out_{}" + inst1_bls_templ = "{inst}_out_{bit}" start_bit = 0 else: # Sense amp is directly connected to the precharge array inst1 = self.precharge_array_inst - inst1_bl_name = "bl_{}" - inst1_br_name = "br_{}" + inst1_bls_templ="{inst}_{bit}" if self.port==0: start_bit=1 else: start_bit=0 - - self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size, - inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst1_start_bit=start_bit) + + self.channel_route_bitlines(inst1=inst1, inst2=inst2, + num_bits=self.word_size, + inst1_bls_template=inst1_bls_templ, + inst1_start_bit=start_bit) def route_write_driver_to_sense_amp(self, port): @@ -601,7 +608,9 @@ class port_data(design.design): # These should be pitch matched in the cell library, # but just in case, do a channel route. - self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size) + self.channel_route_bitlines(inst1=inst1, + inst2=inst2, + num_bits=self.word_size) def route_bitline_pins(self): @@ -647,64 +656,108 @@ class port_data(design.design): if self.write_mask_and_array_inst: self.copy_layout_pin(self.write_mask_and_array_inst, "en", "w_en") - - - def channel_route_bitlines(self, inst1, inst2, num_bits, - inst1_bl_name="bl_{}", inst1_br_name="br_{}", inst1_start_bit=0, - inst2_bl_name="bl_{}", inst2_br_name="br_{}", inst2_start_bit=0): + + + def _group_bitline_instances(self, inst1, inst2, num_bits, + inst1_bls_template, + inst1_start_bit, + inst2_bls_template, + inst2_start_bit): """ - Route the bl and br of two modules using the channel router. + Groups all the parameters into a named tuple and seperates them into + top and bottom instances. """ - + inst_group = namedtuple('InstanceGroup', ('inst', 'bls_template', + 'bl_name', 'br_name', 'start_bit')) + + inst1_group = inst_group(inst1, inst1_bls_template, + inst1.mod.get_bl_name(), + inst1.mod.get_br_name(), + inst1_start_bit) + inst2_group = inst_group(inst2, inst2_bls_template, + inst2.mod.get_bl_name(), + inst2.mod.get_br_name(), + inst2_start_bit) # determine top and bottom automatically. # since they don't overlap, we can just check the bottom y coordinate. if inst1.by() < inst2.by(): - (bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit) - (top_inst, top_bl_name, top_br_name, top_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit) + bot_inst_group = inst1_group + top_inst_group = inst2_group else: - (bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit) - (top_inst, top_bl_name, top_br_name, top_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit) + bot_inst_group = inst2_group + top_inst_group = inst1_group + return (bot_inst_group, top_inst_group) + + def _get_bitline_pins(self, inst_group, bit): + """ + Extracts bl/br pins from an InstanceGroup based on the bit modifier. + """ + full_bl_name = inst_group.bls_template.format( + **{'inst' : inst_group.bl_name, + 'bit' : inst_group.start_bit + bit} + ) + full_br_name = inst_group.bls_template.format( + **{'inst' : inst_group.br_name, + 'bit' : inst_group.start_bit + bit} + ) + return (inst_group.inst.get_pin(full_bl_name), + inst_group.inst.get_pin(full_br_name)) + + + def channel_route_bitlines(self, inst1, inst2, num_bits, + inst1_bls_template="{inst}_{bit}", + inst1_start_bit=0, + inst2_bls_template="{inst}_{bit}", + inst2_start_bit=0): + """ + Route the bl and br of two modules using the channel router. + """ + + bot_inst_group, top_inst_group = self._group_bitline_instances( + inst1, inst2, num_bits, + inst1_bls_template, inst1_start_bit, + inst2_bls_template, inst2_start_bit) # Channel route each mux separately since we don't minimize the number # of tracks in teh channel router yet. If we did, we could route all the bits at once! - offset = bottom_inst.ul() + vector(0,self.m1_pitch) + offset = bot_inst_group.inst.ul() + vector(0,self.m1_pitch) for bit in range(num_bits): - bottom_names = [bottom_inst.get_pin(bottom_bl_name.format(bit+bottom_start_bit)), bottom_inst.get_pin(bottom_br_name.format(bit+bottom_start_bit))] - top_names = [top_inst.get_pin(top_bl_name.format(bit+top_start_bit)), top_inst.get_pin(top_br_name.format(bit+top_start_bit))] + bottom_names = self._get_bitline_pins(bot_inst_group, bit) + top_names = self._get_bitline_pins(top_inst_group, bit) + route_map = list(zip(bottom_names, top_names)) self.create_horizontal_channel_route(route_map, offset, self.m1_stack) def connect_bitlines(self, inst1, inst2, num_bits, - inst1_bl_name="bl_{}", inst1_br_name="br_{}", inst1_start_bit=0, - inst2_bl_name="bl_{}", inst2_br_name="br_{}", inst2_start_bit=0): - + inst1_bls_template="{inst}_{bit}", + inst1_start_bit=0, + inst2_bls_template="{inst}_{bit}", + inst2_start_bit=0): """ Connect the bl and br of two modules. This assumes that they have sufficient space to create a jog in the middle between the two modules (if needed). """ - # determine top and bottom automatically. - # since they don't overlap, we can just check the bottom y coordinate. - if inst1.by() < inst2.by(): - (bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit) - (top_inst, top_bl_name, top_br_name, top_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit) - else: - (bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit) - (top_inst, top_bl_name, top_br_name, top_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit) + bot_inst_group, top_inst_group = self._group_bitline_instances( + inst1, inst2, num_bits, + inst1_bls_template, inst1_start_bit, + inst2_bls_template, inst2_start_bit) + bottom_inst = bot_inst_group.inst + top_inst = top_inst_group.inst for col in range(num_bits): - bottom_bl = bottom_inst.get_pin(bottom_bl_name.format(col+bottom_start_bit)).uc() - bottom_br = bottom_inst.get_pin(bottom_br_name.format(col+bottom_start_bit)).uc() - top_bl = top_inst.get_pin(top_bl_name.format(col+top_start_bit)).bc() - top_br = top_inst.get_pin(top_br_name.format(col+top_start_bit)).bc() + bot_bl_pin, bot_br_pin = self._get_bitline_pins(bot_inst_group, col) + top_bl_pin, top_br_pin = self._get_bitline_pins(top_inst_group, col) + bot_bl, bot_br = bot_bl_pin.uc(), bot_br_pin.uc() + top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc() - yoffset = 0.5*(top_bl.y+bottom_bl.y) - self.add_path("m2",[bottom_bl, vector(bottom_bl.x,yoffset), + yoffset = 0.5*(top_bl.y+bot_bl.y) + self.add_path("m2",[bot_bl, vector(bot_bl.x,yoffset), vector(top_bl.x,yoffset), top_bl]) - self.add_path("m2",[bottom_br, vector(bottom_br.x,yoffset), + self.add_path("m2",[bot_br, vector(bot_br.x,yoffset), vector(top_br.x,yoffset), top_br]) def graph_exclude_precharge(self): From c06cb2bfc2be827196311c533ab0c362e1c8d150 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 17 Feb 2020 14:23:26 +0100 Subject: [PATCH 156/521] write_driver/array: Remove hardcoded pin names all pin names should be wrapped into a function/property. This ensures that there is exactly one place to change the name. Signed-off-by: Bastian Koppelmann --- compiler/modules/write_driver.py | 8 ++++ compiler/modules/write_driver_array.py | 61 +++++++++++++++----------- 2 files changed, 44 insertions(+), 25 deletions(-) diff --git a/compiler/modules/write_driver.py b/compiler/modules/write_driver.py index db08bcf4..78920a10 100644 --- a/compiler/modules/write_driver.py +++ b/compiler/modules/write_driver.py @@ -43,6 +43,14 @@ class write_driver(design.design): def get_br_names(self): return "br" + @property + def din_name(self): + return "din" + + @property + def en_name(self): + return "en" + def get_w_en_cin(self): """Get the relative capacitance of a single input""" # This is approximated from SCMOS. It has roughly 5 3x transistor gates. diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index e6aaa118..16233c88 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -45,6 +45,14 @@ class write_driver_array(design.design): br_name = self.driver.get_br_names() return br_name + @property + def data_name(self): + return "data" + + @property + def en_name(self): + return "en" + def create_netlist(self): self.add_modules() self.add_pins() @@ -65,15 +73,15 @@ class write_driver_array(design.design): def add_pins(self): for i in range(self.word_size): - self.add_pin("data_{0}".format(i), "INPUT") - for i in range(self.word_size): - self.add_pin("bl_{0}".format(i), "OUTPUT") - self.add_pin("br_{0}".format(i), "OUTPUT") + self.add_pin(self.data_name + "_{0}".format(i), "INPUT") + for i in range(self.word_size): + self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT") + self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT") if self.write_size: for i in range(self.num_wmasks): - self.add_pin("en_{0}".format(i), "INPUT") + self.add_pin(self.en_name + "_{0}".format(i), "INPUT") else: - self.add_pin("en", "INPUT") + self.add_pin(self.en_name, "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -96,20 +104,20 @@ class write_driver_array(design.design): mod=self.driver) if self.write_size: - self.connect_inst(["data_{0}".format(index), - "bl_{0}".format(index), - "br_{0}".format(index), - "en_{0}".format(windex), "vdd", "gnd"]) + self.connect_inst([self.data_name + "_{0}".format(index), + self.get_bl_name() + "_{0}".format(index), + self.get_br_name() + "_{0}".format(index), + self.en_name + "_{0}".format(windex), "vdd", "gnd"]) w+=1 # when w equals write size, the next en pin can be connected since we are now at the next wmask bit if w == self.write_size: w = 0 windex+=1 else: - self.connect_inst(["data_{0}".format(index), - "bl_{0}".format(index), - "br_{0}".format(index), - "en", "vdd", "gnd"]) + self.connect_inst([self.data_name + "_{0}".format(index), + self.get_bl_name() + "_{0}".format(index), + self.get_br_name() + "_{0}".format(index), + self.en_name, "vdd", "gnd"]) def place_write_array(self): @@ -134,21 +142,22 @@ class write_driver_array(design.design): def add_layout_pins(self): for i in range(self.word_size): - din_pin = self.driver_insts[i].get_pin("din") - self.add_layout_pin(text="data_{0}".format(i), + inst = self.driver_insts[i] + din_pin = inst.get_pin(inst.mod.din_name) + self.add_layout_pin(text=self.data_name + "_{0}".format(i), layer="m2", offset=din_pin.ll(), width=din_pin.width(), height=din_pin.height()) - bl_pin = self.driver_insts[i].get_pin("bl") - self.add_layout_pin(text="bl_{0}".format(i), + bl_pin = inst.get_pin(inst.mod.get_bl_names()) + self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i), layer="m2", offset=bl_pin.ll(), width=bl_pin.width(), height=bl_pin.height()) - - br_pin = self.driver_insts[i].get_pin("br") - self.add_layout_pin(text="br_{0}".format(i), + + br_pin = inst.get_pin(inst.mod.get_br_names()) + self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i), layer="m2", offset=br_pin.ll(), width=br_pin.width(), @@ -163,7 +172,8 @@ class write_driver_array(design.design): start_layer = "m2") if self.write_size: for bit in range(self.num_wmasks): - en_pin = self.driver_insts[bit*self.write_size].get_pin("en") + inst = self.driver_insts[bit*self.write_size] + en_pin = inst.get_pin(inst.mod.en_name) # Determine width of wmask modified en_pin with/without col mux wmask_en_len = self.words_per_row*(self.write_size * self.driver_spacing) if (self.words_per_row == 1): @@ -171,15 +181,16 @@ class write_driver_array(design.design): else: en_gap = self.driver_spacing - self.add_layout_pin(text="en_{0}".format(bit), + self.add_layout_pin(text=self.en_name + "_{0}".format(bit), layer=en_pin.layer, offset=en_pin.ll(), width=wmask_en_len-en_gap, height=en_pin.height()) else: - self.add_layout_pin(text="en", + inst = self.driver_insts[0] + self.add_layout_pin(text=self.en_name, layer="m1", - offset=self.driver_insts[0].get_pin("en").ll().scale(0,1), + offset=inst.get_pin(inst.mod.en_name).ll().scale(0,1), width=self.width) From 9a12b68680167d7277ca64ba5c7496640393cacf Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 17 Feb 2020 14:25:00 +0100 Subject: [PATCH 157/521] write_driver: Allow custom pin names we don't want to propagate the write driver bl/br names out of the write_driver_array. Thus the write_driver_array gets them named as "bl"/"br" again. Signed-off-by: Bastian Koppelmann --- compiler/base/custom_cell_properties.py | 9 + compiler/modules/write_driver.py | 17 +- compiler/modules/write_driver_array.py | 4 +- compiler/modules/write_driver_array.py.orig | 202 ++++++++++++++++++++ 4 files changed, 225 insertions(+), 7 deletions(-) create mode 100644 compiler/modules/write_driver_array.py.orig diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index 45887561..04d27379 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -116,6 +116,12 @@ class cell_properties(): self._dff_buff_array = _dff_buff_array(use_custom_ports = False, add_body_contacts = False) + self._write_driver = _cell({'din': 'din', + 'bl' : 'bl', + 'br' : 'br', + 'en' : 'en'}) + + @property def bitcell(self): return self._bitcell @@ -132,3 +138,6 @@ class cell_properties(): def dff_buff_array(self): return self._dff_buff_array + @property + def write_driver(self): + return self._write_driver diff --git a/compiler/modules/write_driver.py b/compiler/modules/write_driver.py index 78920a10..9afac81b 100644 --- a/compiler/modules/write_driver.py +++ b/compiler/modules/write_driver.py @@ -10,6 +10,7 @@ import design import utils from globals import OPTS from tech import GDS,layer +from tech import cell_properties as props class write_driver(design.design): """ @@ -19,7 +20,13 @@ class write_driver(design.design): the technology library. """ - pin_names = ["din", "bl", "br", "en", "vdd", "gnd"] + pin_names = [props.write_driver.pin.din, + props.write_driver.pin.bl, + props.write_driver.pin.br, + props.write_driver.pin.en, + props.write_driver.pin.vdd, + props.write_driver.pin.gnd] + type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] if not OPTS.netlist_only: (width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"]) @@ -38,18 +45,18 @@ class write_driver(design.design): self.add_pin_types(self.type_list) def get_bl_names(self): - return "bl" + return props.write_driver.pin.bl def get_br_names(self): - return "br" + return props.write_driver.pin.br @property def din_name(self): - return "din" + return props.write_driver.pin.din @property def en_name(self): - return "en" + return props.write_driver.pin.en def get_w_en_cin(self): """Get the relative capacitance of a single input""" diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 16233c88..08a2e007 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -38,11 +38,11 @@ class write_driver_array(design.design): self.create_layout() def get_bl_name(self): - bl_name = self.driver.get_bl_names() + bl_name = "bl" return bl_name def get_br_name(self): - br_name = self.driver.get_br_names() + br_name = "br" return br_name @property diff --git a/compiler/modules/write_driver_array.py.orig b/compiler/modules/write_driver_array.py.orig new file mode 100644 index 00000000..16233c88 --- /dev/null +++ b/compiler/modules/write_driver_array.py.orig @@ -0,0 +1,202 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +from math import log +import design +from tech import drc +import debug +from sram_factory import factory +from vector import vector +from globals import OPTS + +class write_driver_array(design.design): + """ + Array of tristate drivers to write to the bitlines through the column mux. + Dynamically generated write driver array of all bitlines. + """ + + def __init__(self, name, columns, word_size,write_size=None): + design.design.__init__(self, name) + debug.info(1, "Creating {0}".format(self.name)) + self.add_comment("columns: {0}".format(columns)) + self.add_comment("word_size {0}".format(word_size)) + + self.columns = columns + self.word_size = word_size + self.write_size = write_size + self.words_per_row = int(columns / word_size) + + if self.write_size: + self.num_wmasks = int(self.word_size/self.write_size) + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + def get_bl_name(self): + bl_name = self.driver.get_bl_names() + return bl_name + + def get_br_name(self): + br_name = self.driver.get_br_names() + return br_name + + @property + def data_name(self): + return "data" + + @property + def en_name(self): + return "en" + + def create_netlist(self): + self.add_modules() + self.add_pins() + self.create_write_array() + + def create_layout(self): + + if self.bitcell.width > self.driver.width: + self.width = self.columns * self.bitcell.width + else: + self.width = self.columns * self.driver.width + self.height = self.driver.height + + self.place_write_array() + self.add_layout_pins() + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + for i in range(self.word_size): + self.add_pin(self.data_name + "_{0}".format(i), "INPUT") + for i in range(self.word_size): + self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT") + self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT") + if self.write_size: + for i in range(self.num_wmasks): + self.add_pin(self.en_name + "_{0}".format(i), "INPUT") + else: + self.add_pin(self.en_name, "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def add_modules(self): + self.driver = factory.create(module_type="write_driver") + self.add_mod(self.driver) + + # This is just used for measurements, + # so don't add the module + self.bitcell = factory.create(module_type="bitcell") + + def create_write_array(self): + self.driver_insts = {} + w = 0 + windex=0 + for i in range(0,self.columns,self.words_per_row): + name = "write_driver{}".format(i) + index = int(i/self.words_per_row) + self.driver_insts[index]=self.add_inst(name=name, + mod=self.driver) + + if self.write_size: + self.connect_inst([self.data_name + "_{0}".format(index), + self.get_bl_name() + "_{0}".format(index), + self.get_br_name() + "_{0}".format(index), + self.en_name + "_{0}".format(windex), "vdd", "gnd"]) + w+=1 + # when w equals write size, the next en pin can be connected since we are now at the next wmask bit + if w == self.write_size: + w = 0 + windex+=1 + else: + self.connect_inst([self.data_name + "_{0}".format(index), + self.get_bl_name() + "_{0}".format(index), + self.get_br_name() + "_{0}".format(index), + self.en_name, "vdd", "gnd"]) + + + def place_write_array(self): + from tech import cell_properties + if self.bitcell.width > self.driver.width: + self.driver_spacing = self.bitcell.width + else: + self.driver_spacing = self.driver.width + for i in range(0,self.columns,self.words_per_row): + index = int(i/self.words_per_row) + xoffset = i * self.driver_spacing + + if cell_properties.bitcell.mirror.y and i % 2: + mirror = "MY" + xoffset = xoffset + self.driver.width + else: + mirror = "" + + base = vector(xoffset, 0) + self.driver_insts[index].place(offset=base, mirror=mirror) + + + def add_layout_pins(self): + for i in range(self.word_size): + inst = self.driver_insts[i] + din_pin = inst.get_pin(inst.mod.din_name) + self.add_layout_pin(text=self.data_name + "_{0}".format(i), + layer="m2", + offset=din_pin.ll(), + width=din_pin.width(), + height=din_pin.height()) + bl_pin = inst.get_pin(inst.mod.get_bl_names()) + self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i), + layer="m2", + offset=bl_pin.ll(), + width=bl_pin.width(), + height=bl_pin.height()) + + br_pin = inst.get_pin(inst.mod.get_br_names()) + self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i), + layer="m2", + offset=br_pin.ll(), + width=br_pin.width(), + height=br_pin.height()) + + for n in ["vdd", "gnd"]: + pin_list = self.driver_insts[i].get_pins(n) + for pin in pin_list: + self.add_power_pin(name = n, + loc = pin.center(), + vertical=True, + start_layer = "m2") + if self.write_size: + for bit in range(self.num_wmasks): + inst = self.driver_insts[bit*self.write_size] + en_pin = inst.get_pin(inst.mod.en_name) + # Determine width of wmask modified en_pin with/without col mux + wmask_en_len = self.words_per_row*(self.write_size * self.driver_spacing) + if (self.words_per_row == 1): + en_gap = self.driver_spacing - en_pin.width() + else: + en_gap = self.driver_spacing + + self.add_layout_pin(text=self.en_name + "_{0}".format(bit), + layer=en_pin.layer, + offset=en_pin.ll(), + width=wmask_en_len-en_gap, + height=en_pin.height()) + else: + inst = self.driver_insts[0] + self.add_layout_pin(text=self.en_name, + layer="m1", + offset=inst.get_pin(inst.mod.en_name).ll().scale(0,1), + width=self.width) + + + + + def get_w_en_cin(self): + """Get the relative capacitance of all the enable connections in the bank""" + #The enable is connected to a nand2 for every row. + return self.driver.get_w_en_cin() * len(self.driver_insts) From 680dc6d2c7a2069a616cebcb91acd2b0bd669ad3 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 17 Feb 2020 14:25:55 +0100 Subject: [PATCH 158/521] sense_amp/array: Remove hardcoded pin names all pin names should be wrapped into a function/property. This ensures that there is exactly one place to change the name. Signed-off-by: Bastian Koppelmann --- compiler/modules/sense_amp.py | 11 ++++++-- compiler/modules/sense_amp_array.py | 44 +++++++++++++++++------------ 2 files changed, 35 insertions(+), 20 deletions(-) diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index eb624111..0318d7bc 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -35,6 +35,14 @@ class sense_amp(design.design): def get_br_names(self): return "br" + @property + def dout_name(self): + return "dout" + + @property + def en_name(self): + return "en" + def __init__(self, name): design.design.__init__(self, name) debug.info(2, "Create sense_amp") @@ -79,11 +87,10 @@ class sense_amp(design.design): def get_enable_name(self): """Returns name used for enable net""" #FIXME: A better programmatic solution to designate pins - enable_name = "en" + enable_name = self.en_name debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name)) return enable_name def build_graph(self, graph, inst_name, port_nets): """Adds edges based on inputs/outputs. Overrides base class function.""" self.add_graph_edges(graph, port_nets) - \ No newline at end of file diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index f62b7a1d..452c0767 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -41,6 +41,14 @@ class sense_amp_array(design.design): br_name = self.amp.get_br_names() return br_name + @property + def data_name(self): + return "data" + + @property + def en_name(self): + return "en" + def create_netlist(self): self.add_modules() self.add_pins() @@ -62,10 +70,10 @@ class sense_amp_array(design.design): def add_pins(self): for i in range(0,self.word_size): - self.add_pin("data_{0}".format(i), "OUTPUT") - self.add_pin("bl_{0}".format(i), "INPUT") - self.add_pin("br_{0}".format(i), "INPUT") - self.add_pin("en", "INPUT") + self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT") + self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT") + self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT") + self.add_pin(self.en_name, "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -85,10 +93,10 @@ class sense_amp_array(design.design): name = "sa_d{0}".format(i) self.local_insts.append(self.add_inst(name=name, mod=self.amp)) - self.connect_inst(["bl_{0}".format(i), - "br_{0}".format(i), - "data_{0}".format(i), - "en", "vdd", "gnd"]) + self.connect_inst([self.get_bl_name() + "_{0}".format(i), + self.get_br_name() + "_{0}".format(i), + self.data_name + "_{0}".format(i), + self.en_name, "vdd", "gnd"]) def place_sense_amp_array(self): from tech import cell_properties @@ -128,22 +136,22 @@ class sense_amp_array(design.design): start_layer="m2", vertical=True) - bl_pin = inst.get_pin("bl") - br_pin = inst.get_pin("br") - dout_pin = inst.get_pin("dout") - - self.add_layout_pin(text="bl_{0}".format(i), + bl_pin = inst.get_pin(inst.mod.get_bl_names()) + br_pin = inst.get_pin(inst.mod.get_br_names()) + dout_pin = inst.get_pin(inst.mod.dout_name) + + self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i), layer="m2", offset=bl_pin.ll(), width=bl_pin.width(), height=bl_pin.height()) - self.add_layout_pin(text="br_{0}".format(i), + self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i), layer="m2", offset=br_pin.ll(), width=br_pin.width(), height=br_pin.height()) - - self.add_layout_pin(text="data_{0}".format(i), + + self.add_layout_pin(text=self.data_name + "_{0}".format(i), layer="m2", offset=dout_pin.ll(), width=dout_pin.width(), @@ -152,8 +160,8 @@ class sense_amp_array(design.design): def route_rails(self): # add sclk rail across entire array - sclk_offset = self.amp.get_pin("en").ll().scale(0,1) - self.add_layout_pin(text="en", + sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1) + self.add_layout_pin(text=self.en_name, layer="m1", offset=sclk_offset, width=self.width, From 76256a2f1bc2587fd9cc6554754d657772b67941 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 17 Feb 2020 14:27:35 +0100 Subject: [PATCH 159/521] sense_amp: Allow custom pin names we don't want to propagate the sense amp's bl/br names out of the sense_amp_array. Thus the sense_amp_array gets them named as "bl"/"br" again. Signed-off-by: Bastian Koppelmann --- compiler/base/custom_cell_properties.py | 9 ++++++++- compiler/modules/sense_amp.py | 17 +++++++++++------ compiler/modules/sense_amp_array.py | 4 ++-- 3 files changed, 21 insertions(+), 9 deletions(-) diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index 04d27379..ba671279 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -120,7 +120,10 @@ class cell_properties(): 'bl' : 'bl', 'br' : 'br', 'en' : 'en'}) - + self._sense_amp = _cell({'bl' : 'bl', + 'br' : 'br', + 'dout' : 'dout', + 'en' : 'en'}) @property def bitcell(self): @@ -141,3 +144,7 @@ class cell_properties(): @property def write_driver(self): return self._write_driver + + @property + def sense_amp(self): + return self._sense_amp diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index 0318d7bc..ff5638ba 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -9,6 +9,7 @@ import design import debug import utils from tech import GDS,layer, parameter,drc +from tech import cell_properties as props from globals import OPTS import logical_effort @@ -19,8 +20,12 @@ class sense_amp(design.design): the technology library. Sense amplifier to read a pair of bit-lines. """ - - pin_names = ["bl", "br", "dout", "en", "vdd", "gnd"] + pin_names = [props.sense_amp.pin.bl, + props.sense_amp.pin.br, + props.sense_amp.pin.dout, + props.sense_amp.pin.en, + props.sense_amp.pin.vdd, + props.sense_amp.pin.gnd] type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] if not OPTS.netlist_only: (width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"]) @@ -30,18 +35,18 @@ class sense_amp(design.design): pin_map = [] def get_bl_names(self): - return "bl" + return props.sense_amp.pin.bl def get_br_names(self): - return "br" + return props.sense_amp.pin.br @property def dout_name(self): - return "dout" + return props.sense_amp.pin.dout @property def en_name(self): - return "en" + return props.sense_amp.pin.en def __init__(self, name): design.design.__init__(self, name) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 452c0767..322cc1b3 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -34,11 +34,11 @@ class sense_amp_array(design.design): self.create_layout() def get_bl_name(self): - bl_name = self.amp.get_bl_names() + bl_name = "bl" return bl_name def get_br_name(self): - br_name = self.amp.get_br_names() + br_name = "br" return br_name @property From 843fce41d73e7dd34531e950aa8ecc3872dd662e Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 19 Feb 2020 03:06:11 -0800 Subject: [PATCH 160/521] Fixed issues with sen control logic for read ports. --- compiler/characterizer/delay.py | 2 +- compiler/modules/control_logic.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 2a8d5293..94e38ff2 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -650,7 +650,7 @@ class delay(simulation): debug.error("Timed out, could not find a feasible period.",2) # Clear any write target ports and set read port - self.targ_write_ports = [port] + self.targ_write_ports = [] self.targ_read_ports = [port] debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port)) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index e22d05b3..458b9b96 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -647,7 +647,7 @@ class control_logic(design.design): if self.port_type=="rw": input_name = "we_bar" else: - input_name = "cs_bar" + input_name = "cs" # GATE FOR S_EN self.s_en_gate_inst = self.add_inst(name="buf_s_en_and", mod=self.sen_and3) From e4fef73e3f3d6e80e1e0cd801e223533a293737b Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 19 Feb 2020 15:34:31 -0800 Subject: [PATCH 161/521] Fixed issues with bitcell measurements variable names, made target write ports required during characterization --- compiler/characterizer/delay.py | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 94e38ff2..a9f9542c 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -180,30 +180,30 @@ class delay(simulation): def create_read_bit_measures(self): """ Adds bit measurements for read0 and read1 cycles """ - self.bit_meas = {bit_polarity.NONINVERTING:[], bit_polarity.INVERTING:[]} + self.read_bit_meas = {bit_polarity.NONINVERTING:[], bit_polarity.INVERTING:[]} meas_cycles = (sram_op.READ_ZERO, sram_op.READ_ONE) for cycle in meas_cycles: meas_tag = "a{}_b{}_{}".format(self.probe_address, self.probe_data, cycle.name) single_bit_meas = self.get_bit_measures(meas_tag, self.probe_address, self.probe_data) for polarity,meas in single_bit_meas.items(): meas.meta_str = cycle - self.bit_meas[polarity].append(meas) + self.read_bit_meas[polarity].append(meas) # Dictionary values are lists, reduce to a single list of measurements - return [meas for meas_list in self.bit_meas.values() for meas in meas_list] + return [meas for meas_list in self.read_bit_meas.values() for meas in meas_list] def create_write_bit_measures(self): """ Adds bit measurements for write0 and write1 cycles """ - self.bit_meas = {bit_polarity.NONINVERTING:[], bit_polarity.INVERTING:[]} + self.write_bit_meas = {bit_polarity.NONINVERTING:[], bit_polarity.INVERTING:[]} meas_cycles = (sram_op.WRITE_ZERO, sram_op.WRITE_ONE) for cycle in meas_cycles: meas_tag = "a{}_b{}_{}".format(self.probe_address, self.probe_data, cycle.name) single_bit_meas = self.get_bit_measures(meas_tag, self.probe_address, self.probe_data) for polarity,meas in single_bit_meas.items(): meas.meta_str = cycle - self.bit_meas[polarity].append(meas) + self.write_bit_meas[polarity].append(meas) # Dictionary values are lists, reduce to a single list of measurements - return [meas for meas_list in self.bit_meas.values() for meas in meas_list] + return [meas for meas_list in self.write_bit_meas.values() for meas in meas_list] def get_bit_measures(self, meas_tag, probe_address, probe_data): """ @@ -649,8 +649,9 @@ class delay(simulation): if (time_out <= 0): debug.error("Timed out, could not find a feasible period.",2) - # Clear any write target ports and set read port - self.targ_write_ports = [] + # Write ports are assumed non-critical to timing, so the first available is used + self.targ_write_ports = [self.write_ports[0]] + # Set target read port for simulation self.targ_read_ports = [port] debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port)) @@ -733,7 +734,8 @@ class delay(simulation): # First, check that the memory has the right values at the right times - if not self.check_bit_measures(): + if not self.check_bit_measures(self.read_bit_meas) or \ + not self.check_bit_measures(self.write_bit_meas): return(False,{}) for port in self.targ_write_ports: @@ -824,13 +826,13 @@ class delay(simulation): return dout_success - def check_bit_measures(self): + def check_bit_measures(self, bit_measures): """ Checks the measurements which represent the internal storage voltages at the end of the read cycle. """ success = False - for polarity, meas_list in self.bit_meas.items(): + for polarity, meas_list in bit_measures.items(): for meas in meas_list: val = meas.retrieve_measure() debug.info(2,"{}={}".format(meas.name, val)) @@ -965,7 +967,8 @@ class delay(simulation): # Binary search algorithm to find the min period (max frequency) of input port time_out = 25 - self.targ_write_ports = [port] + # Write ports are assumed non-critical to timing, so the first available is used + self.targ_write_ports = [self.write_ports[0]] self.targ_read_ports = [port] while True: time_out -= 1 @@ -1253,8 +1256,8 @@ class delay(simulation): """ # Using this requires setting at least one port to target for simulation. - if len(self.targ_write_ports) == 0 and len(self.targ_read_ports) == 0: - debug.error("No port selected for characterization.",1) + if len(self.targ_write_ports) == 0 or len(self.targ_read_ports) == 0: + debug.error("Write and read port must be specified for characterization.",1) self.set_stimulus_variables() # Get any available read/write port in case only a single write or read ports is being characterized. From df2f981a34a38ea1760e3c02b3847ec7cf4e069c Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 19 Feb 2020 15:59:26 -0800 Subject: [PATCH 162/521] Adds checks to prevent characterization of redundant corners. --- compiler/characterizer/lib.py | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 6baff201..6d6c6ce5 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -81,17 +81,25 @@ class lib: self.lib_files = [] # Nominal corner - self.add_corner(nom_process, nom_supply, nom_temperature) + corner_set = set() + nom_corner = (nom_process, nom_supply, nom_temperature) + corner_set.add(nom_corner) if not OPTS.nominal_corner_only: # Temperature corners - self.add_corner(nom_process, nom_supply, min_temperature) - self.add_corner(nom_process, nom_supply, max_temperature) + corner_set.add((nom_process, nom_supply, min_temperature)) + corner_set.add((nom_process, nom_supply, max_temperature)) # Supply corners - self.add_corner(nom_process, min_supply, nom_temperature) - self.add_corner(nom_process, max_supply, nom_temperature) + corner_set.add((nom_process, min_supply, nom_temperature)) + corner_set.add((nom_process, max_supply, nom_temperature)) # Process corners - self.add_corner(min_process, nom_supply, nom_temperature) - self.add_corner(max_process, nom_supply, nom_temperature) + corner_set.add((min_process, nom_supply, nom_temperature)) + corner_set.add((max_process, nom_supply, nom_temperature)) + + # Enforce that nominal corner is the first to be characterized + self.add_corner(*nom_corner) + corner_set.remove(nom_corner) + for corner_tuple in corner_set: + self.add_corner(*corner_tuple) def add_corner(self, proc, volt, temp): self.corner_name = "{0}_{1}_{2}V_{3}C".format(self.sram.name, From d6987ac584b188f765c5ba8a129fae17ddf50bfe Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Wed, 19 Feb 2020 16:26:52 -0800 Subject: [PATCH 163/521] added purposes to addText(), removed reference to specific tech from gdsMill --- compiler/base/geometry.py | 55 +++++----- compiler/base/pin_layout.py | 77 +++++++------- compiler/gdsMill/gdsMill/gdsPrimitives.py | 9 +- compiler/gdsMill/gdsMill/vlsiLayout.py | 124 +++++++++++----------- 4 files changed, 130 insertions(+), 135 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index f354cf02..0041d3c9 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -51,7 +51,7 @@ class geometry: y = item[0] * math.sin(angle) + item[1] * mirr * math.cos(angle) + offset[1] coordinate += [[x, y]] return coordinate - + def normalize(self): """ Re-find the LL and UR points after a transform """ (first, second) = self.boundary @@ -64,14 +64,14 @@ class geometry: def update_boundary(self): """ Update the boundary with a new placement. """ self.compute_boundary(self.offset, self.mirror, self.rotate) - + def compute_boundary(self, offset=vector(0, 0), mirror="", rotate=0): """ Transform with offset, mirror and rotation to get the absolute pin location. We must then re-find the ll and ur. The master is the cell instance. """ if OPTS.netlist_only: self.boundary = [vector(0,0), vector(0,0)] return - + (ll, ur) = [vector(0, 0), vector(self.width, self.height)] if mirror == "MX": @@ -83,7 +83,7 @@ class geometry: elif mirror == "XY": ll = ll.scale(-1, -1) ur = ur.scale(-1, -1) - + if rotate == 90: ll = ll.rotate_scale(-1, 1) ur = ur.rotate_scale(-1, 1) @@ -96,19 +96,19 @@ class geometry: self.boundary = [offset + ll, offset + ur] self.normalize() - + def ll(self): """ Return the lower left corner """ return self.boundary[0] - + def ur(self): """ Return the upper right corner """ return self.boundary[1] - + def lr(self): """ Return the lower right corner """ return vector(self.boundary[1].x, self.boundary[0].y) - + def ul(self): """ Return the upper left corner """ return vector(self.boundary[0].x, self.boundary[1].y) @@ -132,12 +132,12 @@ class geometry: def cx(self): """ Return the center x """ return 0.5 * (self.boundary[0].x + self.boundary[1].x) - + def cy(self): """ Return the center y """ return 0.5 * (self.boundary[0].y + self.boundary[1].y) - - + + class instance(geometry): """ An instance of an instance/module with a specified location and @@ -148,7 +148,7 @@ class instance(geometry): geometry.__init__(self) debug.check(mirror not in ["R90", "R180", "R270"], "Please use rotation and not mirroring during instantiation.") - + self.name = name self.mod = mod self.gds = mod.gds @@ -166,7 +166,7 @@ class instance(geometry): self.width = round_to_grid(mod.width) self.height = round_to_grid(mod.height) self.compute_boundary(offset, mirror, rotate) - + debug.info(4, "creating instance: " + self.name) def get_blockages(self, lpp, top=False): @@ -202,11 +202,11 @@ class instance(geometry): new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) return new_blockages - + def gds_write_file(self, new_layout): """Recursively writes all the sub-modules in this instance""" debug.info(4, "writing instance: " + self.name) - # make sure to write out my module/structure + # make sure to write out my module/structure # (it will only be written the first time though) self.mod.gds_write_file(self.gds) # now write an instance of my module/structure @@ -215,7 +215,7 @@ class instance(geometry): offsetInMicrons=self.offset, mirror=self.mirror, rotate=self.rotate) - + def place(self, offset, mirror="R0", rotate=0): """ This updates the placement of an instance. """ # Update the placement of an already added instance @@ -224,8 +224,8 @@ class instance(geometry): self.rotate = rotate self.update_boundary() debug.info(3, "placing instance {}".format(self)) - - + + def get_pin(self,name,index=-1): """ Return an absolute pin that is offset and transformed based on this instance location. Index will return one of several pins.""" @@ -243,20 +243,20 @@ class instance(geometry): def get_num_pins(self, name): """ Return the number of pins of a given name """ return len(self.mod.get_pins(name)) - + def get_pins(self,name): """ Return an absolute pin that is offset and transformed based on this instance location. """ - + import copy pin = copy.deepcopy(self.mod.get_pins(name)) - + new_pins = [] for p in pin: - p.transform(self.offset,self.mirror,self.rotate) + p.transform(self.offset,self.mirror,self.rotate) new_pins.append(p) return new_pins - + def __str__(self): """ override print function output """ return "( inst: " + self.name + " @" + str(self.offset) + " mod=" + self.mod.name + " " + self.mirror + " R=" + str(self.rotate) + ")" @@ -293,7 +293,7 @@ class path(geometry): def get_blockages(self, layer): """ Fail since we don't support paths yet. """ assert(0) - + def __str__(self): """ override print function output """ return "path: layer=" + self.layerNumber + " w=" + self.width @@ -329,6 +329,7 @@ class label(geometry): debug.info(4, "writing label (" + str(self.layerNumber) + "): " + self.text) new_layout.addText(text=self.text, layerNumber=self.layerNumber, + layerPurpose=self.layerPurpose, offsetInMicrons=self.offset, magnification=self.zoom, rotate=None) @@ -336,7 +337,7 @@ class label(geometry): def get_blockages(self, layer): """ Returns an empty list since text cannot be blockages. """ return [] - + def __str__(self): """ override print function output """ return "label: " + self.text + " layer=" + str(self.layerNumber) @@ -345,7 +346,7 @@ class label(geometry): """ override print function output """ return "( label: " + self.text + " @" + str(self.offset) + " layer=" + str(self.layerNumber) + " )" - + class rectangle(geometry): """Represents a rectangular shape""" @@ -363,7 +364,7 @@ class rectangle(geometry): debug.info(4, "creating rectangle (" + str(self.layerNumber) + "): " + str(self.width) + "x" + str(self.height) + " @ " + str(self.offset)) - + def get_blockages(self, layer): """ Returns a list of one rectangle if it is on this layer""" if self.layerNumber == layer: diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index a057f3e0..f18956a8 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -30,7 +30,7 @@ class pin_layout: debug.check(self.width() > 0, "Zero width pin.") debug.check(self.height() > 0, "Zero height pin.") - + # if it's a string, use the name if type(layer_name_pp) == str: self._layer = layer_name_pp @@ -93,17 +93,17 @@ class pin_layout: is a major speedup, if pin_layout is used as a key for dicts. """ return self._hash - + def __lt__(self, other): """ Provide a function for ordering items by the ll point """ (ll, ur) = self.rect (oll, our) = other.rect - + if ll.x < oll.x and ll.y < oll.y: return True - + return False - + def __eq__(self, other): """ Check if these are the same pins for duplicate checks """ if isinstance(other, self.__class__): @@ -128,14 +128,14 @@ class pin_layout: max_y = max(max_y, pin.ur().y) self.rect = [vector(min_x, min_y), vector(max_x, max_y)] - + def fix_minarea(self): """ Try to fix minimum area rule. """ min_area = drc("{}_minarea".format(self.layer)) pass - + def inflate(self, spacing=None): """ Inflate the rectangle by the spacing (or other rule) @@ -143,12 +143,12 @@ class pin_layout: """ if not spacing: spacing = 0.5*drc("{0}_to_{0}".format(self.layer)) - + (ll, ur) = self.rect spacing = vector(spacing, spacing) newll = ll - spacing newur = ur + spacing - + return (newll, newur) def intersection(self, other): @@ -191,7 +191,7 @@ class pin_layout: y_overlaps = True return y_overlaps - + def xcontains(self, other): """ Check if shape contains the x overlap """ (ll, ur) = self.rect @@ -205,13 +205,13 @@ class pin_layout: (oll, our) = other.rect return (oll.y >= ll.y and our.y <= ur.y) - + def contains(self, other): """ Check if a shape contains another rectangle """ # If it is the same shape entirely, it is contained! if self == other: return True - + # Can only overlap on the same layer if not self.same_lpp(self.lpp, other.lpp): return False @@ -230,13 +230,13 @@ class pin_layout: if shape.contains(self): return True return False - + def overlaps(self, other): """ Check if a shape overlaps with a rectangle """ # Can only overlap on the same layer if not self.same_lpp(self.lpp, other.lpp): return False - + x_overlaps = self.xoverlaps(other) y_overlaps = self.yoverlaps(other) @@ -245,11 +245,11 @@ class pin_layout: def area(self): """ Return the area. """ return self.height()*self.width() - + def height(self): """ Return height. Abs is for pre-normalized value.""" return abs(self.rect[1].y-self.rect[0].y) - + def width(self): """ Return width. Abs is for pre-normalized value.""" return abs(self.rect[1].x-self.rect[0].x) @@ -260,7 +260,7 @@ class pin_layout: ll = vector(min(first[0], second[0]), min(first[1], second[1])) ur = vector(max(first[0], second[0]), max(first[1], second[1])) self.rect=[ll, ur] - + def transform(self, offset, mirror, rotate): """ Transform with offset, mirror and rotation @@ -278,7 +278,7 @@ class pin_layout: elif mirror == "XY": ll = ll.scale(-1, -1) ur = ur.scale(-1, -1) - + if rotate == 90: ll = ll.rotate_scale(-1, 1) ur = ur.rotate_scale(-1, 1) @@ -303,7 +303,7 @@ class pin_layout: def cy(self): """ Center y """ return 0.5*(self.rect[0].y+self.rect[1].y) - + # The four possible corners def ll(self): """ Lower left point """ @@ -320,7 +320,7 @@ class pin_layout: def ur(self): """ Upper right point """ return self.rect[1] - + # The possible y edge values def uy(self): """ Upper y value """ @@ -331,15 +331,15 @@ class pin_layout: return self.rect[0].y # The possible x edge values - + def lx(self): """ Left x value """ return self.rect[0].x - + def rx(self): """ Right x value """ return self.rect[1].x - + # The edge centers def rc(self): """ Right center point """ @@ -350,7 +350,7 @@ class pin_layout: """ Left center point """ return vector(self.rect[0].x, 0.5*(self.rect[0].y+self.rect[1].y)) - + def uc(self): """ Upper center point """ return vector(0.5*(self.rect[0].x+self.rect[1].x), @@ -378,6 +378,7 @@ class pin_layout: # imported into Magic. newLayout.addText(text=self.name, layerNumber=layer_num, + purposeNumber=purpose, offsetInMicrons=self.center(), magnification=GDS["zoom"], rotate=None) @@ -392,7 +393,7 @@ class pin_layout: dy = min(r1_ur.y, r2_ur.y) - max(r1_ll.y, r2_ll.y) dx = min(r1_ur.x, r2_ur.x) - max(r1_ll.x, r2_ll.x) - + if dx >= 0 and dy >= 0: return [dx, dy] else: @@ -407,7 +408,7 @@ class pin_layout: def dist(x1, y1, x2, y2): return math.sqrt((x2-x1)**2 + (y2-y1)**2) - + left = r2_ur.x < r1_ll.x right = r1_ur.x < r2_ll.x bottom = r2_ur.y < r1_ll.y @@ -432,7 +433,7 @@ class pin_layout: else: # rectangles intersect return 0 - + def overlap_length(self, other): """ Calculate the intersection segment and determine its length @@ -453,7 +454,7 @@ class pin_layout: # This is where we had a corner intersection or none return 0 - + def compute_overlap_segment(self, other): """ Calculate the intersection segment of two rectangles @@ -469,19 +470,19 @@ class pin_layout: r2_lr = vector(r2_ur.x, r2_ll.y) from itertools import tee - + def pairwise(iterable): "s -> (s0,s1), (s1,s2), (s2, s3), ..." a, b = tee(iterable) next(b, None) return zip(a, b) - + # R1 edges CW r1_cw_points = [r1_ll, r1_ul, r1_ur, r1_lr, r1_ll] r1_edges = [] for (p, q) in pairwise(r1_cw_points): r1_edges.append([p, q]) - + # R2 edges CW r2_cw_points = [r2_ll, r2_ul, r2_ur, r2_lr, r2_ll] r2_edges = [] @@ -509,9 +510,9 @@ class pin_layout: q.y <= max(p.y, r.y) and \ q.y >= min(p.y, r.y): return True - + return False - + def segment_intersection(self, s1, s2): """ Determine the intersection point of two segments @@ -524,22 +525,22 @@ class pin_layout: a1 = b.y - a.y b1 = a.x - b.x c1 = a1*a.x + b1*a.y - + # Line CD represented as a2x + b2y = c2 a2 = d.y - c.y b2 = c.x - d.x c2 = a2*c.x + b2*c.y - + determinant = a1*b2 - a2*b1 if determinant != 0: x = (b2*c1 - b1*c2)/determinant y = (a1*c2 - a2*c1)/determinant - + r = vector(x, y).snap_to_grid() if self.on_segment(a, r, b) and self.on_segment(c, r, d): return r - + return None def same_lpp(self, lpp1, lpp2): @@ -549,5 +550,5 @@ class pin_layout: """ if lpp1[1] == None or lpp2[1] == None: return lpp1[0] == lpp2[0] - + return lpp1[0] == lpp2[0] and lpp1[1] == lpp2[1] diff --git a/compiler/gdsMill/gdsMill/gdsPrimitives.py b/compiler/gdsMill/gdsMill/gdsPrimitives.py index 13b8acf9..8e07524c 100644 --- a/compiler/gdsMill/gdsMill/gdsPrimitives.py +++ b/compiler/gdsMill/gdsMill/gdsPrimitives.py @@ -1,12 +1,5 @@ import math -from globals import OPTS -# default purpose layer is used for addText() in vlsiLayout.py -if OPTS.tech_name == "s8": - purposeLayer=20 -else: - purposeLayer=0 - class GdsStructure: """Class represent a GDS Structure Object""" def __init__(self): @@ -147,7 +140,7 @@ class GdsText: self.elementFlags="" self.plex="" self.drawingLayer="" - self.purposeLayer=purposeLayer + self.purposeLayer=0 self.transFlags=[0,0,0] self.magFactor="" self.rotateAngle="" diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index 412a430c..979180cd 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -35,7 +35,7 @@ class VlsiLayout: modDate.hour, modDate.minute, modDate.second) - + self.info = dict() #information gathered from the GDSII header self.info['units']=self.units self.info['dates']=(modDate.year, @@ -52,12 +52,12 @@ class VlsiLayout: modDate.second) self.info['libraryName']=libraryName self.info['gdsVersion']=gdsVersion - + self.xyTree = [] #This will contain a list of all structure names #expanded to include srefs / arefs separately. #each structure will have an X,Y,offset, and rotate associated #with it. Populate via traverseTheHierarchy method. - + #temp variables used in delegate functions self.tempCoordinates=None self.tempPassFail = True @@ -73,14 +73,14 @@ class VlsiLayout: if(rotateAngle): angle = math.radians(float(rotateAngle)) - coordinatesRotate = [] #this will hold the rotated values + coordinatesRotate = [] #this will hold the rotated values for coordinate in coordinatesToRotate: # This is the CCW rotation matrix newX = coordinate[0]*math.cos(angle) - coordinate[1]*math.sin(angle) newY = coordinate[0]*math.sin(angle) + coordinate[1]*math.cos(angle) coordinatesRotate.extend((newX,newY)) return coordinatesRotate - + def rename(self,newName): #take the root structure and copy it to a new structure with the new name self.structures[newName] = self.structures[self.rootStructureName] @@ -129,8 +129,8 @@ class VlsiLayout: modDate.hour, modDate.minute, modDate.second) - - + + #repopulate the 2d map so drawing occurs correctly self.prepareForWrite() @@ -155,15 +155,15 @@ class VlsiLayout: debug.check(len(structureNames)==1,"Multiple possible root structures in the layout: {}".format(str(structureNames))) self.rootStructureName = structureNames[0] - - def traverseTheHierarchy(self, startingStructureName=None, delegateFunction = None, + + def traverseTheHierarchy(self, startingStructureName=None, delegateFunction = None, transformPath = [], rotateAngle = 0, transFlags = [0,0,0], coordinates = (0,0)): #since this is a recursive function, must deal with the default - #parameters explicitly + #parameters explicitly if startingStructureName == None: - startingStructureName = self.rootStructureName + startingStructureName = self.rootStructureName - #set up the rotation matrix + #set up the rotation matrix if(rotateAngle == None or rotateAngle == ""): angle = 0 else: @@ -193,10 +193,10 @@ class VlsiLayout: try: if(len(self.structures[startingStructureName].srefs)>0): #does this structure reference any others? #if so, go through each and call this function again - #if not, return back to the caller (caller can be this function) + #if not, return back to the caller (caller can be this function) for sref in self.structures[startingStructureName].srefs: - #here, we are going to modify the sref coordinates based on the parent objects rotation - self.traverseTheHierarchy(startingStructureName = sref.sName, + #here, we are going to modify the sref coordinates based on the parent objects rotation + self.traverseTheHierarchy(startingStructureName = sref.sName, delegateFunction = delegateFunction, transformPath = transformPath, rotateAngle = sref.rotateAngle, @@ -204,12 +204,12 @@ class VlsiLayout: coordinates = sref.coordinates) except KeyError: debug.error("Could not find structure {} in GDS file.".format(startingStructureName),-1) - + #MUST HANDLE AREFs HERE AS WELL #when we return, drop the last transform from the transformPath del transformPath[-1] return - + def initialize(self): self.deduceHierarchy() # self.traverseTheHierarchy() @@ -217,17 +217,17 @@ class VlsiLayout: for layerNumber in self.layerNumbersInUse: self.processLabelPins((layerNumber, None)) - - + + def populateCoordinateMap(self): def addToXyTree(startingStructureName = None,transformPath = None): uVector = np.array([[1.0],[0.0],[0.0]]) #start with normal basis vectors vVector = np.array([[0.0],[1.0],[0.0]]) origin = np.array([[0.0],[0.0],[1.0]]) #and an origin (Z component is 1.0 to indicate position instead of vector) - #make a copy of all the transforms and reverse it + #make a copy of all the transforms and reverse it reverseTransformPath = transformPath[:] if len(reverseTransformPath) > 1: - reverseTransformPath.reverse() + reverseTransformPath.reverse() #now go through each transform and apply them to our basis and origin in succession for transform in reverseTransformPath: origin = np.dot(transform[0], origin) #rotate @@ -237,20 +237,20 @@ class VlsiLayout: uVector = np.dot(transform[1], uVector) #scale vVector = np.dot(transform[1], vVector) #scale origin = np.dot(transform[2], origin) #translate - #we don't need to do a translation on the basis vectors + #we don't need to do a translation on the basis vectors #uVector = transform[2] * uVector #translate #vVector = transform[2] * vVector #translate #populate the xyTree with each structureName and coordinate space self.xyTree.append((startingStructureName,origin,uVector,vVector)) self.traverseTheHierarchy(delegateFunction = addToXyTree) - + def microns(self, userUnits): """Utility function to convert user units to microns""" userUnit = self.units[1]/self.units[0] userUnitsPerMicron = userUnit / userunit layoutUnitsPerMicron = userUnitsPerMicron / self.units[0] return userUnits / layoutUnitsPerMicron - + def userUnits(self, microns): """Utility function to convert microns to user units""" userUnit = self.units[1]/self.units[0] @@ -270,7 +270,7 @@ class VlsiLayout: if self.debug: debug.info(0,"DEBUG: GdsMill vlsiLayout: changeRoot: %s "%newRoot) - + # Determine if newRoot exists # layoutToAdd (default) or nameOfLayout if (newRoot == 0 | ((newRoot not in self.structures) & ~create)): @@ -282,19 +282,19 @@ class VlsiLayout: self.rootStructureName = newRoot - + def addInstance(self,layoutToAdd,nameOfLayout=0,offsetInMicrons=(0,0),mirror=None,rotate=None): """ Method to insert one layout into another at a particular offset. """ offsetInLayoutUnits = (self.userUnits(offsetInMicrons[0]),self.userUnits(offsetInMicrons[1])) - if self.debug: + if self.debug: debug.info(0,"DEBUG: GdsMill vlsiLayout: addInstance: type {0}, nameOfLayout {1}".format(type(layoutToAdd),nameOfLayout)) debug.info(0,"DEBUG: name={0} offset={1} mirror={2} rotate={3}".format(layoutToAdd.rootStructureName,offsetInMicrons, mirror, rotate)) - # Determine if we are instantiating the root design of + # Determine if we are instantiating the root design of # layoutToAdd (default) or nameOfLayout if nameOfLayout == 0: StructureFound = True @@ -303,7 +303,7 @@ class VlsiLayout: StructureName = nameOfLayout #layoutToAdd StructureFound = False for structure in layoutToAdd.structures: - if StructureName in structure: + if StructureName in structure: if self.debug: debug.info(1,"DEBUG: Structure %s Found"%StructureName) StructureFound = True @@ -311,7 +311,7 @@ class VlsiLayout: debug.check(StructureFound,"Could not find layout to instantiate {}".format(StructureName)) - # If layoutToAdd is a unique object (not this), then copy hierarchy, + # If layoutToAdd is a unique object (not this), then copy hierarchy, # otherwise, if it is a text name of an internal structure, use it. if layoutToAdd != self: @@ -330,7 +330,7 @@ class VlsiLayout: layoutToAddSref.coordinates = offsetInLayoutUnits if mirror or rotate: - + layoutToAddSref.transFlags = [0,0,0] # transFlags = (mirror around x-axis, magnification, rotation) # If magnification or rotation is true, it is the flags are then @@ -356,7 +356,7 @@ class VlsiLayout: #add the sref to the root structure self.structures[self.rootStructureName].srefs.append(layoutToAddSref) - + def addBox(self,layerNumber=0, purposeNumber=0, offsetInMicrons=(0,0), width=1.0, height=1.0,center=False): """ Method to add a box to a layout @@ -373,7 +373,7 @@ class VlsiLayout: (offsetInLayoutUnits[0],offsetInLayoutUnits[1]+heightInLayoutUnits), offsetInLayoutUnits] else: - startPoint = (offsetInLayoutUnits[0]-widthInLayoutUnits/2.0, offsetInLayoutUnits[1]-heightInLayoutUnits/2.0) + startPoint = (offsetInLayoutUnits[0]-widthInLayoutUnits/2.0, offsetInLayoutUnits[1]-heightInLayoutUnits/2.0) coordinates=[startPoint, (startPoint[0]+widthInLayoutUnits,startPoint[1]), (startPoint[0]+widthInLayoutUnits,startPoint[1]+heightInLayoutUnits), @@ -386,7 +386,7 @@ class VlsiLayout: boundaryToAdd.purposeLayer = purposeNumber #add the sref to the root structure self.structures[self.rootStructureName].boundaries.append(boundaryToAdd) - + def addPath(self, layerNumber=0, purposeNumber=0, coordinates=[(0,0)], width=1.0): """ Method to add a path to a layout @@ -405,11 +405,12 @@ class VlsiLayout: pathToAdd.coordinates = layoutUnitCoordinates #add the sref to the root structure self.structures[self.rootStructureName].paths.append(pathToAdd) - - def addText(self, text, layerNumber=0, offsetInMicrons=(0,0), magnification=0.1, rotate = None): + + def addText(self, text, layerNumber=0, purposeNumber=0, offsetInMicrons=(0,0), magnification=0.1, rotate = None): offsetInLayoutUnits = (self.userUnits(offsetInMicrons[0]),self.userUnits(offsetInMicrons[1])) textToAdd = GdsText() textToAdd.drawingLayer = layerNumber + textToAdd.purposeLayer = purposeNumber textToAdd.coordinates = [offsetInLayoutUnits] textToAdd.transFlags = [0,0,0] textToAdd.textString = self.padText(text) @@ -438,7 +439,7 @@ class VlsiLayout: return 1 else: return 0 - + def intersectionPoint(self,startPoint1,endPoint1,startPoint2,endPoint2): if((endPoint1[0]-startPoint1[0])!=0 and (endPoint2[0]-startPoint2[0])!=0): pSlope = (endPoint1[1]-startPoint1[1])/(endPoint1[0]-startPoint1[0]) @@ -458,7 +459,7 @@ class VlsiLayout: newY = None elif((endPoint1[0]-startPoint1[0])==0 and (endPoint2[0]-startPoint2[0])!=0): qSlope = (endPoint2[1]-startPoint2[1])/(endPoint2[0]-startPoint2[0]) - qIntercept = startPoint2[1]-qSlope*startPoint2[0] + qIntercept = startPoint2[1]-qSlope*startPoint2[0] newX=endPoint1[0] newY=qSlope*newX+qIntercept elif((endPoint1[0]-startPoint1[0])!=0 and (endPoint2[0]-startPoint2[0])==0): @@ -467,14 +468,14 @@ class VlsiLayout: newX=endPoint2[0] newY=pSlope*newX+pIntercept return (newX,newY) - + def isCollinear(self,testPoint,point1,point2): slope1 = (testPoint[1]-point1[1])/(testPoint[0]-point1[0]) slope2 = (point2[1]-point1[1])/(point2[0]-point1[0]) if slope1 == slope2: return True return False - + def doShapesIntersect(self,shape1Coordinates, shape2Coordinates): """ Utility function to determine if 2 arbitrary shapes intersect. @@ -491,7 +492,7 @@ class VlsiLayout: if(self.isBounded(intersect,startPoint1,endPoint1) and self.isBounded(intersect,startPoint2,endPoint2)): return True #these shapes overlap! return False #these shapes are ok - + def isPointInsideOfBox(self,pointCoordinates,boxCoordinates): """ Check if a point is contained in the shape @@ -516,7 +517,7 @@ class VlsiLayout: pointCoordinates[1] Date: Wed, 19 Feb 2020 23:32:11 -0800 Subject: [PATCH 164/521] Changed layout input names of s_en AND gate to match the schematic --- compiler/modules/control_logic.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 458b9b96..1612938d 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -670,7 +670,7 @@ class control_logic(design.design): if self.port_type=="rw": input_name = "we_bar" else: - input_name = "cs_bar" + input_name = "cs" sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name]) self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets) From 88bc1f09cb29bff19a3c92855942c520a6852c03 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Thu, 20 Feb 2020 17:01:52 +0000 Subject: [PATCH 165/521] Characterization for extra rows --- compiler/characterizer/delay.py | 3 +- compiler/characterizer/functional.py | 5 +- compiler/characterizer/simulation.py | 7 +- compiler/characterizer/trim_spice.py | 4 +- compiler/gen_stimulus.py | 3 +- compiler/globals.py | 2 + compiler/openram.py | 3 +- .../tests/21_ngspice_delay_extra_rows_test.py | 95 +++++++++++++++++++ 8 files changed, 115 insertions(+), 7 deletions(-) create mode 100755 compiler/tests/21_ngspice_delay_extra_rows_test.py diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 2a8d5293..9b59c9e6 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -1063,7 +1063,8 @@ class delay(simulation): self.trimsp.set_configuration(self.num_banks, self.num_rows, self.num_cols, - self.word_size) + self.word_size, + self.num_spare_rows) self.trimsp.trim(self.probe_address,self.probe_data) else: # The non-reduced netlist file when it is disabled diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 6d827aa3..cbd9b8d5 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -287,7 +287,10 @@ class functional(simulation): def gen_addr(self): """ Generates a random address value to write to. """ - random_value = random.randint(0,(2**self.addr_size)-1) + if (self.num_spare_rows == 0): + random_value = random.randint(0,(2**self.addr_size)-1) + else: + random_value = random.randint(0,((2**(self.addr_size-1)-1))+(self.num_spare_rows * self.words_per_row)) addr_bits = self.convert_to_bin(random_value,True) return addr_bits diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index adbe5f5f..b21c0bd0 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -25,12 +25,14 @@ class simulation(): self.word_size = self.sram.word_size self.addr_size = self.sram.addr_size self.write_size = self.sram.write_size + self.num_spare_rows = self.sram.num_spare_rows self.sp_file = spfile self.all_ports = self.sram.all_ports self.readwrite_ports = self.sram.readwrite_ports self.read_ports = self.sram.read_ports self.write_ports = self.sram.write_ports + self.words_per_row = self.sram.words_per_row if self.write_size: self.num_wmasks = int(self.word_size/self.write_size) else: @@ -135,7 +137,10 @@ class simulation(): if c=="0": self.addr_values[port][bit].append(0) elif c=="1": - self.addr_values[port][bit].append(1) + if((self.num_spare_rows != 0) and (bit == (self.addr_size - 1))): + self.addr_values[port][bit].append(0) + else: + self.addr_values[port][bit].append(1) else: debug.error("Non-binary address string",1) bit -= 1 diff --git a/compiler/characterizer/trim_spice.py b/compiler/characterizer/trim_spice.py index ffc45a9c..d20dfe42 100644 --- a/compiler/characterizer/trim_spice.py +++ b/compiler/characterizer/trim_spice.py @@ -6,7 +6,7 @@ # All rights reserved. # import debug -from math import log +from math import log,ceil import re class trim_spice(): @@ -42,7 +42,7 @@ class trim_spice(): self.word_size = word_size self.words_per_row = self.num_columns / self.word_size - self.row_addr_size = int(log(self.num_rows, 2)) + self.row_addr_size = ceil(log(self.num_rows, 2)) self.col_addr_size = int(log(self.words_per_row, 2)) self.bank_addr_size = self.col_addr_size + self.row_addr_size self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2)) diff --git a/compiler/gen_stimulus.py b/compiler/gen_stimulus.py index 0c5d988c..5e351577 100755 --- a/compiler/gen_stimulus.py +++ b/compiler/gen_stimulus.py @@ -52,11 +52,12 @@ import sram class fake_sram(sram.sram): """ This is an SRAM that doesn't actually create itself, just computes the sizes. """ - def __init__(self, word_size, num_words, num_banks, name): + def __init__(self, word_size, num_words, num_banks, name, num_spare_rows): self.name = name self.word_size = word_size self.num_words = num_words self.num_banks = num_banks + self.num_spare_rows = num_spare_rows c = reload(__import__(OPTS.bitcell)) self.mod_bitcell = getattr(c, OPTS.bitcell) self.bitcell = self.mod_bitcell() diff --git a/compiler/globals.py b/compiler/globals.py index e9b77d66..69ead34f 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -532,6 +532,8 @@ def report_status(): debug.error("{0} is not an integer in config file.".format(OPTS.sram_size)) if type(OPTS.write_size) is not int and OPTS.write_size is not None: debug.error("{0} is not an integer in config file.".format(OPTS.write_size)) + if type(OPTS.num_spare_rows) is not int and OPT.num_spare_rows is not None: + debug.error("{0} is not an integer in config file.".format(OPTS.num_spare_rows)) # If a write mask is specified by the user, the mask write size should be the same as # the word size so that an entire word is written at once. diff --git a/compiler/openram.py b/compiler/openram.py index 63a8cfd6..cf18f97b 100755 --- a/compiler/openram.py +++ b/compiler/openram.py @@ -53,7 +53,8 @@ from sram_config import sram_config # Configure the SRAM organization c = sram_config(word_size=OPTS.word_size, num_words=OPTS.num_words, - write_size=OPTS.write_size) + write_size=OPTS.write_size, + num_spare_rows=OPTS.num_spare_rows) debug.print_raw("Words per row: {}".format(c.words_per_row)) output_extensions = ["sp", "v", "lib", "py", "html", "log"] diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py new file mode 100755 index 00000000..328dc630 --- /dev/null +++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class timing_sram_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.spice_name="ngspice" + OPTS.analytical_delay = False + OPTS.netlist_only = True + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import delay + from sram_config import sram_config + c = sram_config(word_size=1, + num_words=16, + num_banks=1, + num_spare_rows=5) + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") + s = factory.create(module_type="sram", sram_config=c) + + tempspice = OPTS.openram_temp + "temp.sp" + s.sp_write(tempspice) + + probe_address = "0" + ("1" * (s.s.addr_size - 1)) + probe_data = s.s.word_size - 1 + debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data)) + + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + d = delay(s.s, tempspice, corner) + import tech + loads = [tech.spice["dff_in_cap"]*4] + slews = [tech.spice["rise_time"]*2] + data, port_data = d.analyze(probe_address, probe_data, slews, loads) + #Combine info about port into all data + data.update(port_data[0]) + + if OPTS.tech_name == "freepdk45": + golden_data = {'delay_hl': [0.2264205], + 'delay_lh': [0.2264205], + 'leakage_power': 0.0021017429999999997, + 'min_period': 0.859, + 'read0_power': [0.3339161], + 'read1_power': [0.31329440000000003], + 'slew_hl': [0.2590786], + 'slew_lh': [0.2590786], + 'write0_power': [0.36360849999999995], + 'write1_power': [0.3486931]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'delay_hl': [1.85985], + 'delay_lh': [1.85985], + 'leakage_power': 0.006418553, + 'min_period': 6.875, + 'read0_power': [12.656310000000001], + 'read1_power': [12.11682], + 'slew_hl': [1.868942], + 'slew_lh': [1.868942], + 'write0_power': [13.978110000000001], + 'write1_power': [11.437930000000001]} + else: + self.assertTrue(False) # other techs fail + + # Check if no too many or too few results + self.assertTrue(len(data.keys())==len(golden_data.keys())) + + self.assertTrue(self.check_golden_data(data,golden_data,0.25)) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 694ea5c20ea58d831068fde3c596548420f5f756 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Thu, 20 Feb 2020 17:31:58 +0000 Subject: [PATCH 166/521] Characterization for extra rows --- compiler/modules/bank.py | 2 +- compiler/tests/21_ngspice_delay_extra_rows_test.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index aea4e909..e2f0186a 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -8,7 +8,7 @@ import debug import design from sram_factory import factory -from math import log +from math import log, ceil from tech import drc from vector import vector from globals import OPTS diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py index 328dc630..66827ef5 100755 --- a/compiler/tests/21_ngspice_delay_extra_rows_test.py +++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py @@ -33,7 +33,7 @@ class timing_sram_test(openram_test): c = sram_config(word_size=1, num_words=16, num_banks=1, - num_spare_rows=5) + num_spare_rows=3) c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") From c9cb387912b62b13ec3eed726ae98de20a445233 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Thu, 20 Feb 2020 18:35:54 -0800 Subject: [PATCH 167/521] fixed variable typo --- compiler/base/geometry.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 0041d3c9..cfda3553 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -329,7 +329,7 @@ class label(geometry): debug.info(4, "writing label (" + str(self.layerNumber) + "): " + self.text) new_layout.addText(text=self.text, layerNumber=self.layerNumber, - layerPurpose=self.layerPurpose, + purposeNumber=self.layerPurpose, offsetInMicrons=self.offset, magnification=self.zoom, rotate=None) From 0e641bf9054e55197cbd4988a5765cd7590bb1f7 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 21 Feb 2020 13:29:43 +0100 Subject: [PATCH 168/521] Remove write_driver_array.py.orig this was the remainder of applying a diff using "patch". To avoid this mistake, add the filetypes created by "patch" to the .gitignore. Signed-off-by: Bastian Koppelmann --- .gitignore | 4 +- compiler/modules/write_driver_array.py.orig | 202 -------------------- 2 files changed, 3 insertions(+), 203 deletions(-) delete mode 100644 compiler/modules/write_driver_array.py.orig diff --git a/.gitignore b/.gitignore index b16e3d0b..948e7d19 100644 --- a/.gitignore +++ b/.gitignore @@ -1,8 +1,10 @@ .DS_Store *~ +*.orig +*.rej *.pyc *.aux *.out *.toc *.synctex.gz -**/model_data \ No newline at end of file +**/model_data diff --git a/compiler/modules/write_driver_array.py.orig b/compiler/modules/write_driver_array.py.orig deleted file mode 100644 index 16233c88..00000000 --- a/compiler/modules/write_driver_array.py.orig +++ /dev/null @@ -1,202 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -from math import log -import design -from tech import drc -import debug -from sram_factory import factory -from vector import vector -from globals import OPTS - -class write_driver_array(design.design): - """ - Array of tristate drivers to write to the bitlines through the column mux. - Dynamically generated write driver array of all bitlines. - """ - - def __init__(self, name, columns, word_size,write_size=None): - design.design.__init__(self, name) - debug.info(1, "Creating {0}".format(self.name)) - self.add_comment("columns: {0}".format(columns)) - self.add_comment("word_size {0}".format(word_size)) - - self.columns = columns - self.word_size = word_size - self.write_size = write_size - self.words_per_row = int(columns / word_size) - - if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) - - self.create_netlist() - if not OPTS.netlist_only: - self.create_layout() - - def get_bl_name(self): - bl_name = self.driver.get_bl_names() - return bl_name - - def get_br_name(self): - br_name = self.driver.get_br_names() - return br_name - - @property - def data_name(self): - return "data" - - @property - def en_name(self): - return "en" - - def create_netlist(self): - self.add_modules() - self.add_pins() - self.create_write_array() - - def create_layout(self): - - if self.bitcell.width > self.driver.width: - self.width = self.columns * self.bitcell.width - else: - self.width = self.columns * self.driver.width - self.height = self.driver.height - - self.place_write_array() - self.add_layout_pins() - self.add_boundary() - self.DRC_LVS() - - def add_pins(self): - for i in range(self.word_size): - self.add_pin(self.data_name + "_{0}".format(i), "INPUT") - for i in range(self.word_size): - self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT") - self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT") - if self.write_size: - for i in range(self.num_wmasks): - self.add_pin(self.en_name + "_{0}".format(i), "INPUT") - else: - self.add_pin(self.en_name, "INPUT") - self.add_pin("vdd", "POWER") - self.add_pin("gnd", "GROUND") - - def add_modules(self): - self.driver = factory.create(module_type="write_driver") - self.add_mod(self.driver) - - # This is just used for measurements, - # so don't add the module - self.bitcell = factory.create(module_type="bitcell") - - def create_write_array(self): - self.driver_insts = {} - w = 0 - windex=0 - for i in range(0,self.columns,self.words_per_row): - name = "write_driver{}".format(i) - index = int(i/self.words_per_row) - self.driver_insts[index]=self.add_inst(name=name, - mod=self.driver) - - if self.write_size: - self.connect_inst([self.data_name + "_{0}".format(index), - self.get_bl_name() + "_{0}".format(index), - self.get_br_name() + "_{0}".format(index), - self.en_name + "_{0}".format(windex), "vdd", "gnd"]) - w+=1 - # when w equals write size, the next en pin can be connected since we are now at the next wmask bit - if w == self.write_size: - w = 0 - windex+=1 - else: - self.connect_inst([self.data_name + "_{0}".format(index), - self.get_bl_name() + "_{0}".format(index), - self.get_br_name() + "_{0}".format(index), - self.en_name, "vdd", "gnd"]) - - - def place_write_array(self): - from tech import cell_properties - if self.bitcell.width > self.driver.width: - self.driver_spacing = self.bitcell.width - else: - self.driver_spacing = self.driver.width - for i in range(0,self.columns,self.words_per_row): - index = int(i/self.words_per_row) - xoffset = i * self.driver_spacing - - if cell_properties.bitcell.mirror.y and i % 2: - mirror = "MY" - xoffset = xoffset + self.driver.width - else: - mirror = "" - - base = vector(xoffset, 0) - self.driver_insts[index].place(offset=base, mirror=mirror) - - - def add_layout_pins(self): - for i in range(self.word_size): - inst = self.driver_insts[i] - din_pin = inst.get_pin(inst.mod.din_name) - self.add_layout_pin(text=self.data_name + "_{0}".format(i), - layer="m2", - offset=din_pin.ll(), - width=din_pin.width(), - height=din_pin.height()) - bl_pin = inst.get_pin(inst.mod.get_bl_names()) - self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i), - layer="m2", - offset=bl_pin.ll(), - width=bl_pin.width(), - height=bl_pin.height()) - - br_pin = inst.get_pin(inst.mod.get_br_names()) - self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i), - layer="m2", - offset=br_pin.ll(), - width=br_pin.width(), - height=br_pin.height()) - - for n in ["vdd", "gnd"]: - pin_list = self.driver_insts[i].get_pins(n) - for pin in pin_list: - self.add_power_pin(name = n, - loc = pin.center(), - vertical=True, - start_layer = "m2") - if self.write_size: - for bit in range(self.num_wmasks): - inst = self.driver_insts[bit*self.write_size] - en_pin = inst.get_pin(inst.mod.en_name) - # Determine width of wmask modified en_pin with/without col mux - wmask_en_len = self.words_per_row*(self.write_size * self.driver_spacing) - if (self.words_per_row == 1): - en_gap = self.driver_spacing - en_pin.width() - else: - en_gap = self.driver_spacing - - self.add_layout_pin(text=self.en_name + "_{0}".format(bit), - layer=en_pin.layer, - offset=en_pin.ll(), - width=wmask_en_len-en_gap, - height=en_pin.height()) - else: - inst = self.driver_insts[0] - self.add_layout_pin(text=self.en_name, - layer="m1", - offset=inst.get_pin(inst.mod.en_name).ll().scale(0,1), - width=self.width) - - - - - def get_w_en_cin(self): - """Get the relative capacitance of all the enable connections in the bank""" - #The enable is connected to a nand2 for every row. - return self.driver.get_w_en_cin() * len(self.driver_insts) From 35110a4453dd7b9f03959c326f3a6141c229b12e Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 Feb 2020 00:34:28 +0000 Subject: [PATCH 169/521] Improve debug of non-manhattan error --- compiler/base/hierarchy_layout.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 451d1356..2e0bf755 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -322,9 +322,10 @@ class layout(): """ Creates a path like pin with center-line convention """ - - debug.check(start.x == end.x or start.y == end.y, - "Cannot have a non-manhatten layout pin.") + if start.x != end.x and start.y != end.y: + file_name = "non_rectilinear.gds" + self.gds_write(file_name) + debug.error("Cannot have a non-manhatten layout pin: {}".format(file_name), -1) minwidth_layer = drc["minwidth_{}".format(layer)] From 6bcffb8efb680f1321098580c52e59bf3fb0e2a8 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 Feb 2020 00:34:59 +0000 Subject: [PATCH 170/521] Change default cell height and fix contact width error --- compiler/pgates/pgate.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 6d385d09..8b9a1c66 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -26,8 +26,8 @@ class pgate(design.design): if height: self.height = height elif not height: - # By default, we make it 8 M1 pitch tall - self.height = 8*self.m1_pitch + # By default, we make it 10 M1 pitch tall + self.height = 10*self.m1_pitch self.create_netlist() if not OPTS.netlist_only: @@ -103,7 +103,7 @@ class pgate(design.design): - vector(0.5 * contact_width - 0.5 * self.poly_width, 0) elif position == "right": contact_offset = left_gate_offset \ - + vector(0.5 * contact.width + 0.5 * self.poly_width, 0) + + vector(0.5 * contact_width + 0.5 * self.poly_width, 0) else: debug.error("Invalid contact placement option.", -1) From d565c9ac727917fc32efb999c13ffb671f620386 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 Feb 2020 00:35:32 +0000 Subject: [PATCH 171/521] Generalize input y offsets --- compiler/pgates/pnand2.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index dd04ccb9..7c40c7ab 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -190,16 +190,16 @@ class pnand2(pgate.pgate): def route_inputs(self): """ Route the A and B inputs """ - inputB_yoffset = self.nmos2_pos.y + self.nmos.active_height \ - + self.m2_space + 0.5 * self.m2_width + inputB_yoffset = self.nmos2_inst.uy() + 0.5 * contact.poly_contact.height self.route_input_gate(self.pmos2_inst, self.nmos2_inst, inputB_yoffset, "B", - position="center") + position="right") # This will help with the wells and the input/output placement - self.inputA_yoffset = inputB_yoffset + self.input_spacing + self.inputA_yoffset = self.pmos2_inst.by() - self.poly_extend_active \ + - contact.poly_contact.height self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, From 585a708e0c6972a3799ffc3b3919884ee40546ab Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 Feb 2020 00:36:02 +0000 Subject: [PATCH 172/521] Generalize y offsets in pnand3 --- compiler/pgates/pnand3.py | 46 ++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 9ec9ff60..087cffd5 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -87,13 +87,14 @@ class pnand3(pgate.pgate): """ Pre-compute some handy layout parameters. """ # Compute the overlap of the source and drain pins - self.overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll() - + overlap_xoffset = self.pmos.get_pin("D").ll().x - self.pmos.get_pin("S").ll().x + self.ptx_offset = vector(overlap_xoffset, 0) + # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. self.width = 3 * self.pmos.active_width + self.pmos.active_contact.width \ + 2 * self.active_space + 0.5 * self.nwell_enclose_active \ - - self.overlap_offset.x + - self.ptx_offset.x self.well_width = self.width + 2 * self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. @@ -157,10 +158,10 @@ class pnand3(pgate.pgate): - self.top_bottom_space) self.pmos1_inst.place(pmos1_pos) - pmos2_pos = pmos1_pos + self.overlap_offset + pmos2_pos = pmos1_pos + self.ptx_offset self.pmos2_inst.place(pmos2_pos) - self.pmos3_pos = pmos2_pos + self.overlap_offset + self.pmos3_pos = pmos2_pos + self.ptx_offset self.pmos3_inst.place(self.pmos3_pos) @@ -168,10 +169,10 @@ class pnand3(pgate.pgate): self.top_bottom_space) self.nmos1_inst.place(nmos1_pos) - nmos2_pos = nmos1_pos + self.overlap_offset + nmos2_pos = nmos1_pos + self.ptx_offset self.nmos2_inst.place(nmos2_pos) - self.nmos3_pos = nmos2_pos + self.overlap_offset + self.nmos3_pos = nmos2_pos + self.ptx_offset self.nmos3_inst.place(self.nmos3_pos) # This will help with the wells and the input/output placement @@ -194,34 +195,29 @@ class pnand3(pgate.pgate): def route_inputs(self): """ Route the A and B inputs """ - # wire space or wire and one contact space - metal_spacing = max(self.m1_space + self.m1_width, - self.m2_space + self.m2_width, - self.m1_space + 0.5 *contact.poly_contact.width + 0.5 * self.m1_width) - - active_spacing = max(self.m1_space, - 0.5 * contact.poly_contact.first_layer_width + self.poly_to_active) - inputC_yoffset = self.nmos3_pos.y + self.nmos.active_height + active_spacing + self.inputC_yoffset = self.nmos3_inst.uy() + 0.5 * contact.poly_contact.height self.route_input_gate(self.pmos3_inst, self.nmos3_inst, - inputC_yoffset, + self.inputC_yoffset, "C", position="center") - inputB_yoffset = inputC_yoffset + metal_spacing - self.route_input_gate(self.pmos2_inst, - self.nmos2_inst, - inputB_yoffset, - "B", - position="center") - - self.inputA_yoffset = inputB_yoffset + metal_spacing + self.inputA_yoffset = self.pmos1_inst.by() - self.poly_extend_active \ + - contact.poly_contact.height self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, "A", position="center") + + self.inputB_yoffset = 0.5*(self.inputA_yoffset + self.inputC_yoffset) + self.route_input_gate(self.pmos2_inst, + self.nmos2_inst, + self.inputB_yoffset, + "B", + position="center") + def route_output(self): """ Route the Z output """ # PMOS1 drain @@ -243,7 +239,7 @@ class pnand3(pgate.pgate): directions=("V", "V")) # PMOS3 and NMOS3 are drain aligned - self.add_path("m2", [pmos3_pin.center(), nmos3_pin.uc()]) + self.add_path("m2", [pmos3_pin.center(), nmos3_pin.center()]) # Route in the A input track (top track) mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset) self.add_path("m2", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()]) From 254e584e35d51f5327effa5241ff4132d86cd9fa Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 Feb 2020 00:36:22 +0000 Subject: [PATCH 173/521] Cleanup and simplify ptx for multiple technologies --- compiler/pgates/ptx.py | 153 ++++++++++++++++++++++------------------- 1 file changed, 84 insertions(+), 69 deletions(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index f331dc28..8dd0da33 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -10,6 +10,7 @@ import debug from tech import layer, drc, spice from vector import vector from sram_factory import factory +import contact class ptx(design.design): @@ -28,6 +29,7 @@ class ptx(design.design): tx_type="nmos", connect_active=False, connect_poly=False, + series_devices=False, num_contacts=None): # We need to keep unique names because outputting to GDSII # will use the last record with a given name. I.e., you will @@ -50,6 +52,7 @@ class ptx(design.design): self.tx_width = width self.connect_active = connect_active self.connect_poly = connect_poly + self.series_devices = series_devices self.num_contacts = num_contacts # Since it has variable height, it is not a pgate. @@ -127,27 +130,25 @@ class ptx(design.design): directions=("V", "V"), dimensions=(1, self.num_contacts)) - # The contacted poly pitch - self.poly_pitch = max(2 * self.contact_to_gate + self.contact_width + self.poly_width, - self.poly_space) - - # The contacted poly pitch - self.contact_spacing = 2 * self.contact_to_gate + \ - self.contact_width + self.poly_width - - # This is measured because of asymmetric enclosure rules - active_enclose_contact = 0.5*(self.active_contact.width - self.contact_width) + # This is the extra poly spacing due to the poly contact to poly contact pitch + # of contacted gates + extra_poly_contact_width = contact.poly_contact.width - self.poly_width - # This is the distance from the side of - # poly gate to the contacted end of active - # (i.e. the "outside" contacted diffusion sizes) - self.end_to_poly = self.active_contact.width - active_enclose_contact + \ - self.contact_to_gate + # This is the spacing between S/D contacts + # This is the spacing between the poly gates + self.min_poly_pitch = self.poly_space + self.poly_width + self.contacted_poly_pitch = self.poly_space + contact.poly_contact.width + self.contact_pitch = 2 * self.contact_to_gate + self.poly_width + self.contact_width + self.poly_pitch = max(self.min_poly_pitch, + self.contacted_poly_pitch, + self.contact_pitch) + + self.end_to_contact = 0.5 * self.active_contact.width # Active width is determined by enclosure on both ends and contacted pitch, # at least one poly and n-1 poly pitches - self.active_width = 2 * self.end_to_poly + self.poly_width + \ - (self.mults - 1) * self.poly_pitch + self.active_width = 2 * self.end_to_contact + self.active_contact.width \ + + 2 * self.contact_to_gate + self.poly_width + (self.mults - 1) * self.poly_pitch # Active height is just the transistor width self.active_height = self.tx_width @@ -287,12 +288,11 @@ class ptx(design.design): Add the poly gates(s) and (optionally) connect them. """ # poly is one contacted spacing from the end and down an extension - poly_offset = self.active_offset \ - + vector(self.poly_width, self.poly_height).scale(0.5, 0.5) \ - + vector(self.end_to_poly, -self.poly_extend_active) - + poly_offset = self.contact_offset \ + + vector(0.5 * self.active_contact.width + 0.5 * self.poly_width + self.contact_to_gate, 0) + # poly_positions are the bottom center of the poly gates - poly_positions = [] + self.poly_positions = [] # It is important that these are from left to right, # so that the pins are in the right @@ -309,11 +309,11 @@ class ptx(design.design): offset=poly_offset, height=self.poly_height, width=self.poly_width) - poly_positions.append(poly_offset) + self.poly_positions.append(poly_offset) poly_offset = poly_offset + vector(self.poly_pitch,0) if self.connect_poly: - self.connect_fingered_poly(poly_positions) + self.connect_fingered_poly(self.poly_positions) def add_active(self): """ @@ -362,59 +362,74 @@ class ptx(design.design): """ return 1 - def get_contact_positions(self): - """ - Create a list of the centers of drain and source contact positions. - """ - # The first one will always be a source - source_positions = [self.contact_offset] - drain_positions = [] - # It is important that these are from left to right, - # so that the pins are in the right - # order for the accessors. - for i in range(self.mults): - if i%2: - # It's a source... so offset from previous drain. - source_positions.append(drain_positions[-1] + vector(self.contact_spacing, 0)) - else: - # It's a drain... so offset from previous source. - drain_positions.append(source_positions[-1] + vector(self.contact_spacing, 0)) - - return [source_positions,drain_positions] - def add_active_contacts(self): """ Add the active contacts to the transistor. """ + drain_positions = [] + source_positions = [] - [source_positions,drain_positions] = self.get_contact_positions() - - for pos in source_positions: - contact=self.add_via_center(layers=self.active_stack, + # First one is always a SOURCE + label = "S" + pos = self.contact_offset + contact=self.add_via_center(layers=self.active_stack, + offset=pos, + size=(1, self.num_contacts), + directions=("V","V"), + implant_type=self.implant_type, + well_type=self.well_type) + self.add_layout_pin_rect_center(text=label, + layer="m1", offset=pos, - size=(1, self.num_contacts), - directions=("V","V"), - implant_type=self.implant_type, - well_type=self.well_type) - self.add_layout_pin_rect_center(text="S", - layer="m1", - offset=pos, - width=contact.mod.second_layer_width, - height=contact.mod.second_layer_height) + width=contact.mod.second_layer_width, + height=contact.mod.second_layer_height) + source_positions.append(pos) - - for pos in drain_positions: - contact=self.add_via_center(layers=self.active_stack, - offset=pos, - size=(1, self.num_contacts), - directions=("V","V"), - implant_type=self.implant_type, - well_type=self.well_type) - self.add_layout_pin_rect_center(text="D", - layer="m1", + # Skip these if they are going to be in series + if not self.series_devices: + for (poly1, poly2) in zip(self.poly_positions, self.poly_positions[1:]): + pos = vector(0.5 * (poly1.x + poly2.x), + self.contact_offset.y) + # Alternate source and drains + if label == "S": + label = "D" + drain_positions.append(pos) + else: + label = "S" + source_positions.append(pos) + + contact=self.add_via_center(layers=self.active_stack, offset=pos, - width=contact.mod.second_layer_width, - height=contact.mod.second_layer_height) + size=(1, self.num_contacts), + directions=("V","V"), + implant_type=self.implant_type, + well_type=self.well_type) + self.add_layout_pin_rect_center(text=label, + layer="m1", + offset=pos, + width=contact.mod.second_layer_width, + height=contact.mod.second_layer_height) + + pos = vector(self.active_offset.x + self.active_width - 0.5 * self.active_contact.width, + self.contact_offset.y) + # Last one is the opposite of previous + if label == "S": + label = "D" + drain_positions.append(pos) + else: + label = "S" + source_positions.append(pos) + contact=self.add_via_center(layers=self.active_stack, + offset=pos, + size=(1, self.num_contacts), + directions=("V","V"), + implant_type=self.implant_type, + well_type=self.well_type) + self.add_layout_pin_rect_center(text=label, + layer="m1", + offset=pos, + width=contact.mod.second_layer_width, + height=contact.mod.second_layer_height) if self.connect_active: self.connect_fingered_active(drain_positions, source_positions) From 5409f0be7dd153a4117f639d55c1640930bffd07 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 25 Feb 2020 08:06:26 -0800 Subject: [PATCH 174/521] Update project link and student contributors --- README.md | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/README.md b/README.md index 64c8aa25..997303ab 100644 --- a/README.md +++ b/README.md @@ -195,7 +195,7 @@ specific technology (e.g., [FreePDK45]) should be a subdirectory + Report bugs by submitting [Github issues]. + Develop new features (see [how to contribute](./CONTRIBUTING.md)) + Submit code/fixes using a [Github pull request] -+ Follow our [project][Github projects]. ++ Follow our [project][Github project]. + Read and cite our [ICCAD paper][OpenRAMpaper] # Further Help @@ -214,15 +214,7 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). - [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect. - [James Stine] from [VLSIARCH] co-founded the project. -- Hunter Nichols maintains and updates the timing characterization. -- Michael Grimes created and maintains the multiport netlist code. -- Jennifer Sowash is creating the OpenRAM IP library. -- Jesse Cirimelli-Low created the datasheet generation. -- Samira Ataei created early multi-bank layouts and control logic. -- Bin Wu created early parameterized cells. -- Yusu Wang is porting parameterized cells to new technologies. -- Brian Chen created early prototypes of the timing characterizer. -- Jeff Butera created early prototypes of the bank layout. +- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera If I forgot to add you, please let me know! @@ -236,7 +228,7 @@ If I forgot to add you, please let me know! [Github issues]: https://github.com/VLSIDA/OpenRAM/issues [Github pull request]: https://github.com/VLSIDA/OpenRAM/pulls -[Github projects]: https://github.com/VLSIDA/OpenRAM/projects +[Github project]: https://github.com/VLSIDA/OpenRAM [documentation]: https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing [dev-group]: mailto:openram-dev-group@ucsc.edu From 0db0c5a3a914b03dfce7f011464d1c0d25a4f56c Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 25 Feb 2020 08:09:08 -0800 Subject: [PATCH 175/521] Update version to 1.1.4 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 70e4b54b..3277ab1d 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.3" +VERSION = "1.1.4" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From 266d68c3955046d811bb84c5a0cd1e3bd787c250 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 Feb 2020 17:09:07 +0000 Subject: [PATCH 176/521] Generalize pgate width based on nwell/pwell contacts --- compiler/pgates/pgate.py | 9 +++++++++ compiler/pgates/pinv.py | 17 +---------------- compiler/pgates/pnand2.py | 14 +++----------- compiler/pgates/pnand3.py | 17 +++++------------ compiler/pgates/pnor2.py | 5 +++-- 5 files changed, 21 insertions(+), 41 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 8b9a1c66..59ec2448 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -264,3 +264,12 @@ class pgate(design.design): # offset=implant_offset, # width=implant_width, # height=implant_height) + + def determine_width(self): + """ Determine the width based on the well contacts (assumed to be on the right side) """ + # Width is determined by well contact and spacing + self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + self.well_width = self.width + 2 * self.nwell_enclose_active + # Height is an input parameter, so it is not recomputed. + + diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index c0f1f955..3c2e41a2 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -51,9 +51,9 @@ class pinv(pgate.pgate): def create_layout(self): """ Calls all functions related to the generation of the layout """ - self.setup_layout_constants() self.place_ptx() self.add_well_contacts() + self.determine_width() self.extend_wells() self.route_supply_rails() self.connect_rails() @@ -147,21 +147,6 @@ class pinv(pgate.pgate): debug.check(self.pmos_width >= drc("minwidth_tx"), "Cannot finger PMOS transistors to fit cell height.") - def setup_layout_constants(self): - """ - Compute the width and height - """ - - # the width is determined the multi-finger PMOS device width plus - # the well contact width, spacing between them - # space is for power supply contact to nwell m1 spacing - self.width = self.pmos.active_offset.x + self.pmos.active_width \ - + self.active_space + contact.nwell_contact.width \ - + 0.5 * self.nwell_enclose_active \ - + self.m1_space - # This includes full enclosures on each end - self.well_width = self.width + 2*self.nwell_enclose_active - # Height is an input parameter, so it is not recomputed. def add_ptx(self): """ Create the PMOS and NMOS transistors. """ diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 7c40c7ab..05eabbe0 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -49,10 +49,11 @@ class pnand2(pgate.pgate): """ Calls all functions related to the generation of the layout """ self.setup_layout_constants() - self.route_supply_rails() self.place_ptx() - self.connect_rails() self.add_well_contacts() + self.determine_width() + self.route_supply_rails() + self.connect_rails() self.extend_wells() self.route_inputs() self.route_output() @@ -96,15 +97,6 @@ class pnand2(pgate.pgate): # source and drain pins self.overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll() - # Two PMOS devices and a well contact. Separation between each. - # Enclosure space on the sides. - self.width = 2 * self.pmos.active_width + contact.active_contact.width \ - + 2 * self.active_space \ - + 0.5 * self.nwell_enclose_active - - self.well_width = self.width + 2 * self.nwell_enclose_active - # Height is an input parameter, so it is not recomputed. - # This is the extra space needed to ensure DRC rules # to the active contacts extra_contact_space = max(-self.nmos.get_pin("D").by(), 0) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 087cffd5..0a46b633 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -57,13 +57,15 @@ class pnand3(pgate.pgate): """ Calls all functions related to the generation of the layout """ self.setup_layout_constants() - self.route_supply_rails() self.place_ptx() - self.connect_rails() self.add_well_contacts() + self.determine_width() + self.route_supply_rails() + self.connect_rails() self.extend_wells() self.route_inputs() self.route_output() + def add_ptx(self): """ Create the PMOS and NMOS transistors. """ @@ -90,14 +92,6 @@ class pnand3(pgate.pgate): overlap_xoffset = self.pmos.get_pin("D").ll().x - self.pmos.get_pin("S").ll().x self.ptx_offset = vector(overlap_xoffset, 0) - # Two PMOS devices and a well contact. Separation between each. - # Enclosure space on the sides. - self.width = 3 * self.pmos.active_width + self.pmos.active_contact.width \ - + 2 * self.active_space + 0.5 * self.nwell_enclose_active \ - - self.ptx_offset.x - self.well_width = self.width + 2 * self.nwell_enclose_active - # Height is an input parameter, so it is not recomputed. - # This is the extra space needed to ensure DRC rules # to the active contacts nmos = factory.create(module_type="ptx", tx_type="nmos") @@ -164,7 +158,6 @@ class pnand3(pgate.pgate): self.pmos3_pos = pmos2_pos + self.ptx_offset self.pmos3_inst.place(self.pmos3_pos) - nmos1_pos = vector(self.pmos.active_offset.x, self.top_bottom_space) self.nmos1_inst.place(nmos1_pos) @@ -189,7 +182,7 @@ class pnand3(pgate.pgate): self.connect_pin_to_rail(self.nmos1_inst, "S", "gnd") - self.connect_pin_to_rail(self.pmos1_inst, "S", "vdd") + self.connect_pin_to_rail(self.pmos1_inst, "S", "vdd") self.connect_pin_to_rail(self.pmos2_inst, "D", "vdd") diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index d6605d68..3d998d25 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -48,10 +48,11 @@ class pnor2(pgate.pgate): """ Calls all functions related to the generation of the layout """ self.setup_layout_constants() - self.route_supply_rails() self.place_ptx() - self.connect_rails() self.add_well_contacts() + self.determine_width() + self.route_supply_rails() + self.connect_rails() self.extend_wells() self.route_inputs() self.route_output() From 1d8f2a4ad6dea40bab54a49ff68d12b3934782d8 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Thu, 27 Feb 2020 07:09:26 +0100 Subject: [PATCH 177/521] Update documentation --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 997303ab..82fe75ed 100644 --- a/README.md +++ b/README.md @@ -18,7 +18,7 @@ An open-source static random access memory (SRAM) compiler. # What is OpenRAM? -OpenRAM is an open-source Python framework to create the layout, +OpenRAM is an award winning open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both From 073bd47b316e3f9ff103071d76a465ff3e024f0d Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 Feb 2020 18:23:36 +0000 Subject: [PATCH 178/521] Add source/drain/gate to structure --- compiler/pgates/ptx.py | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 8dd0da33..46726b37 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -293,7 +293,8 @@ class ptx(design.design): # poly_positions are the bottom center of the poly gates self.poly_positions = [] - + self.poly_gates = [] + # It is important that these are from left to right, # so that the pins are in the right # order for the accessors @@ -304,13 +305,15 @@ class ptx(design.design): offset=poly_offset, height=self.poly_height, width=self.poly_width) - self.add_layout_pin_rect_center(text="G", - layer="poly", - offset=poly_offset, - height=self.poly_height, - width=self.poly_width) + gate = self.add_layout_pin_rect_center(text="G", + layer="poly", + offset=poly_offset, + height=self.poly_height, + width=self.poly_width) self.poly_positions.append(poly_offset) - poly_offset = poly_offset + vector(self.poly_pitch,0) + self.poly_gates.append(gate) + + poly_offset = poly_offset + vector(self.poly_pitch, 0) if self.connect_poly: self.connect_fingered_poly(self.poly_positions) @@ -369,6 +372,10 @@ class ptx(design.design): drain_positions = [] source_positions = [] + # Keep a list of the source/drain contacts + self.source_contacts = [] + self.drain_contacts = [] + # First one is always a SOURCE label = "S" pos = self.contact_offset @@ -383,6 +390,7 @@ class ptx(design.design): offset=pos, width=contact.mod.second_layer_width, height=contact.mod.second_layer_height) + self.source_contacts.append(contact) source_positions.append(pos) # Skip these if they are going to be in series @@ -409,6 +417,11 @@ class ptx(design.design): offset=pos, width=contact.mod.second_layer_width, height=contact.mod.second_layer_height) + + if label == "S": + self.source_contacts.append(contact) + else: + self.drain_contacts.append(contact) pos = vector(self.active_offset.x + self.active_width - 0.5 * self.active_contact.width, self.contact_offset.y) @@ -430,6 +443,10 @@ class ptx(design.design): offset=pos, width=contact.mod.second_layer_width, height=contact.mod.second_layer_height) + if label == "S": + self.source_contacts.append(contact) + else: + self.drain_contacts.append(contact) if self.connect_active: self.connect_fingered_active(drain_positions, source_positions) From 0b739793885e6f411e40fdd4c364e211ccdd1f30 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 Feb 2020 18:23:49 +0000 Subject: [PATCH 179/521] Space inputs by M1 pitch --- compiler/pgates/pnand3.py | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 0a46b633..a9fd19b7 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -36,7 +36,8 @@ class pnand3(pgate.pgate): self.pmos_width = self.pmos_size * drc("minwidth_tx") # FIXME: Allow these to be sized - debug.check(size == 1,"Size 1 pnand3 is only supported now.") + debug.check(size == 1, + "Size 1 pnand3 is only supported now.") self.tx_mults = 1 # Creates the netlist and layout @@ -66,7 +67,6 @@ class pnand3(pgate.pgate): self.route_inputs() self.route_output() - def add_ptx(self): """ Create the PMOS and NMOS transistors. """ self.nmos = factory.create(module_type="ptx", @@ -148,8 +148,7 @@ class pnand3(pgate.pgate): """ pmos1_pos = vector(self.pmos.active_offset.x, - self.height - self.pmos.active_height \ - - self.top_bottom_space) + self.height - self.pmos.active_height - self.top_bottom_space) self.pmos1_inst.place(pmos1_pos) pmos2_pos = pmos1_pos + self.ptx_offset @@ -168,9 +167,6 @@ class pnand3(pgate.pgate): self.nmos3_pos = nmos2_pos + self.ptx_offset self.nmos3_inst.place(self.nmos3_pos) - # This will help with the wells and the input/output placement - self.output_pos = vector(0, 0.5*self.height) - def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ @@ -187,29 +183,30 @@ class pnand3(pgate.pgate): self.connect_pin_to_rail(self.pmos2_inst, "D", "vdd") def route_inputs(self): - """ Route the A and B inputs """ - self.inputC_yoffset = self.nmos3_inst.uy() + 0.5 * contact.poly_contact.height + """ Route the A and B and C inputs """ + + # Put B right on the well line + self.inputB_yoffset = self.nwell_y_offset + self.route_input_gate(self.pmos2_inst, + self.nmos2_inst, + self.inputB_yoffset, + "B", + position="center") + + self.inputC_yoffset = self.inputB_yoffset - self.m1_pitch self.route_input_gate(self.pmos3_inst, self.nmos3_inst, self.inputC_yoffset, "C", position="center") - self.inputA_yoffset = self.pmos1_inst.by() - self.poly_extend_active \ - - contact.poly_contact.height + self.inputA_yoffset = self.inputB_yoffset + self.m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, "A", position="center") - - self.inputB_yoffset = 0.5*(self.inputA_yoffset + self.inputC_yoffset) - self.route_input_gate(self.pmos2_inst, - self.nmos2_inst, - self.inputB_yoffset, - "B", - position="center") def route_output(self): """ Route the Z output """ From e1b97f58e1cdd084395467c9796a3cbfee725631 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 Feb 2020 18:24:09 +0000 Subject: [PATCH 180/521] Add instance center location --- compiler/base/geometry.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index cfda3553..5d7f8d76 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -136,7 +136,7 @@ class geometry: def cy(self): """ Return the center y """ return 0.5 * (self.boundary[0].y + self.boundary[1].y) - + class instance(geometry): """ From bb2305d56a313bd5a5210b551bca0f54f63168a9 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 Feb 2020 18:24:39 +0000 Subject: [PATCH 181/521] PEP8 format fixes --- compiler/modules/hierarchical_decoder.py | 158 +++++++++-------------- compiler/pgates/pgate.py | 10 +- 2 files changed, 69 insertions(+), 99 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 242ef476..7d625b75 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -77,27 +77,27 @@ class hierarchical_decoder(design.design): height=self.cell_height) self.add_mod(self.pre3_8) - def determine_predecodes(self,num_inputs): + def determine_predecodes(self, num_inputs): """ Determines the number of 2:4 pre-decoder and 3:8 pre-decoder needed based on the number of inputs """ if (num_inputs == 2): - return (1,0) + return (1, 0) elif (num_inputs == 3): - return(0,1) + return(0, 1) elif (num_inputs == 4): - return(2,0) + return(2, 0) elif (num_inputs == 5): - return(1,1) + return(1, 1) elif (num_inputs == 6): - return(3,0) + return(3, 0) elif (num_inputs == 7): - return(2,1) + return(2, 1) elif (num_inputs == 8): - return(1,2) + return(1, 2) elif (num_inputs == 9): - return(0,3) + return(0, 3) else: - debug.error("Invalid number of inputs for hierarchical decoder",-1) + debug.error("Invalid number of inputs for hierarchical decoder", -1) def setup_netlist_constants(self): self.predec_groups = [] # This array is a 2D array. @@ -122,35 +122,35 @@ class hierarchical_decoder(design.design): index = index + 1 self.predec_groups.append(lines) - def setup_layout_constants(self): """ Calculate the overall dimensions of the hierarchical decoder """ # If we have 4 or fewer rows, the predecoder is the decoder itself if self.num_inputs>=4: - self.total_number_of_predecoder_outputs = 4*self.no_of_pre2x4 + 8*self.no_of_pre3x8 + self.total_number_of_predecoder_outputs = 4 * self.no_of_pre2x4 + 8 * self.no_of_pre3x8 else: - self.total_number_of_predecoder_outputs = 0 - debug.error("Not enough rows ({}) for a hierarchical decoder. Non-hierarchical not supported yet.".format(self.num_inputs),-1) + self.total_number_of_predecoder_outputs = 0 + debug.error("Not enough rows ({}) for a hierarchical decoder. Non-hierarchical not supported yet.".format(self.num_inputs), + -1) # Calculates height and width of pre-decoder, if self.no_of_pre3x8 > 0: - self.predecoder_width = self.pre3_8.width + self.predecoder_width = self.pre3_8.width else: self.predecoder_width = self.pre2_4.width - self.predecoder_height = self.pre2_4.height*self.no_of_pre2x4 + self.pre3_8.height*self.no_of_pre3x8 + self.predecoder_height = self.pre2_4.height * self.no_of_pre2x4 + self.pre3_8.height * self.no_of_pre3x8 - # Calculates height and width of row-decoder + # Calculates height and width of row-decoder if (self.num_inputs == 4 or self.num_inputs == 5): nand_width = self.nand2.width else: - nand_width = self.nand3.width - self.internal_routing_width = self.m2_pitch*self.total_number_of_predecoder_outputs + nand_width = self.nand3.width + self.internal_routing_width = self.m2_pitch * self.total_number_of_predecoder_outputs self.row_decoder_height = self.inv.height * self.rows - self.input_routing_width = (self.num_inputs+1) * self.m2_pitch - # Calculates height and width of hierarchical decoder + self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch + # Calculates height and width of hierarchical decoder self.height = self.row_decoder_height self.width = self.input_routing_width + self.predecoder_width \ + self.internal_routing_width + nand_width + self.inv.width @@ -158,7 +158,7 @@ class hierarchical_decoder(design.design): def route_input_rails(self): """ Create input rails for the predecoders """ # inputs should be as high as the decoders - input_height = self.no_of_pre2x4*self.pre2_4.height + self.no_of_pre3x8*self.pre3_8.height + input_height = self.no_of_pre2x4 * self.pre2_4.height + self.no_of_pre3x8 * self.pre3_8.height # Find the left-most predecoder min_x = 0 @@ -166,7 +166,7 @@ class hierarchical_decoder(design.design): min_x = min(min_x, -self.pre2_4.width) if self.no_of_pre3x8 > 0: min_x = min(min_x, -self.pre3_8.width) - input_offset=vector(min_x - self.input_routing_width,0) + input_offset=vector(min_x - self.input_routing_width, 0) input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)] self.input_rails = self.create_vertical_pin_bus(layer="m2", @@ -177,7 +177,6 @@ class hierarchical_decoder(design.design): self.route_input_to_predecodes() - def route_input_to_predecodes(self): """ Route the vertical input rail to the predecoders """ for pre_num in range(self.no_of_pre2x4): @@ -191,11 +190,10 @@ class hierarchical_decoder(design.design): # To prevent conflicts, we will offset each input connect so # that it aligns with the vdd/gnd rails - decoder_offset = decoder_pin.bc() + vector(0,(i+1)*self.inv.height) - input_offset = input_pos.scale(1,0) + decoder_offset.scale(0,1) + decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height) + input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1) self.route_input_rail(decoder_offset, input_offset) - for pre_num in range(self.no_of_pre3x8): for i in range(3): @@ -208,11 +206,10 @@ class hierarchical_decoder(design.design): # To prevent conflicts, we will offset each input connect so # that it aligns with the vdd/gnd rails - decoder_offset = decoder_pin.bc() + vector(0,(i+1)*self.inv.height) - input_offset = input_pos.scale(1,0) + decoder_offset.scale(0,1) + decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height) + input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1) - self.route_input_rail(decoder_offset, input_offset) - + self.route_input_rail(decoder_offset, input_offset) def route_input_rail(self, input_offset, output_offset): """ Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """ @@ -222,7 +219,6 @@ class hierarchical_decoder(design.design): self.add_via_center(layers=self.m2_stack, offset=output_offset) self.add_path(("m3"), [input_offset, output_offset]) - def add_pins(self): """ Add the module pins """ @@ -235,7 +231,6 @@ class hierarchical_decoder(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - def create_pre_decoder(self): """ Creates pre-decoder and places labels input address [A] """ @@ -245,7 +240,7 @@ class hierarchical_decoder(design.design): for i in range(self.no_of_pre3x8): self.create_pre3x8(i) - def create_pre2x4(self,num): + def create_pre2x4(self, num): """ Add a 2x4 predecoder to the left of the origin """ if (self.num_inputs == 2): @@ -265,8 +260,7 @@ class hierarchical_decoder(design.design): mod=self.pre2_4)) self.connect_inst(pins) - - def create_pre3x8(self,num): + def create_pre3x8(self, num): """ Add 3x8 predecoder to the left of the origin and above any 2x4 decoders """ # If we had 2x4 predecodes, those are used as the lower # decode output bits @@ -280,11 +274,10 @@ class hierarchical_decoder(design.design): pins.append("out_{0}".format(output_index + out_index_offset)) pins.extend(["vdd", "gnd"]) - self.pre3x8_inst.append(self.add_inst(name="pre3x8_{0}".format(num), + self.pre3x8_inst.append(self.add_inst(name="pre3x8_{0}".format(num), mod=self.pre3_8)) self.connect_inst(pins) - def place_pre_decoder(self): """ Creates pre-decoder and places labels input address [A] """ @@ -294,23 +287,23 @@ class hierarchical_decoder(design.design): for i in range(self.no_of_pre3x8): self.place_pre3x8(i) - def place_pre2x4(self,num): + def place_pre2x4(self, num): """ Place 2x4 predecoder to the left of the origin """ if (self.num_inputs == 2): - base = vector(-self.pre2_4.width,0) + base = vector(-self.pre2_4.width, 0) else: base= vector(-self.pre2_4.width, num * self.pre2_4.height) self.pre2x4_inst[num].place(base) - def place_pre3x8(self,num): + def place_pre3x8(self, num): """ Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """ if (self.num_inputs == 3): - offset = vector(-self.pre_3_8.width,0) - mirror ="R0" + offset = vector(-self.pre_3_8.width, 0) + mirror = "R0" else: - height = self.no_of_pre2x4*self.pre2_4.height + num*self.pre3_8.height + height = self.no_of_pre2x4 * self.pre2_4.height + num * self.pre3_8.height offset = vector(-self.pre3_8.width, height) self.pre3x8_inst[num].place(offset) @@ -331,7 +324,7 @@ class hierarchical_decoder(design.design): if (self.num_inputs == 4 or self.num_inputs == 5): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): - row = len(self.predec_groups[0])*j + i + row = len(self.predec_groups[0]) * j + i if (row < self.rows): name = self.NAND_FORMAT.format(row) self.nand_inst.append(self.add_inst(name=name, @@ -342,14 +335,13 @@ class hierarchical_decoder(design.design): "vdd", "gnd"] self.connect_inst(pins) - # Row Decoder NAND GATE array for address inputs >5. elif (self.num_inputs > 5): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): for k in range(len(self.predec_groups[2])): - row = (len(self.predec_groups[0])*len(self.predec_groups[1])) * k \ - + len(self.predec_groups[0])*j + i + row = (len(self.predec_groups[0]) * len(self.predec_groups[1])) * k \ + + len(self.predec_groups[0]) * j + i if (row < self.rows): name = self.NAND_FORMAT.format(row) @@ -363,9 +355,8 @@ class hierarchical_decoder(design.design): "vdd", "gnd"] self.connect_inst(pins) - def create_decoder_inv_array(self): - """ + """ Add a column of INV gates for the decoder. """ @@ -378,15 +369,12 @@ class hierarchical_decoder(design.design): "decode_{0}".format(row), "vdd", "gnd"]) - def place_decoder_inv_array(self): """ Place the column of INV gates for the decoder above the predecoders and to the right of the NAND decoders. """ - z_pin = self.inv.get_pin("Z") - if (self.num_inputs == 4 or self.num_inputs == 5): x_off = self.internal_routing_width + self.nand2.width else: @@ -396,27 +384,24 @@ class hierarchical_decoder(design.design): if (row % 2 == 0): inv_row_height = self.inv.height * row mirror = "R0" - y_dir = 1 else: inv_row_height = self.inv.height * (row + 1) mirror = "MX" - y_dir = -1 y_off = inv_row_height - offset = vector(x_off,y_off) + offset = vector(x_off, y_off) self.inv_inst[row].place(offset=offset, mirror=mirror) def place_row_decoder(self): - """ + """ Place the row-decoder by placing NAND2/NAND3 and Inverters - and add the primary decoder output pins. + and add the primary decoder output pins. """ if (self.num_inputs >= 4): self.place_decoder_nand_array() self.place_decoder_inv_array() self.route_decoder() - def place_decoder_nand_array(self): """ Add a column of NAND gates for final decode """ @@ -433,22 +418,16 @@ class hierarchical_decoder(design.design): """ Add a column of NAND gates for the decoder above the predecoders.""" for row in range(self.rows): - name = self.NAND_FORMAT.format(row) if ((row % 2) == 0): - y_off = nand_mod.height*row - y_dir = 1 + y_off = nand_mod.height * row mirror = "R0" else: - y_off = nand_mod.height*(row + 1) - y_dir = -1 + y_off = nand_mod.height * (row + 1) mirror = "MX" self.nand_inst[row].place(offset=[self.internal_routing_width, y_off], mirror=mirror) - - - def route_decoder(self): """ Route the nand to inverter in the decoder and add the pins. """ @@ -457,9 +436,9 @@ class hierarchical_decoder(design.design): # route nand output to output inv input zr_pos = self.nand_inst[row].get_pin("Z").rc() al_pos = self.inv_inst[row].get_pin("A").lc() - # ensure the bend is in the middle - mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y) - mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y) + # ensure the bend is in the middle + mid1_pos = vector(0.5 * (zr_pos.x + al_pos.x), zr_pos.y) + mid2_pos = vector(0.5 * (zr_pos.x + al_pos.x), al_pos.y) self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos]) z_pin = self.inv_inst[row].get_pin("Z") @@ -469,21 +448,18 @@ class hierarchical_decoder(design.design): width=z_pin.width(), height=z_pin.height()) - - def route_predecode_rails(self): """ Creates vertical metal 2 rails to connect predecoder and decoder stages.""" # This is not needed for inputs <4 since they have no pre/decode stages. if (self.num_inputs >= 4): - input_offset = vector(0.5*self.m2_width,0) + input_offset = vector(0.5 * self.m2_width, 0) input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)] self.predecode_rails = self.create_vertical_pin_bus(layer="m2", pitch=self.m2_pitch, offset=input_offset, names=input_bus_names, length=self.height) - self.route_rails_to_predecodes() self.route_rails_to_decoder() @@ -497,8 +473,7 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(pre_num * 4 + i) out_name = "out_{}".format(i) pin = self.pre2x4_inst[pre_num].get_pin(out_name) - self.route_predecode_rail_m3(predecode_name, pin) - + self.route_predecode_rail_m3(predecode_name, pin) # FIXME: convert to connect_bus for pre_num in range(self.no_of_pre3x8): @@ -506,10 +481,8 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(pre_num * 8 + i + self.no_of_pre2x4 * 4) out_name = "out_{}".format(i) pin = self.pre3x8_inst[pre_num].get_pin(out_name) - self.route_predecode_rail_m3(predecode_name, pin) + self.route_predecode_rail_m3(predecode_name, pin) - - def route_rails_to_decoder(self): """ Use the self.predec_groups to determine the connections to the decoder NAND gates. Inputs of NAND2/NAND3 gates come from different groups. @@ -536,11 +509,11 @@ class hierarchical_decoder(design.design): for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? if (row_index < self.rows): - predecode_name = "predecode_{}".format(index_A) + predecode_name = "predecode_{}".format(index_A) self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A")) - predecode_name = "predecode_{}".format(index_B) + predecode_name = "predecode_{}".format(index_B) self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B")) - predecode_name = "predecode_{}".format(index_C) + predecode_name = "predecode_{}".format(index_C) self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("C")) row_index = row_index + 1 @@ -548,8 +521,8 @@ class hierarchical_decoder(design.design): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ # The vias will be placed in the center and right of the cells, respectively. - xoffset = self.nand_inst[0].rx() - for num in range(0,self.rows): + xoffset = self.nand_inst[0].cx() + for num in range(0, self.rows): for pin_name in ["vdd", "gnd"]: # The nand and inv are the same height rows... supply_pin = self.nand_inst[num].get_pin(pin_name) @@ -558,39 +531,36 @@ class hierarchical_decoder(design.design): loc=pin_pos) # Make a redundant rail too - for num in range(0,self.rows,2): + for num in range(0, self.rows, 2): for pin_name in ["vdd", "gnd"]: start = self.nand_inst[num].get_pin(pin_name).lc() end = self.inv_inst[num].get_pin(pin_name).rc() - mid = (start+end).scale(0.5,0.5) + mid = (start + end).scale(0.5, 0.5) self.add_rect_center(layer="m1", offset=mid, - width=end.x-start.x) - + width=end.x - start.x) # Copy the pins from the predecoders for pre in self.pre2x4_inst + self.pre3x8_inst: self.copy_layout_pin(pre, "vdd") self.copy_layout_pin(pre, "gnd") - def route_predecode_rail(self, rail_name, pin): """ Connect the routing rail to the given metal1 pin """ - rail_pos = vector(self.predecode_rails[rail_name].x,pin.lc().y) + rail_pos = vector(self.predecode_rails[rail_name].x, pin.lc().y) self.add_path("m1", [rail_pos, pin.lc()]) self.add_via_center(layers=self.m1_stack, offset=rail_pos) - def route_predecode_rail_m3(self, rail_name, pin): """ Connect the routing rail to the given metal1 pin """ # This routes the pin up to the rail, basically, to avoid conflicts. # It would be fixed with a channel router. - mid_point = vector(pin.cx(), pin.cy()+self.inv.height/2) - rail_pos = vector(self.predecode_rails[rail_name].x,mid_point.y) + mid_point = vector(pin.cx(), pin.cy() + self.inv.height / 2) + rail_pos = vector(self.predecode_rails[rail_name].x, mid_point.y) self.add_via_center(layers=self.m1_stack, offset=pin.center()) - self.add_wire(("m3","via2","m2"), [rail_pos, mid_point, pin.uc()]) + self.add_wire(("m3", "via2", "m2"), [rail_pos, mid_point, pin.uc()]) self.add_via_center(layers=self.m2_stack, offset=rail_pos) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 59ec2448..a6a11a28 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -128,16 +128,16 @@ class pgate(design.design): """ Extend the n/p wells to cover whole cell """ # This should match the cells in the cell library - nwell_y_offset = 0.48 * self.height - full_height = self.height + 0.5*self.m1_width + self.nwell_y_offset = 0.48 * self.height + full_height = self.height + 0.5* self.m1_width # FIXME: float rounding problem if "nwell" in layer: # Add a rail width to extend the well to the top of the rail nwell_max_offset = max(self.find_highest_layer_coords("nwell").y, full_height) - nwell_position = vector(0, nwell_y_offset) - vector(self.well_extend_active, 0) - nwell_height = nwell_max_offset - nwell_y_offset + nwell_position = vector(0, self.nwell_y_offset) - vector(self.well_extend_active, 0) + nwell_height = nwell_max_offset - self.nwell_y_offset self.add_rect(layer="nwell", offset=nwell_position, width=self.well_width, @@ -153,7 +153,7 @@ class pgate(design.design): pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y, -0.5 * self.m1_width) pwell_position = vector(-self.well_extend_active, pwell_min_offset) - pwell_height = nwell_y_offset - pwell_position.y + pwell_height = self.nwell_y_offset - pwell_position.y self.add_rect(layer="pwell", offset=pwell_position, width=self.well_width, From f62016ad9fff6157c3a8e818a8403b95cbfec7f5 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 3 Mar 2020 12:40:08 +0000 Subject: [PATCH 182/521] revert dff_buf for no body contact --- compiler/modules/dff_buf.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 6f06b778..8f581606 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -91,8 +91,8 @@ class dff_buf(design.design): def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - self.connect_inst(props.dff_buff.buf_ports) - #self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) + #self.connect_inst(props.dff_buff.buf_ports) + self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1", mod=self.inv1) From 7ba9e09e12bc81b361d182d9795b10aeaea02d3a Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 4 Mar 2020 22:23:05 +0000 Subject: [PATCH 183/521] Incomplete precharge layer decoupling --- compiler/base/hierarchy_layout.py | 13 ++-- compiler/modules/hierarchical_decoder.py | 2 +- compiler/modules/wordline_driver.py | 5 +- compiler/pgates/pgate.py | 4 +- compiler/pgates/precharge.py | 94 +++++++++++++----------- 5 files changed, 63 insertions(+), 55 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 2e0bf755..6b1ca3fd 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -517,12 +517,12 @@ class layout(): self.connect_inst([]) return inst - def add_via_stack(self, offset, direction, from_layer, to_layer, - size=[1,1]): + def add_via_stack(self, offset, from_layer, to_layer, + direction=None, + size=[1, 1]): """ Punch a stack of vias from a start layer to a target layer. """ - return self.__add_via_stack_internal(offset=offset, direction=direction, from_layer=from_layer, @@ -531,8 +531,9 @@ class layout(): last_via=None, size=size) - def add_via_stack_center(self, offset, direction, from_layer, to_layer, - size=[1,1]): + def add_via_stack_center(self, offset, from_layer, to_layer, + direction=None, + size=[1, 1]): """ Punch a stack of vias from a start layer to a target layer by the center coordinate accounting for mirroring and rotation. @@ -545,7 +546,6 @@ class layout(): last_via=None, size=size) - def __add_via_stack_internal(self, offset, direction, from_layer, to_layer, via_func, last_via, size): """ @@ -581,7 +581,6 @@ class layout(): last_via=via, size=size) - def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"): """Adds a ptx module to the design.""" import ptx diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 7d625b75..f9c21619 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -521,7 +521,7 @@ class hierarchical_decoder(design.design): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ # The vias will be placed in the center and right of the cells, respectively. - xoffset = self.nand_inst[0].cx() + xoffset = self.nand_inst[0].rx() for num in range(0, self.rows): for pin_name in ["vdd", "gnd"]: # The nand and inv are the same height rows... diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 27671fd2..35a2b8bf 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -75,8 +75,7 @@ class wordline_driver(design.design): """ # Find the x offsets for where the vias/pins should be placed - a_xoffset = self.nand_inst[0].rx() - b_xoffset = self.inv2_inst[0].lx() + a_xoffset = self.nand_inst[0].lx() for num in range(self.rows): # this will result in duplicate polygons for rails, but who cares @@ -90,7 +89,7 @@ class wordline_driver(design.design): supply_pin = self.inv2_inst[num].get_pin(name) # Add pins in two locations - for xoffset in [a_xoffset, b_xoffset]: + for xoffset in [a_xoffset]: pin_pos = vector(xoffset, supply_pin.cy()) self.add_power_pin(name, pin_pos) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index a6a11a28..7693fa07 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -267,8 +267,8 @@ class pgate(design.design): def determine_width(self): """ Determine the width based on the well contacts (assumed to be on the right side) """ - # Width is determined by well contact and spacing - self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + # Width is determined by well contact and spacing and allowing a supply via between each cell + self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width self.well_width = self.width + 2 * self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index acb2062f..4a494763 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -12,7 +12,7 @@ from tech import parameter from vector import vector from globals import OPTS from sram_factory import factory - +from tech import drc class precharge(design.design): """ @@ -30,7 +30,10 @@ class precharge(design.design): self.width = self.bitcell.width self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br - + self.bitcell_bl_pin =self.bitcell.get_pin(self.bitcell_bl) + self.bitcell_br_pin =self.bitcell.get_pin(self.bitcell_br) + print(self.bitcell_bl_pin) + print(self.bitcell_br_pin) # Creates the netlist and layout # Since it has variable height, it is not a pgate. self.create_netlist() @@ -50,6 +53,7 @@ class precharge(design.design): self.create_ptx() def create_layout(self): + self.place_ptx() self.connect_poly() self.route_en() @@ -120,17 +124,18 @@ class precharge(design.design): contact_xdiff = self.pmos.get_pin("S").lx() # adds the lower pmos to layout - bl_xoffset = self.bitcell.get_pin(self.bitcell_bl).lx() + bl_xoffset = self.bitcell_bl_pin.lx() self.lower_pmos_position = vector(max(bl_xoffset - contact_xdiff, self.nwell_enclose_active), self.pmos.active_offset.y) self.lower_pmos_inst.place(self.lower_pmos_position) # adds the upper pmos(s) to layout - ydiff = self.pmos.height + 2 * self.m1_space + contact.poly_contact.width + ydiff = self.pmos.height + 4 * self.m2_space self.upper_pmos1_pos = self.lower_pmos_position + vector(0, ydiff) self.upper_pmos1_inst.place(self.upper_pmos1_pos) + # Second pmos to the right of the first upper_pmos2_pos = self.upper_pmos1_pos + overlap_offset self.upper_pmos2_inst.place(upper_pmos2_pos) @@ -161,16 +166,25 @@ class precharge(design.design): """ Adds the en input rail, en contact/vias, and connects to the pmos """ - + + if self.bitcell_bl_pin.layer == "m1": + layer = "m2" + else: + layer = "m1" + # adds the en contact to connect the gates to the en rail on metal1 offset = self.lower_pmos_inst.get_pin("G").ul() \ - + vector(0, 0.5 * self.poly_space) + + vector(0, self.m2_pitch) self.add_via_center(layers=self.poly_stack, offset=offset) + if layer == "m2": + self.add_via_center(layers=self.m1_stack, + offset=offset) + # adds the en rail on metal1 self.add_layout_pin_segment_center(text="en_bar", - layer="m1", + layer=layer, start=offset.scale(0, 1), end=offset.scale(0, 1) + vector(self.width, 0)) @@ -201,20 +215,21 @@ class precharge(design.design): """ Adds both bit-line and bit-line-bar to the module """ - + layer_width = drc("minwidth_" + self.bitcell_br_pin.layer) + layer_space = drc("{0}_to_{0}".format(self.bitcell_br_pin.layer)) + layer = self.bitcell_bl_pin.layer + # adds the BL on metal 2 - offset = vector(self.bitcell.get_pin(self.bitcell_bl).cx(), 0) \ - - vector(0.5 * self.m2_width, 0) + offset = vector(layer_space - 0.5 * layer_width, 0) self.bl_pin = self.add_layout_pin(text="bl", - layer="m2", + layer=layer, offset=offset, height=self.height) # adds the BR on metal 2 - offset = vector(self.bitcell.get_pin(self.bitcell_br).cx(), 0) \ - - vector(0.5 * self.m2_width, 0) + offset = vector(self.width - layer_space - 0.5 * layer_width, 0) self.br_pin = self.add_layout_pin(text="br", - layer="m2", + layer=layer, offset=offset, height=self.height) @@ -225,11 +240,12 @@ class precharge(design.design): self.add_bitline_contacts() self.connect_pmos_m2(self.lower_pmos_inst.get_pin("S"), self.get_pin("bl")) + self.connect_pmos_m2(self.lower_pmos_inst.get_pin("D"), + self.get_pin("br")) + self.connect_pmos_m2(self.upper_pmos1_inst.get_pin("S"), self.get_pin("bl")) - self.connect_pmos_m1(self.lower_pmos_inst.get_pin("D"), - self.get_pin("br")) - self.connect_pmos_m1(self.upper_pmos2_inst.get_pin("D"), + self.connect_pmos_m2(self.upper_pmos2_inst.get_pin("D"), self.get_pin("br")) def add_bitline_contacts(self): @@ -237,34 +253,28 @@ class precharge(design.design): Adds contacts/via from metal1 to metal2 for bit-lines """ - upper_pin = self.upper_pmos1_inst.get_pin("S") - lower_pin = self.lower_pmos_inst.get_pin("S") - # BL goes up to M2 at the transistor - self.bl_contact =self.add_via_center(layers=self.m1_stack, - offset=upper_pin.center(), + # BL + lower_pin = self.lower_pmos_inst.get_pin("S") + self.lower_via = self.add_via_center(layers=self.m1_stack, + offset=lower_pin.center(), directions=("V", "V")) - self.add_via_center(layers=self.m1_stack, - offset=lower_pin.center(), - directions=("V", "V")) - # BR routes over on M1 first - self.add_via_center(layers=self.m1_stack, - offset=vector(self.br_pin.cx(), upper_pin.cy()), - directions=("V", "V")) - self.add_via_center(layers=self.m1_stack, - offset=vector(self.br_pin.cx(), lower_pin.cy()), - directions=("V", "V")) + lower_pin = self.lower_pmos_inst.get_pin("D") + self.lower_via = self.add_via_center(layers=self.m1_stack, + offset=lower_pin.center(), + directions=("V", "V")) + + # BR + upper_pin = self.upper_pmos1_inst.get_pin("S") + self.upper_via2 = self.add_via_center(layers=self.m1_stack, + offset=upper_pin.center(), + directions=("V", "V")) - def connect_pmos_m1(self, pmos_pin, bit_pin): - """ - Connect a pmos pin to bitline pin - """ - - left_pos = vector(min(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) - right_pos = vector(max(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) - - self.add_path("m1", [left_pos, right_pos] ) + upper_pin = self.upper_pmos2_inst.get_pin("D") + self.upper_via2 = self.add_via_center(layers=self.m1_stack, + offset=upper_pin.center(), + directions=("V", "V")) def connect_pmos_m2(self, pmos_pin, bit_pin): """ @@ -274,7 +284,7 @@ class precharge(design.design): left_pos = vector(min(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) right_pos = vector(max(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) - self.add_path("m2", [left_pos, right_pos], self.bl_contact.height) + self.add_path("m2", [left_pos, right_pos]) def get_en_cin(self): """Get the relative capacitance of the enable in the precharge cell""" From d7529ce526d49eddab2ca802960d75c4c722f28d Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Wed, 4 Mar 2020 17:05:19 -0800 Subject: [PATCH 184/521] Vdd/gnd via stacks now use perferred directions, added cell property to override --- compiler/base/hierarchy_layout.py | 123 +++++++++++++------------ compiler/modules/bitcell_base_array.py | 11 ++- 2 files changed, 73 insertions(+), 61 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 451d1356..3c2e8992 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -37,7 +37,7 @@ class layout(): self.objs = [] # Holds all other objects (labels, geometries, etc) self.pin_map = {} # Holds name->pin_layout map for all pins self.visited = [] # List of modules we have already visited - self.is_library_cell = False # Flag for library cells + self.is_library_cell = False # Flag for library cells self.gds_read() try: from tech import power_grid @@ -71,7 +71,7 @@ class layout(): (inv_num + 1) * height - \ (inv_num % 2) * drc["minwidth_m1"]) y_dir = -1 - + return (base_offset, y_dir) def find_lowest_coords(self): @@ -90,7 +90,7 @@ class layout(): lowesty2 = min(inst.by() for inst in self.insts) else: lowestx2 = lowesty2 = None - + if lowestx1 == None and lowestx2 == None: return None elif lowestx1 == None: @@ -146,7 +146,7 @@ class layout(): subcoord = inst.mod.find_highest_layer_coords(layer) + inst.offset highestx = max(highestx, subcoord.x) highesty = max(highesty, subcoord.y) - + return vector(highestx, highesty) def find_lowest_layer_coords(self, layer): @@ -172,7 +172,7 @@ class layout(): lowesty = min(lowesty, subcoord.y) return vector(lowestx, lowesty) - + def translate_all(self, offset): """ Translates all objects, instances, and pins by the given (x,y) offset @@ -189,7 +189,7 @@ class layout(): pin_list = self.pin_map[pin_name] for pin in pin_list: pin.rect = [pin.ll() - offset, pin.ur() - offset] - + def add_inst(self, name, mod, offset=[0, 0], mirror="R0", rotate=0): """ Adds an instance of a mod to this module """ self.insts.append(geometry.instance(name, mod, offset, mirror, rotate)) @@ -204,7 +204,7 @@ class layout(): if inst.name == name: return inst return None - + def add_rect(self, layer, offset, width=None, height=None): """ Adds a rectangle on a given layer,offset with width and height @@ -260,7 +260,7 @@ class layout(): start-offset, minwidth_layer, end.y-start.y) - + def get_pin(self, text): """ Return the pin or list of pins @@ -275,7 +275,7 @@ class layout(): except Exception: self.gds_write("missing_pin.gds") debug.error("No pin found with name {0} on {1}. Saved as missing_pin.gds.".format(text,self.name),-1) - + def get_pins(self, text): """ Return a pin list (instead of a single pin) @@ -290,17 +290,17 @@ class layout(): Return a pin list of all pins """ return self.pin_map.keys() - + def copy_layout_pin(self, instance, pin_name, new_name=""): """ Create a copied version of the layout pin at the current level. You can optionally rename the pin to a new name. """ pins = instance.get_pins(pin_name) - + debug.check(len(pins) > 0, "Could not find pin {}".format(pin_name)) - + for pin in pins: if new_name == "": new_name = pin.name @@ -317,7 +317,7 @@ class layout(): """ for pin_name in self.pin_map.keys(): self.copy_layout_pin(instance, pin_name, prefix+pin_name) - + def add_layout_pin_segment_center(self, text, layer, start, end): """ Creates a path like pin with center-line convention @@ -325,9 +325,9 @@ class layout(): debug.check(start.x == end.x or start.y == end.y, "Cannot have a non-manhatten layout pin.") - + minwidth_layer = drc["minwidth_{}".format(layer)] - + # one of these will be zero width = max(start.x, end.x) - min(start.x, end.x) height = max(start.y, end.y) - min(start.y, end.y) @@ -341,7 +341,7 @@ class layout(): # This makes sure it is long enough, but also it is not 0 width! height = max(minwidth_layer, height) width = max(minwidth_layer, width) - + return self.add_layout_pin(text, layer, ll_offset, @@ -358,13 +358,13 @@ class layout(): ll_offset = offset - vector(0.5 * width, 0.5 * height) return self.add_layout_pin(text, layer, ll_offset, width, height) - + def remove_layout_pin(self, text): """ Delete a labeled pin (or all pins of the same name) """ self.pin_map[text] = set() - + def add_layout_pin(self, text, layer, offset, width=None, height=None): """ Create a labeled pin @@ -408,7 +408,7 @@ class layout(): layer=layer, offset=offset + vector(0.5 * width, 0.5 * height)) - + def add_label(self, text, layer, offset=[0, 0], zoom=-1): """Adds a text label on the given layer,offset, and zoom level""" # negative layers indicate "unused" layers in a given technology @@ -447,7 +447,7 @@ class layout(): layer_stack=layers, path=coordinates, layer_widths=layer_widths) - + def add_wire(self, layers, coordinates): """Connects a routing path on given layer,coordinates,width. The layers are the (horizontal, via, vertical). """ @@ -462,14 +462,14 @@ class layout(): """ Return the preferred routing directions """ from tech import preferred_directions return preferred_directions[layer] - + def add_via(self, layers, offset, size=[1,1], directions=None, implant_type=None, well_type=None): """ Add a three layer via structure. """ if not directions: directions = (self.get_preferred_direction(layers[0]), self.get_preferred_direction(layers[2])) - + from sram_factory import factory via = factory.create(module_type="contact", layer_stack=layers, @@ -494,7 +494,7 @@ class layout(): if not directions: directions = (self.get_preferred_direction(layers[0]), self.get_preferred_direction(layers[2])) - + from sram_factory import factory via = factory.create(module_type="contact", layer_stack=layers, @@ -504,7 +504,7 @@ class layout(): well_type=well_type) height = via.height width = via.width - + corrected_offset = offset + vector(-0.5 * width, -0.5 * height) @@ -580,7 +580,7 @@ class layout(): last_via=via, size=size) - + def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"): """Adds a ptx module to the design.""" import ptx @@ -602,11 +602,11 @@ class layout(): # This must be done for netlist only mode too if os.path.isfile(self.gds_file): self.is_library_cell = True - + if OPTS.netlist_only: self.gds = None return - + # open the gds file if it exists or else create a blank layout if os.path.isfile(self.gds_file): debug.info(3, "opening {}".format(self.gds_file)) @@ -662,7 +662,7 @@ class layout(): height=height, center=False) debug.info(2, "Adding {0} boundary {1}".format(self.name, boundary)) - + self.visited.append(self.name) def gds_write(self, gds_name): @@ -681,10 +681,10 @@ class layout(): # which may have been previously processed! # MRG: 10/4/18 We need to clear if we make changes and write a second GDS! self.clear_visited() - + # recursively create all the remaining objects self.gds_write_file(self.gds) - + # populates the xyTree data structure for gds # self.gds.prepareForWrite() writer.writeToFile(gds_name) @@ -706,7 +706,7 @@ class layout(): lpp = techlayer[layer] else: lpp = layer - + blockages = [] for i in self.objs: blockages += i.get_blockages(lpp) @@ -724,7 +724,7 @@ class layout(): pin_names = copy.deepcopy(self.pins) if self.name.startswith("pmos") or self.name.startswith("nmos"): pin_names.remove("B") - + blockages = [] for pin_name in pin_names: pin_list = self.get_pins(pin_name) @@ -784,7 +784,7 @@ class layout(): # half minwidth so we can return the center line offsets half_minwidth = 0.5 * drc["minwidth_{}".format(layer)] - + line_positions = {} if vertical: for i in range(len(names)): @@ -829,7 +829,7 @@ class layout(): layer_stack=("m1", "via1", "m2")): """ Vertical version of connect_bus. """ self.connect_bus(mapping, inst, bus_offsets, layer_stack, False) - + def connect_bus(self, mapping, inst, bus_offsets, layer_stack, horizontal): """ Connect a mapping of pin -> name for a bus. This could be @@ -842,7 +842,7 @@ class layout(): route_layer = vertical_layer else: route_layer = horizontal_layer - + for (pin_name, bus_name) in mapping: pin = inst.get_pin(pin_name) pin_pos = pin.center() @@ -854,7 +854,7 @@ class layout(): else: # left/right then up/down mid_pos = vector(bus_pos.x, pin_pos.y) - + self.add_wire(layer_stack, [bus_pos, mid_pos, pin_pos]) @@ -865,7 +865,7 @@ class layout(): offset=pin_pos) # FIXME: output pins tend to not be rotate, # but supply pins are. Make consistent? - + # We only need a via if they happened to align perfectly # so the add_wire didn't add a via if (horizontal and bus_pos.y == pin_pos.y) or (not horizontal and bus_pos.x == pin_pos.x): @@ -899,7 +899,7 @@ class layout(): self.m3_space) else: debug.error("Cannot find layer pitch.") - + def add_horizontal_trunk_route(self, pins, trunk_offset, @@ -915,7 +915,7 @@ class layout(): # if we are less than a pitch, just create a non-preferred layer jog if max_x-min_x <= pitch: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)] - + # Add the horizontal trunk on the vertical layer! self.add_path(self.vertical_layer, [vector(min_x - half_layer_width, trunk_offset.y), @@ -955,7 +955,7 @@ class layout(): if max_y-min_y <= pitch: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)] - + # Add the vertical trunk on the horizontal layer! self.add_path(self.horizontal_layer, [vector(trunk_offset.x, min_y - half_layer_width), @@ -978,7 +978,7 @@ class layout(): self.add_path(self.horizontal_layer, [pin.center(), mid]) self.add_via_center(layers=layer_stack, offset=mid) - + def create_channel_route(self, netlist, offset, layer_stack, @@ -996,7 +996,7 @@ class layout(): Remove the pin from the graph and all conflicts """ g.pop(pin, None) - + # Remove the pin from all conflicts # FIXME: This is O(n^2), so maybe optimize it. for other_pin,conflicts in g.items(): @@ -1010,21 +1010,21 @@ class layout(): Check all the pin pairs on two nets and return a pin overlap if any pin overlaps. """ - + for pin1 in net1: for pin2 in net2: if vcg_pin_overlap(pin1, pin2, vertical, pitch): return True return False - + def vcg_pin_overlap(pin1, pin2, vertical, pitch): """ Check for vertical or horizontal overlap of the two pins """ # FIXME: If the pins are not in a row, this may break. # However, a top pin shouldn't overlap another top pin, # for example, so the # extra comparison *shouldn't* matter. - + # Pin 1 must be in the "BOTTOM" set x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x-pin2.center().x) Date: Wed, 4 Mar 2020 17:39:11 -0800 Subject: [PATCH 185/521] Precharge updates. Enable different layers for bitlines. Jog bitlines to fit precharge transistors for close proximity bitlines. PEP8 cleanup. --- compiler/base/hierarchy_layout.py | 2 +- compiler/modules/precharge_array.py | 29 ++----- compiler/pgates/precharge.py | 129 +++++++++++++++++----------- 3 files changed, 88 insertions(+), 72 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 6b1ca3fd..35aa73b1 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -316,7 +316,7 @@ class layout(): You can optionally rename the pin to a new name. """ for pin_name in self.pin_map.keys(): - self.copy_layout_pin(instance, pin_name, prefix+pin_name) + self.copy_layout_pin(instance, pin_name, prefix + pin_name) def add_layout_pin_segment_center(self, text, layer, start, end): """ diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index efc9c4a3..d5b0e799 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -12,6 +12,7 @@ from vector import vector from sram_factory import factory from globals import OPTS + class precharge_array(design.design): """ Dynamically generated precharge array of all bitlines. Cols is number @@ -68,11 +69,8 @@ class precharge_array(design.design): size=self.size, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) - - self.add_mod(self.pc_cell) - def add_layout_pins(self): self.add_layout_pin(text="en_bar", @@ -86,20 +84,9 @@ class precharge_array(design.design): for i in range(len(self.local_insts)): inst = self.local_insts[i] - bl_pin = inst.get_pin("bl") - self.add_layout_pin(text="bl_{0}".format(i), - layer="m2", - offset=bl_pin.ll(), - width=drc("minwidth_m2"), - height=bl_pin.height()) - br_pin = inst.get_pin("br") - self.add_layout_pin(text="br_{0}".format(i), - layer="m2", - offset=br_pin.ll(), - width=drc("minwidth_m2"), - height=bl_pin.height()) + self.copy_layout_pin(inst, "bl", "bl_{0}".format(i)) + self.copy_layout_pin(inst, "br", "br_{0}".format(i)) - def create_insts(self): """Creates a precharge array by horizontally tiling the precharge cell""" self.local_insts = [] @@ -112,7 +99,6 @@ class precharge_array(design.design): self.local_insts.append(inst) self.connect_inst(["bl_{0}".format(i), "br_{0}".format(i), "en_bar", "vdd"]) - def place_insts(self): """ Places precharge array by horizontally tiling the precharge cell""" from tech import cell_properties @@ -130,8 +116,11 @@ class precharge_array(design.design): xoffset = xoffset + self.pc_cell.width def get_en_cin(self): - """Get the relative capacitance of all the clk connections in the precharge array""" - #Assume single port + """ + Get the relative capacitance of all the clk connections + in the precharge array + """ + # Assume single port precharge_en_cin = self.pc_cell.get_en_cin() - return precharge_en_cin*self.columns + return precharge_en_cin * self.columns diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 4a494763..3f0560f5 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -14,6 +14,7 @@ from globals import OPTS from sram_factory import factory from tech import drc + class precharge(design.design): """ Creates a single precharge cell @@ -32,8 +33,14 @@ class precharge(design.design): self.bitcell_br = bitcell_br self.bitcell_bl_pin =self.bitcell.get_pin(self.bitcell_bl) self.bitcell_br_pin =self.bitcell.get_pin(self.bitcell_br) - print(self.bitcell_bl_pin) - print(self.bitcell_br_pin) + + if self.bitcell_bl_pin.layer == "m1": + self.bitline_layer = "m1" + self.en_layer = "m2" + else: + self.bitline_layer = "m2" + self.en_layer = "m1" + # Creates the netlist and layout # Since it has variable height, it is not a pgate. self.create_netlist() @@ -82,18 +89,24 @@ class precharge(design.design): # Adds the rail across the width of the cell vdd_position = vector(0.5 * self.width, self.height) - self.add_rect_center(layer="m1", + layer_width = drc("minwidth_" + self.en_layer) + self.add_rect_center(layer=self.en_layer, offset=vdd_position, width=self.width, - height=self.m1_width) + height=layer_width) pmos_pin = self.upper_pmos2_inst.get_pin("S") # center of vdd rail pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y) self.add_path("m1", [pmos_pin.uc(), pmos_vdd_pos]) + if self.en_layer != "m1": + self.add_via_center(layers=self.m1_stack, + offset=pmos_vdd_pos) + + # Add vdd pin above the transistor - self.add_power_pin("vdd", pmos_pin.center(), vertical=True) + self.add_power_pin("vdd", self.well_contact_pos, vertical=True) def create_ptx(self): """ @@ -117,6 +130,8 @@ class precharge(design.design): Place both the upper_pmos and lower_pmos to the module """ + # reserve some offset to jog the bitlines + self.initial_yoffset = self.pmos.active_offset.y + self.m2_pitch # Compute the other pmos2 location, # but determining offset to overlap the source and drain pins overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll() @@ -127,11 +142,11 @@ class precharge(design.design): bl_xoffset = self.bitcell_bl_pin.lx() self.lower_pmos_position = vector(max(bl_xoffset - contact_xdiff, self.nwell_enclose_active), - self.pmos.active_offset.y) + self.initial_yoffset) self.lower_pmos_inst.place(self.lower_pmos_position) - # adds the upper pmos(s) to layout - ydiff = self.pmos.height + 4 * self.m2_space + # adds the upper pmos(s) to layout with 2 M2 tracks + ydiff = self.pmos.height + self.m2_pitch self.upper_pmos1_pos = self.lower_pmos_position + vector(0, ydiff) self.upper_pmos1_inst.place(self.upper_pmos1_pos) @@ -167,24 +182,20 @@ class precharge(design.design): Adds the en input rail, en contact/vias, and connects to the pmos """ - if self.bitcell_bl_pin.layer == "m1": - layer = "m2" - else: - layer = "m1" - - # adds the en contact to connect the gates to the en rail on metal1 + # adds the en contact to connect the gates to the en rail + # midway in the 4 M2 tracks offset = self.lower_pmos_inst.get_pin("G").ul() \ - + vector(0, self.m2_pitch) + + vector(0, 0.5 * self.m2_pitch) self.add_via_center(layers=self.poly_stack, offset=offset) - if layer == "m2": + if self.en_layer == "m2": self.add_via_center(layers=self.m1_stack, offset=offset) # adds the en rail on metal1 self.add_layout_pin_segment_center(text="en_bar", - layer=layer, + layer=self.en_layer, start=offset.scale(0, 1), end=offset.scale(0, 1) + vector(self.width, 0)) @@ -194,16 +205,15 @@ class precharge(design.design): """ # adds the contact from active to metal1 - well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \ - + vector(0, self.upper_pmos1_inst.uy() + contact.active_contact.height / 2 \ - + self.nwell_extend_active) + self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \ + + vector(0, self.upper_pmos1_inst.uy() + contact.active_contact.height / 2 \ + + self.nwell_extend_active) self.add_via_center(layers=self.active_stack, - offset=well_contact_pos, + offset=self.well_contact_pos, implant_type="n", well_type="n") - # leave an extra pitch for the height - self.height = well_contact_pos.y + contact.active_contact.height + self.m1_pitch + self.height = self.well_contact_pos.y + contact.active_contact.height + self.m1_space # nwell should span the whole design since it is pmos only self.add_rect(layer="nwell", @@ -215,44 +225,59 @@ class precharge(design.design): """ Adds both bit-line and bit-line-bar to the module """ - layer_width = drc("minwidth_" + self.bitcell_br_pin.layer) - layer_space = drc("{0}_to_{0}".format(self.bitcell_br_pin.layer)) - layer = self.bitcell_bl_pin.layer + layer_width = drc("minwidth_" + self.bitline_layer) + layer_space = drc("{0}_to_{0}".format(self.bitline_layer)) - # adds the BL on metal 2 - offset = vector(layer_space - 0.5 * layer_width, 0) - self.bl_pin = self.add_layout_pin(text="bl", - layer=layer, - offset=offset, - height=self.height) - - # adds the BR on metal 2 - offset = vector(self.width - layer_space - 0.5 * layer_width, 0) - self.br_pin = self.add_layout_pin(text="br", - layer=layer, - offset=offset, - height=self.height) + yoffset = self.initial_yoffset - 0.5 * self.m2_pitch + # adds the BL + self.bl_xoffset = layer_space + 0.5 * layer_width + top_pos = vector(self.bl_xoffset, self.height) + mid1_pos = vector(self.bl_xoffset, yoffset) + mid2_pos = vector(self.bitcell_bl_pin.cx(), yoffset) + pin_pos = vector(self.bitcell_bl_pin.cx(), 0) + self.add_path(self.bitline_layer, + [top_pos, mid1_pos, mid2_pos, pin_pos]) + self.bl_pin = self.add_layout_pin_segment_center(text="bl", + layer=self.bitline_layer, + start=pin_pos, + end=mid2_pos) + + # adds the BR + self.br_xoffset = self.width - layer_space - 0.5 * layer_width + top_pos = vector(self.br_xoffset, self.height) + mid1_pos = vector(self.br_xoffset, yoffset) + mid2_pos = vector(self.bitcell_br_pin.cx(), yoffset) + pin_pos = vector(self.bitcell_br_pin.cx(), 0) + self.add_path(self.bitline_layer, + [top_pos, mid1_pos, mid2_pos, pin_pos]) + self.br_pin = self.add_layout_pin_segment_center(text="br", + layer=self.bitline_layer, + start=pin_pos, + end=mid2_pos) def connect_to_bitlines(self): """ Connect the bitlines to the devices """ self.add_bitline_contacts() - self.connect_pmos_m2(self.lower_pmos_inst.get_pin("S"), - self.get_pin("bl")) - self.connect_pmos_m2(self.lower_pmos_inst.get_pin("D"), - self.get_pin("br")) + self.connect_pmos(self.lower_pmos_inst.get_pin("S"), + self.bl_xoffset) + self.connect_pmos(self.lower_pmos_inst.get_pin("D"), + self.br_xoffset) - self.connect_pmos_m2(self.upper_pmos1_inst.get_pin("S"), - self.get_pin("bl")) - self.connect_pmos_m2(self.upper_pmos2_inst.get_pin("D"), - self.get_pin("br")) + self.connect_pmos(self.upper_pmos1_inst.get_pin("S"), + self.bl_xoffset) + self.connect_pmos(self.upper_pmos2_inst.get_pin("D"), + self.br_xoffset) def add_bitline_contacts(self): """ Adds contacts/via from metal1 to metal2 for bit-lines """ + # No contacts needed if M1 + if self.bitline_layer == "m1": + return # BL lower_pin = self.lower_pmos_inst.get_pin("S") @@ -276,15 +301,17 @@ class precharge(design.design): offset=upper_pin.center(), directions=("V", "V")) - def connect_pmos_m2(self, pmos_pin, bit_pin): + def connect_pmos(self, pmos_pin, bit_xoffset): """ Connect a pmos pin to bitline pin """ - left_pos = vector(min(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) - right_pos = vector(max(pmos_pin.cx(), bit_pin.cx()), pmos_pin.cy()) + left_pos = vector(min(pmos_pin.cx(), bit_xoffset), pmos_pin.cy()) + right_pos = vector(max(pmos_pin.cx(), bit_xoffset), pmos_pin.cy()) - self.add_path("m2", [left_pos, right_pos]) + self.add_path(self.bitline_layer, + [left_pos, right_pos], + width=pmos_pin.height()) def get_en_cin(self): """Get the relative capacitance of the enable in the precharge cell""" From 7adeef6c9e46e3f43259ed8594c2283422a0b167 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 5 Mar 2020 10:21:18 -0800 Subject: [PATCH 186/521] PEP8 Formatting --- compiler/modules/port_data.py | 146 ++++++++++++++-------------------- 1 file changed, 60 insertions(+), 86 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 7c37d670..fbf5223a 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -1,18 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California +# Copyright (c) 2016-2019 Regents of the University of California # All rights reserved. # -import sys -from tech import drc, parameter +from tech import drc import debug import design from sram_factory import factory from collections import namedtuple from vector import vector - from globals import OPTS + class port_data(design.design): """ Create the data port (column mux, sense amps, write driver, etc.) for the given port number. @@ -24,18 +23,21 @@ class port_data(design.design): sram_config.set_local_config(self) self.port = port if self.write_size is not None: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(self.word_size / self.write_size) else: self.num_wmasks = 0 if name == "": name = "port_data_{0}".format(self.port) design.design.__init__(self, name) - debug.info(2, "create data port of size {0} with {1} words per row".format(self.word_size,self.words_per_row)) + debug.info(2, + "create data port of size {0} with {1} words per row".format(self.word_size, + self.words_per_row)) self.create_netlist() if not OPTS.netlist_only: - debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.") + debug.check(len(self.all_ports)<=2, + "Bank layout cannot handle more than two ports.") self.create_layout() self.add_boundary() @@ -93,8 +95,6 @@ class port_data(design.design): else: self.column_mux_array_inst = None - - def create_layout(self): self.compute_instance_offsets() self.place_instances() @@ -104,33 +104,32 @@ class port_data(design.design): def add_pins(self): """ Adding pins for port address module""" - self.add_pin("rbl_bl","INOUT") - self.add_pin("rbl_br","INOUT") + self.add_pin("rbl_bl", "INOUT") + self.add_pin("rbl_br", "INOUT") for bit in range(self.num_cols): bl_name = self.get_bl_name(self.port) br_name = self.get_br_name(self.port) - self.add_pin("{0}_{1}".format(bl_name, bit),"INOUT") - self.add_pin("{0}_{1}".format(br_name, bit),"INOUT") + self.add_pin("{0}_{1}".format(bl_name, bit), "INOUT") + self.add_pin("{0}_{1}".format(br_name, bit), "INOUT") if self.port in self.read_ports: for bit in range(self.word_size): - self.add_pin("dout_{}".format(bit),"OUTPUT") + self.add_pin("dout_{}".format(bit), "OUTPUT") if self.port in self.write_ports: for bit in range(self.word_size): - self.add_pin("din_{}".format(bit),"INPUT") + self.add_pin("din_{}".format(bit), "INPUT") # Will be empty if no col addr lines sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)] for pin_name in sel_names: - self.add_pin(pin_name,"INPUT") + self.add_pin(pin_name, "INPUT") if self.port in self.read_ports: self.add_pin("s_en", "INPUT") self.add_pin("p_en_bar", "INPUT") if self.port in self.write_ports: self.add_pin("w_en", "INPUT") for bit in range(self.num_wmasks): - self.add_pin("bank_wmask_{}".format(bit),"INPUT") - self.add_pin("vdd","POWER") - self.add_pin("gnd","GROUND") - + self.add_pin("bank_wmask_{}".format(bit), "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def route_layout(self): """ Create routing among the modules """ @@ -172,8 +171,8 @@ class port_data(design.design): """ Propagate all vdd/gnd pins up to this level for all modules """ for inst in self.insts: - self.copy_power_pins(inst,"vdd") - self.copy_power_pins(inst,"gnd") + self.copy_power_pins(inst, "vdd") + self.copy_power_pins(inst, "gnd") def add_modules(self): @@ -193,7 +192,6 @@ class port_data(design.design): else: self.sense_amp_array = None - if self.col_addr_size > 0: self.column_mux_array = factory.create(module_type="column_mux_array", columns=self.num_cols, @@ -204,7 +202,6 @@ class port_data(design.design): else: self.column_mux_array = None - if self.port in self.write_ports: self.write_driver_array = factory.create(module_type="write_driver_array", columns=self.num_cols, @@ -234,29 +231,27 @@ class port_data(design.design): else: self.num_col_addr_lines = 0 - # A space for wells or jogging m2 between modules - self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"), - 3*self.m2_pitch) + self.m2_gap = max(2 * drc("pwell_to_nwell") + drc("nwell_enclose_active"), + 3 * self.m2_pitch) - # create arrays of bitline and bitline_bar names for read, write, or all ports + # create arrays of bitline and bitline_bar names for read, + # write, or all ports self.bitcell = factory.create(module_type="bitcell") self.bl_names = self.bitcell.get_all_bl_names() self.br_names = self.bitcell.get_all_br_names() self.wl_names = self.bitcell.get_all_wl_names() # used for bl/br names self.precharge = factory.create(module_type="precharge", - bitcell_bl = self.bl_names[0], - bitcell_br = self.br_names[0]) + bitcell_bl=self.bl_names[0], + bitcell_br=self.br_names[0]) # We create a dummy here to get bl/br names to add those pins to this # module, which happens before we create the real precharge_array self.precharge_array = factory.create(module_type="precharge_array", - columns=self.num_cols + 1, - bitcell_bl=self.bl_names[self.port], - bitcell_br=self.br_names[self.port]) - - + columns=self.num_cols + 1, + bitcell_bl=self.bl_names[self.port], + bitcell_br=self.br_names[self.port]) def create_precharge_array(self): """ Creating Precharge """ @@ -285,13 +280,11 @@ class port_data(design.design): temp.extend(["p_en_bar", "vdd"]) self.connect_inst(temp) - def place_precharge_array(self, offset): """ Placing Precharge """ self.precharge_array_inst.place(offset=offset, mirror="MX") - def create_column_mux_array(self): """ Creating Column Mux when words_per_row > 1 . """ @@ -314,7 +307,6 @@ class port_data(design.design): temp.append("gnd") self.connect_inst(temp) - def place_column_mux_array(self, offset): """ Placing Column Mux when words_per_row > 1 . """ if self.col_addr_size == 0: @@ -322,7 +314,6 @@ class port_data(design.design): self.column_mux_array_inst.place(offset=offset, mirror="MX") - def create_sense_amp_array(self): """ Creating Sense amp """ self.sense_amp_array_inst = self.add_inst(name="sense_amp_array{}".format(self.port), @@ -340,16 +331,13 @@ class port_data(design.design): temp.append("{0}_out_{1}".format(bl_name, bit)) temp.append("{0}_out_{1}".format(br_name, bit)) - temp.extend(["s_en", "vdd", "gnd"]) self.connect_inst(temp) - def place_sense_amp_array(self, offset): """ Placing Sense amp """ self.sense_amp_array_inst.place(offset=offset, mirror="MX") - def create_write_driver_array(self): """ Creating Write Driver """ self.write_driver_array_inst = self.add_inst(name="write_driver_array{}".format(self.port), @@ -378,12 +366,10 @@ class port_data(design.design): self.connect_inst(temp) - def place_write_driver_array(self, offset): """ Placing Write Driver """ self.write_driver_array_inst.place(offset=offset, mirror="MX") - def create_write_mask_and_array(self): """ Creating Write Mask AND Array """ self.write_mask_and_array_inst = self.add_inst(name="write_mask_and_array{}".format(self.port), @@ -398,12 +384,10 @@ class port_data(design.design): temp.extend(["vdd", "gnd"]) self.connect_inst(temp) - def place_write_mask_and_array(self, offset): """ Placing Write Mask AND array """ self.write_mask_and_array_inst.place(offset=offset, mirror="MX") - def compute_instance_offsets(self): """ Compute the empty instance offsets for port0 and port1 (if needed) @@ -458,19 +442,17 @@ class port_data(design.design): if self.column_mux_offset: self.place_column_mux_array(self.column_mux_offset) - def route_sense_amp_out(self, port): """ Add pins for the sense amp output """ for bit in range(self.word_size): data_pin = self.sense_amp_array_inst.get_pin("data_{}".format(bit)) self.add_layout_pin_rect_center(text="dout_{0}".format(bit), - layer=data_pin.layer, + layer=data_pin.layer, offset=data_pin.center(), height=data_pin.height(), width=data_pin.width()) - def route_write_driver_in(self, port): """ Connecting write driver """ @@ -479,7 +461,6 @@ class port_data(design.design): din_name = "din_{}".format(row) self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name) - def route_write_mask_and_array_in(self, port): """ Add pins for the write mask and array input """ @@ -488,7 +469,6 @@ class port_data(design.design): bank_wmask_name = "bank_wmask_{}".format(bit) self.copy_layout_pin(self.write_mask_and_array_inst, wmask_in_name, bank_wmask_name) - def route_write_mask_and_array_to_write_driver(self,port): """ Routing of wdriver_sel_{} between write mask AND array and write driver array. Adds layout pin for write mask AND array output and via for write driver enable """ @@ -511,15 +491,15 @@ class port_data(design.design): while (wmask_out_pin.lx() + self.m2_pitch > inst2.get_pin("data_{0}".format(loc)).rx()): loc += 1 length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch - debug.check(loc<=self.num_wmasks,"Couldn't route the write mask select.") + debug.check(loc<=self.num_wmasks, + "Couldn't route the write mask select.") else: # Stride by the write size rather than finding the next pin to the right loc += self.write_size - length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch - + length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch beg_pos = wmask_out_pin.center() - middle_pos = vector(length,wmask_out_pin.cy()) + middle_pos = vector(length, wmask_out_pin.cy()) end_pos = vector(length, wdriver_en_pin.cy()) # Add via for the write driver array's enable input @@ -529,7 +509,6 @@ class port_data(design.design): # Route between write mask AND array and write driver array self.add_wire(self.m1_stack, [beg_pos, middle_pos, end_pos]) - def route_column_mux_to_precharge_array(self, port): """ Routing of BL and BR between col mux and precharge array """ @@ -547,7 +526,6 @@ class port_data(design.design): num_bits=self.num_cols, inst2_start_bit=insn2_start_bit) - def route_sense_amp_to_column_mux_or_precharge_array(self, port): """ Routing of BL and BR between sense_amp and column mux or precharge array """ inst2 = self.sense_amp_array_inst @@ -573,12 +551,9 @@ class port_data(design.design): num_bits=self.word_size, inst1_start_bit=start_bit) - def route_write_driver_to_column_mux_or_precharge_array(self, port): """ Routing of BL and BR between sense_amp and column mux or precharge array """ inst2 = self.write_driver_array_inst - inst2_bl_name = inst2.mod.get_bl_name() - inst2_br_name = inst2.mod.get_br_name() if self.col_addr_size>0: # Write driver is connected to the col mux @@ -599,7 +574,6 @@ class port_data(design.design): inst1_bls_template=inst1_bls_templ, inst1_start_bit=start_bit) - def route_write_driver_to_sense_amp(self, port): """ Routing of BL and BR between write driver and sense amp """ @@ -612,7 +586,6 @@ class port_data(design.design): inst2=inst2, num_bits=self.word_size) - def route_bitline_pins(self): """ Add the bitline pins for the given port """ @@ -630,12 +603,15 @@ class port_data(design.design): for bit in range(self.num_cols): if self.precharge_array_inst: - self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(bit+bit_offset), "bl_{}".format(bit)) - self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(bit+bit_offset), "br_{}".format(bit)) + self.copy_layout_pin(self.precharge_array_inst, + "bl_{}".format(bit + bit_offset), + "bl_{}".format(bit)) + self.copy_layout_pin(self.precharge_array_inst, + "br_{}".format(bit + bit_offset), + "br_{}".format(bit)) else: debug.error("Didn't find precharge array.") - def route_control_pins(self): """ Add the control pins: s_en, p_en_bar, w_en """ if self.precharge_array_inst: @@ -656,8 +632,6 @@ class port_data(design.design): if self.write_mask_and_array_inst: self.copy_layout_pin(self.write_mask_and_array_inst, "en", "w_en") - - def _group_bitline_instances(self, inst1, inst2, num_bits, inst1_bls_template, inst1_start_bit, @@ -694,17 +668,16 @@ class port_data(design.design): Extracts bl/br pins from an InstanceGroup based on the bit modifier. """ full_bl_name = inst_group.bls_template.format( - **{'inst' : inst_group.bl_name, - 'bit' : inst_group.start_bit + bit} - ) + **{'inst': inst_group.bl_name, + 'bit': inst_group.start_bit + bit} + ) full_br_name = inst_group.bls_template.format( - **{'inst' : inst_group.br_name, - 'bit' : inst_group.start_bit + bit} - ) + **{'inst': inst_group.br_name, + 'bit': inst_group.start_bit + bit} + ) return (inst_group.inst.get_pin(full_bl_name), inst_group.inst.get_pin(full_br_name)) - def channel_route_bitlines(self, inst1, inst2, num_bits, inst1_bls_template="{inst}_{bit}", inst1_start_bit=0, @@ -721,14 +694,13 @@ class port_data(design.design): # Channel route each mux separately since we don't minimize the number # of tracks in teh channel router yet. If we did, we could route all the bits at once! - offset = bot_inst_group.inst.ul() + vector(0,self.m1_pitch) + offset = bot_inst_group.inst.ul() + vector(0, self.m1_pitch) for bit in range(num_bits): bottom_names = self._get_bitline_pins(bot_inst_group, bit) top_names = self._get_bitline_pins(top_inst_group, bit) route_map = list(zip(bottom_names, top_names)) self.create_horizontal_channel_route(route_map, offset, self.m1_stack) - def connect_bitlines(self, inst1, inst2, num_bits, inst1_bls_template="{inst}_{bit}", @@ -742,11 +714,9 @@ class port_data(design.design): """ bot_inst_group, top_inst_group = self._group_bitline_instances( - inst1, inst2, num_bits, - inst1_bls_template, inst1_start_bit, - inst2_bls_template, inst2_start_bit) - bottom_inst = bot_inst_group.inst - top_inst = top_inst_group.inst + inst1, inst2, num_bits, + inst1_bls_template, inst1_start_bit, + inst2_bls_template, inst2_start_bit) for col in range(num_bits): bot_bl_pin, bot_br_pin = self._get_bitline_pins(bot_inst_group, col) @@ -754,11 +724,15 @@ class port_data(design.design): bot_bl, bot_br = bot_bl_pin.uc(), bot_br_pin.uc() top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc() - yoffset = 0.5*(top_bl.y+bot_bl.y) - self.add_path("m2",[bot_bl, vector(bot_bl.x,yoffset), - vector(top_bl.x,yoffset), top_bl]) - self.add_path("m2",[bot_br, vector(bot_br.x,yoffset), - vector(top_br.x,yoffset), top_br]) + yoffset = 0.5 * (top_bl.y + bot_bl.y) + self.add_path("m2", [bot_bl, + vector(bot_bl.x, yoffset), + vector(top_bl.x, yoffset), + top_bl]) + self.add_path("m2", [bot_br, + vector(bot_br.x, yoffset), + vector(top_br.x, yoffset), + top_br]) def graph_exclude_precharge(self): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" From 9c1f0657dda328a0c3339aad1ffb1b63aff2f668 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 5 Mar 2020 11:58:36 -0800 Subject: [PATCH 187/521] PEP8 Formatting --- compiler/modules/bank.py | 333 ++++++++++++++++++--------------------- 1 file changed, 154 insertions(+), 179 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index f5f3feb6..60c84a1e 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -17,9 +17,9 @@ from globals import OPTS class bank(design.design): """ Dynamically generated a single bank including bitcell array, - hierarchical_decoder, precharge, (optional column_mux and column decoder), + hierarchical_decoder, precharge, (optional column_mux and column decoder), write driver and sense amplifiers. - This can create up to two ports in any combination: rw, w, r. + This can create up to two ports in any combination: rw, w, r. """ def __init__(self, sram_config, name=""): @@ -27,15 +27,15 @@ class bank(design.design): self.sram_config = sram_config sram_config.set_local_config(self) if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(self.word_size / self.write_size) else: self.num_wmasks = 0 if name == "": name = "bank_{0}_{1}".format(self.word_size, self.num_words) design.design.__init__(self, name) - debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,self.num_words)) - + debug.info(2, "create sram of size {0} with {1} words".format(self.word_size, + self.num_words)) # The local control signals are gated when we have bank select logic, # so this prefix will be added to all of the input signals to create @@ -47,18 +47,17 @@ class bank(design.design): self.create_netlist() if not OPTS.netlist_only: - debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.") + debug.check(len(self.all_ports)<=2, + "Bank layout cannot handle more than two ports.") self.create_layout() self.add_boundary() - def create_netlist(self): self.compute_sizes() self.add_modules() self.add_pins() # Must create the replica bitcell array first self.create_instances() - def create_layout(self): self.place_instances() @@ -66,35 +65,34 @@ class bank(design.design): self.route_layout() # Can remove the following, but it helps for debug! - #self.add_lvs_correspondence_points() + # self.add_lvs_correspondence_points() # Remember the bank center for further placement - self.bank_array_ll = self.offset_all_coordinates().scale(-1,-1) + self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1) self.bank_array_ur = self.bitcell_array_inst.ur() self.bank_array_ul = self.bitcell_array_inst.ul() - self.DRC_LVS() def add_pins(self): """ Adding pins for Bank module""" for port in self.read_ports: for bit in range(self.word_size): - self.add_pin("dout{0}_{1}".format(port,bit),"OUTPUT") + self.add_pin("dout{0}_{1}".format(port, bit), "OUTPUT") for port in self.all_ports: - self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]),"OUTPUT") + self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]), "OUTPUT") for port in self.write_ports: for bit in range(self.word_size): - self.add_pin("din{0}_{1}".format(port,bit),"INPUT") + self.add_pin("din{0}_{1}".format(port,bit), "INPUT") for port in self.all_ports: for bit in range(self.addr_size): - self.add_pin("addr{0}_{1}".format(port,bit),"INPUT") + self.add_pin("addr{0}_{1}".format(port,bit), "INPUT") # For more than one bank, we have a bank select and name # the signals gated_*. if self.num_banks > 1: for port in self.all_ports: - self.add_pin("bank_sel{}".format(port),"INPUT") + self.add_pin("bank_sel{}".format(port), "INPUT") for port in self.read_ports: self.add_pin("s_en{0}".format(port), "INPUT") for port in self.all_ports: @@ -102,12 +100,11 @@ class bank(design.design): for port in self.write_ports: self.add_pin("w_en{0}".format(port), "INPUT") for bit in range(self.num_wmasks): - self.add_pin("bank_wmask{0}_{1}".format(port,bit),"INPUT") + self.add_pin("bank_wmask{0}_{1}".format(port, bit), "INPUT") for port in self.all_ports: self.add_pin("wl_en{0}".format(port), "INPUT") - self.add_pin("vdd","POWER") - self.add_pin("gnd","GROUND") - + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def route_layout(self): """ Create routing amoung the modules """ @@ -124,7 +121,7 @@ class bank(design.design): self.route_supplies() - def route_rbl(self,port): + def route_rbl(self, port): """ Route the rbl_bl and rbl_wl """ bl_pin_name = self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) @@ -135,8 +132,6 @@ class bank(design.design): height=bl_pin.height(), width=bl_pin.width()) - - def route_bitlines(self, port): """ Route the bitlines depending on the port type rw, w, or r. """ @@ -146,7 +141,6 @@ class bank(design.design): self.route_port_data_out(port) self.route_port_data_to_bitcell_array(port) - def create_instances(self): """ Create the instances of the netlist. """ @@ -161,19 +155,18 @@ class bank(design.design): Compute the empty instance offsets for port0 and port1 (if needed) """ - self.port_data_offsets = [None]*len(self.all_ports) - self.port_address_offsets = [None]*len(self.all_ports) - - self.column_decoder_offsets = [None]*len(self.all_ports) - self.bank_select_offsets = [None]*len(self.all_ports) + self.port_data_offsets = [None] * len(self.all_ports) + self.port_address_offsets = [None] * len(self.all_ports) + self.column_decoder_offsets = [None] * len(self.all_ports) + self.bank_select_offsets = [None] * len(self.all_ports) # The center point for these cells are the upper-right corner of # the bitcell array. # The port address decoder/driver logic is placed on the right and mirrored on Y-axis. # The port data write/sense/precharge/mux is placed on the top and mirrored on the X-axis. - self.bitcell_array_top = self.bitcell_array.height - self.bitcell_array_right = self.bitcell_array.width + self.bitcell_array_top = self.bitcell_array.height + self.bitcell_array_right = self.bitcell_array.width # These are the offsets of the main array (excluding dummy and replica rows/cols) self.main_bitcell_array_top = self.bitcell_array.bitcell_array_inst.uy() @@ -185,7 +178,6 @@ class bank(design.design): self.compute_instance_port0_offsets() if len(self.all_ports)==2: self.compute_instance_port1_offsets() - def compute_instance_port0_offsets(self): """ @@ -196,29 +188,30 @@ class bank(design.design): # UPPER RIGHT QUADRANT # Bitcell array is placed at (0,0) - self.bitcell_array_offset = vector(0,0) + self.bitcell_array_offset = vector(0, 0) # LOWER RIGHT QUADRANT # Below the bitcell array - self.port_data_offsets[port] = vector(self.main_bitcell_array_left - self.bitcell_array.cell.width,0) + self.port_data_offsets[port] = vector(self.main_bitcell_array_left - self.bitcell_array.cell.width, 0) # UPPER LEFT QUADRANT # To the left of the bitcell array - x_offset = self.m2_gap + self.port_address.width - self.port_address_offsets[port] = vector(-x_offset,self.main_bitcell_array_bottom) + x_offset = self.m2_gap + self.port_address.width + self.port_address_offsets[port] = vector(-x_offset, + self.main_bitcell_array_bottom) # LOWER LEFT QUADRANT - # Place the col decoder left aligned with wordline driver + # Place the col decoder left aligned with wordline driver # This is also placed so that it's supply rails do not align with the SRAM-level # control logic to allow control signals to easily pass over in M3 # by placing 1/2 a cell pitch down x_offset = self.central_bus_width[port] + self.port_address.wordline_driver.width if self.col_addr_size > 0: x_offset += self.column_decoder.width + self.col_addr_bus_width - y_offset = 0.5*self.dff.height + self.column_decoder.height + y_offset = 0.5 * self.dff.height + self.column_decoder.height else: y_offset = 0 - self.column_decoder_offsets[port] = vector(-x_offset,-y_offset) + self.column_decoder_offsets[port] = vector(-x_offset, -y_offset) # Bank select gets placed below the column decoder (x_offset doesn't change) if self.col_addr_size > 0: @@ -227,7 +220,7 @@ class bank(design.design): y_offset = self.port_address_offsets[port].y if self.num_banks > 1: y_offset += self.bank_select.height + drc("well_to_well") - self.bank_select_offsets[port] = vector(-x_offset,-y_offset) + self.bank_select_offsets[port] = vector(-x_offset, -y_offset) def compute_instance_port1_offsets(self): """ @@ -246,18 +239,19 @@ class bank(design.design): # LOWER RIGHT QUADRANT # To the left of the bitcell array x_offset = self.bitcell_array_right + self.port_address.width + self.m2_gap - self.port_address_offsets[port] = vector(x_offset,self.main_bitcell_array_bottom) + self.port_address_offsets[port] = vector(x_offset, + self.main_bitcell_array_bottom) # UPPER RIGHT QUADRANT - # Place the col decoder right aligned with wordline driver + # Place the col decoder right aligned with wordline driver # Above the bitcell array with a well spacing - x_offset = self.bitcell_array_right + self.central_bus_width[port] + self.port_address.wordline_driver.width + x_offset = self.bitcell_array_right + self.central_bus_width[port] + self.port_address.wordline_driver.width if self.col_addr_size > 0: x_offset += self.column_decoder.width + self.col_addr_bus_width - y_offset = self.bitcell_array_top + 0.5*self.dff.height + self.column_decoder.height + y_offset = self.bitcell_array_top + 0.5 * self.dff.height + self.column_decoder.height else: y_offset = self.bitcell_array_top - self.column_decoder_offsets[port] = vector(x_offset,y_offset) + self.column_decoder_offsets[port] = vector(x_offset, y_offset) # Bank select gets placed above the column decoder (x_offset doesn't change) if self.col_addr_size > 0: @@ -265,7 +259,7 @@ class bank(design.design): self.port_data[port].column_mux_offset.y + self.port_data[port].column_mux_array.height) else: y_offset = self.port_address_offsets[port].y - self.bank_select_offsets[port] = vector(x_offset,y_offset) + self.bank_select_offsets[port] = vector(x_offset, y_offset) def place_instances(self): """ Place the instances. """ @@ -281,19 +275,20 @@ class bank(design.design): self.place_column_decoder(self.column_decoder_offsets) self.place_bank_select(self.bank_select_offsets) - def compute_sizes(self): """ Computes the required sizes to create the bank """ - self.num_cols = int(self.words_per_row*self.word_size) + self.num_cols = int(self.words_per_row * self.word_size) self.num_rows = int(self.num_words / self.words_per_row) self.row_addr_size = int(log(self.num_rows, 2)) self.col_addr_size = int(log(self.words_per_row, 2)) self.addr_size = self.col_addr_size + self.row_addr_size - debug.check(self.num_rows*self.num_cols==self.word_size*self.num_words,"Invalid bank sizes.") - debug.check(self.addr_size==self.col_addr_size + self.row_addr_size,"Invalid address break down.") + debug.check(self.num_rows * self.num_cols==self.word_size * self.num_words, + "Invalid bank sizes.") + debug.check(self.addr_size==self.col_addr_size + self.row_addr_size, + "Invalid address break down.") # The order of the control signals on the control bus: self.input_control_signals = [] @@ -312,13 +307,13 @@ class bank(design.design): self.num_control_lines = [len(x) for x in self.input_control_signals] # The width of this bus is needed to place other modules (e.g. decoder) for each port - self.central_bus_width = [self.m2_pitch*x + self.m2_width for x in self.num_control_lines] + self.central_bus_width = [self.m2_pitch * x + self.m2_width for x in self.num_control_lines] # These will be outputs of the gaters if this is multibank, if not, normal signals. self.control_signals = [] for port in self.all_ports: if self.num_banks > 1: - self.control_signals.append(["gated_"+str for str in self.input_control_signals[port]]) + self.control_signals.append(["gated_" + str for str in self.input_control_signals[port]]) else: self.control_signals.append(self.input_control_signals[port]) @@ -326,19 +321,18 @@ class bank(design.design): if self.col_addr_size>0: self.num_col_addr_lines = 2**self.col_addr_size else: - self.num_col_addr_lines = 0 - self.col_addr_bus_width = self.m2_pitch*self.num_col_addr_lines + self.num_col_addr_lines = 0 + self.col_addr_bus_width = self.m2_pitch * self.num_col_addr_lines # A space for wells or jogging m2 - self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"), - 3*self.m2_pitch) - + self.m2_gap = max(2 * drc("pwell_to_nwell") + drc("nwell_enclose_active"), + 3 * self.m2_pitch) def add_modules(self): """ Add all the modules using the class loader """ # create arrays of bitline and bitline_bar names for read, write, or all ports - self.bitcell = factory.create(module_type="bitcell") + self.bitcell = factory.create(module_type="bitcell") self.bl_names = self.bitcell.get_all_bl_names() self.br_names = self.bitcell.get_all_br_names() self.wl_names = self.bitcell.get_all_wl_names() @@ -352,13 +346,11 @@ class bank(design.design): self.port_data.append(temp_pre) self.add_mod(self.port_data[port]) - self.port_address = factory.create(module_type="port_address", cols=self.num_cols, rows=self.num_rows) self.add_mod(self.port_address) - self.port_rbl_map = self.all_ports self.num_rbl = len(self.all_ports) @@ -370,22 +362,20 @@ class bank(design.design): bitcell_ports=self.all_ports) self.add_mod(self.bitcell_array) - if(self.num_banks > 1): self.bank_select = factory.create(module_type="bank_select") self.add_mod(self.bank_select) - def create_bitcell_array(self): """ Creating Bitcell Array """ - self.bitcell_array_inst=self.add_inst(name="replica_bitcell_array", + self.bitcell_array_inst=self.add_inst(name="replica_bitcell_array", mod=self.bitcell_array) temp = [] for col in range(self.num_cols): for bitline in self.bitline_names: - temp.append("{0}_{1}".format(bitline,col)) + temp.append("{0}_{1}".format(bitline, col)) for rbl in range(self.num_rbl): rbl_bl_name=self.bitcell_array.get_rbl_bl_name(rbl) temp.append(rbl_bl_name) @@ -393,23 +383,21 @@ class bank(design.design): temp.append(rbl_br_name) for row in range(self.num_rows): for wordline in self.wl_names: - temp.append("{0}_{1}".format(wordline,row)) + temp.append("{0}_{1}".format(wordline, row)) for port in self.all_ports: temp.append("wl_en{0}".format(port)) temp.append("vdd") temp.append("gnd") self.connect_inst(temp) - def place_bitcell_array(self, offset): """ Placing Bitcell Array """ self.bitcell_array_inst.place(offset) - def create_port_data(self): """ Creating Port Data """ - self.port_data_inst = [None]*len(self.all_ports) + self.port_data_inst = [None] * len(self.all_ports) for port in self.all_ports: self.port_data_inst[port]=self.add_inst(name="port_data{}".format(port), mod=self.port_data[port]) @@ -419,17 +407,17 @@ class bank(design.design): rbl_br_name=self.bitcell_array.get_rbl_br_name(self.port_rbl_map[port]) temp.append(rbl_bl_name) temp.append(rbl_br_name) - for col in range(self.num_cols): - temp.append("{0}_{1}".format(self.bl_names[port],col)) - temp.append("{0}_{1}".format(self.br_names[port],col)) + for col in range(self.num_cols): + temp.append("{0}_{1}".format(self.bl_names[port], col)) + temp.append("{0}_{1}".format(self.br_names[port], col)) if port in self.read_ports: for bit in range(self.word_size): - temp.append("dout{0}_{1}".format(port,bit)) + temp.append("dout{0}_{1}".format(port, bit)) if port in self.write_ports: for bit in range(self.word_size): - temp.append("din{0}_{1}".format(port,bit)) + temp.append("din{0}_{1}".format(port, bit)) # Will be empty if no col addr lines - sel_names = ["sel{0}_{1}".format(port,x) for x in range(self.num_col_addr_lines)] + sel_names = ["sel{0}_{1}".format(port, x) for x in range(self.num_col_addr_lines)] temp.extend(sel_names) if port in self.read_ports: temp.append("s_en{0}".format(port)) @@ -438,17 +426,16 @@ class bank(design.design): temp.append("w_en{0}".format(port)) for bit in range(self.num_wmasks): temp.append("bank_wmask{0}_{1}".format(port, bit)) - temp.extend(["vdd","gnd"]) + temp.extend(["vdd", "gnd"]) self.connect_inst(temp) - def place_port_data(self, offsets): """ Placing Port Data """ for port in self.all_ports: # Top one is unflipped, bottom is flipped along X direction - if port%2 == 1: + if port % 2 == 1: mirror = "R0" else: mirror = "MX" @@ -457,42 +444,40 @@ class bank(design.design): def create_port_address(self): """ Create the hierarchical row decoder """ - self.port_address_inst = [None]*len(self.all_ports) + self.port_address_inst = [None] * len(self.all_ports) for port in self.all_ports: - self.port_address_inst[port] = self.add_inst(name="port_address{}".format(port), + self.port_address_inst[port] = self.add_inst(name="port_address{}".format(port), mod=self.port_address) temp = [] for bit in range(self.row_addr_size): - temp.append("addr{0}_{1}".format(port,bit+self.col_addr_size)) + temp.append("addr{0}_{1}".format(port, bit + self.col_addr_size)) temp.append("wl_en{0}".format(port)) for row in range(self.num_rows): - temp.append("{0}_{1}".format(self.wl_names[port],row)) + temp.append("{0}_{1}".format(self.wl_names[port], row)) temp.extend(["vdd", "gnd"]) self.connect_inst(temp) - def place_port_address(self, offsets): """ Place the hierarchical row decoder """ debug.check(len(offsets)>=len(self.all_ports), "Insufficient offsets to place row decoder array.") - # The address and control bus will be in between decoder and the main memory array - # This bus will route address bits to the decoder input and column mux inputs. + # The address and control bus will be in between decoder and the main memory array + # This bus will route address bits to the decoder input and column mux inputs. # The wires are actually routed after we placed the stuff on both sides. # The predecoder is below the x-axis and the main decoder is above the x-axis # The address flop and decoder are aligned in the x coord. for port in self.all_ports: - if port%2: + if port % 2: mirror = "MY" else: mirror = "R0" self.port_address_inst[port].place(offset=offsets[port], mirror=mirror) - def create_column_decoder(self): - """ + """ Create a 2:4 or 3:8 column address decoder. """ @@ -510,40 +495,38 @@ class bank(design.design): self.column_decoder = factory.create(module_type="hierarchical_predecode3x8", height=self.dff.height) else: # No error checking before? - debug.error("Invalid column decoder?",-1) + debug.error("Invalid column decoder?", -1) self.add_mod(self.column_decoder) - self.column_decoder_inst = [None]*len(self.all_ports) + self.column_decoder_inst = [None] * len(self.all_ports) for port in self.all_ports: - self.column_decoder_inst[port] = self.add_inst(name="col_address_decoder{}".format(port), + self.column_decoder_inst[port] = self.add_inst(name="col_address_decoder{}".format(port), mod=self.column_decoder) temp = [] for bit in range(self.col_addr_size): - temp.append("addr{0}_{1}".format(port,bit)) + temp.append("addr{0}_{1}".format(port, bit)) for bit in range(self.num_col_addr_lines): - temp.append("sel{0}_{1}".format(port,bit)) + temp.append("sel{0}_{1}".format(port, bit)) temp.extend(["vdd", "gnd"]) self.connect_inst(temp) - def place_column_decoder(self, offsets): - """ + """ Place a 2:4 or 3:8 column address decoder. """ if self.col_addr_size == 0: return - debug.check(len(offsets)>=len(self.all_ports), "Insufficient offsets to place column decoder.") + debug.check(len(offsets)>=len(self.all_ports), + "Insufficient offsets to place column decoder.") for port in self.all_ports: - if port%2 == 1: + if port % 2 == 1: mirror = "XY" else: mirror = "R0" self.column_decoder_inst[port].place(offset=offsets[port], mirror=mirror) - - def create_bank_select(self): """ Create the bank select logic. """ @@ -551,7 +534,7 @@ class bank(design.design): if not self.num_banks > 1: return - self.bank_select_inst = [None]*len(self.all_ports) + self.bank_select_inst = [None] * len(self.all_ports) for port in self.all_ports: self.bank_select_inst[port] = self.add_inst(name="bank_select{}".format(port), mod=self.bank_select) @@ -563,24 +546,23 @@ class bank(design.design): temp.extend(["vdd", "gnd"]) self.connect_inst(temp) - def place_bank_select(self, offsets): """ Place the bank select logic. """ if not self.num_banks > 1: return - debug.check(len(offsets)>=len(self.all_ports), "Insufficient offsets to place bank select logic.") + debug.check(len(offsets)>=len(self.all_ports), + "Insufficient offsets to place bank select logic.") for port in self.all_ports: self.bank_select_inst[port].place(offsets[port]) - def route_supplies(self): """ Propagate all vdd/gnd pins up to this level for all modules """ for inst in self.insts: - self.copy_power_pins(inst,"vdd") - self.copy_power_pins(inst,"gnd") + self.copy_power_pins(inst, "vdd") + self.copy_power_pins(inst, "gnd") def route_bank_select(self, port): """ Route the bank select logic. """ @@ -595,7 +577,7 @@ class bank(design.design): bank_sel_signals = ["clk_buf", "s_en", "p_en_bar", "bank_sel"] gated_bank_sel_signals = ["gated_clk_buf", "gated_s_en", "gated_p_en_bar"] - copy_control_signals = self.input_control_signals[port]+["bank_sel{}".format(port)] + copy_control_signals = self.input_control_signals[port] + ["bank_sel{}".format(port)] for signal in range(len(copy_control_signals)): self.copy_layout_pin(self.bank_select_inst[port], bank_sel_signals[signal], copy_control_signals[signal]) @@ -604,25 +586,24 @@ class bank(design.design): out_pos = self.bank_select_inst[port].get_pin(gated_bank_sel_signals[signal]).rc() name = self.control_signals[port][signal] bus_pos = vector(self.bus_xoffset[port][name].x, out_pos.y) - self.add_path("m3",[out_pos, bus_pos]) + self.add_path("m3", [out_pos, bus_pos]) self.add_via_center(layers=self.m2_stack, offset=bus_pos) self.add_via_center(layers=self.m1_stack, offset=out_pos) self.add_via_center(layers=self.m2_stack, offset=out_pos) - def setup_routing_constraints(self): - """ + """ After the modules are instantiated, find the dimensions for the - control bus, power ring, etc. + control bus, power ring, etc. """ - self.max_y_offset = max([x.uy() for x in self.insts]) + 3*self.m1_width + self.max_y_offset = max([x.uy() for x in self.insts]) + 3 * self.m1_width self.min_y_offset = min([x.by() for x in self.insts]) - self.max_x_offset = max([x.rx() for x in self.insts]) + 3*self.m1_width + self.max_x_offset = max([x.rx() for x in self.insts]) + 3 * self.m1_width self.min_x_offset = min([x.lx() for x in self.insts]) # # Create the core bbox for the power rings @@ -632,7 +613,6 @@ class bank(design.design): self.height = ur.y - ll.y self.width = ur.x - ll.x - def route_central_bus(self): """ Create the address, supply, and control signal central bus lines. """ @@ -640,13 +620,13 @@ class bank(design.design): # Overall central bus width. It includes all the column mux lines, # and control lines. - self.bus_xoffset = [None]*len(self.all_ports) + self.bus_xoffset = [None] * len(self.all_ports) # Port 0 # The bank is at (0,0), so this is to the left of the y-axis. - # 2 pitches on the right for vias/jogs to access the inputs + # 2 pitches on the right for vias/jogs to access the inputs control_bus_offset = vector(-self.m2_pitch * self.num_control_lines[0] - self.m2_pitch, self.min_y_offset) # The control bus is routed up to two pitches below the bitcell array - control_bus_length = self.main_bitcell_array_bottom - self.min_y_offset - 2*self.m1_pitch + control_bus_length = self.main_bitcell_array_bottom - self.min_y_offset - 2 * self.m1_pitch self.bus_xoffset[0] = self.create_bus(layer="m2", pitch=self.m2_pitch, offset=control_bus_offset, @@ -658,7 +638,7 @@ class bank(design.design): # Port 1 if len(self.all_ports)==2: # The other control bus is routed up to two pitches above the bitcell array - control_bus_length = self.max_y_offset - self.main_bitcell_array_top - 2*self.m1_pitch + control_bus_length = self.max_y_offset - self.main_bitcell_array_top - 2 * self.m1_pitch control_bus_offset = vector(self.bitcell_array_right + self.m2_pitch, self.max_y_offset - control_bus_length) # The bus for the right port is reversed so that the rbl_wl is closest to the array @@ -669,7 +649,6 @@ class bank(design.design): length=control_bus_length, vertical=True, make_pins=(self.num_banks==1)) - def route_port_data_to_bitcell_array(self, port): """ Routing of BL and BR between port data and bitcell array """ @@ -677,11 +656,11 @@ class bank(design.design): # Connect the regular bitlines inst2 = self.port_data_inst[port] inst1 = self.bitcell_array_inst - inst1_bl_name = self.bl_names[port]+"_{}" - inst1_br_name = self.br_names[port]+"_{}" + inst1_bl_name = self.bl_names[port] + "_{}" + inst1_br_name = self.br_names[port] + "_{}" - inst2_bl_name = inst2.mod.get_bl_names()+"_{}" - inst2_br_name = inst2.mod.get_br_names()+"_{}" + inst2_bl_name = inst2.mod.get_bl_names() + "_{}" + inst2_br_name = inst2.mod.get_br_names() + "_{}" self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols, inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, @@ -693,20 +672,17 @@ class bank(design.design): self.connect_bitline(inst1, inst2, rbl_bl_name, "rbl_bl") self.connect_bitline(inst1, inst2, rbl_br_name, "rbl_br") - - def route_port_data_out(self, port): """ Add pins for the port data out """ for bit in range(self.word_size): data_pin = self.port_data_inst[port].get_pin("dout_{0}".format(bit)) - self.add_layout_pin_rect_center(text="dout{0}_{1}".format(port,bit), - layer=data_pin.layer, + self.add_layout_pin_rect_center(text="dout{0}_{1}".format(port, bit), + layer=data_pin.layer, offset=data_pin.center(), height=data_pin.height(), width=data_pin.width()) - def route_port_address_in(self, port): """ Routes the row decoder inputs and supplies """ @@ -714,17 +690,15 @@ class bank(design.design): for row in range(self.row_addr_size): addr_idx = row + self.col_addr_size decoder_name = "addr_{}".format(row) - addr_name = "addr{0}_{1}".format(port,addr_idx) + addr_name = "addr{0}_{1}".format(port, addr_idx) self.copy_layout_pin(self.port_address_inst[port], decoder_name, addr_name) - - def route_port_data_in(self, port): """ Connecting port data in """ for row in range(self.word_size): data_name = "din_{}".format(row) - din_name = "din{0}_{1}".format(port,row) + din_name = "din{0}_{1}".format(port, row) self.copy_layout_pin(self.port_data_inst[port], data_name, din_name) if self.word_size: @@ -732,8 +706,6 @@ class bank(design.design): wmask_name = "bank_wmask_{}".format(row) bank_wmask_name = "bank_wmask{0}_{1}".format(port, row) self.copy_layout_pin(self.port_data_inst[port], wmask_name, bank_wmask_name) - - def channel_route_bitlines(self, inst1, inst2, num_bits, inst1_bl_name="bl_{}", inst1_br_name="br_{}", @@ -751,19 +723,18 @@ class bank(design.design): (bottom_inst, bottom_bl_name, bottom_br_name) = (inst2, inst2_bl_name, inst2_br_name) (top_inst, top_bl_name, top_br_name) = (inst1, inst1_bl_name, inst1_br_name) - # Channel route each mux separately since we don't minimize the number # of tracks in teh channel router yet. If we did, we could route all the bits at once! - offset = bottom_inst.ul() + vector(0,self.m1_pitch) + offset = bottom_inst.ul() + vector(0, self.m1_pitch) for bit in range(num_bits): bottom_names = [bottom_inst.get_pin(bottom_bl_name.format(bit)), bottom_inst.get_pin(bottom_br_name.format(bit))] - top_names = [top_inst.get_pin(top_bl_name.format(bit)), top_inst.get_pin(top_br_name.format(bit))] + top_names = [top_inst.get_pin(top_bl_name.format(bit)), top_inst.get_pin(top_br_name.format(bit))] route_map = list(zip(bottom_names, top_names)) self.create_horizontal_channel_route(route_map, offset, self.m1_stack) def connect_bitline(self, inst1, inst2, inst1_name, inst2_name): """ - Connect two pins of two modules. + Connect two pins of two modules. This assumes that they have sufficient space to create a jog in the middle between the two modules (if needed). """ @@ -784,11 +755,13 @@ class bank(design.design): bottom_loc = bottom_pin.uc() top_loc = top_pin.bc() - yoffset = 0.5*(top_loc.y+bottom_loc.y) - self.add_path(top_pin.layer,[bottom_loc, vector(bottom_loc.x,yoffset), - vector(top_loc.x,yoffset), top_loc]) + yoffset = 0.5 * (top_loc.y + bottom_loc.y) + self.add_path(top_pin.layer, + [bottom_loc, + vector(bottom_loc.x, yoffset), + vector(top_loc.x, yoffset), + top_loc]) - def connect_bitlines(self, inst1, inst2, num_bits, inst1_bl_name, inst1_br_name, inst2_bl_name, inst2_br_name): @@ -799,14 +772,13 @@ class bank(design.design): for col in range(num_bits): self.connect_bitline(inst1, inst2, inst1_bl_name.format(col), inst2_bl_name.format(col)) self.connect_bitline(inst1, inst2, inst1_br_name.format(col), inst2_br_name.format(col)) - def route_port_address(self, port): """ Connect Wordline driver to bitcell array wordline """ self.route_port_address_in(port) - if port%2: + if port % 2: self.route_port_address_right(port) else: self.route_port_address_left(port) @@ -817,21 +789,20 @@ class bank(design.design): for row in range(self.num_rows): # The mid guarantees we exit the input cell to the right. driver_wl_pos = self.port_address_inst[port].get_pin("wl_{}".format(row)).rc() - bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port]+"_{}".format(row)).lc() - mid1 = driver_wl_pos.scale(0,1) + vector(0.5*self.port_address_inst[port].rx() + 0.5*self.bitcell_array_inst.lx(),0) - mid2 = mid1.scale(1,0)+bitcell_wl_pos.scale(0.5,1) + bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port] + "_{}".format(row)).lc() + mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].rx() + 0.5 * self.bitcell_array_inst.lx(), 0) + mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0.5, 1) self.add_path("m1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) - def route_port_address_right(self, port): """ Connecting Wordline driver output to Bitcell WL connection """ for row in range(self.num_rows): # The mid guarantees we exit the input cell to the right. driver_wl_pos = self.port_address_inst[port].get_pin("wl_{}".format(row)).lc() - bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port]+"_{}".format(row)).rc() - mid1 = driver_wl_pos.scale(0,1) + vector(0.5*self.port_address_inst[port].lx() + 0.5*self.bitcell_array_inst.rx(),0) - mid2 = mid1.scale(1,0)+bitcell_wl_pos.scale(0,1) + bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port] + "_{}".format(row)).rc() + mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].lx() + 0.5 * self.bitcell_array_inst.rx(), 0) + mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0, 1) self.add_path("m1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) def route_column_address_lines(self, port): @@ -845,7 +816,7 @@ class bank(design.design): decode_names = ["Zb", "Z"] # The Address LSB - self.copy_layout_pin(self.column_decoder_inst[port], "A", "addr{}_0".format(port)) + self.copy_layout_pin(self.column_decoder_inst[port], "A", "addr{}_0".format(port)) elif self.col_addr_size > 1: decode_names = [] @@ -854,11 +825,11 @@ class bank(design.design): for i in range(self.col_addr_size): decoder_name = "in_{}".format(i) - addr_name = "addr{0}_{1}".format(port,i) + addr_name = "addr{0}_{1}".format(port, i) self.copy_layout_pin(self.column_decoder_inst[port], decoder_name, addr_name) - if port%2: - offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines*self.m2_pitch, 0) + if port % 2: + offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines * self.m2_pitch, 0) else: offset = self.column_decoder_inst[port].lr() + vector(self.m2_pitch, 0) @@ -871,7 +842,8 @@ class bank(design.design): self.create_vertical_channel_route(route_map, offset, self.m1_stack) def add_lvs_correspondence_points(self): - """ This adds some points for easier debugging if LVS goes wrong. + """ + This adds some points for easier debugging if LVS goes wrong. These should probably be turned off by default though, since extraction will show these as ports in the extracted netlist. """ @@ -880,7 +852,7 @@ class bank(design.design): wl_name = "wl_{}".format(i) wl_pin = self.bitcell_array_inst.get_pin(wl_name) self.add_label(text=wl_name, - layer="m1", + layer="m1", offset=wl_pin.center()) # Add the bitline names @@ -890,35 +862,35 @@ class bank(design.design): bl_pin = self.bitcell_array_inst.get_pin(bl_name) br_pin = self.bitcell_array_inst.get_pin(br_name) self.add_label(text=bl_name, - layer="m2", + layer="m2", offset=bl_pin.center()) self.add_label(text=br_name, - layer="m2", + layer="m2", offset=br_pin.center()) - # # Add the data output names to the sense amp output + # # Add the data output names to the sense amp output # for i in range(self.word_size): # data_name = "data_{}".format(i) # data_pin = self.sense_amp_array_inst.get_pin(data_name) # self.add_label(text="sa_out_{}".format(i), - # layer="m2", + # layer="m2", # offset=data_pin.center()) # Add labels on the decoder for port in self.write_ports: for i in range(self.word_size): data_name = "dec_out_{}".format(i) - pin_name = "in_{}".format(i) + pin_name = "in_{}".format(i) data_pin = self.wordline_driver_inst[port].get_pin(pin_name) self.add_label(text=data_name, - layer="m1", + layer="m1", offset=data_pin.center()) def route_control_lines(self, port): """ Route the control lines of the entire bank """ # Make a list of tuples that we will connect. - # From control signal to the module pin + # From control signal to the module pin # Connection from the central bus to the main control block crosses # pre-decoder and this connection is in metal3 connection = [] @@ -943,58 +915,59 @@ class bank(design.design): for (control_signal, pin_pos) in connection: control_mid_pos = self.bus_xoffset[port][control_signal] - control_pos = vector(self.bus_xoffset[port][control_signal].x ,pin_pos.y) + control_pos = vector(self.bus_xoffset[port][control_signal].x, pin_pos.y) self.add_wire(self.m1_stack, [control_mid_pos, control_pos, pin_pos]) self.add_via_center(layers=self.m1_stack, offset=control_pos) - # clk to wordline_driver - control_signal = self.prefix+"wl_en{}".format(port) - if port%2: + control_signal = self.prefix + "wl_en{}".format(port) + if port % 2: pin_pos = self.port_address_inst[port].get_pin("wl_en").uc() - mid_pos = pin_pos + vector(0,2*self.m2_gap) # to route down to the top of the bus + mid_pos = pin_pos + vector(0, 2 * self.m2_gap) # to route down to the top of the bus else: pin_pos = self.port_address_inst[port].get_pin("wl_en").bc() - mid_pos = pin_pos - vector(0,2*self.m2_gap) # to route down to the top of the bus + mid_pos = pin_pos - vector(0, 2 * self.m2_gap) # to route down to the top of the bus control_x_offset = self.bus_xoffset[port][control_signal].x control_pos = vector(control_x_offset, mid_pos.y) - self.add_wire(self.m1_stack,[pin_pos, mid_pos, control_pos]) + self.add_wire(self.m1_stack, [pin_pos, mid_pos, control_pos]) self.add_via_center(layers=self.m1_stack, offset=control_pos) def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): """Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline""" - #Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption + # Decoder is assumed to have settled before the negative edge of the clock. + # Delay model relies on this assumption stage_effort_list = [] wordline_cout = self.bitcell_array.get_wordline_cin() + external_cout - stage_effort_list += self.port_address.wordline_driver.determine_wordline_stage_efforts(wordline_cout,inp_is_rise) + stage_effort_list += self.port_address.wordline_driver.determine_wordline_stage_efforts(wordline_cout, + inp_is_rise) return stage_effort_list def get_wl_en_cin(self): """Get the relative capacitance of all the clk connections in the bank""" - #wl_en only used in the wordline driver. + # wl_en only used in the wordline driver. return self.port_address.wordline_driver.get_wl_en_cin() def get_w_en_cin(self): """Get the relative capacitance of all the clk connections in the bank""" - #wl_en only used in the wordline driver. - port = self.write_ports[0] + # wl_en only used in the wordline driver. + port = self.write_ports[0] return self.port_data[port].write_driver.get_w_en_cin() def get_clk_bar_cin(self): """Get the relative capacitance of all the clk_bar connections in the bank""" - #Current bank only uses clock bar (clk_buf_bar) as an enable for the precharge array. + # Current bank only uses clock bar (clk_buf_bar) as an enable for the precharge array. - #Precharges are the all the same in Mulitport, one is picked + # Precharges are the all the same in Mulitport, one is picked port = self.read_ports[0] return self.port_data[port].precharge_array.get_en_cin() def get_sen_cin(self): """Get the relative capacitance of all the sense amp enable connections in the bank""" - #Current bank only uses sen as an enable for the sense amps. - port = self.read_ports[0] + # Current bank only uses sen as an enable for the sense amps. + port = self.read_ports[0] return self.port_data[port].sense_amp_array.get_en_cin() def graph_exclude_precharge(self): @@ -1005,5 +978,7 @@ class bank(design.design): def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" - return self.bitcell_array_inst.mod.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col) + return self.bitcell_array_inst.mod.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, + row, + col) From 531262970243a7eb165c713960499b628164ddd2 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 5 Mar 2020 12:10:13 -0800 Subject: [PATCH 188/521] Remove jog in precharge. Jog is in port data --- compiler/pgates/precharge.py | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 3f0560f5..56382712 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -228,32 +228,25 @@ class precharge(design.design): layer_width = drc("minwidth_" + self.bitline_layer) layer_space = drc("{0}_to_{0}".format(self.bitline_layer)) - yoffset = self.initial_yoffset - 0.5 * self.m2_pitch # adds the BL self.bl_xoffset = layer_space + 0.5 * layer_width top_pos = vector(self.bl_xoffset, self.height) - mid1_pos = vector(self.bl_xoffset, yoffset) - mid2_pos = vector(self.bitcell_bl_pin.cx(), yoffset) - pin_pos = vector(self.bitcell_bl_pin.cx(), 0) - self.add_path(self.bitline_layer, - [top_pos, mid1_pos, mid2_pos, pin_pos]) + pin_pos = vector(self.bl_xoffset, 0) + self.add_path(self.bitline_layer, [top_pos, pin_pos]) self.bl_pin = self.add_layout_pin_segment_center(text="bl", layer=self.bitline_layer, start=pin_pos, - end=mid2_pos) + end=top_pos) # adds the BR self.br_xoffset = self.width - layer_space - 0.5 * layer_width top_pos = vector(self.br_xoffset, self.height) - mid1_pos = vector(self.br_xoffset, yoffset) - mid2_pos = vector(self.bitcell_br_pin.cx(), yoffset) - pin_pos = vector(self.bitcell_br_pin.cx(), 0) - self.add_path(self.bitline_layer, - [top_pos, mid1_pos, mid2_pos, pin_pos]) + pin_pos = vector(self.br_xoffset, 0) + self.add_path(self.bitline_layer, [top_pos, pin_pos]) self.br_pin = self.add_layout_pin_segment_center(text="br", layer=self.bitline_layer, start=pin_pos, - end=mid2_pos) + end=top_pos) def connect_to_bitlines(self): """ From 5b2365336989c2c7fd78a79a7d5da71e5c5b250a Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 5 Mar 2020 16:13:49 -0800 Subject: [PATCH 189/521] PEP8 Formatting --- compiler/sram/sram_1bank.py | 147 +++++++++++++++++++----------------- 1 file changed, 78 insertions(+), 69 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 2f37d927..ae16b6bd 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -19,9 +19,9 @@ class sram_1bank(sram_base): sram_base.__init__(self, name, sram_config) def create_modules(self): - """ + """ This adds the modules for a single bank SRAM with control - logic. + logic. """ self.bank_inst=self.create_bank(0) @@ -40,7 +40,7 @@ class sram_1bank(sram_base): self.data_dff_insts = self.create_data_dff() def place_instances(self): - """ + """ This places the instances for a single bank SRAM with control logic and up to 2 ports. """ @@ -53,19 +53,19 @@ class sram_1bank(sram_base): # the sense amps/column mux and cell array) # The x-coordinate is placed to allow a single clock wire (plus an extra pitch) # up to the row address DFFs. - control_pos = [None]*len(self.all_ports) - row_addr_pos = [None]*len(self.all_ports) - col_addr_pos = [None]*len(self.all_ports) - wmask_pos = [None]*len(self.all_ports) - data_pos = [None]*len(self.all_ports) + control_pos = [None] * len(self.all_ports) + row_addr_pos = [None] * len(self.all_ports) + col_addr_pos = [None] * len(self.all_ports) + wmask_pos = [None] * len(self.all_ports) + data_pos = [None] * len(self.all_ports) if self.write_size: - max_gap_size = self.m3_pitch*self.word_size + 2*self.m1_pitch - max_gap_size_wmask = self.m2_pitch*max(self.num_wmasks+1,self.col_addr_size+1) + 2*self.m1_pitch + max_gap_size = self.m3_pitch * self.word_size + 2 * self.m1_pitch + max_gap_size_wmask = self.m2_pitch * max(self.num_wmasks + 1, self.col_addr_size + 1) + 2 * self.m1_pitch else: # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk # The M1 pitch is for supply rail spacings - max_gap_size = self.m2_pitch*max(self.word_size+1,self.col_addr_size+1) + 2*self.m1_pitch + max_gap_size = self.m2_pitch * max(self.word_size + 1,self.col_addr_size + 1) + 2 * self.m1_pitch # Port 0 port = 0 @@ -79,7 +79,7 @@ class sram_1bank(sram_base): # Add the data flops below the write mask flops. data_pos[port] = vector(self.bank.bank_array_ll.x, - -max_gap_size - max_gap_size_wmask - 2*self.dff.height) + -max_gap_size - max_gap_size_wmask - 2 * self.dff.height) self.data_dff_insts[port].place(data_pos[port]) else: # Add the data flops below the bank to the right of the lower-left of bank array @@ -93,8 +93,7 @@ class sram_1bank(sram_base): self.data_dff_insts[port].place(data_pos[port]) else: wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0) - data_pos[port] = vector(self.bank.bank_array_ll.x,0) - + data_pos[port] = vector(self.bank.bank_array_ll.x, 0) # Add the col address flops below the bank to the left of the lower-left of bank array if self.col_addr_dff: @@ -106,11 +105,11 @@ class sram_1bank(sram_base): -max_gap_size - self.col_addr_dff_insts[port].height) self.col_addr_dff_insts[port].place(col_addr_pos[port]) else: - col_addr_pos[port] = vector(self.bank.bank_array_ll.x,0) + col_addr_pos[port] = vector(self.bank.bank_array_ll.x, 0) # This includes 2 M2 pitches for the row addr clock line. - control_pos[port] = vector(-self.control_logic_insts[port].width - 2*self.m2_pitch, - self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y - 2*self.bank.m2_gap ) + control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch, + self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y - 2 * self.bank.m2_gap) self.control_logic_insts[port].place(control_pos[port]) # The row address bits are placed above the control logic aligned on the right. @@ -133,7 +132,7 @@ class sram_1bank(sram_base): # Add the data flops below the write mask flops data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.height + max_gap_size_wmask + max_gap_size + 2*self.dff.height) + self.bank.height + max_gap_size_wmask + max_gap_size + 2 * self.dff.height) self.data_dff_insts[port].place(data_pos[port], mirror="MX") else: # Add the data flops above the bank to the left of the upper-right of bank array @@ -158,11 +157,10 @@ class sram_1bank(sram_base): col_addr_pos[port] = self.bank_inst.ur() # This includes 2 M2 pitches for the row addr clock line - control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2*self.m2_pitch, - self.bank.bank_array_ur.y + self.control_logic_insts[port].height - + control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2 * self.m2_pitch, + self.bank.bank_array_ur.y + self.control_logic_insts[port].height - \ (self.control_logic_insts[port].height - self.control_logic_insts[port].mod.control_logic_center.y) - + 2*self.bank.m2_gap) - #import pdb; pdb.set_trace() + + 2 * self.bank.m2_gap) self.control_logic_insts[port].place(control_pos[port], mirror="XY") # The row address bits are placed above the control logic aligned on the left. @@ -172,7 +170,6 @@ class sram_1bank(sram_base): row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY") - def add_layout_pins(self): """ Add the top-level pins for a single bank SRAM with control. @@ -180,28 +177,39 @@ class sram_1bank(sram_base): for port in self.all_ports: # Connect the control pins as inputs for signal in self.control_logic_inputs[port] + ["clk"]: - self.copy_layout_pin(self.control_logic_insts[port], signal, signal+"{}".format(port)) + self.copy_layout_pin(self.control_logic_insts[port], + signal, + signal + "{}".format(port)) if port in self.read_ports: for bit in range(self.word_size): - self.copy_layout_pin(self.bank_inst, "dout{0}_{1}".format(port,bit), "dout{0}[{1}]".format(port,bit)) + self.copy_layout_pin(self.bank_inst, + "dout{0}_{1}".format(port, bit), + "dout{0}[{1}]".format(port, bit)) # Lower address bits for bit in range(self.col_addr_size): - self.copy_layout_pin(self.col_addr_dff_insts[port], "din_{}".format(bit),"addr{0}[{1}]".format(port,bit)) + self.copy_layout_pin(self.col_addr_dff_insts[port], + "din_{}".format(bit), + "addr{0}[{1}]".format(port, bit)) # Upper address bits for bit in range(self.row_addr_size): - self.copy_layout_pin(self.row_addr_dff_insts[port], "din_{}".format(bit),"addr{0}[{1}]".format(port,bit+self.col_addr_size)) + self.copy_layout_pin(self.row_addr_dff_insts[port], + "din_{}".format(bit), + "addr{0}[{1}]".format(port, bit + self.col_addr_size)) if port in self.write_ports: for bit in range(self.word_size): - self.copy_layout_pin(self.data_dff_insts[port], "din_{}".format(bit), "din{0}[{1}]".format(port,bit)) + self.copy_layout_pin(self.data_dff_insts[port], + "din_{}".format(bit), + "din{0}[{1}]".format(port, bit)) if self.write_size: for bit in range(self.num_wmasks): - self.copy_layout_pin(self.wmask_dff_insts[port], "din_{}".format(bit), "wmask{0}[{1}]".format(port,bit)) + self.copy_layout_pin(self.wmask_dff_insts[port], + "din_{}".format(bit), + "wmask{0}[{1}]".format(port, bit)) - def route_layout(self): """ Route a single bank SRAM """ @@ -255,13 +263,15 @@ class sram_1bank(sram_base): offset=clk_steiner_pos) # Note, the via to the control logic is taken care of above - self.add_wire(("m3","via2","m2"),[row_addr_clk_pos, mid1_pos, clk_steiner_pos]) + self.add_wire(("m3", "via2", "m2"), + [row_addr_clk_pos, mid1_pos, clk_steiner_pos]) if self.col_addr_dff: dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk") dff_clk_pos = dff_clk_pin.center() mid_pos = vector(clk_steiner_pos.x, dff_clk_pos.y) - self.add_wire(("m3","via2","m2"),[dff_clk_pos, mid_pos, clk_steiner_pos]) + self.add_wire(("m3", "via2", "m2"), + [dff_clk_pos, mid_pos, clk_steiner_pos]) if port in self.write_ports: data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk") @@ -269,8 +279,11 @@ class sram_1bank(sram_base): mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y) # In some designs, the steiner via will be too close to the mid_pos via # so make the wire as wide as the contacts - self.add_path("m2",[mid_pos, clk_steiner_pos], width=max(m2_via.width,m2_via.height)) - self.add_wire(("m3","via2","m2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos]) + self.add_path("m2", + [mid_pos, clk_steiner_pos], + width=max(m2_via.width, m2_via.height)) + self.add_wire(("m3", "via2", "m2"), + [data_dff_clk_pos, mid_pos, clk_steiner_pos]) if self.write_size: wmask_dff_clk_pin = self.wmask_dff_insts[port].get_pin("clk") @@ -280,7 +293,6 @@ class sram_1bank(sram_base): # so make the wire as wide as the contacts self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height)) self.add_wire(("m3", "via2", "m2"), [wmask_dff_clk_pos, mid_pos, clk_steiner_pos]) - def route_control_logic(self): """ Route the control logic pins that are not inputs """ @@ -291,28 +303,28 @@ class sram_1bank(sram_base): if "clk" in signal: continue src_pin = self.control_logic_insts[port].get_pin(signal) - dest_pin = self.bank_inst.get_pin(signal+"{}".format(port)) + dest_pin = self.bank_inst.get_pin(signal + "{}".format(port)) self.connect_vbus_m2m3(src_pin, dest_pin) for port in self.all_ports: # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") - dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) + dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) self.connect_vbus_m2m3(src_pin, dest_pin) - def route_row_addr_dff(self): """ Connect the output of the row flops to the bank pins """ for port in self.all_ports: for bit in range(self.row_addr_size): flop_name = "dout_{}".format(bit) - bank_name = "addr{0}_{1}".format(port,bit+self.col_addr_size) + bank_name = "addr{0}_{1}".format(port, bit + self.col_addr_size) flop_pin = self.row_addr_dff_insts[port].get_pin(flop_name) bank_pin = self.bank_inst.get_pin(bank_name) flop_pos = flop_pin.center() bank_pos = bank_pin.center() - mid_pos = vector(bank_pos.x,flop_pos.y) - self.add_wire(("m3","via2","m2"),[flop_pos, mid_pos,bank_pos]) + mid_pos = vector(bank_pos.x, flop_pos.y) + self.add_wire(("m3", "via2", "m2"), + [flop_pos, mid_pos, bank_pos]) self.add_via_center(layers=self.m2_stack, offset=flop_pos) @@ -320,11 +332,11 @@ class sram_1bank(sram_base): """ Connect the output of the col flops to the bank pins """ for port in self.all_ports: if port%2: - offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.col_addr_size+2)*self.m1_pitch) + offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.col_addr_size + 2) * self.m1_pitch) else: - offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) + offset = self.col_addr_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch) - bus_names = ["addr_{}".format(x) for x in range(self.col_addr_size)] + bus_names = ["addr_{}".format(x) for x in range(self.col_addr_size)] col_addr_bus_offsets = self.create_horizontal_bus(layer="m1", pitch=self.m1_pitch, offset=offset, @@ -335,10 +347,9 @@ class sram_1bank(sram_base): data_dff_map = zip(dff_names, bus_names) self.connect_horizontal_bus(data_dff_map, self.col_addr_dff_insts[port], col_addr_bus_offsets) - bank_names = ["addr{0}_{1}".format(port,x) for x in range(self.col_addr_size)] + bank_names = ["addr{0}_{1}".format(port, x) for x in range(self.col_addr_size)] data_bank_map = zip(bank_names, bus_names) self.connect_horizontal_bus(data_bank_map, self.bank_inst, col_addr_bus_offsets) - def route_data_dff(self): """ Connect the output of the data flops to the write driver """ @@ -346,14 +357,14 @@ class sram_1bank(sram_base): for port in self.write_ports: if self.write_size: if port % 2: - offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size + 2)*self.m3_pitch) + offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size + 2) * self.m3_pitch) else: offset = self.data_dff_insts[port].ul() + vector(0, 2 * self.m3_pitch) else: - if port%2: - offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch) + if port % 2: + offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size + 2) * self.m1_pitch) else: - offset = self.data_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) + offset = self.data_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch) dff_names = ["dout_{}".format(x) for x in range(self.word_size)] dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] @@ -362,13 +373,13 @@ class sram_1bank(sram_base): pin_offset = self.data_dff_insts[port].get_pin(x).center() self.add_via_center(layers=self.m1_stack, offset=pin_offset, - directions = ("V", "V")) + directions=("V", "V")) self.add_via_center(layers=self.m2_stack, offset=pin_offset) self.add_via_center(layers=self.m3_stack, offset=pin_offset) - bank_names = ["din{0}_{1}".format(port,x) for x in range(self.word_size)] + bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size)] bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] if self.write_size: for x in bank_names: @@ -397,7 +408,7 @@ class sram_1bank(sram_base): # This is where the channel will start (y-dimension at least) for port in self.write_ports: if port % 2: - offset = self.wmask_dff_insts[port].ll() - vector(0, (self.num_wmasks+2) * self.m1_pitch) + offset = self.wmask_dff_insts[port].ll() - vector(0, (self.num_wmasks + 2) * self.m1_pitch) else: offset = self.wmask_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch) @@ -416,16 +427,14 @@ class sram_1bank(sram_base): self.add_via_center(layers=self.m1_stack, offset=offset_pin) - route_map = list(zip(bank_pins, dff_pins)) self.create_horizontal_channel_route(netlist=route_map, offset=offset, layer_stack=self.m1_stack) - def add_lvs_correspondence_points(self): - """ - This adds some points for easier debugging if LVS goes wrong. + """ + This adds some points for easier debugging if LVS goes wrong. These should probably be turned off by default though, since extraction will show these as ports in the extracted netlist. """ @@ -438,7 +447,7 @@ class sram_1bank(sram_base): def graph_exclude_data_dff(self): """Removes data dff and wmask dff (if applicable) from search graph. """ - #Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay. + # Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay. for inst in self.data_dff_insts: self.graph_inst_exclude.add(inst) if self.write_size: @@ -447,7 +456,7 @@ class sram_1bank(sram_base): def graph_exclude_addr_dff(self): """Removes data dff from search graph. """ - #Address is considered not part of the critical path, subjectively removed + # Address is considered not part of the critical path, subjectively removed for inst in self.row_addr_dff_insts: self.graph_inst_exclude.add(inst) @@ -457,27 +466,27 @@ class sram_1bank(sram_base): def graph_exclude_ctrl_dffs(self): """Exclude dffs for CSB, WEB, etc from graph""" - #Insts located in control logic, exclusion function called here + # Insts located in control logic, exclusion function called here for inst in self.control_logic_insts: inst.mod.graph_exclude_dffs() def get_sen_name(self, sram_name, port=0): """Returns the s_en spice name.""" - #Naming scheme is hardcoded using this function, should be built into the - #graph in someway. + # Naming scheme is hardcoded using this function, should be built into the + # graph in someway. sen_name = "s_en{}".format(port) control_conns = self.get_conns(self.control_logic_insts[port]) - #Sanity checks + # Sanity checks if sen_name not in control_conns: - debug.error("Signal={} not contained in control logic connections={}"\ - .format(sen_name, control_conns)) + debug.error("Signal={} not contained in control logic connections={}".format(sen_name, + control_conns)) if sen_name in self.pins: - debug.error("Internal signal={} contained in port list. Name defined by the parent.") + debug.error("Internal signal={} contained in port list. Name defined by the parent.".format(sen_name)) return "X{}.{}".format(sram_name, sen_name) def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" - #Sanity check in case it was forgotten + # Sanity check in case it was forgotten if inst_name.find('x') != 0: - inst_name = 'x'+inst_name - return self.bank_inst.mod.get_cell_name(inst_name+'.x'+self.bank_inst.name, row, col) + inst_name = 'x' + inst_name + return self.bank_inst.mod.get_cell_name(inst_name + '.x' + self.bank_inst.name, row, col) From 6506622dfb7dde6d300123e5b51cc5866698716d Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 5 Mar 2020 16:20:21 -0800 Subject: [PATCH 190/521] PEP8 Formatting --- compiler/sram/sram.py | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index dfde78f7..0efad5cc 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -5,13 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import sys import datetime -import getpass import debug from globals import OPTS, print_time -from sram_config import sram_config - + + class sram(): """ This is not a design module, but contains an SRAM design instance. @@ -28,7 +26,7 @@ class sram(): from design import design design.name_map=[] - debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size, + debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size, self.num_words, self.num_banks)) start_time = datetime.datetime.now() @@ -40,30 +38,28 @@ class sram(): elif self.num_banks == 2: from sram_2bank import sram_2bank as sram else: - debug.error("Invalid number of banks.",-1) + debug.error("Invalid number of banks.", -1) - self.s = sram(name, sram_config) + self.s = sram(name, sram_config) self.s.create_netlist() if not OPTS.netlist_only: self.s.create_layout() if not OPTS.is_unit_test: print_time("SRAM creation", datetime.datetime.now(), start_time) - - def sp_write(self,name): + def sp_write(self, name): self.s.sp_write(name) - def lef_write(self,name): + def lef_write(self, name): self.s.lef_write(name) - def gds_write(self,name): + def gds_write(self, name): self.s.gds_write(name) - def verilog_write(self,name): + def verilog_write(self, name): self.s.verilog_write(name) - def save(self): """ Save all the output files while reporting time to do it as well. """ @@ -107,7 +103,6 @@ class sram(): debug.print_raw("LIB: Characterizing... ") lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) print_time("Characterization", datetime.datetime.now(), start_time) - # Write the config file start_time = datetime.datetime.now() From 05f9e809b403a363812394bae22f08645e1fcfe2 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 5 Mar 2020 16:27:35 -0800 Subject: [PATCH 191/521] PEP8 Formatting --- compiler/sram/sram_base.py | 150 ++++++++++++++++--------------------- 1 file changed, 66 insertions(+), 84 deletions(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index c7c91e90..d2fbe9fc 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -5,20 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import sys import datetime -import getpass import debug -from datetime import datetime from importlib import reload from vector import vector from globals import OPTS, print_time -import logical_effort from design import design from verilog import verilog from lef import lef from sram_factory import factory -import logical_effort + class sram_base(design, verilog, lef): """ @@ -36,11 +32,11 @@ class sram_base(design, verilog, lef): self.bank_insts = [] if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(self.word_size / self.write_size) else: self.num_wmasks = 0 - #For logical effort delay calculations. + # For logical effort delay calculations. self.all_mods_except_control_done = False def add_pins(self): @@ -48,11 +44,11 @@ class sram_base(design, verilog, lef): for port in self.write_ports: for bit in range(self.word_size): - self.add_pin("din{0}[{1}]".format(port,bit),"INPUT") + self.add_pin("din{0}[{1}]".format(port, bit), "INPUT") for port in self.all_ports: for bit in range(self.addr_size): - self.add_pin("addr{0}[{1}]".format(port,bit),"INPUT") + self.add_pin("addr{0}[{1}]".format(port, bit), "INPUT") # These are used to create the physical pins self.control_logic_inputs = [] @@ -69,22 +65,21 @@ class sram_base(design, verilog, lef): self.control_logic_outputs.append(self.control_logic_r.get_outputs()) for port in self.all_ports: - self.add_pin("csb{}".format(port),"INPUT") + self.add_pin("csb{}".format(port), "INPUT") for port in self.readwrite_ports: - self.add_pin("web{}".format(port),"INPUT") + self.add_pin("web{}".format(port), "INPUT") for port in self.all_ports: - self.add_pin("clk{}".format(port),"INPUT") + self.add_pin("clk{}".format(port), "INPUT") # add the optional write mask pins for port in self.write_ports: for bit in range(self.num_wmasks): - self.add_pin("wmask{0}[{1}]".format(port,bit),"INPUT") + self.add_pin("wmask{0}[{1}]".format(port, bit), "INPUT") for port in self.read_ports: for bit in range(self.word_size): - self.add_pin("dout{0}[{1}]".format(port,bit),"OUTPUT") + self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT") - self.add_pin("vdd","POWER") - self.add_pin("gnd","GROUND") - + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def create_netlist(self): """ Netlist creation """ @@ -100,23 +95,21 @@ class sram_base(design, verilog, lef): self.width=0 self.height=0 - if not OPTS.is_unit_test: - print_time("Submodules",datetime.now(), start_time) - + print_time("Submodules", datetime.now(), start_time) def create_layout(self): - """ Layout creation """ + """ Layout creation """ start_time = datetime.now() self.place_instances() if not OPTS.is_unit_test: - print_time("Placement",datetime.now(), start_time) + print_time("Placement", datetime.now(), start_time) start_time = datetime.now() self.route_layout() self.route_supplies() if not OPTS.is_unit_test: - print_time("Routing",datetime.now(), start_time) + print_time("Routing", datetime.now(), start_time) self.add_lvs_correspondence_points() @@ -130,10 +123,10 @@ class sram_base(design, verilog, lef): # We only enable final verification if we have routed the design self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) if not OPTS.is_unit_test: - print_time("Verification",datetime.now(), start_time) + print_time("Verification", datetime.now(), start_time) def create_modules(self): - debug.error("Must override pure virtual function.",-1) + debug.error("Must override pure virtual function.", -1) def route_supplies(self): """ Route the supply grid and connect the pins to them. """ @@ -141,8 +134,8 @@ class sram_base(design, verilog, lef): # Copy the pins to the top level # This will either be used to route or left unconnected. for inst in self.insts: - self.copy_power_pins(inst,"vdd") - self.copy_power_pins(inst,"gnd") + self.copy_power_pins(inst, "vdd") + self.copy_power_pins(inst, "gnd") import tech if not OPTS.route_supplies: @@ -164,33 +157,31 @@ class sram_base(design, verilog, lef): from supply_grid_router import supply_grid_router as router rtr=router(grid_stack, self) rtr.route() - def compute_bus_sizes(self): """ Compute the independent bus widths shared between two and four bank SRAMs """ # address size + control signals + one-hot bank select signals - self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks,2) + 1 + self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks, 2) + 1 # data bus size self.num_horizontal_line = self.word_size - self.vertical_bus_width = self.m2_pitch*self.num_vertical_line + self.vertical_bus_width = self.m2_pitch * self.num_vertical_line # vertical bus height depends on 2 or 4 banks - self.data_bus_height = self.m3_pitch*self.num_horizontal_line - self.data_bus_width = 2*(self.bank.width + self.bank_to_bus_distance) + self.vertical_bus_width + self.data_bus_height = self.m3_pitch * self.num_horizontal_line + self.data_bus_width = 2 * (self.bank.width + self.bank_to_bus_distance) + self.vertical_bus_width - self.control_bus_height = self.m1_pitch*(self.control_size+2) + self.control_bus_height = self.m1_pitch * (self.control_size + 2) self.control_bus_width = self.bank.width + self.bank_to_bus_distance + self.vertical_bus_width - self.supply_bus_height = self.m1_pitch*2 # 2 for vdd/gnd placed with control bus + self.supply_bus_height = self.m1_pitch * 2 # 2 for vdd/gnd placed with control bus self.supply_bus_width = self.data_bus_width # Sanity check to ensure we can fit the control logic above a single bank (0.9 is a hack really) - debug.check(self.bank.width + self.vertical_bus_width > 0.9*self.control_logic.width, + debug.check(self.bank.width + self.vertical_bus_width > 0.9 * self.control_logic.width, "Bank is too small compared to control logic.") - def add_busses(self): """ Add the horizontal and vertical busses """ # Vertical bus @@ -213,24 +204,22 @@ class sram_base(design, verilog, lef): names=self.control_bus_names[port], length=self.vertical_bus_height) - self.addr_bus_names=["A{0}[{1}]".format(port,i) for i in range(self.addr_size)] + self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.addr_size)] self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2", pitch=self.m2_pitch, offset=self.addr_bus_offset, names=self.addr_bus_names, length=self.addr_bus_height)) - - self.bank_sel_bus_names = ["bank_sel{0}_{1}".format(port,i) for i in range(self.num_banks)] + self.bank_sel_bus_names = ["bank_sel{0}_{1}".format(port, i) for i in range(self.num_banks)] self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2", pitch=self.m2_pitch, offset=self.bank_sel_bus_offset, names=self.bank_sel_bus_names, length=self.vertical_bus_height)) - # Horizontal data bus - self.data_bus_names = ["DATA{0}[{1}]".format(port,i) for i in range(self.word_size)] + self.data_bus_names = ["DATA{0}[{1}]".format(port, i) for i in range(self.word_size)] self.data_bus_positions = self.create_horizontal_pin_bus(layer="m3", pitch=self.m3_pitch, offset=self.data_bus_offset, @@ -249,7 +238,7 @@ class sram_base(design, verilog, lef): # the decoder in 4-bank SRAMs self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1", pitch=self.m1_pitch, - offset=self.supply_bus_offset+vector(0,self.m1_pitch), + offset=self.supply_bus_offset + vector(0, self.m1_pitch), names=["gnd"], length=self.supply_bus_width)) self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1", @@ -258,20 +247,17 @@ class sram_base(design, verilog, lef): names=self.control_bus_names[port], length=self.control_bus_width)) - - def add_multi_bank_modules(self): """ Create the multibank address flops and bank decoder """ from dff_buf_array import dff_buf_array self.msb_address = dff_buf_array(name="msb_address", rows=1, - columns=self.num_banks/2) + columns=self.num_banks / 2) self.add_mod(self.msb_address) if self.num_banks>2: self.msb_decoder = self.bank.decoder.pre2_4 self.add_mod(self.msb_decoder) - def add_modules(self): self.bitcell = factory.create(module_type=OPTS.bitcell) @@ -293,7 +279,6 @@ class sram_base(design, verilog, lef): if self.write_size: self.wmask_dff = factory.create("dff_array", module_name="wmask_dff", rows=1, columns=self.num_wmasks) self.add_mod(self.wmask_dff) - # Create the bank module (up to four are instantiated) self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") @@ -305,7 +290,8 @@ class sram_base(design, verilog, lef): self.bank_count = 0 - #The control logic can resize itself based on the other modules. Requires all other modules added before control logic. + # The control logic can resize itself based on the other modules. + # Requires all other modules added before control logic. self.all_mods_except_control_done = True c = reload(__import__(OPTS.control_logic)) @@ -320,40 +306,40 @@ class sram_base(design, verilog, lef): port_type="rw") self.add_mod(self.control_logic_rw) if len(self.writeonly_ports)>0: - self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows, + self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, sram=self, port_type="w") self.add_mod(self.control_logic_w) if len(self.readonly_ports)>0: - self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, + self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, sram=self, port_type="r") self.add_mod(self.control_logic_r) - def create_bank(self,bank_num): - """ Create a bank """ + def create_bank(self, bank_num): + """ Create a bank """ self.bank_insts.append(self.add_inst(name="bank{0}".format(bank_num), mod=self.bank)) temp = [] for port in self.read_ports: for bit in range(self.word_size): - temp.append("dout{0}[{1}]".format(port,bit)) + temp.append("dout{0}[{1}]".format(port, bit)) for port in self.all_ports: temp.append("rbl_bl{0}".format(port)) for port in self.write_ports: for bit in range(self.word_size): - temp.append("bank_din{0}[{1}]".format(port,bit)) + temp.append("bank_din{0}[{1}]".format(port, bit)) for port in self.all_ports: for bit in range(self.bank_addr_size): - temp.append("a{0}[{1}]".format(port,bit)) + temp.append("a{0}[{1}]".format(port, bit)) if(self.num_banks > 1): for port in self.all_ports: - temp.append("bank_sel{0}[{1}]".format(port,bank_num)) + temp.append("bank_sel{0}[{1}]".format(port, bank_num)) for port in self.read_ports: temp.append("s_en{0}".format(port)) for port in self.all_ports: @@ -369,7 +355,6 @@ class sram_base(design, verilog, lef): return self.bank_insts[-1] - def place_bank(self, bank_inst, position, x_flip, y_flip): """ Place a bank at the given position with orientations """ @@ -400,7 +385,6 @@ class sram_base(design, verilog, lef): return bank_inst - def create_row_addr_dff(self): """ Add all address flops for the main decoder """ insts = [] @@ -412,13 +396,12 @@ class sram_base(design, verilog, lef): inputs = [] outputs = [] for bit in range(self.row_addr_size): - inputs.append("addr{}[{}]".format(port,bit+self.col_addr_size)) - outputs.append("a{}[{}]".format(port,bit+self.col_addr_size)) + inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size)) + outputs.append("a{}[{}]".format(port, bit + self.col_addr_size)) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) return insts - def create_col_addr_dff(self): """ Add and place all address flops for the column decoder """ @@ -431,14 +414,13 @@ class sram_base(design, verilog, lef): inputs = [] outputs = [] for bit in range(self.col_addr_size): - inputs.append("addr{}[{}]".format(port,bit)) - outputs.append("a{}[{}]".format(port,bit)) + inputs.append("addr{}[{}]".format(port, bit)) + outputs.append("a{}[{}]".format(port, bit)) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) return insts - def create_data_dff(self): """ Add and place all data flops """ insts = [] @@ -454,8 +436,8 @@ class sram_base(design, verilog, lef): inputs = [] outputs = [] for bit in range(self.word_size): - inputs.append("din{}[{}]".format(port,bit)) - outputs.append("bank_din{}[{}]".format(port,bit)) + inputs.append("din{}[{}]".format(port, bit)) + outputs.append("bank_din{}[{}]".format(port, bit)) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) @@ -483,7 +465,6 @@ class sram_base(design, verilog, lef): return insts - def create_control_logic(self): """ Add control logic instances """ @@ -516,12 +497,13 @@ class sram_base(design, verilog, lef): return insts - def connect_vbus_m2m3(self, src_pin, dest_pin): - """ Helper routine to connect an instance to a vertical bus. + """ + Helper routine to connect an instance to a vertical bus. Routes horizontal then vertical L shape. Dest pin is assumed to be on M2. - Src pin can be on M1/M2/M3.""" + Src pin can be on M1/M2/M3. + """ if src_pin.cx() Date: Fri, 6 Mar 2020 09:03:52 -0800 Subject: [PATCH 192/521] Route RBL to edge of bank. --- compiler/modules/bank.py | 31 ++++++++++++++++------ compiler/sram/sram_1bank.py | 5 ++-- compiler/sram/sram_base.py | 51 +++++++++++++++++++++++++++++++------ 3 files changed, 69 insertions(+), 18 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 60c84a1e..7ba33230 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -126,11 +126,22 @@ class bank(design.design): bl_pin_name = self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name) - self.add_layout_pin(text="rbl_bl{0}".format(port), - layer=bl_pin.layer, - offset=bl_pin.ll(), - height=bl_pin.height(), - width=bl_pin.width()) + # This will ensure the pin is only on the top or bottom edge + if port % 2: + via_offset = bl_pin.uc() + left_right_offset = vector(self.max_x_offset, via_offset.y) + else: + via_offset = bl_pin.bc() + left_right_offset = vector(self.min_x_offset, via_offset.y) + if bl_pin == "m1": + self.add_via_center(layers=self.m1_stack, + offset=via_offset) + self.add_via_center(layers=self.m2_stack, + offset=via_offset) + self.add_layout_pin_segment_center(text="rbl_bl{0}".format(port), + layer="m3", + start=left_right_offset, + end=via_offset) def route_bitlines(self, port): """ Route the bitlines depending on the port type rw, w, or r. """ @@ -662,9 +673,13 @@ class bank(design.design): inst2_bl_name = inst2.mod.get_bl_names() + "_{}" inst2_br_name = inst2.mod.get_br_names() + "_{}" - self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols, - inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, - inst2_bl_name=inst2_bl_name, inst2_br_name=inst2_br_name) + self.connect_bitlines(inst1=inst1, + inst2=inst2, + num_bits=self.num_cols, + inst1_bl_name=inst1_bl_name, + inst1_br_name=inst1_br_name, + inst2_bl_name=inst2_bl_name, + inst2_br_name=inst2_br_name) # Connect the replica bitlines rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index ae16b6bd..76e9f805 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -310,8 +310,9 @@ class sram_1bank(sram_base): # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) - self.connect_vbus_m2m3(src_pin, dest_pin) - + + self.connect_hbus_m2m3(src_pin, dest_pin) + def route_row_addr_dff(self): """ Connect the output of the row flops to the bank pins """ for port in self.all_ports: diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index d2fbe9fc..e8a91486 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -84,7 +84,7 @@ class sram_base(design, verilog, lef): def create_netlist(self): """ Netlist creation """ - start_time = datetime.now() + start_time = datetime.datetime.now() # Must create the control logic before pins to get the pins self.add_modules() @@ -96,20 +96,20 @@ class sram_base(design, verilog, lef): self.height=0 if not OPTS.is_unit_test: - print_time("Submodules", datetime.now(), start_time) + print_time("Submodules", datetime.datetime.now(), start_time) def create_layout(self): """ Layout creation """ - start_time = datetime.now() + start_time = datetime.datetime.now() self.place_instances() if not OPTS.is_unit_test: - print_time("Placement", datetime.now(), start_time) + print_time("Placement", datetime.datetime.now(), start_time) - start_time = datetime.now() + start_time = datetime.datetime.now() self.route_layout() self.route_supplies() if not OPTS.is_unit_test: - print_time("Routing", datetime.now(), start_time) + print_time("Routing", datetime.datetime.now(), start_time) self.add_lvs_correspondence_points() @@ -119,11 +119,11 @@ class sram_base(design, verilog, lef): self.width = highest_coord[0] self.height = highest_coord[1] - start_time = datetime.now() + start_time = datetime.datetime.now() # We only enable final verification if we have routed the design self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) if not OPTS.is_unit_test: - print_time("Verification", datetime.now(), start_time) + print_time("Verification", datetime.datetime.now(), start_time) def create_modules(self): debug.error("Must override pure virtual function.", -1) @@ -526,6 +526,41 @@ class sram_base(design, verilog, lef): self.add_via_center(layers=self.m2_stack, offset=in_pos) + def connect_hbus_m2m3(self, src_pin, dest_pin): + """ + Helper routine to connect an instance to a horizontal bus. + Routes horizontal then vertical L shape. + Dest pin is on M1/M2/M3. + Src pin can be on M1/M2/M3. + """ + + if src_pin.cx() Date: Fri, 6 Mar 2020 09:48:20 -0800 Subject: [PATCH 193/521] Move rbl route away from bitcell array --- compiler/modules/bank.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 7ba33230..5e6ce004 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -128,10 +128,10 @@ class bank(design.design): bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name) # This will ensure the pin is only on the top or bottom edge if port % 2: - via_offset = bl_pin.uc() + via_offset = bl_pin.uc() + vector(0, self.m2_pitch) left_right_offset = vector(self.max_x_offset, via_offset.y) else: - via_offset = bl_pin.bc() + via_offset = bl_pin.bc() - vector(0, self.m2_pitch) left_right_offset = vector(self.min_x_offset, via_offset.y) if bl_pin == "m1": self.add_via_center(layers=self.m1_stack, From 23501c7b352a32b9f87b77d7eda43d92a5c1bc51 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 6 Mar 2020 13:26:40 -0800 Subject: [PATCH 194/521] Convert pnand+pinv to pand in decoders. --- compiler/modules/hierarchical_decoder.py | 163 ++++++----------- compiler/modules/hierarchical_predecode.py | 167 +++++++----------- compiler/modules/hierarchical_predecode2x4.py | 24 ++- compiler/modules/hierarchical_predecode3x8.py | 32 ++-- compiler/pgates/pnand3.py | 6 +- 5 files changed, 143 insertions(+), 249 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index f9c21619..6e98c5e0 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -20,8 +20,7 @@ class hierarchical_decoder(design.design): def __init__(self, name, rows): design.design.__init__(self, name) - self.NAND_FORMAT = "DEC_NAND_{0}" - self.INV_FORMAT = "DEC_INV_{0}" + self.AND_FORMAT = "DEC_AND_{0}" self.pre2x4_inst = [] self.pre3x8_inst = [] @@ -58,12 +57,12 @@ class hierarchical_decoder(design.design): self.inv = factory.create(module_type="pinv", height=self.cell_height) self.add_mod(self.inv) - self.nand2 = factory.create(module_type="pnand2", + self.and2 = factory.create(module_type="pand2", + height=self.cell_height) + self.add_mod(self.and2) + self.and3 = factory.create(module_type="pand3", height=self.cell_height) - self.add_mod(self.nand2) - self.nand3 = factory.create(module_type="pnand3", - height=self.cell_height) - self.add_mod(self.nand3) + self.add_mod(self.and3) self.add_decoders() @@ -143,9 +142,9 @@ class hierarchical_decoder(design.design): # Calculates height and width of row-decoder if (self.num_inputs == 4 or self.num_inputs == 5): - nand_width = self.nand2.width + nand_width = self.and2.width else: - nand_width = self.nand3.width + nand_width = self.and3.width self.internal_routing_width = self.m2_pitch * self.total_number_of_predecoder_outputs self.row_decoder_height = self.inv.height * self.rows @@ -309,33 +308,32 @@ class hierarchical_decoder(design.design): self.pre3x8_inst[num].place(offset) def create_row_decoder(self): - """ Create the row-decoder by placing NAND2/NAND3 and Inverters + """ Create the row-decoder by placing AND2/AND3 and Inverters and add the primary decoder output pins. """ if (self.num_inputs >= 4): - self.create_decoder_nand_array() - self.create_decoder_inv_array() + self.create_decoder_and_array() - def create_decoder_nand_array(self): - """ Add a column of NAND gates for final decode """ + def create_decoder_and_array(self): + """ Add a column of AND gates for final decode """ - self.nand_inst = [] + self.and_inst = [] - # Row Decoder NAND GATE array for address inputs <5. + # Row Decoder AND GATE array for address inputs <5. if (self.num_inputs == 4 or self.num_inputs == 5): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): row = len(self.predec_groups[0]) * j + i if (row < self.rows): - name = self.NAND_FORMAT.format(row) - self.nand_inst.append(self.add_inst(name=name, - mod=self.nand2)) + name = self.AND_FORMAT.format(row) + self.and_inst.append(self.add_inst(name=name, + mod=self.and2)) pins =["out_{0}".format(i), "out_{0}".format(j + len(self.predec_groups[0])), - "Z_{0}".format(row), + "decode_{0}".format(row), "vdd", "gnd"] self.connect_inst(pins) - # Row Decoder NAND GATE array for address inputs >5. + # Row Decoder AND GATE array for address inputs >5. elif (self.num_inputs > 5): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): @@ -344,104 +342,57 @@ class hierarchical_decoder(design.design): + len(self.predec_groups[0]) * j + i if (row < self.rows): - name = self.NAND_FORMAT.format(row) - self.nand_inst.append(self.add_inst(name=name, - mod=self.nand3)) + name = self.AND_FORMAT.format(row) + self.and_inst.append(self.add_inst(name=name, + mod=self.and3)) pins = ["out_{0}".format(i), "out_{0}".format(j + len(self.predec_groups[0])), "out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])), - "Z_{0}".format(row), + "decode_{0}".format(row), "vdd", "gnd"] self.connect_inst(pins) - def create_decoder_inv_array(self): - """ - Add a column of INV gates for the decoder. - """ - - self.inv_inst = [] - for row in range(self.rows): - name = self.INV_FORMAT.format(row) - self.inv_inst.append(self.add_inst(name=name, - mod=self.inv)) - self.connect_inst(args=["Z_{0}".format(row), - "decode_{0}".format(row), - "vdd", "gnd"]) - - def place_decoder_inv_array(self): - """ - Place the column of INV gates for the decoder above the predecoders - and to the right of the NAND decoders. - """ - - if (self.num_inputs == 4 or self.num_inputs == 5): - x_off = self.internal_routing_width + self.nand2.width - else: - x_off = self.internal_routing_width + self.nand3.width - - for row in range(self.rows): - if (row % 2 == 0): - inv_row_height = self.inv.height * row - mirror = "R0" - else: - inv_row_height = self.inv.height * (row + 1) - mirror = "MX" - y_off = inv_row_height - offset = vector(x_off, y_off) - self.inv_inst[row].place(offset=offset, - mirror=mirror) - def place_row_decoder(self): """ - Place the row-decoder by placing NAND2/NAND3 and Inverters + Place the row-decoder by placing AND2/AND3 and Inverters and add the primary decoder output pins. """ if (self.num_inputs >= 4): - self.place_decoder_nand_array() - self.place_decoder_inv_array() + self.place_decoder_and_array() self.route_decoder() - def place_decoder_nand_array(self): - """ Add a column of NAND gates for final decode """ + def place_decoder_and_array(self): + """ Add a column of AND gates for final decode """ - # Row Decoder NAND GATE array for address inputs <5. + # Row Decoder AND GATE array for address inputs <5. if (self.num_inputs == 4 or self.num_inputs == 5): - self.place_nand_array(nand_mod=self.nand2) + self.place_and_array(and_mod=self.and2) - # Row Decoder NAND GATE array for address inputs >5. + # Row Decoder AND GATE array for address inputs >5. # FIXME: why this correct offset?) elif (self.num_inputs > 5): - self.place_nand_array(nand_mod=self.nand3) + self.place_and_array(and_mod=self.and3) - def place_nand_array(self, nand_mod): - """ Add a column of NAND gates for the decoder above the predecoders.""" + def place_and_array(self, and_mod): + """ Add a column of AND gates for the decoder above the predecoders.""" for row in range(self.rows): if ((row % 2) == 0): - y_off = nand_mod.height * row + y_off = and_mod.height * row mirror = "R0" else: - y_off = nand_mod.height * (row + 1) + y_off = and_mod.height * (row + 1) mirror = "MX" - self.nand_inst[row].place(offset=[self.internal_routing_width, y_off], - mirror=mirror) + self.and_inst[row].place(offset=[self.internal_routing_width, y_off], + mirror=mirror) def route_decoder(self): - """ Route the nand to inverter in the decoder and add the pins. """ + """ Add the pins. """ for row in range(self.rows): - - # route nand output to output inv input - zr_pos = self.nand_inst[row].get_pin("Z").rc() - al_pos = self.inv_inst[row].get_pin("A").lc() - # ensure the bend is in the middle - mid1_pos = vector(0.5 * (zr_pos.x + al_pos.x), zr_pos.y) - mid2_pos = vector(0.5 * (zr_pos.x + al_pos.x), al_pos.y) - self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos]) - - z_pin = self.inv_inst[row].get_pin("Z") + z_pin = self.and_inst[row].get_pin("Z") self.add_layout_pin(text="decode_{0}".format(row), layer="m1", offset=z_pin.ll(), @@ -484,12 +435,12 @@ class hierarchical_decoder(design.design): self.route_predecode_rail_m3(predecode_name, pin) def route_rails_to_decoder(self): - """ Use the self.predec_groups to determine the connections to the decoder NAND gates. - Inputs of NAND2/NAND3 gates come from different groups. + """ Use the self.predec_groups to determine the connections to the decoder AND gates. + Inputs of AND2/AND3 gates come from different groups. For example for these groups [ [0,1,2,3] ,[4,5,6,7], - [8,9,10,11,12,13,14,15] ] the first NAND3 inputs are connected to - [0,4,8] and second NAND3 is connected to [0,4,9] ........... and the - 128th NAND3 is connected to [3,7,15] + [8,9,10,11,12,13,14,15] ] the first AND3 inputs are connected to + [0,4,8] and second AND3 is connected to [0,4,9] ........... and the + 128th AND3 is connected to [3,7,15] """ row_index = 0 if (self.num_inputs == 4 or self.num_inputs == 5): @@ -498,9 +449,9 @@ class hierarchical_decoder(design.design): # FIXME: convert to connect_bus? if (row_index < self.rows): predecode_name = "predecode_{}".format(index_A) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A")) - predecode_name = "predecode_{}".format(index_B) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B")) + self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("A")) + predecode_name = "predecode_{}".format(index_B) + self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("B")) row_index = row_index + 1 elif (self.num_inputs > 5): @@ -510,35 +461,25 @@ class hierarchical_decoder(design.design): # FIXME: convert to connect_bus? if (row_index < self.rows): predecode_name = "predecode_{}".format(index_A) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A")) + self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("A")) predecode_name = "predecode_{}".format(index_B) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B")) + self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("B")) predecode_name = "predecode_{}".format(index_C) - self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("C")) + self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("C")) row_index = row_index + 1 def route_vdd_gnd(self): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ # The vias will be placed in the center and right of the cells, respectively. - xoffset = self.nand_inst[0].rx() + xoffset = self.and_inst[0].rx() for num in range(0, self.rows): for pin_name in ["vdd", "gnd"]: # The nand and inv are the same height rows... - supply_pin = self.nand_inst[num].get_pin(pin_name) + supply_pin = self.and_inst[num].get_pin(pin_name) pin_pos = vector(xoffset, supply_pin.cy()) self.add_power_pin(name=pin_name, loc=pin_pos) - - # Make a redundant rail too - for num in range(0, self.rows, 2): - for pin_name in ["vdd", "gnd"]: - start = self.nand_inst[num].get_pin(pin_name).lc() - end = self.inv_inst[num].get_pin(pin_name).rc() - mid = (start + end).scale(0.5, 0.5) - self.add_rect_center(layer="m1", - offset=mid, - width=end.x - start.x) # Copy the pins from the predecoders for pre in self.pre2x4_inst + self.pre3x8_inst: diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 88bae534..ccee34a9 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -32,61 +32,58 @@ class hierarchical_predecode(design.design): self.add_pin("gnd", "GROUND") def add_modules(self): - """ Add the INV and NAND gate modules """ + """ Add the INV and AND gate modules """ self.inv = factory.create(module_type="pinv", height=self.cell_height) self.add_mod(self.inv) - self.add_nand(self.number_of_inputs) - self.add_mod(self.nand) + self.add_and(self.number_of_inputs) + self.add_mod(self.and_mod) - def add_nand(self, inputs): + def add_and(self, inputs): """ Create the NAND for the predecode input stage """ if inputs==2: - self.nand = factory.create(module_type="pnand2", - height=self.cell_height) + self.and_mod = factory.create(module_type="pand2", + height=self.cell_height) elif inputs==3: - self.nand = factory.create(module_type="pnand3", - height=self.cell_height) + self.and_mod = factory.create(module_type="pand3", + height=self.cell_height) else: debug.error("Invalid number of predecode inputs: {}".format(inputs), -1) def setup_layout_constraints(self): - self.height = self.number_of_outputs * self.nand.height + self.height = self.number_of_outputs * self.and_mod.height # x offset for input inverters self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch - # x offset to NAND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches - self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch + # x offset to AND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches + self.x_off_and = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch # x offset to output inverters - self.x_off_inv_2 = self.x_off_nand + self.nand.width - - # Height width are computed - self.width = self.x_off_inv_2 + self.inv.width + self.width = self.x_off_and + self.and_mod.width def route_rails(self): """ Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """ input_names = ["in_{}".format(x) for x in range(self.number_of_inputs)] - offset = vector(0.5*self.m2_width,2*self.m1_width) + offset = vector(0.5 * self.m2_width, self.m1_pitch) self.input_rails = self.create_vertical_pin_bus(layer="m2", pitch=self.m2_pitch, offset=offset, names=input_names, - length=self.height - 2*self.m1_width) + length=self.height - 2 * self.m1_pitch) invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)] non_invert_names = ["A_{}".format(x) for x in range(self.number_of_inputs)] decode_names = invert_names + non_invert_names - offset = vector(self.x_off_inv_1 + self.inv.width + 2*self.m2_pitch, 2*self.m1_width) + offset = vector(self.x_off_inv_1 + self.inv.width + 2 * self.m2_pitch, self.m1_pitch) self.decode_rails = self.create_vertical_bus(layer="m2", pitch=self.m2_pitch, offset=offset, names=decode_names, - length=self.height - 2*self.m1_width) + length=self.height - 2 * self.m1_pitch) def create_input_inverters(self): """ Create the input inverters to invert input signals for the decode stage. """ @@ -112,62 +109,35 @@ class hierarchical_predecode(design.design): self.in_inst[inv_num].place(offset=offset, mirror=mirror) - def create_output_inverters(self): - """ Create inverters for the inverted output decode signals. """ - self.inv_inst = [] - for inv_num in range(self.number_of_outputs): - name = "pre_nand_inv_{}".format(inv_num) - self.inv_inst.append(self.add_inst(name=name, - mod=self.inv)) - self.connect_inst(["Z_{}".format(inv_num), - "out_{}".format(inv_num), - "vdd", "gnd"]) + def create_and_array(self, connections): + """ Create the AND stage for the decodes """ + self.and_inst = [] + for and_input in range(self.number_of_outputs): + inout = str(self.number_of_inputs) + "x" + str(self.number_of_outputs) + name = "Xpre{0}_and_{1}".format(inout, and_input) + self.and_inst.append(self.add_inst(name=name, + mod=self.and_mod)) + self.connect_inst(connections[and_input]) - - def place_output_inverters(self): - """ Place inverters for the inverted output decode signals. """ - for inv_num in range(self.number_of_outputs): - if (inv_num % 2 == 0): - y_off = inv_num * self.inv.height + def place_and_array(self): + """ Place the AND stage for the decodes """ + for and_input in range(self.number_of_outputs): + # inout = str(self.number_of_inputs) + "x" + str(self.number_of_outputs) + if (and_input % 2 == 0): + y_off = and_input * self.and_mod.height mirror = "R0" else: - y_off =(inv_num + 1)*self.inv.height + y_off = (and_input + 1) * self.and_mod.height mirror = "MX" - offset = vector(self.x_off_inv_2, y_off) - self.inv_inst[inv_num].place(offset=offset, - mirror=mirror) - - def create_nand_array(self,connections): - """ Create the NAND stage for the decodes """ - self.nand_inst = [] - for nand_input in range(self.number_of_outputs): - inout = str(self.number_of_inputs)+"x"+str(self.number_of_outputs) - name = "Xpre{0}_nand_{1}".format(inout,nand_input) - self.nand_inst.append(self.add_inst(name=name, - mod=self.nand)) - self.connect_inst(connections[nand_input]) - - - def place_nand_array(self): - """ Place the NAND stage for the decodes """ - for nand_input in range(self.number_of_outputs): - inout = str(self.number_of_inputs)+"x"+str(self.number_of_outputs) - if (nand_input % 2 == 0): - y_off = nand_input * self.inv.height - mirror = "R0" - else: - y_off = (nand_input + 1) * self.inv.height - mirror = "MX" - offset = vector(self.x_off_nand, y_off) - self.nand_inst[nand_input].place(offset=offset, - mirror=mirror) - + offset = vector(self.x_off_and, y_off) + self.and_inst[and_input].place(offset=offset, + mirror=mirror) def route(self): self.route_input_inverters() self.route_inputs_to_rails() - self.route_nand_to_rails() - self.route_output_inverters() + self.route_and_to_rails() + self.route_output_and() self.route_vdd_gnd() def route_inputs_to_rails(self): @@ -175,39 +145,30 @@ class hierarchical_predecode(design.design): for num in range(self.number_of_inputs): # route one signal next to each vdd/gnd rail since this is # typically where the p/n devices are and there are no - # pins in the nand gates. - y_offset = (num+self.number_of_inputs) * self.inv.height + contact.m1_via.width + self.m1_space - in_pin = "in_{}".format(num) + # pins in the and gates. + y_offset = (num + self.number_of_inputs) * self.inv.height + contact.m1_via.width + self.m1_space + in_pin = "in_{}".format(num) a_pin = "A_{}".format(num) - in_pos = vector(self.input_rails[in_pin].x,y_offset) - a_pos = vector(self.decode_rails[a_pin].x,y_offset) - self.add_path("m1",[in_pos, a_pos]) - self.add_via_center(layers = self.m1_stack, + in_pos = vector(self.input_rails[in_pin].x, y_offset) + a_pos = vector(self.decode_rails[a_pin].x, y_offset) + self.add_path("m1", [in_pos, a_pos]) + self.add_via_center(layers=self.m1_stack, offset=[self.input_rails[in_pin].x, y_offset]) - self.add_via_center(layers = self.m1_stack, + self.add_via_center(layers=self.m1_stack, offset=[self.decode_rails[a_pin].x, y_offset]) - def route_output_inverters(self): + def route_output_and(self): """ - Route all conections of the outputs inverters + Route all conections of the outputs and gates """ for num in range(self.number_of_outputs): - # route nand output to output inv input - zr_pos = self.nand_inst[num].get_pin("Z").rc() - al_pos = self.inv_inst[num].get_pin("A").lc() - # ensure the bend is in the middle - mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y) - mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y) - self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos]) - - z_pin = self.inv_inst[num].get_pin("Z") + z_pin = self.and_inst[num].get_pin("Z") self.add_layout_pin(text="out_{}".format(num), layer="m1", offset=z_pin.ll(), height=z_pin.height(), width=z_pin.width()) - def route_input_inverters(self): """ @@ -219,7 +180,7 @@ class hierarchical_predecode(design.design): #add output so that it is just below the vdd or gnd rail # since this is where the p/n devices are and there are no - # pins in the nand gates. + # pins in the and gates. y_offset = (inv_num+1) * self.inv.height - 3*self.m1_space inv_out_pos = self.in_inst[inv_num].get_pin("Z").rc() right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(),0) @@ -236,13 +197,12 @@ class hierarchical_predecode(design.design): self.add_via_center(layers=self.m1_stack, offset=in_pos) - - def route_nand_to_rails(self): - # This 2D array defines the connection mapping - nand_input_line_combination = self.get_nand_input_line_combination() + def route_and_to_rails(self): + # This 2D array defines the connection mapping + and_input_line_combination = self.get_and_input_line_combination() for k in range(self.number_of_outputs): - # create x offset list - index_lst= nand_input_line_combination[k] + # create x offset list + index_lst= and_input_line_combination[k] if self.number_of_inputs == 2: gate_lst = ["A","B"] @@ -251,35 +211,32 @@ class hierarchical_predecode(design.design): # this will connect pins A,B or A,B,C for rail_pin,gate_pin in zip(index_lst,gate_lst): - pin_pos = self.nand_inst[k].get_pin(gate_pin).lc() + pin_pos = self.and_inst[k].get_pin(gate_pin).lc() rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y) self.add_path("m1", [rail_pos, pin_pos]) self.add_via_center(layers=self.m1_stack, offset=rail_pos) - - - def route_vdd_gnd(self): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ # Find the x offsets for where the vias/pins should be placed in_xoffset = self.in_inst[0].rx() + self.m1_space - out_xoffset = self.inv_inst[0].lx() - self.m1_space - for num in range(0,self.number_of_outputs): + # out_xoffset = self.and_inst[0].cx() + self.m1_space + for num in range(0, self.number_of_outputs): # this will result in duplicate polygons for rails, but who cares # Route both supplies for n in ["vdd", "gnd"]: - nand_pin = self.nand_inst[num].get_pin(n) - supply_offset = nand_pin.ll().scale(0,1) + and_pin = self.and_inst[num].get_pin(n) + supply_offset = and_pin.ll().scale(0, 1) self.add_rect(layer="m1", offset=supply_offset, - width=self.inv_inst[num].rx()) + width=self.and_inst[num].rx()) # Add pins in two locations - for xoffset in [in_xoffset, out_xoffset]: - pin_pos = vector(xoffset, nand_pin.cy()) + for xoffset in [in_xoffset]: + pin_pos = vector(xoffset, and_pin.cy()) self.add_power_pin(n, pin_pos) diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index f05f54b0..b1aacc5a 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -27,33 +27,31 @@ class hierarchical_predecode2x4(hierarchical_predecode): self.add_pins() self.add_modules() self.create_input_inverters() - self.create_output_inverters() - connections =[["inbar_0", "inbar_1", "Z_0", "vdd", "gnd"], - ["in_0", "inbar_1", "Z_1", "vdd", "gnd"], - ["inbar_0", "in_1", "Z_2", "vdd", "gnd"], - ["in_0", "in_1", "Z_3", "vdd", "gnd"]] - self.create_nand_array(connections) + connections =[["inbar_0", "inbar_1", "out_0", "vdd", "gnd"], + ["in_0", "inbar_1", "out_1", "vdd", "gnd"], + ["inbar_0", "in_1", "out_2", "vdd", "gnd"], + ["in_0", "in_1", "out_3", "vdd", "gnd"]] + self.create_and_array(connections) def create_layout(self): """ The general organization is from left to right: 1) a set of M2 rails for input signals 2) a set of inverters to invert input signals 3) a set of M2 rails for the vdd, gnd, inverted inputs, inputs - 4) a set of NAND gates for inversion + 4) a set of AND gates for inversion """ self.setup_layout_constraints() self.route_rails() self.place_input_inverters() - self.place_output_inverters() - self.place_nand_array() + self.place_and_array() self.route() self.add_boundary() - self.DRC_LVS() + self.DRC_LVS() - def get_nand_input_line_combination(self): - """ These are the decoder connections of the NAND gates to the A,B pins """ + def get_and_input_line_combination(self): + """ These are the decoder connections of the AND gates to the A,B pins """ combination = [["Abar_0", "Abar_1"], ["A_0", "Abar_1"], ["Abar_0", "A_1"], ["A_0", "A_1"]] - return combination \ No newline at end of file + return combination diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index 20b629bb..4f2294f1 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -20,26 +20,25 @@ class hierarchical_predecode3x8(hierarchical_predecode): hierarchical_predecode.__init__(self, name, 3, height) self.create_netlist() - if not OPTS.netlist_only: + if not OPTS.netlist_only: self.create_layout() def create_netlist(self): self.add_pins() self.add_modules() self.create_input_inverters() - self.create_output_inverters() - connections=[["inbar_0", "inbar_1", "inbar_2", "Z_0", "vdd", "gnd"], - ["in_0", "inbar_1", "inbar_2", "Z_1", "vdd", "gnd"], - ["inbar_0", "in_1", "inbar_2", "Z_2", "vdd", "gnd"], - ["in_0", "in_1", "inbar_2", "Z_3", "vdd", "gnd"], - ["inbar_0", "inbar_1", "in_2", "Z_4", "vdd", "gnd"], - ["in_0", "inbar_1", "in_2", "Z_5", "vdd", "gnd"], - ["inbar_0", "in_1", "in_2", "Z_6", "vdd", "gnd"], - ["in_0", "in_1", "in_2", "Z_7", "vdd", "gnd"]] - self.create_nand_array(connections) + connections=[["inbar_0", "inbar_1", "inbar_2", "out_0", "vdd", "gnd"], + ["in_0", "inbar_1", "inbar_2", "out_1", "vdd", "gnd"], + ["inbar_0", "in_1", "inbar_2", "out_2", "vdd", "gnd"], + ["in_0", "in_1", "inbar_2", "out_3", "vdd", "gnd"], + ["inbar_0", "inbar_1", "in_2", "out_4", "vdd", "gnd"], + ["in_0", "inbar_1", "in_2", "out_5", "vdd", "gnd"], + ["inbar_0", "in_1", "in_2", "out_6", "vdd", "gnd"], + ["in_0", "in_1", "in_2", "out_7", "vdd", "gnd"]] + self.create_and_array(connections) def create_layout(self): - """ + """ The general organization is from left to right: 1) a set of M2 rails for input signals 2) a set of inverters to invert input signals @@ -49,20 +48,19 @@ class hierarchical_predecode3x8(hierarchical_predecode): self.setup_layout_constraints() self.route_rails() self.place_input_inverters() - self.place_output_inverters() - self.place_nand_array() + self.place_and_array() self.route() self.add_boundary() self.DRC_LVS() - def get_nand_input_line_combination(self): + def get_and_input_line_combination(self): """ These are the decoder connections of the NAND gates to the A,B,C pins """ combination = [["Abar_0", "Abar_1", "Abar_2"], ["A_0", "Abar_1", "Abar_2"], ["Abar_0", "A_1", "Abar_2"], ["A_0", "A_1", "Abar_2"], - ["Abar_0", "Abar_1", "A_2"], + ["Abar_0", "Abar_1", "A_2"], ["A_0", "Abar_1", "A_2"], ["Abar_0", "A_1", "A_2"], ["A_0", "A_1", "A_2"]] - return combination \ No newline at end of file + return combination diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index a9fd19b7..2bbdaf91 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -185,6 +185,7 @@ class pnand3(pgate.pgate): def route_inputs(self): """ Route the A and B and C inputs """ + m1_pitch = self.m1_space + contact.m1_via.first_layer_height # Put B right on the well line self.inputB_yoffset = self.nwell_y_offset self.route_input_gate(self.pmos2_inst, @@ -193,20 +194,19 @@ class pnand3(pgate.pgate): "B", position="center") - self.inputC_yoffset = self.inputB_yoffset - self.m1_pitch + self.inputC_yoffset = self.inputB_yoffset - m1_pitch self.route_input_gate(self.pmos3_inst, self.nmos3_inst, self.inputC_yoffset, "C", position="center") - self.inputA_yoffset = self.inputB_yoffset + self.m1_pitch + self.inputA_yoffset = self.inputB_yoffset + m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, "A", position="center") - def route_output(self): """ Route the Z output """ From c5a1be703c45dc1cda282915237d45820d3bf5bb Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 6 Mar 2020 13:39:46 -0800 Subject: [PATCH 195/521] Rotate via and PEP8 formatting --- compiler/modules/wordline_driver.py | 16 ++++++++-------- compiler/pgates/pnand2.py | 4 ++-- compiler/pgates/pnand3.py | 2 +- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 35a2b8bf..d84457ba 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -115,7 +115,7 @@ class wordline_driver(design.design): "vdd", "gnd"]) def place_drivers(self): - nand2_xoffset = 2*self.m1_width + 5*self.m1_space + nand2_xoffset = 2 * self.m1_width + 5 * self.m1_space inv2_xoffset = nand2_xoffset + self.nand2.width self.width = inv2_xoffset + self.inv.width @@ -123,10 +123,10 @@ class wordline_driver(design.design): for row in range(self.rows): if (row % 2): - y_offset = self.inv.height*(row + 1) + y_offset = self.inv.height * (row + 1) inst_mirror = "MX" else: - y_offset = self.inv.height*row + y_offset = self.inv.height * row inst_mirror = "R0" nand2_offset = [nand2_xoffset, y_offset] @@ -168,8 +168,8 @@ class wordline_driver(design.design): zr_pos = nand_inst.get_pin("Z").rc() al_pos = inv2_inst.get_pin("A").lc() # ensure the bend is in the middle - mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y) - mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y) + mid1_pos = vector(0.5 * (zr_pos.x + al_pos.x), zr_pos.y) + mid2_pos = vector(0.5 * (zr_pos.x + al_pos.x), al_pos.y) self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos]) # connect the decoder input pin to nand2 B @@ -180,7 +180,7 @@ class wordline_driver(design.design): up_or_down = self.m2_space if row % 2 else -self.m2_space input_offset = vector(0, b_pos.y + up_or_down) base_offset = vector(clk_offset.x, input_offset.y) - contact_offset = vector(0.5 * self.m2_width + self.m2_space + 0.5 * contact.m1_via.width, 0) + contact_offset = vector(0.5 * self.m2_width + self.m2_space + 0.5 * contact.m1_via.width, 0) mid_via_offset = base_offset + contact_offset # must under the clk line in M1 @@ -207,7 +207,7 @@ class wordline_driver(design.design): end=wl_offset - vector(self.m1_width, 0)) def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): - """ + """ Follows the clk_buf to a wordline signal adding each stages stage effort to a list. """ @@ -224,7 +224,7 @@ class wordline_driver(design.design): return stage_effort_list def get_wl_en_cin(self): - """ + """ Get the relative capacitance of all the enable connections in the bank """ diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 05eabbe0..8ecc115e 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -234,8 +234,8 @@ class pnand2(pgate.pgate): self.add_layout_pin_rect_center(text="Z", layer="m1", offset=out_offset, - width=contact.m1_via.first_layer_height, - height=contact.m1_via.first_layer_width) + width=contact.m1_via.first_layer_width, + height=contact.m1_via.first_layer_height) def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 2bbdaf91..927ac6fd 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -259,7 +259,7 @@ class pnand3(pgate.pgate): # In fF c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"]) transition_prob = 0.1094 - return transition_prob *(c_load + c_para) + return transition_prob * (c_load + c_para) def input_load(self): """Return the relative input capacitance of a single input""" From fd7af7fc259fdf932b0c5d3c070f7b85b0beb886 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 6 Mar 2020 15:03:31 -0800 Subject: [PATCH 196/521] Matt sucks skip test --- compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 472a60a6..49e1a125 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -15,6 +15,7 @@ from globals import OPTS from sram_factory import factory import debug +@unittest.skip("SKIPPING 20_psram_1bank_4mux_1rw_1r_test - Matt sucks, don't do this") class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): From a5afbfe0aa825847633c456ac24ebae1b17bc0d4 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Sun, 22 Mar 2020 20:54:49 +0000 Subject: [PATCH 197/521] Fixed errors in extra rows characterization --- compiler/characterizer/lib.py | 5 ++++- compiler/gen_stimulus.py | 5 ++++- compiler/globals.py | 4 +--- compiler/options.py | 1 + compiler/sram/sram_config.py | 2 +- 5 files changed, 11 insertions(+), 6 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 6d6c6ce5..e3b1230d 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -559,7 +559,10 @@ class lib: char_results = self.d.analytical_delay(self.slews,self.loads) self.char_sram_results, self.char_port_results = char_results else: - probe_address = "1" * self.sram.addr_size + if (self.sram.num_spare_rows == 0): + probe_address = "1" * self.sram.addr_size + else: + probe_address = "0" + "1" * (self.sram.addr_size - 1) probe_data = self.sram.word_size - 1 char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads) self.char_sram_results, self.char_port_results = char_results diff --git a/compiler/gen_stimulus.py b/compiler/gen_stimulus.py index 5e351577..cfea17d4 100755 --- a/compiler/gen_stimulus.py +++ b/compiler/gen_stimulus.py @@ -76,7 +76,10 @@ d.period = period # Set the load of outputs and slew of inputs d.set_load_slew(load,slew) # Set the probe address/bit -probe_address = "1" * sram.addr_size +if (self.num_spare_rows == 0): + probe_address = "1" * sram.addr_size +else: + probe_address = "0" + ("1" * sram.addr_size - 1) probe_data = sram.word_size - 1 d.set_probe(probe_address, probe_data) diff --git a/compiler/globals.py b/compiler/globals.py index c864f53b..f883a648 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -539,9 +539,7 @@ def report_status(): debug.error("{0} is not an integer in config file.".format(OPTS.sram_size)) if type(OPTS.write_size) is not int and OPTS.write_size is not None: debug.error("{0} is not an integer in config file.".format(OPTS.write_size)) - if type(OPTS.num_spare_rows) is not int and OPT.num_spare_rows is not None: - debug.error("{0} is not an integer in config file.".format(OPTS.num_spare_rows)) - + # If a write mask is specified by the user, the mask write size should be the same as # the word size so that an entire word is written at once. if OPTS.write_size is not None: diff --git a/compiler/options.py b/compiler/options.py index d891ebd9..1c5d3e6a 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -44,6 +44,7 @@ class options(optparse.Values): # word_size = 0 # You can manually specify banks, but it is better to auto-detect it. num_banks = 1 + num_spare_rows = 0 ################### # Optimization options diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index cc1b44b5..e5d9c8dc 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -81,7 +81,7 @@ class sram_config: self.num_cols = int(self.words_per_row*self.word_size) self.num_rows_temp = int(self.num_words_per_bank/self.words_per_row) self.num_rows = self.num_rows_temp + self.num_spare_rows - debug.info(1,"Rows: {} Cols: {}".format(self.num_rows,self.num_cols)) + debug.info(1,"Rows: {} Cols: {}".format(self.num_rows_temp,self.num_cols)) # Compute the address and bank sizes self.row_addr_size = ceil(log(self.num_rows, 2)) From f21791a904ee2ca16fb0e5db4f4a6a4757d4d874 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 23 Mar 2020 11:36:45 -0700 Subject: [PATCH 198/521] Add source drain contact options to ptx. --- compiler/pgates/pnor2.py | 3 +- compiler/pgates/ptx.py | 105 +++++++++++++-------- compiler/tests/03_ptx_1finger_nmos_test.py | 1 + 3 files changed, 68 insertions(+), 41 deletions(-) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 3d998d25..453a62b6 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -187,8 +187,7 @@ class pnor2(pgate.pgate): def route_inputs(self): """ Route the A and B inputs """ # Use M2 spaces so we can drop vias on the pins later! - inputB_yoffset = self.nmos2_pos.y + self.nmos.active_height \ - + self.m2_space + self.m2_width + inputB_yoffset = self.nmos2_inst.uy() + 0.5 * contact.poly_contact.height self.route_input_gate(self.pmos2_inst, self.nmos2_inst, inputB_yoffset, diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 46726b37..ae20d586 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -27,15 +27,23 @@ class ptx(design.design): width=drc("minwidth_tx"), mults=1, tx_type="nmos", + add_source_contact=True, + add_drain_contact=True, + series_devices=False, connect_active=False, connect_poly=False, - series_devices=False, num_contacts=None): # We need to keep unique names because outputting to GDSII # will use the last record with a given name. I.e., you will # over-write a design in GDS if one has and the other doesn't # have poly connected, for example. name = "{0}_m{1}_w{2:.3f}".format(tx_type, mults, width) + if not add_source_contact: + name += "_ns" + if not add_drain_contact: + name += "_nd" + if series_devices: + name += "_sd" if connect_active: name += "_a" if connect_poly: @@ -52,6 +60,8 @@ class ptx(design.design): self.tx_width = width self.connect_active = connect_active self.connect_poly = connect_poly + self.add_source_contact = add_source_contact + self.add_drain_contact = add_drain_contact self.series_devices = series_devices self.num_contacts = num_contacts @@ -379,18 +389,24 @@ class ptx(design.design): # First one is always a SOURCE label = "S" pos = self.contact_offset - contact=self.add_via_center(layers=self.active_stack, - offset=pos, - size=(1, self.num_contacts), - directions=("V","V"), - implant_type=self.implant_type, - well_type=self.well_type) - self.add_layout_pin_rect_center(text=label, - layer="m1", + if self.add_source_contact: + contact=self.add_via_center(layers=self.active_stack, offset=pos, - width=contact.mod.second_layer_width, - height=contact.mod.second_layer_height) - self.source_contacts.append(contact) + size=(1, self.num_contacts), + directions=("V","V"), + implant_type=self.implant_type, + well_type=self.well_type) + self.source_contacts.append(contact) + if self.add_source_contact: + self.add_layout_pin_rect_center(text=label, + layer="m1", + offset=pos, + width=contact.mod.second_layer_width, + height=contact.mod.second_layer_height) + else: + self.add_layout_pin_rect_center(text=label, + layer="active", + offset=pos) source_positions.append(pos) # Skip these if they are going to be in series @@ -406,22 +422,26 @@ class ptx(design.design): label = "S" source_positions.append(pos) - contact=self.add_via_center(layers=self.active_stack, - offset=pos, - size=(1, self.num_contacts), - directions=("V","V"), - implant_type=self.implant_type, - well_type=self.well_type) - self.add_layout_pin_rect_center(text=label, - layer="m1", + if (label=="S" and self.add_source_contact) or (label=="D" and self.add_drain_contact): + contact=self.add_via_center(layers=self.active_stack, offset=pos, - width=contact.mod.second_layer_width, - height=contact.mod.second_layer_height) - - if label == "S": - self.source_contacts.append(contact) + size=(1, self.num_contacts), + directions=("V", "V"), + implant_type=self.implant_type, + well_type=self.well_type) + self.add_layout_pin_rect_center(text=label, + layer="m1", + offset=pos, + width=contact.mod.second_layer_width, + height=contact.mod.second_layer_height) + if label == "S": + self.source_contacts.append(contact) + else: + self.drain_contacts.append(contact) else: - self.drain_contacts.append(contact) + self.add_layout_pin_rect_center(text=label, + layer="active", + offset=pos) pos = vector(self.active_offset.x + self.active_width - 0.5 * self.active_contact.width, self.contact_offset.y) @@ -432,21 +452,28 @@ class ptx(design.design): else: label = "S" source_positions.append(pos) - contact=self.add_via_center(layers=self.active_stack, - offset=pos, - size=(1, self.num_contacts), - directions=("V","V"), - implant_type=self.implant_type, - well_type=self.well_type) - self.add_layout_pin_rect_center(text=label, - layer="m1", + + if (label=="S" and self.add_source_contact) or (label=="D" and self.add_drain_contact): + contact=self.add_via_center(layers=self.active_stack, offset=pos, - width=contact.mod.second_layer_width, - height=contact.mod.second_layer_height) - if label == "S": - self.source_contacts.append(contact) + size=(1, self.num_contacts), + directions=("V", "V"), + implant_type=self.implant_type, + well_type=self.well_type) + if label == "S": + self.source_contacts.append(contact) + else: + self.drain_contacts.append(contact) + if (label=="S" and self.add_source_contact) or (label=="D" and self.add_drain_contact): + self.add_layout_pin_rect_center(text=label, + layer="m1", + offset=pos, + width=contact.mod.second_layer_width, + height=contact.mod.second_layer_height) else: - self.drain_contacts.append(contact) + self.add_layout_pin_rect_center(text=label, + layer="active", + offset=pos) if self.connect_active: self.connect_fingered_active(drain_positions, source_positions) diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index ae323d90..0774af4a 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -15,6 +15,7 @@ from globals import OPTS from sram_factory import factory import debug + class ptx_1finger_nmos_test(openram_test): def runTest(self): From 0ee6963198844a7cbb5905e3278b576f01b6564f Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 23 Mar 2020 11:46:21 -0700 Subject: [PATCH 199/521] Remove unused contact in pnand2 --- compiler/pgates/pnand2.py | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 8ecc115e..4a813269 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -66,13 +66,23 @@ class pnand2(pgate.pgate): def add_ptx(self): """ Create the PMOS and NMOS transistors. """ - self.nmos = factory.create(module_type="ptx", - width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - connect_poly=True, - connect_active=True) - self.add_mod(self.nmos) + self.nmos_nd = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_drain_contact=False, + connect_poly=True, + connect_active=True) + self.add_mod(self.nmos_nd) + + self.nmos_ns = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact=False, + connect_poly=True, + connect_active=True) + self.add_mod(self.nmos_ns) self.pmos = factory.create(module_type="ptx", width=self.pmos_width, @@ -99,9 +109,9 @@ class pnand2(pgate.pgate): # This is the extra space needed to ensure DRC rules # to the active contacts - extra_contact_space = max(-self.nmos.get_pin("D").by(), 0) + extra_contact_space = max(-self.nmos_nd.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell - self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, + self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, self.poly_extend_active + self.poly_space) def route_supply_rails(self): @@ -130,11 +140,11 @@ class pnand2(pgate.pgate): self.connect_inst(["Z", "B", "vdd", "vdd"]) self.nmos1_inst = self.add_inst(name="pnand2_nmos1", - mod=self.nmos) + mod=self.nmos_nd) self.connect_inst(["Z", "B", "net1", "gnd"]) self.nmos2_inst = self.add_inst(name="pnand2_nmos2", - mod=self.nmos) + mod=self.nmos_ns) self.connect_inst(["net1", "A", "gnd", "gnd"]) def place_ptx(self): @@ -160,7 +170,7 @@ class pnand2(pgate.pgate): # Output position will be in between the PMOS and NMOS self.output_pos = vector(0, - 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height)) + 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos_nd.active_height)) def add_well_contacts(self): """ @@ -169,7 +179,7 @@ class pnand2(pgate.pgate): """ self.add_nwell_contact(self.pmos, self.pmos2_pos) - self.add_pwell_contact(self.nmos, self.nmos2_pos) + self.add_pwell_contact(self.nmos_nd, self.nmos2_pos) def connect_rails(self): """ Connect the nmos and pmos to its respective power rails """ From 717cbb0fe56f4b3b66c53a771824d093aa67fd26 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 23 Mar 2020 11:52:19 -0700 Subject: [PATCH 200/521] Remove unused contact in pnand3 --- compiler/pgates/pnand3.py | 44 ++++++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 927ac6fd..5d6999e6 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -69,14 +69,34 @@ class pnand3(pgate.pgate): def add_ptx(self): """ Create the PMOS and NMOS transistors. """ - self.nmos = factory.create(module_type="ptx", - width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - connect_poly=True, - connect_active=True) - self.add_mod(self.nmos) + self.nmos_nsnd = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact=False, + add_drain_contact=False, + connect_poly=True, + connect_active=True) + self.add_mod(self.nmos_nsnd) + self.nmos_ns = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact=False, + connect_poly=True, + connect_active=True) + self.add_mod(self.nmos_ns) + + self.nmos_nd = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_drain_contact=False, + connect_poly=True, + connect_active=True) + self.add_mod(self.nmos_nd) + self.pmos = factory.create(module_type="ptx", width=self.pmos_width, mults=self.tx_mults, @@ -130,15 +150,15 @@ class pnand3(pgate.pgate): self.connect_inst(["Z", "C", "vdd", "vdd"]) self.nmos1_inst = self.add_inst(name="pnand3_nmos1", - mod=self.nmos) + mod=self.nmos_nd) self.connect_inst(["Z", "C", "net1", "gnd"]) self.nmos2_inst = self.add_inst(name="pnand3_nmos2", - mod=self.nmos) + mod=self.nmos_nsnd) self.connect_inst(["net1", "B", "net2", "gnd"]) self.nmos3_inst = self.add_inst(name="pnand3_nmos3", - mod=self.nmos) + mod=self.nmos_ns) self.connect_inst(["net2", "A", "gnd", "gnd"]) def place_ptx(self): @@ -171,7 +191,7 @@ class pnand3(pgate.pgate): """ Add n/p well taps to the layout and connect to supplies """ self.add_nwell_contact(self.pmos, self.pmos3_pos) - self.add_pwell_contact(self.nmos, self.nmos3_pos) + self.add_pwell_contact(self.nmos_ns, self.nmos3_pos) def connect_rails(self): """ Connect the nmos and pmos to its respective power rails """ @@ -259,7 +279,7 @@ class pnand3(pgate.pgate): # In fF c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"]) transition_prob = 0.1094 - return transition_prob * (c_load + c_para) + return transition_prob * (c_load + c_para) def input_load(self): """Return the relative input capacitance of a single input""" From f598a359d5dd3ff976d3dd3dfccf1cb8f08c64ac Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 23 Mar 2020 11:55:17 -0700 Subject: [PATCH 201/521] Remove unused contact in pnor2 --- compiler/pgates/pnor2.py | 50 ++++++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 20 deletions(-) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 453a62b6..3efe542d 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -73,33 +73,43 @@ class pnor2(pgate.pgate): connect_active=True) self.add_mod(self.nmos) - self.pmos = factory.create(module_type="ptx", - width=self.pmos_width, - mults=self.tx_mults, - tx_type="pmos", - connect_poly=True, - connect_active=True) - self.add_mod(self.pmos) + self.pmos_nd = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_drain_contact=False, + connect_poly=True, + connect_active=True) + self.add_mod(self.pmos_nd) + self.pmos_ns = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact=False, + connect_poly=True, + connect_active=True) + self.add_mod(self.pmos_ns) + def setup_layout_constants(self): """ Pre-compute some handy layout parameters. """ # metal spacing to allow contacts on any layer self.input_spacing = max(self.poly_space + contact.poly_contact.first_layer_width, self.m1_space + contact.m1_via.first_layer_width, - self.m2_space + contact.m2_via.first_layer_width, + self.m2_space + contact.m2_via.first_layer_width, self.m3_space + contact.m2_via.second_layer_width) # Compute the other pmos2 location, but determining # offset to overlap the source and drain pins - self.overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll() + self.overlap_offset = self.pmos_ns.get_pin("D").ll() - self.pmos_nd.get_pin("S").ll() # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.width = 2 * self.pmos.active_width \ - + self.pmos.active_contact.width \ - + 2 * self.active_space \ - + 0.5 * self.nwell_enclose_active + self.width = 2 * self.pmos_ns.active_width \ + + self.pmos_ns.active_contact.width \ + + 2 * self.active_space \ + + 0.5 * self.nwell_enclose_active self.well_width = self.width + 2 * self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. @@ -107,7 +117,7 @@ class pnor2(pgate.pgate): # to the active contacts extra_contact_space = max(-self.nmos.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell - self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, + self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, self.poly_extend_active, self.poly_space) @@ -130,11 +140,11 @@ class pnor2(pgate.pgate): """ self.pmos1_inst = self.add_inst(name="pnor2_pmos1", - mod=self.pmos) + mod=self.pmos_nd) self.connect_inst(["vdd", "A", "net1", "vdd"]) self.pmos2_inst = self.add_inst(name="pnor2_pmos2", - mod=self.pmos) + mod=self.pmos_ns) self.connect_inst(["net1", "B", "Z", "vdd"]) self.nmos1_inst = self.add_inst(name="pnor2_nmos1", @@ -151,15 +161,15 @@ class pnor2(pgate.pgate): to provide maximum routing in channel """ - pmos1_pos = vector(self.pmos.active_offset.x, - self.height - self.pmos.active_height \ + pmos1_pos = vector(self.pmos_ns.active_offset.x, + self.height - self.pmos_ns.active_height \ - self.top_bottom_space) self.pmos1_inst.place(pmos1_pos) self.pmos2_pos = pmos1_pos + self.overlap_offset self.pmos2_inst.place(self.pmos2_pos) - nmos1_pos = vector(self.pmos.active_offset.x, self.top_bottom_space) + nmos1_pos = vector(self.pmos_ns.active_offset.x, self.top_bottom_space) self.nmos1_inst.place(nmos1_pos) self.nmos2_pos = nmos1_pos + self.overlap_offset @@ -172,7 +182,7 @@ class pnor2(pgate.pgate): def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ - self.add_nwell_contact(self.pmos, self.pmos2_pos) + self.add_nwell_contact(self.pmos_ns, self.pmos2_pos) self.add_pwell_contact(self.nmos, self.nmos2_pos) def connect_rails(self): From f491876a5a595a077cfbc07ee4e75e88160dab9c Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 23 Mar 2020 13:49:08 -0700 Subject: [PATCH 202/521] Move up B input in pnor2 --- compiler/pgates/pnor2.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 3efe542d..75840f26 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -197,7 +197,7 @@ class pnor2(pgate.pgate): def route_inputs(self): """ Route the A and B inputs """ # Use M2 spaces so we can drop vias on the pins later! - inputB_yoffset = self.nmos2_inst.uy() + 0.5 * contact.poly_contact.height + inputB_yoffset = self.nmos2_inst.uy() + contact.poly_contact.height self.route_input_gate(self.pmos2_inst, self.nmos2_inst, inputB_yoffset, From e9d0db44fd6de2cdaf0590096b6f7fa2a9dd8d52 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 23 Mar 2020 16:55:38 -0700 Subject: [PATCH 203/521] Add li_stack contact to ptx and pgate if it exists. --- compiler/pgates/pgate.py | 27 +++++++++++++------ compiler/pgates/ptx.py | 57 ++++++++++++++++------------------------ 2 files changed, 41 insertions(+), 43 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 7693fa07..d83825ea 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -64,7 +64,7 @@ class pgate(design.design): width=source_pin.width()) def route_input_gate(self, pmos_inst, nmos_inst, ypos, name, position="left"): - """ + """ Route the input gate to the left side of the cell for access. Position specifies to place the contact the left, center, or right of gate. @@ -107,8 +107,12 @@ class pgate(design.design): else: debug.error("Invalid contact placement option.", -1) - v=self.add_via_center(layers=self.poly_stack, - offset=contact_offset) + if hasattr(self, "li_stack"): + self.add_via_center(layers=self.li_stack, + offset=contact_offset) + + self.add_via_center(layers=self.poly_stack, + offset=contact_offset) self.add_layout_pin_rect_center(text=name, layer="m1", @@ -182,13 +186,17 @@ class pgate(design.design): contact_offset = vector(contact_xoffset, contact_yoffset) # Offset by half a contact in x and y contact_offset += vector(0.5 * pmos.active_contact.first_layer_width, - 0.5 * pmos.active_contact.first_layer_height) + 0.5 * pmos.active_contact.first_layer_height) self.nwell_contact = self.add_via_center(layers=layer_stack, offset=contact_offset, implant_type="n", well_type="n") + if hasattr(self, "li_stack"): + self.add_via_center(layers=self.li_stack, + offset=contact_offset) + self.add_rect_center(layer="m1", - offset=contact_offset + vector(0, 0.5 * (self.height-contact_offset.y)), + offset=contact_offset + vector(0, 0.5 * (self.height - contact_offset.y)), width=self.nwell_contact.mod.second_layer_width, height=self.height - contact_offset.y) @@ -221,8 +229,6 @@ class pgate(design.design): layer_stack = self.active_stack - pwell_position = vector(0, -0.5 * self.m1_width) - # To the right a spacing away from the nmos right active edge contact_xoffset = nmos_pos.x + nmos.active_width \ + self.active_space @@ -240,8 +246,13 @@ class pgate(design.design): offset=contact_offset, implant_type="p", well_type="p") + + if hasattr(self, "li_stack"): + self.add_via_center(layers=self.li_stack, + offset=contact_offset) + self.add_rect_center(layer="m1", - offset=contact_offset.scale(1,0.5), + offset=contact_offset.scale(1, 0.5), width=self.pwell_contact.mod.second_layer_width, height=contact_offset.y) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index ae20d586..dee475c9 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -390,19 +390,8 @@ class ptx(design.design): label = "S" pos = self.contact_offset if self.add_source_contact: - contact=self.add_via_center(layers=self.active_stack, - offset=pos, - size=(1, self.num_contacts), - directions=("V","V"), - implant_type=self.implant_type, - well_type=self.well_type) + contact = self.add_diff_contact(label, pos) self.source_contacts.append(contact) - if self.add_source_contact: - self.add_layout_pin_rect_center(text=label, - layer="m1", - offset=pos, - width=contact.mod.second_layer_width, - height=contact.mod.second_layer_height) else: self.add_layout_pin_rect_center(text=label, layer="active", @@ -423,17 +412,7 @@ class ptx(design.design): source_positions.append(pos) if (label=="S" and self.add_source_contact) or (label=="D" and self.add_drain_contact): - contact=self.add_via_center(layers=self.active_stack, - offset=pos, - size=(1, self.num_contacts), - directions=("V", "V"), - implant_type=self.implant_type, - well_type=self.well_type) - self.add_layout_pin_rect_center(text=label, - layer="m1", - offset=pos, - width=contact.mod.second_layer_width, - height=contact.mod.second_layer_height) + contact = self.add_diff_contact(label, pos) if label == "S": self.source_contacts.append(contact) else: @@ -454,22 +433,11 @@ class ptx(design.design): source_positions.append(pos) if (label=="S" and self.add_source_contact) or (label=="D" and self.add_drain_contact): - contact=self.add_via_center(layers=self.active_stack, - offset=pos, - size=(1, self.num_contacts), - directions=("V", "V"), - implant_type=self.implant_type, - well_type=self.well_type) + contact = self.add_diff_contact(label, pos) if label == "S": self.source_contacts.append(contact) else: self.drain_contacts.append(contact) - if (label=="S" and self.add_source_contact) or (label=="D" and self.add_drain_contact): - self.add_layout_pin_rect_center(text=label, - layer="m1", - offset=pos, - width=contact.mod.second_layer_width, - height=contact.mod.second_layer_height) else: self.add_layout_pin_rect_center(text=label, layer="active", @@ -478,6 +446,25 @@ class ptx(design.design): if self.connect_active: self.connect_fingered_active(drain_positions, source_positions) + def add_diff_contact(self, label, pos): + contact=self.add_via_center(layers=self.active_stack, + offset=pos, + size=(1, self.num_contacts), + directions=("V","V"), + implant_type=self.implant_type, + well_type=self.well_type) + + if hasattr(self, "li_stack"): + self.add_via_center(layers=self.li_stack, + offset=pos) + + self.add_layout_pin_rect_center(text=label, + layer="m1", + offset=pos, + width=contact.mod.second_layer_width, + height=contact.mod.second_layer_height) + return(contact) + def get_cin(self): """Returns the relative gate cin of the tx""" return self.tx_width / drc("minwidth_tx") From 1e2163c3a6319964604e7927e6f35b7307c8a532 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 24 Mar 2020 12:40:41 -0700 Subject: [PATCH 204/521] Hack for pnand3 pin spacing --- compiler/pgates/pnand3.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 5d6999e6..6f4d2472 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -214,14 +214,14 @@ class pnand3(pgate.pgate): "B", position="center") - self.inputC_yoffset = self.inputB_yoffset - m1_pitch + self.inputC_yoffset = self.inputB_yoffset - 1.25 * m1_pitch self.route_input_gate(self.pmos3_inst, self.nmos3_inst, self.inputC_yoffset, "C", position="center") - self.inputA_yoffset = self.inputB_yoffset + m1_pitch + self.inputA_yoffset = self.inputB_yoffset + 1.25 * m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, From 2f353187ba3a87ef465c65b82ba81174201f8c5e Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 24 Mar 2020 12:41:15 -0700 Subject: [PATCH 205/521] Skywater extraction mode for si unit scales --- compiler/pgates/ptx.py | 2 +- compiler/verify/magic.py | 36 +++++++++++++++++++----------------- 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index dee475c9..8fbb94d8 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -99,7 +99,7 @@ class ptx(design.design): body_dir = 'POWER' dir_list = ['INOUT', 'INPUT', 'INOUT', body_dir] self.add_pin_list(pin_list, dir_list) - + # self.spice.append("\n.SUBCKT {0} {1}".format(self.name, # " ".join(self.pins))) # Just make a guess since these will actually diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 63aeaabe..1d3562cc 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -22,7 +22,6 @@ and include its appropriate license. import os import re -import time import shutil import debug from globals import OPTS @@ -67,26 +66,29 @@ def write_magic_script(cell_name, extract=False, final_verification=False): else: pre = "" if final_verification: - f.write(pre+"extract unique all\n".format(cell_name)) - f.write(pre+"extract\n".format(cell_name)) - #f.write(pre+"ext2spice hierarchy on\n") - #f.write(pre+"ext2spice scale off\n") + f.write(pre + "extract unique all\n".format(cell_name)) + # Hack to work around unit scales in SkyWater + if OPTS.tech_name=="s8": + f.write(pre + "extract style ngspice(si)\n") + f.write(pre + "extract\n".format(cell_name)) + # f.write(pre + "ext2spice hierarchy on\n") + # f.write(pre + "ext2spice scale off\n") # lvs exists in 8.2.79, but be backword compatible for now - #f.write(pre+"ext2spice lvs\n") - f.write(pre+"ext2spice hierarchy on\n") - f.write(pre+"ext2spice format ngspice\n") - f.write(pre+"ext2spice cthresh infinite\n") - f.write(pre+"ext2spice rthresh infinite\n") - f.write(pre+"ext2spice renumber off\n") - f.write(pre+"ext2spice scale off\n") - f.write(pre+"ext2spice blackbox on\n") - f.write(pre+"ext2spice subcircuit top auto\n") - f.write(pre+"ext2spice global off\n") + # f.write(pre + "ext2spice lvs\n") + f.write(pre + "ext2spice hierarchy on\n") + f.write(pre + "ext2spice format ngspice\n") + f.write(pre + "ext2spice cthresh infinite\n") + f.write(pre + "ext2spice rthresh infinite\n") + f.write(pre + "ext2spice renumber off\n") + f.write(pre + "ext2spice scale off\n") + f.write(pre + "ext2spice blackbox on\n") + f.write(pre + "ext2spice subcircuit top auto\n") + f.write(pre + "ext2spice global off\n") # Can choose hspice, ngspice, or spice3, # but they all seem compatible enough. - #f.write(pre+"ext2spice format ngspice\n") - f.write(pre+"ext2spice {}\n".format(cell_name)) + #f.write(pre + "ext2spice format ngspice\n") + f.write(pre + "ext2spice {}\n".format(cell_name)) f.write("quit -noprompt\n") f.write("EOF\n") From 1e3734cb267447e9e62fba22a2103865ba88e6be Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 26 Mar 2020 11:08:53 -0700 Subject: [PATCH 206/521] Hack to fix pnand3 in freepdk45 --- compiler/pgates/pnand3.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 6f4d2472..9aa54733 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -214,14 +214,16 @@ class pnand3(pgate.pgate): "B", position="center") - self.inputC_yoffset = self.inputB_yoffset - 1.25 * m1_pitch + # FIXME: constant hack + self.inputC_yoffset = self.inputB_yoffset - 1.1 * m1_pitch self.route_input_gate(self.pmos3_inst, self.nmos3_inst, self.inputC_yoffset, "C", position="center") - self.inputA_yoffset = self.inputB_yoffset + 1.25 * m1_pitch + # FIXME: constant hack + self.inputA_yoffset = self.inputB_yoffset + 1.1 * m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, From d2c97d75a78c3082577203be47e3a6a78fdd06aa Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 26 Mar 2020 11:49:32 -0700 Subject: [PATCH 207/521] Add well contact and min area to power pin of precharge --- compiler/base/hierarchy_layout.py | 21 +++++++++++++-------- compiler/pgates/precharge.py | 22 +++++++++++++++------- 2 files changed, 28 insertions(+), 15 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 049d2307..043d71b5 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -9,6 +9,7 @@ import collections import geometry import gdsMill import debug +from math import sqrt from tech import drc, GDS from tech import layer as techlayer from tech import layer_stacks @@ -1193,11 +1194,9 @@ class layout(): "supply router." .format(name,inst.name,self.pwr_grid_layer)) - - def add_power_pin(self, name, loc, size=[1, 1], vertical=False, start_layer="m1"): """ - Add a single power pin from the lowest power_grid layer down to M1 at + Add a single power pin from the lowest power_grid layer down to M1 (or li) at the given center location. The starting layer is specified to determine which vias are needed. """ @@ -1211,23 +1210,29 @@ class layout(): else: direction = None - via = self.add_via_stack_center(from_layer=start_layer, to_layer=self.pwr_grid_layer, size=size, offset=loc, direction=direction) - + # Hack for min area + if OPTS.tech_name == "s8": + height = width = sqrt(drc["minarea_m3"]) + else: + width = via.width + height = via.height if start_layer == self.pwr_grid_layer: self.add_layout_pin_rect_center(text=name, layer=self.pwr_grid_layer, - offset=loc) + offset=loc, + width=width, + height=height) else: self.add_layout_pin_rect_center(text=name, layer=self.pwr_grid_layer, offset=loc, - width=via.width, - height=via.height) + width=width, + height=height) def add_power_ring(self, bbox): """ diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 56382712..ee0f96d1 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -96,17 +96,24 @@ class precharge(design.design): height=layer_width) pmos_pin = self.upper_pmos2_inst.get_pin("S") + # center of vdd rail pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y) self.add_path("m1", [pmos_pin.uc(), pmos_vdd_pos]) + + # if enable is not on M1, the supply can be if self.en_layer != "m1": self.add_via_center(layers=self.m1_stack, offset=pmos_vdd_pos) + self.add_power_pin("vdd", + self.well_contact_pos, + vertical=True) - - # Add vdd pin above the transistor - self.add_power_pin("vdd", self.well_contact_pos, vertical=True) + # Hack for li layers + if OPTS.tech_name == "s8": + self.add_via_center(layers=self.li_stack, + offset=self.well_contact_pos) def create_ptx(self): """ @@ -191,7 +198,6 @@ class precharge(design.design): if self.en_layer == "m2": self.add_via_center(layers=self.m1_stack, offset=offset) - # adds the en rail on metal1 self.add_layout_pin_segment_center(text="en_bar", @@ -205,9 +211,11 @@ class precharge(design.design): """ # adds the contact from active to metal1 - self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \ - + vector(0, self.upper_pmos1_inst.uy() + contact.active_contact.height / 2 \ - + self.nwell_extend_active) + offset_height = self.upper_pmos1_inst.uy() + \ + 0.5 * contact.active_contact.height + \ + self.nwell_extend_active + self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) + \ + vector(0, offset_height) self.add_via_center(layers=self.active_stack, offset=self.well_contact_pos, implant_type="n", From 9907daaffa8557af0edc324623d5f8358c3dc172 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 26 Mar 2020 13:05:02 -0700 Subject: [PATCH 208/521] Min area only for multiple layers --- compiler/base/hierarchy_layout.py | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 043d71b5..63d53d39 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1215,19 +1215,17 @@ class layout(): size=size, offset=loc, direction=direction) - # Hack for min area - if OPTS.tech_name == "s8": - height = width = sqrt(drc["minarea_m3"]) - else: - width = via.width - height = via.height if start_layer == self.pwr_grid_layer: self.add_layout_pin_rect_center(text=name, layer=self.pwr_grid_layer, - offset=loc, - width=width, - height=height) + offset=loc) else: + # Hack for min area + if OPTS.tech_name == "s8": + height = width = sqrt(drc["minarea_m3"]) + else: + width = via.width + height = via.height self.add_layout_pin_rect_center(text=name, layer=self.pwr_grid_layer, offset=loc, From b0d2946c809b9f14322fbd8560e5301d0e81763f Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Mon, 30 Mar 2020 20:00:32 -0700 Subject: [PATCH 209/521] update to sense amp and write driver modules --- compiler/modules/sense_amp_array.py | 33 ++++++++++++----------- compiler/modules/write_driver_array.py | 18 ++++++------- compiler/tests/09_sense_amp_array_test.py | 10 ++++--- 3 files changed, 33 insertions(+), 28 deletions(-) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 322cc1b3..1c9c7d19 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -22,7 +22,7 @@ class sense_amp_array(design.design): def __init__(self, name, word_size, words_per_row): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) - self.add_comment("word_size {0}".format(word_size)) + self.add_comment("word_size {0}".format(word_size)) self.add_comment("words_per_row: {0}".format(words_per_row)) self.word_size = word_size @@ -56,7 +56,7 @@ class sense_amp_array(design.design): def create_layout(self): self.height = self.amp.height - + if self.bitcell.width > self.amp.width: self.width = self.bitcell.width * self.word_size * self.words_per_row else: @@ -76,16 +76,16 @@ class sense_amp_array(design.design): self.add_pin(self.en_name, "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - + def add_modules(self): self.amp = factory.create(module_type="sense_amp") - + self.add_mod(self.amp) # This is just used for measurements, # so don't add the module self.bitcell = factory.create(module_type="bitcell") - + def create_sense_amp_array(self): self.local_insts = [] for i in range(0,self.word_size): @@ -121,11 +121,11 @@ class sense_amp_array(design.design): amp_position = vector(xoffset, 0) self.local_insts[i].place(offset=amp_position,mirror=mirror) - + def add_layout_pins(self): for i in range(len(self.local_insts)): inst = self.local_insts[i] - + self.add_power_pin(name = "gnd", loc = inst.get_pin("gnd").center(), start_layer="m2", @@ -141,40 +141,41 @@ class sense_amp_array(design.design): dout_pin = inst.get_pin(inst.mod.dout_name) self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i), - layer="m2", + layer=bl_pin.layer, offset=bl_pin.ll(), width=bl_pin.width(), height=bl_pin.height()) self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i), - layer="m2", + layer=br_pin.layer, offset=br_pin.ll(), width=br_pin.width(), height=br_pin.height()) self.add_layout_pin(text=self.data_name + "_{0}".format(i), - layer="m2", + layer=dout_pin.layer, offset=dout_pin.ll(), width=dout_pin.width(), height=dout_pin.height()) - - + + def route_rails(self): # add sclk rail across entire array + sclk = self.amp.get_pin(self.amp.en_name) sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1) self.add_layout_pin(text=self.en_name, - layer="m1", + layer=sclk.layer, offset=sclk_offset, width=self.width, - height=drc("minwidth_m1")) + height=drc("minwidth_" + sclk.layer)) def input_load(self): return self.amp.input_load() - + def get_en_cin(self): """Get the relative capacitance of all the sense amp enable connections in the array""" sense_amp_en_cin = self.amp.get_en_cin() return sense_amp_en_cin * self.word_size - + def get_drain_cin(self): """Get the relative capacitance of the drain of the PMOS isolation TX""" from tech import parameter diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 08a2e007..c83bd130 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -23,7 +23,7 @@ class write_driver_array(design.design): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) - self.add_comment("word_size {0}".format(word_size)) + self.add_comment("word_size {0}".format(word_size)) self.columns = columns self.word_size = word_size @@ -57,15 +57,15 @@ class write_driver_array(design.design): self.add_modules() self.add_pins() self.create_write_array() - + def create_layout(self): - + if self.bitcell.width > self.driver.width: self.width = self.columns * self.bitcell.width else: self.width = self.columns * self.driver.width self.height = self.driver.height - + self.place_write_array() self.add_layout_pins() self.add_boundary() @@ -139,26 +139,26 @@ class write_driver_array(design.design): base = vector(xoffset, 0) self.driver_insts[index].place(offset=base, mirror=mirror) - + def add_layout_pins(self): for i in range(self.word_size): inst = self.driver_insts[i] din_pin = inst.get_pin(inst.mod.din_name) self.add_layout_pin(text=self.data_name + "_{0}".format(i), - layer="m2", + layer=din_pin.layer, offset=din_pin.ll(), width=din_pin.width(), height=din_pin.height()) bl_pin = inst.get_pin(inst.mod.get_bl_names()) self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i), - layer="m2", + layer=bl_pin.layer, offset=bl_pin.ll(), width=bl_pin.width(), height=bl_pin.height()) br_pin = inst.get_pin(inst.mod.get_br_names()) self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i), - layer="m2", + layer=br_pin.layer, offset=br_pin.ll(), width=br_pin.width(), height=br_pin.height()) @@ -194,7 +194,7 @@ class write_driver_array(design.design): width=self.width) - + def get_w_en_cin(self): """Get the relative capacitance of all the enable connections in the bank""" diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index 3baf51f0..88b5a9aa 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -22,6 +22,10 @@ class sense_amp_test(openram_test): globals.init_openram(config_file) # check sense amp array for single port + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1) + self.local_check(a) + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2) self.local_check(a) @@ -29,7 +33,7 @@ class sense_amp_test(openram_test): debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) self.local_check(a) - + # check sense amp array for multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 @@ -44,9 +48,9 @@ class sense_amp_test(openram_test): debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) self.local_check(a) - + globals.end_openram() - + # run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() From d916322b74a6aec0472b13eb173f1bcd279ba0f6 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 31 Mar 2020 10:15:46 -0700 Subject: [PATCH 210/521] PEP8 updates --- compiler/modules/sense_amp_array.py | 31 +++++++++++----------- compiler/modules/write_driver_array.py | 36 +++++++++++--------------- 2 files changed, 30 insertions(+), 37 deletions(-) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 1c9c7d19..d8cb2869 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -13,6 +13,7 @@ import debug from globals import OPTS import logical_effort + class sense_amp_array(design.design): """ Array of sense amplifiers to read the bitlines through the column mux. @@ -69,7 +70,7 @@ class sense_amp_array(design.design): self.DRC_LVS() def add_pins(self): - for i in range(0,self.word_size): + for i in range(0, self.word_size): self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT") self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT") self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT") @@ -88,7 +89,7 @@ class sense_amp_array(design.design): def create_sense_amp_array(self): self.local_insts = [] - for i in range(0,self.word_size): + for i in range(0, self.word_size): name = "sa_d{0}".format(i) self.local_insts.append(self.add_inst(name=name, @@ -105,7 +106,7 @@ class sense_amp_array(design.design): else: amp_spacing = self.amp.width * self.words_per_row - for i in range(0,self.word_size): + for i in range(0, self.word_size): xoffset = amp_spacing * i # align the xoffset to the grid of bitcells. This way we @@ -119,20 +120,19 @@ class sense_amp_array(design.design): mirror = "" amp_position = vector(xoffset, 0) - self.local_insts[i].place(offset=amp_position,mirror=mirror) - + self.local_insts[i].place(offset=amp_position, mirror=mirror) def add_layout_pins(self): for i in range(len(self.local_insts)): inst = self.local_insts[i] - self.add_power_pin(name = "gnd", - loc = inst.get_pin("gnd").center(), + self.add_power_pin(name="gnd", + loc=inst.get_pin("gnd").center(), start_layer="m2", vertical=True) - self.add_power_pin(name = "vdd", - loc = inst.get_pin("vdd").center(), + self.add_power_pin(name="vdd", + loc=inst.get_pin("vdd").center(), start_layer="m2", vertical=True) @@ -157,16 +157,15 @@ class sense_amp_array(design.design): width=dout_pin.width(), height=dout_pin.height()) - def route_rails(self): # add sclk rail across entire array sclk = self.amp.get_pin(self.amp.en_name) - sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1) + sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0, 1) self.add_layout_pin(text=self.en_name, - layer=sclk.layer, - offset=sclk_offset, - width=self.width, - height=drc("minwidth_" + sclk.layer)) + layer=sclk.layer, + offset=sclk_offset, + width=self.width, + height=drc("minwidth_" + sclk.layer)) def input_load(self): return self.amp.input_load() @@ -179,6 +178,6 @@ class sense_amp_array(design.design): def get_drain_cin(self): """Get the relative capacitance of the drain of the PMOS isolation TX""" from tech import parameter - #Bitcell drain load being used to estimate PMOS drain load + # Bitcell drain load being used to estimate PMOS drain load drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap']) return drain_load diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index c83bd130..d1244aed 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -5,21 +5,20 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from math import log import design -from tech import drc import debug from sram_factory import factory from vector import vector from globals import OPTS + class write_driver_array(design.design): """ Array of tristate drivers to write to the bitlines through the column mux. Dynamically generated write driver array of all bitlines. """ - def __init__(self, name, columns, word_size,write_size=None): + def __init__(self, name, columns, word_size, write_size=None): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) @@ -31,7 +30,7 @@ class write_driver_array(design.design): self.words_per_row = int(columns / word_size) if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(self.word_size / self.write_size) self.create_netlist() if not OPTS.netlist_only: @@ -97,9 +96,9 @@ class write_driver_array(design.design): self.driver_insts = {} w = 0 windex=0 - for i in range(0,self.columns,self.words_per_row): + for i in range(0, self.columns, self.words_per_row): name = "write_driver{}".format(i) - index = int(i/self.words_per_row) + index = int(i / self.words_per_row) self.driver_insts[index]=self.add_inst(name=name, mod=self.driver) @@ -119,15 +118,14 @@ class write_driver_array(design.design): self.get_br_name() + "_{0}".format(index), self.en_name, "vdd", "gnd"]) - def place_write_array(self): from tech import cell_properties if self.bitcell.width > self.driver.width: self.driver_spacing = self.bitcell.width else: self.driver_spacing = self.driver.width - for i in range(0,self.columns,self.words_per_row): - index = int(i/self.words_per_row) + for i in range(0, self.columns, self.words_per_row): + index = int(i / self.words_per_row) xoffset = i * self.driver_spacing if cell_properties.bitcell.mirror.y and i % 2: @@ -139,7 +137,6 @@ class write_driver_array(design.design): base = vector(xoffset, 0) self.driver_insts[index].place(offset=base, mirror=mirror) - def add_layout_pins(self): for i in range(self.word_size): inst = self.driver_insts[i] @@ -166,16 +163,16 @@ class write_driver_array(design.design): for n in ["vdd", "gnd"]: pin_list = self.driver_insts[i].get_pins(n) for pin in pin_list: - self.add_power_pin(name = n, - loc = pin.center(), + self.add_power_pin(name=n, + loc=pin.center(), vertical=True, - start_layer = "m2") + start_layer="m2") if self.write_size: for bit in range(self.num_wmasks): - inst = self.driver_insts[bit*self.write_size] + inst = self.driver_insts[bit * self.write_size] en_pin = inst.get_pin(inst.mod.en_name) # Determine width of wmask modified en_pin with/without col mux - wmask_en_len = self.words_per_row*(self.write_size * self.driver_spacing) + wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing) if (self.words_per_row == 1): en_gap = self.driver_spacing - en_pin.width() else: @@ -184,19 +181,16 @@ class write_driver_array(design.design): self.add_layout_pin(text=self.en_name + "_{0}".format(bit), layer=en_pin.layer, offset=en_pin.ll(), - width=wmask_en_len-en_gap, + width=wmask_en_len - en_gap, height=en_pin.height()) else: inst = self.driver_insts[0] self.add_layout_pin(text=self.en_name, layer="m1", - offset=inst.get_pin(inst.mod.en_name).ll().scale(0,1), + offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1), width=self.width) - - - def get_w_en_cin(self): """Get the relative capacitance of all the enable connections in the bank""" - #The enable is connected to a nand2 for every row. + # The enable is connected to a nand2 for every row. return self.driver.get_w_en_cin() * len(self.driver_insts) From 6e2a5d7a1a29118a1a3d9620118876d5538f3112 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 1 Apr 2020 04:24:43 -0700 Subject: [PATCH 211/521] set sram output cap in characterizer to be 4x dff input cap --- compiler/characterizer/lib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 6d6c6ce5..d429bcd5 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -45,7 +45,7 @@ class lib: """ Determine the load/slews if they aren't specified in the config file. """ # These are the parameters to determine the table sizes #self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8]) - self.load_scales = np.array([0.25, 1, 8]) + self.load_scales = np.array([0.25, 1, 4]) #self.load_scales = np.array([0.25, 1]) self.load = tech.spice["dff_in_cap"] self.loads = self.load_scales*self.load From bc9cbe70a7712f1b0df7b60edbc760b090e6cc38 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Apr 2020 09:42:07 -0700 Subject: [PATCH 212/521] Poly overlap doesn't convert to tx device --- compiler/pgates/precharge.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index ee0f96d1..bbde06ad 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -111,7 +111,7 @@ class precharge(design.design): vertical=True) # Hack for li layers - if OPTS.tech_name == "s8": + if hasattr(self, "li_stack"): self.add_via_center(layers=self.li_stack, offset=self.well_contact_pos) @@ -166,7 +166,7 @@ class precharge(design.design): Connects the upper and lower pmos together """ - offset = self.lower_pmos_inst.get_pin("G").ll() + offset = self.lower_pmos_inst.get_pin("G").ul() # connects the top and bottom pmos' gates together ylength = self.upper_pmos1_inst.get_pin("G").ll().y - offset.y self.add_rect(layer="poly", From da334e47aa32ea8e016ba76330053787094a99ea Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Apr 2020 11:14:50 -0700 Subject: [PATCH 213/521] Separate pbitcell tests for precharge --- compiler/tests/04_precharge_pbitcell_test.py | 52 ++++++++++++++++++++ compiler/tests/04_precharge_test.py | 22 +-------- 2 files changed, 53 insertions(+), 21 deletions(-) create mode 100755 compiler/tests/04_precharge_pbitcell_test.py diff --git a/compiler/tests/04_precharge_pbitcell_test.py b/compiler/tests/04_precharge_pbitcell_test.py new file mode 100755 index 00000000..fd2f8283 --- /dev/null +++ b/compiler/tests/04_precharge_pbitcell_test.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class precharge_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check precharge in multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + factory.reset() + debug.info(2, "Checking precharge for pbitcell (innermost connections)") + tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + factory.reset() + debug.info(2, "Checking precharge for pbitcell (innermost connections)") + tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(tx) + + factory.reset() + debug.info(2, "Checking precharge for pbitcell (outermost connections)") + tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 1c12ad8b..76d433a8 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -15,6 +15,7 @@ from globals import OPTS from sram_factory import factory import debug + class precharge_test(openram_test): def runTest(self): @@ -26,27 +27,6 @@ class precharge_test(openram_test): tx = factory.create(module_type="precharge", size=1) self.local_check(tx) - # check precharge in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - - factory.reset() - debug.info(2, "Checking precharge for pbitcell (innermost connections)") - tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(tx) - - factory.reset() - debug.info(2, "Checking precharge for pbitcell (innermost connections)") - tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") - self.local_check(tx) - - factory.reset() - debug.info(2, "Checking precharge for pbitcell (outermost connections)") - tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(tx) - globals.end_openram() # run the test from the command line From 3074cf3b86c150189541416558997029cb2261d4 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Apr 2020 11:15:29 -0700 Subject: [PATCH 214/521] Small format cleanup --- compiler/bitcells/pbitcell.py | 70 ++++++++++++++++++----------------- compiler/pgates/ptx.py | 12 +++--- 2 files changed, 43 insertions(+), 39 deletions(-) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 61bd9710..be96a129 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -7,7 +7,7 @@ # import contact import debug -from tech import drc, parameter +from tech import drc, parameter, layer from vector import vector from ptx import ptx from globals import OPTS @@ -975,42 +975,44 @@ class pbitcell(bitcell_base.bitcell_base): """ Connects wells between ptx modules and places well contacts """ - # extend pwell to encompass entire nmos region of the cell up to the - # height of the tallest nmos transistor - max_nmos_well_height = max(self.inverter_nmos.well_height, - self.readwrite_nmos.well_height, - self.write_nmos.well_height, - self.read_nmos.well_height) - well_height = max_nmos_well_height + self.port_ypos \ - - self.nwell_enclose_active - self.gnd_position.y - # FIXME fudge factor xpos - well_width = self.width + 2*self.nwell_enclose_active - offset = vector(self.leftmost_xpos - self.nwell_enclose_active, self.botmost_ypos) - self.add_rect(layer="pwell", - offset=offset, - width=well_width, - height=well_height) - + if "pwell" in layer: + # extend pwell to encompass entire nmos region of the cell up to the + # height of the tallest nmos transistor + max_nmos_well_height = max(self.inverter_nmos.well_height, + self.readwrite_nmos.well_height, + self.write_nmos.well_height, + self.read_nmos.well_height) + well_height = max_nmos_well_height + self.port_ypos \ + - self.nwell_enclose_active - self.gnd_position.y + # FIXME fudge factor xpos + well_width = self.width + 2*self.nwell_enclose_active + offset = vector(self.leftmost_xpos - self.nwell_enclose_active, self.botmost_ypos) + self.add_rect(layer="pwell", + offset=offset, + width=well_width, + height=well_height) + # extend nwell to encompass inverter_pmos # calculate offset of the left pmos well - inverter_well_xpos = -(self.inverter_nmos.active_width + 0.5 * self.inverter_to_inverter_spacing) \ - - self.nwell_enclose_active - inverter_well_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \ - + self.inverter_gap - self.nwell_enclose_active + if "nwell" in layer: + inverter_well_xpos = -(self.inverter_nmos.active_width + 0.5 * self.inverter_to_inverter_spacing) \ + - self.nwell_enclose_active + inverter_well_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \ + + self.inverter_gap - self.nwell_enclose_active + + # calculate width of the two combined nwells + # calculate height to encompass nimplant connected to vdd + well_width = 2 * (self.inverter_nmos.active_width + 0.5 * self.inverter_to_inverter_spacing) \ + + 2 * self.nwell_enclose_active + well_height = self.vdd_position.y - inverter_well_ypos \ + + self.nwell_enclose_active + drc["minwidth_tx"] - # calculate width of the two combined nwells - # calculate height to encompass nimplant connected to vdd - well_width = 2 * (self.inverter_nmos.active_width + 0.5 * self.inverter_to_inverter_spacing) \ - + 2 * self.nwell_enclose_active - well_height = self.vdd_position.y - inverter_well_ypos \ - + self.nwell_enclose_active + drc["minwidth_tx"] - - # FIXME fudge factor xpos - offset = [inverter_well_xpos + 2*self.nwell_enclose_active, inverter_well_ypos] - self.add_rect(layer="nwell", - offset=offset, - width=well_width, - height=well_height) + # FIXME fudge factor xpos + offset = [inverter_well_xpos + 2*self.nwell_enclose_active, inverter_well_ypos] + self.add_rect(layer="nwell", + offset=offset, + width=well_width, + height=well_height) # add well contacts # connect pimplants to gnd diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 8fbb94d8..b9d04f32 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -196,6 +196,8 @@ class ptx(design.design): # The well is not included in the height and width self.height = self.poly_height self.width = self.active_width + self.well_height = self.height + self.well_width = self.width # This is the center of the first active contact offset (centered vertically) self.contact_offset = self.active_offset + vector(0.5 * self.active_contact.width, @@ -353,10 +355,10 @@ class ptx(design.design): if not (well_name in layer or "vtg" in layer): return - center_pos = self.active_offset + vector(0.5*self.active_width, - 0.5*self.active_height) - well_ll = center_pos - vector(0.5*self.well_width, - 0.5*self.well_height) + center_pos = self.active_offset + vector(0.5 * self.active_width, + 0.5 * self.active_height) + well_ll = center_pos - vector(0.5 * self.well_width, + 0.5 * self.well_height) if well_name in layer: self.add_rect(layer=well_name, offset=well_ll, @@ -450,7 +452,7 @@ class ptx(design.design): contact=self.add_via_center(layers=self.active_stack, offset=pos, size=(1, self.num_contacts), - directions=("V","V"), + directions=("V", "V"), implant_type=self.implant_type, well_type=self.well_type) From 3e41664db6f6c955013221c1683db0b1017d2145 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Apr 2020 11:26:31 -0700 Subject: [PATCH 215/521] Split precharge array to multiport and normal cell --- .../tests/08_precharge_array_1rw1r_test.py | 50 +++++++++++++++++++ compiler/tests/08_precharge_array_test.py | 19 ------- 2 files changed, 50 insertions(+), 19 deletions(-) create mode 100755 compiler/tests/08_precharge_array_1rw1r_test.py diff --git a/compiler/tests/08_precharge_array_1rw1r_test.py b/compiler/tests/08_precharge_array_1rw1r_test.py new file mode 100755 index 00000000..8f51c2d4 --- /dev/null +++ b/compiler/tests/08_precharge_array_1rw1r_test.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class precharge_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check precharge array in multi-port + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + factory.reset() + debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell") + pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(pc) + + # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") + # pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0") + # self.local_check(pc) + + # debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)") + # pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2") + # self.local_check(pc) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index d4f5591b..b301a909 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -25,25 +25,6 @@ class precharge_test(openram_test): debug.info(2, "Checking 3 column precharge") pc = factory.create(module_type="precharge_array", columns=3) self.local_check(pc) - - # check precharge array in multi-port - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 0 - - factory.reset() - debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell") - pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(pc) - - # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") - # pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0") - # self.local_check(pc) - - # debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)") - # pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2") - # self.local_check(pc) globals.end_openram() From 7956b63d9f9cf84f2f27d8397a64a9219fd9ebf9 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Apr 2020 11:26:45 -0700 Subject: [PATCH 216/521] Add licon option to precharge --- compiler/modules/precharge_array.py | 7 ++++--- compiler/pgates/precharge.py | 6 ++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index d5b0e799..af612af4 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -73,11 +73,12 @@ class precharge_array(design.design): def add_layout_pins(self): + en_bar_pin = self.pc_cell.get_pin("en_bar") self.add_layout_pin(text="en_bar", - layer="m1", - offset=self.pc_cell.get_pin("en_bar").ll(), + layer=en_bar_pin.layer, + offset=en_bar_pin.ll(), width=self.width, - height=drc("minwidth_m1")) + height=en_bar_pin.height()) for inst in self.local_insts: self.copy_layout_pin(inst, "vdd") diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index bbde06ad..afe14a05 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -198,6 +198,9 @@ class precharge(design.design): if self.en_layer == "m2": self.add_via_center(layers=self.m1_stack, offset=offset) + if hasattr(self, "li_stack"): + self.add_via_center(layers=self.li_stack, + offset=offset) # adds the en rail on metal1 self.add_layout_pin_segment_center(text="en_bar", @@ -220,6 +223,9 @@ class precharge(design.design): offset=self.well_contact_pos, implant_type="n", well_type="n") + if hasattr(self, "li_stack"): + self.add_via_center(layers=self.li_stack, + offset=self.well_contact_pos) self.height = self.well_contact_pos.y + contact.active_contact.height + self.m1_space From 3b662026d22af05aac792c923a1968ff0724f29d Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Apr 2020 11:36:04 -0700 Subject: [PATCH 217/521] pnand3 constant hack for input separation --- compiler/pgates/pnand3.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 9aa54733..3eeba41e 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -215,7 +215,7 @@ class pnand3(pgate.pgate): position="center") # FIXME: constant hack - self.inputC_yoffset = self.inputB_yoffset - 1.1 * m1_pitch + self.inputC_yoffset = self.inputB_yoffset - 1.15 * m1_pitch self.route_input_gate(self.pmos3_inst, self.nmos3_inst, self.inputC_yoffset, @@ -223,7 +223,7 @@ class pnand3(pgate.pgate): position="center") # FIXME: constant hack - self.inputA_yoffset = self.inputB_yoffset + 1.1 * m1_pitch + self.inputA_yoffset = self.inputB_yoffset + 1.15 * m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, From a9d3548be1b0579c39e3dee6d96a52c30780aafc Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Apr 2020 15:54:06 -0700 Subject: [PATCH 218/521] Refactor drc/lvs error output --- compiler/base/hierarchy_design.py | 28 +++++++++++------------- compiler/characterizer/lib.py | 15 +++++-------- compiler/modules/hierarchical_decoder.py | 14 ++++++++++-- 3 files changed, 30 insertions(+), 27 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index e4c77987..09d7ea9c 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -7,15 +7,11 @@ # import hierarchy_layout import hierarchy_spice -import globals import verify import debug import os from globals import OPTS -import graph_util -total_drc_errors = 0 -total_lvs_errors = 0 class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): """ @@ -51,14 +47,12 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Final verification option does not allow nets to be connected by label. # Unit tests will check themselves. if OPTS.is_unit_test: - return + return ("skipped", "skipped") if not OPTS.check_lvsdrc: - return + return ("skipped", "skipped") # Do not run if disabled in options. if (OPTS.inline_lvsdrc or top_level): - global total_drc_errors - global total_lvs_errors tempspice = "{0}/{1}.sp".format(OPTS.openram_temp,self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name) self.sp_write(tempspice) @@ -68,11 +62,11 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) debug.check(num_drc_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_drc_errors)) debug.check(num_lvs_errors == 0,"LVS failed for {0} with {1} errors(s)".format(self.name,num_lvs_errors)) - total_drc_errors += num_drc_errors - total_lvs_errors += num_lvs_errors os.remove(tempspice) os.remove(tempgds) + + return (num_drc_errors, num_lvs_errors) def DRC(self, final_verification=False): """Checks DRC for a module""" @@ -80,31 +74,35 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Do not run if disabled in options. if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): - global total_drc_errors tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name) self.gds_write(tempgds) num_errors = verify.run_drc(self.name, tempgds, final_verification=final_verification) - total_drc_errors += num_errors debug.check(num_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_error)) os.remove(tempgds) + return num_errors + else: + return "skipped" + def LVS(self, final_verification=False): """Checks LVS for a module""" # Unit tests will check themselves. # Do not run if disabled in options. if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): - global total_lvs_errors tempspice = "{0}/{1}.sp".format(OPTS.openram_temp,self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name) self.sp_write(tempspice) self.gds_write(tempgds) num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) - total_lvs_errors += num_errors debug.check(num_errors == 0,"LVS failed for {0} with {1} error(s)".format(self.name,num_errors)) os.remove(tempspice) - os.remove(tempgds) + os.remove(tempgds) + + return num_errors + else: + return "skipped" def init_graph_params(self): """Initializes parameters relevant to the graph creation""" diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 6d6c6ce5..2742dff2 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -621,17 +621,12 @@ class lib: )) # information of checks - from hierarchy_design import total_drc_errors - from hierarchy_design import total_lvs_errors - DRC = 'skipped' - LVS = 'skipped' - if OPTS.check_lvsdrc: - DRC = str(total_drc_errors) - LVS = str(total_lvs_errors) - - datasheet.write("{0},{1},".format(DRC, LVS)) + (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True, top_level=True) + datasheet.write("{0},{1},".format(drc_errors, lvs_errors)) + # write area - datasheet.write(str(self.sram.width * self.sram.height)+',') + datasheet.write(str(self.sram.width * self.sram.height) + ',') + # write timing information for all ports for port in self.all_ports: #din timings diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 6e98c5e0..ebc67ee6 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -25,8 +25,7 @@ class hierarchical_decoder(design.design): self.pre2x4_inst = [] self.pre3x8_inst = [] - b = factory.create(module_type="bitcell") - self.cell_height = b.height + (self.cell_height, self.cell_multiple) = self.find_decoder_height() self.rows = rows self.num_inputs = math.ceil(math.log(self.rows, 2)) (self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) @@ -35,6 +34,17 @@ class hierarchical_decoder(design.design): if not OPTS.netlist_only: self.create_layout() + def find_decoder_height(self): + b = factory.create(module_type="bitcell") + + cell_height = b.height + and3 = factory.create(module_type="pand3", + height=cell_height) + + # Try to make a nand with a given height + # Default + return (b.height, 1) + def create_netlist(self): self.add_modules() self.setup_netlist_constants() From a3683c5898582c8a0415bc06a86a18d76590986f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Apr 2020 16:39:47 -0700 Subject: [PATCH 219/521] Separate pbitcell from hierarchical decoder --- .../06_hierarchical_decoder_pbitcell_test.py | 73 +++++++++++++++++++ .../tests/06_hierarchical_decoder_test.py | 43 ----------- 2 files changed, 73 insertions(+), 43 deletions(-) create mode 100755 compiler/tests/06_hierarchical_decoder_pbitcell_test.py diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py new file mode 100755 index 00000000..1fb3a3f6 --- /dev/null +++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py @@ -0,0 +1,73 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class hierarchical_decoder_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + # check hierarchical decoder for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + factory.reset() + debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=16) + self.local_check(a) + + factory.reset() + debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=17) + self.local_check(a) + + factory.reset() + debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=23) + self.local_check(a) + + debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=32) + self.local_check(a) + + factory.reset() + debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=65) + self.local_check(a) + + debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=128) + self.local_check(a) + + factory.reset() + debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=341) + self.local_check(a) + + debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)") + a = factory.create(module_type="hierarchical_decoder", rows=512) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index 9d8353f3..ab7e844f 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -63,49 +63,6 @@ class hierarchical_decoder_test(openram_test): a = factory.create(module_type="hierarchical_decoder", rows=512) self.local_check(a) - # check hierarchical decoder for multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - factory.reset() - debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=16) - self.local_check(a) - - factory.reset() - debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=17) - self.local_check(a) - - factory.reset() - debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=23) - self.local_check(a) - - debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=32) - self.local_check(a) - - factory.reset() - debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=65) - self.local_check(a) - - debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=128) - self.local_check(a) - - factory.reset() - debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=341) - self.local_check(a) - - debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=512) - self.local_check(a) - globals.end_openram() # run the test from the command line From 0d6c84036d18ceb1484def9f6760d0cef9cb2571 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 2 Apr 2020 09:47:13 -0700 Subject: [PATCH 220/521] Adjust fudge factor for pin spacing. --- compiler/pgates/pnand3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 3eeba41e..cc6fd0f8 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -223,7 +223,7 @@ class pnand3(pgate.pgate): position="center") # FIXME: constant hack - self.inputA_yoffset = self.inputB_yoffset + 1.15 * m1_pitch + self.inputA_yoffset = self.inputB_yoffset + 1.12 * m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, From 5349323acdda050cf1b020022b0404ead7d56788 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 2 Apr 2020 09:47:39 -0700 Subject: [PATCH 221/521] PEP8 cleanup. DRC/LVS returns errors. --- compiler/base/hierarchy_design.py | 111 +++++++++++++---------- compiler/modules/hierarchical_decoder.py | 18 ++-- compiler/sram/sram_base.py | 2 +- 3 files changed, 75 insertions(+), 56 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 09d7ea9c..5119da2e 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -29,39 +29,42 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): hierarchy_layout.layout.__init__(self, name) self.init_graph_params() - def get_layout_pins(self,inst): + def get_layout_pins(self, inst): """ Return a map of pin locations of the instance offset """ # find the instance for i in self.insts: if i.name == inst.name: break else: - debug.error("Couldn't find instance {0}".format(inst_name),-1) + debug.error("Couldn't find instance {0}".format(inst_name), -1) inst_map = inst.mod.pin_map return inst_map - - def DRC_LVS(self, final_verification=False, top_level=False): + def DRC_LVS(self, final_verification=False, force_check=False): """Checks both DRC and LVS for a module""" # Final verification option does not allow nets to be connected by label. # Unit tests will check themselves. - if OPTS.is_unit_test: + if not force_check and OPTS.is_unit_test: return ("skipped", "skipped") - if not OPTS.check_lvsdrc: + if not force_check and not OPTS.check_lvsdrc: return ("skipped", "skipped") # Do not run if disabled in options. - if (OPTS.inline_lvsdrc or top_level): + if (OPTS.inline_lvsdrc or force_check): - tempspice = "{0}/{1}.sp".format(OPTS.openram_temp,self.name) - tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name) + tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) + tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) self.sp_write(tempspice) self.gds_write(tempgds) - num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) - num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) - debug.check(num_drc_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_drc_errors)) - debug.check(num_lvs_errors == 0,"LVS failed for {0} with {1} errors(s)".format(self.name,num_lvs_errors)) + num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) + num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) + debug.check(num_drc_errors == 0, + "DRC failed for {0} with {1} error(s)".format(self.name, + num_drc_errors)) + debug.check(num_lvs_errors == 0, + "LVS failed for {0} with {1} errors(s)".format(self.name, + num_lvs_errors)) os.remove(tempspice) os.remove(tempgds) @@ -74,10 +77,12 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Do not run if disabled in options. if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): - tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name) + tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) self.gds_write(tempgds) - num_errors = verify.run_drc(self.name, tempgds, final_verification=final_verification) - debug.check(num_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_error)) + num_errors = verify.run_drc(self.name, tempgds, final_verification=final_verification) + debug.check(num_errors == 0, + "DRC failed for {0} with {1} error(s)".format(self.name, + num_errors)) os.remove(tempgds) @@ -91,12 +96,14 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Do not run if disabled in options. if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): - tempspice = "{0}/{1}.sp".format(OPTS.openram_temp,self.name) - tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name) + tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) + tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) self.sp_write(tempspice) self.gds_write(tempgds) num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) - debug.check(num_errors == 0,"LVS failed for {0} with {1} error(s)".format(self.name,num_errors)) + debug.check(num_errors == 0, + "LVS failed for {0} with {1} error(s)".format(self.name, + num_errors)) os.remove(tempspice) os.remove(tempgds) @@ -106,40 +113,44 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): def init_graph_params(self): """Initializes parameters relevant to the graph creation""" - #Only initializes a set for checking instances which should not be added + # Only initializes a set for checking instances which should not be added self.graph_inst_exclude = set() - def build_graph(self, graph, inst_name, port_nets): + def build_graph(self, graph, inst_name, port_nets): """Recursively create graph from instances in module.""" - #Translate port names to external nets + # Translate port names to external nets if len(port_nets) != len(self.pins): - debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,self.pins),1) - port_dict = {pin:port for pin,port in zip(self.pins, port_nets)} + debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets, + self.pins), + 1) + port_dict = {pin: port for pin, port in zip(self.pins, port_nets)} debug.info(3, "Instance name={}".format(inst_name)) for subinst, conns in zip(self.insts, self.conns): if subinst in self.graph_inst_exclude: continue - subinst_name = inst_name+'.X'+subinst.name + subinst_name = inst_name + '.X' + subinst.name subinst_ports = self.translate_nets(conns, port_dict, inst_name) subinst.mod.build_graph(graph, subinst_name, subinst_ports) def build_names(self, name_dict, inst_name, port_nets): """Collects all the nets and the parent inst of that net.""" - #Translate port names to external nets + # Translate port names to external nets if len(port_nets) != len(self.pins): - debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,self.pins),1) - port_dict = {pin:port for pin,port in zip(self.pins, port_nets)} + debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets, + self.pins), + 1) + port_dict = {pin: port for pin, port in zip(self.pins, port_nets)} debug.info(3, "Instance name={}".format(inst_name)) for subinst, conns in zip(self.insts, self.conns): - subinst_name = inst_name+'.X'+subinst.name + subinst_name = inst_name + '.X' + subinst.name subinst_ports = self.translate_nets(conns, port_dict, inst_name) for si_port, conn in zip(subinst_ports, conns): - #Only add for first occurrence + # Only add for first occurrence if si_port.lower() not in name_dict: - mod_info = {'mod':self, 'int_net':conn} + mod_info = {'mod': self, 'int_net': conn} name_dict[si_port.lower()] = mod_info - subinst.mod.build_names(name_dict, subinst_name, subinst_ports) + subinst.mod.build_names(name_dict, subinst_name, subinst_ports) def find_aliases(self, inst_name, port_nets, path_nets, alias, alias_mod, exclusion_set=None): """Given a list of nets, will compare the internal alias of a mod to determine @@ -159,17 +170,17 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): int_mod = self.name_dict[net]['mod'] if int_mod.is_net_alias(int_net, alias, alias_mod, exclusion_set): aliases.append(net) - return aliases + return aliases def is_net_alias(self, known_net, net_alias, mod, exclusion_set): """Checks if the alias_net in input mod is the same as the input net for this mod (self).""" if self in exclusion_set: return False - #Check ports of this mod + # Check ports of this mod for pin in self.pins: if self.is_net_alias_name_check(known_net, pin, net_alias, mod): return True - #Check connections of all other subinsts + # Check connections of all other subinsts mod_set = set() for subinst, inst_conns in zip(self.insts, self.conns): for inst_conn, mod_pin in zip(inst_conns, subinst.mod.pins): @@ -179,7 +190,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if subinst.mod.is_net_alias(mod_pin, net_alias, mod, exclusion_set): return True mod_set.add(subinst.mod) - return False + return False def is_net_alias_name_check(self, parent_net, child_net, alias_net, mod): """Utility function for checking single net alias.""" @@ -188,8 +199,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): parent_net.lower() == alias_net.lower() def get_mod_net(self, parent_net, child_inst, child_conns): - """Given an instance and net, returns the internal net in the mod - corresponding to input net.""" + """ + Given an instance and net, returns the internal net in the mod + corresponding to input net. + """ for conn, pin in zip(child_conns, child_inst.mod.pins): if parent_net.lower() == conn.lower(): return pin @@ -203,27 +216,27 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): converted_conns.append(port_dict[conn]) else: converted_conns.append("{}.{}".format(inst_name, conn)) - return converted_conns + return converted_conns def add_graph_edges(self, graph, port_nets): """For every input, adds an edge to every output. Only intended to be used for gates and other simple modules.""" - #The final pin names will depend on the spice hierarchy, so - #they are passed as an input. - pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} + # The final pin names will depend on the spice hierarchy, so + # they are passed as an input. + pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} input_pins = self.get_inputs() output_pins = self.get_outputs() inout_pins = self.get_inouts() - for inp in input_pins+inout_pins: - for out in output_pins+inout_pins: - if inp != out: #do not add self loops - graph.add_edge(pin_dict[inp], pin_dict[out], self) + for inp in input_pins + inout_pins: + for out in output_pins + inout_pins: + if inp != out: # do not add self loops + graph.add_edge(pin_dict[inp], pin_dict[out], self) def __str__(self): """ override print function output """ pins = ",".join(self.pins) insts = [" {}".format(x) for x in self.insts] - objs = [" {}".format(x) for x in self.objs] + objs = [" {}".format(x) for x in self.objs] s = "********** design {0} **********".format(self.name) s += "\n pins ({0})={1}\n".format(len(self.pins), pins) s += "\n objs ({0})=\n{1}\n".format(len(self.objs), "\n".join(objs)) @@ -234,8 +247,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): """ override print function output """ text="( design: " + self.name + " pins=" + str(self.pins) + " " + str(self.width) + "x" + str(self.height) + " )\n" for i in self.objs: - text+=str(i)+",\n" + text+=str(i) + ",\n" for i in self.insts: - text+=str(i)+",\n" + text+=str(i) + ",\n" return text diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index ebc67ee6..fbc3e535 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -37,13 +37,19 @@ class hierarchical_decoder(design.design): def find_decoder_height(self): b = factory.create(module_type="bitcell") - cell_height = b.height - and3 = factory.create(module_type="pand3", - height=cell_height) - - # Try to make a nand with a given height - # Default return (b.height, 1) + + cell_multiple = 1 + while cell_multiple < 3: + cell_height = cell_multiple * b.height + and3 = factory.create(module_type="pand3", + height=cell_height) + (drc_errors, lvs_errors) = and3.DRC_LVS(force_check=True) + if drc_errors + lvs_errors == 0: + return (cell_height, cell_multiple) + cell_multiple += 1 + else: + debug.error("Couldn't find a valid decoder height multiple.", -1) def create_netlist(self): self.add_modules() diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index e8a91486..38f89bc6 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -121,7 +121,7 @@ class sram_base(design, verilog, lef): start_time = datetime.datetime.now() # We only enable final verification if we have routed the design - self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) + self.DRC_LVS(final_verification=OPTS.route_supplies, roce_check=True) if not OPTS.is_unit_test: print_time("Verification", datetime.datetime.now(), start_time) From 9106e22b58d8241178c0aefa1651e486d79075ba Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 2 Apr 2020 10:37:21 -0700 Subject: [PATCH 222/521] Fix typo and syntax error. --- compiler/sram/sram_base.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 38f89bc6..81f71775 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -121,7 +121,7 @@ class sram_base(design, verilog, lef): start_time = datetime.datetime.now() # We only enable final verification if we have routed the design - self.DRC_LVS(final_verification=OPTS.route_supplies, roce_check=True) + self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=True) if not OPTS.is_unit_test: print_time("Verification", datetime.datetime.now(), start_time) From 67de7efd49933c5d95c134130013abcf366b6127 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 2 Apr 2020 11:31:28 -0700 Subject: [PATCH 223/521] Fix syntax error. No DRC/LVS in netlist only mode. --- compiler/base/hierarchy_design.py | 18 +++++++++++++++--- compiler/characterizer/lib.py | 2 +- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 5119da2e..e06b1d6f 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -42,8 +42,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): def DRC_LVS(self, final_verification=False, force_check=False): """Checks both DRC and LVS for a module""" - - # Final verification option does not allow nets to be connected by label. + + # No layout to check + if OPTS.netlist_only: + return ("skipped", "skipped") # Unit tests will check themselves. if not force_check and OPTS.is_unit_test: return ("skipped", "skipped") @@ -56,7 +58,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) self.sp_write(tempspice) self.gds_write(tempgds) - + # Final verification option does not allow nets to be connected by label. num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) debug.check(num_drc_errors == 0, @@ -70,12 +72,18 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): os.remove(tempgds) return (num_drc_errors, num_lvs_errors) + else: + return ("skipped", "skipped") def DRC(self, final_verification=False): """Checks DRC for a module""" # Unit tests will check themselves. # Do not run if disabled in options. + # No layout to check + if OPTS.netlist_only: + return "skipped" + if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) self.gds_write(tempgds) @@ -95,6 +103,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Unit tests will check themselves. # Do not run if disabled in options. + # No layout to check + if OPTS.netlist_only: + return "skipped" + if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 2742dff2..8f829fae 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -621,7 +621,7 @@ class lib: )) # information of checks - (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True, top_level=True) + (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True, force_check=True) datasheet.write("{0},{1},".format(drc_errors, lvs_errors)) # write area From 1d5e5e3607b3f0af40de3b21d31c3dd4d439bbd5 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 2 Apr 2020 12:42:28 -0700 Subject: [PATCH 224/521] Don't run lvs/drc or route supplies in verilog test --- compiler/tests/25_verilog_sram_test.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index c385e455..bcaa7c9f 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -19,7 +19,9 @@ class verilog_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - + OPTS.route_supplies=False + OPTS.check_lvsdrc=False + from sram import sram from sram_config import sram_config c = sram_config(word_size=2, From f105c9ab3608a2b891d63a7c4ac89abb28fb418f Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 2 Apr 2020 12:43:19 -0700 Subject: [PATCH 225/521] Netlist only in verilog test --- compiler/tests/25_verilog_sram_test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index bcaa7c9f..120974ff 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -21,7 +21,7 @@ class verilog_test(openram_test): globals.init_openram(config_file) OPTS.route_supplies=False OPTS.check_lvsdrc=False - + OPTS.netlist_only=True from sram import sram from sram_config import sram_config c = sram_config(word_size=2, From 2850b9efb5d333920700d41a1a40197c4423425c Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 2 Apr 2020 12:52:42 -0700 Subject: [PATCH 226/521] Don't force check in lib characterization. PEP8 formatting. --- compiler/base/hierarchy_design.py | 18 +++++++++++------- compiler/characterizer/lib.py | 2 +- compiler/modules/hierarchical_decoder.py | 5 +++-- compiler/sram/sram_base.py | 2 +- compiler/verify/none.py | 16 ++++++++++++---- 5 files changed, 28 insertions(+), 15 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index e06b1d6f..82682b71 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -52,7 +52,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if not force_check and not OPTS.check_lvsdrc: return ("skipped", "skipped") # Do not run if disabled in options. - if (OPTS.inline_lvsdrc or force_check): + if (OPTS.inline_lvsdrc or force_check or final_verification): tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) @@ -61,12 +61,16 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Final verification option does not allow nets to be connected by label. num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) - debug.check(num_drc_errors == 0, - "DRC failed for {0} with {1} error(s)".format(self.name, - num_drc_errors)) - debug.check(num_lvs_errors == 0, - "LVS failed for {0} with {1} errors(s)".format(self.name, - num_lvs_errors)) + + # force_check is used to determine decoder height and other things, so we shouldn't fail + # if that flag is set + if OPTS.inline_lvsdrc and not force_check: + debug.check(num_drc_errors == 0, + "DRC failed for {0} with {1} error(s)".format(self.name, + num_drc_errors)) + debug.check(num_lvs_errors == 0, + "LVS failed for {0} with {1} errors(s)".format(self.name, + num_lvs_errors)) os.remove(tempspice) os.remove(tempgds) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 8f829fae..37e27c23 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -621,7 +621,7 @@ class lib: )) # information of checks - (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True, force_check=True) + (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True) datasheet.write("{0},{1},".format(drc_errors, lvs_errors)) # write area diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index fbc3e535..0a54a401 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -36,9 +36,10 @@ class hierarchical_decoder(design.design): def find_decoder_height(self): b = factory.create(module_type="bitcell") - + # Old behavior return (b.height, 1) - + + # Search for the smallest multiple that works cell_multiple = 1 while cell_multiple < 3: cell_height = cell_multiple * b.height diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 81f71775..563d128c 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -121,7 +121,7 @@ class sram_base(design, verilog, lef): start_time = datetime.datetime.now() # We only enable final verification if we have routed the design - self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=True) + self.DRC_LVS(final_verification=OPTS.route_supplies) if not OPTS.is_unit_test: print_time("Verification", datetime.datetime.now(), start_time) diff --git a/compiler/verify/none.py b/compiler/verify/none.py index 9d7ac938..41e5780e 100644 --- a/compiler/verify/none.py +++ b/compiler/verify/none.py @@ -16,14 +16,16 @@ drc_warned = False lvs_warned = False pex_warned = False + def run_drc(cell_name, gds_name, extract=False, final_verification=False): global drc_warned if not drc_warned: debug.warning("DRC unable to run.") drc_warned=True - # Since we warned, return a failing test. + # Since we warned, return a failing test. return 1 - + + def run_lvs(cell_name, gds_name, sp_name, final_verification=False): global lvs_warned if not lvs_warned: @@ -32,17 +34,23 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): # Since we warned, return a failing test. return 1 + def run_pex(name, gds_name, sp_name, output=None, final_verification=False): - global pex_warned + global pex_warned if not pex_warned: debug.warning("PEX unable to run.") pex_warned=True - # Since we warned, return a failing test. + # Since we warned, return a failing test. return 1 + def print_drc_stats(): pass + + def print_lvs_stats(): pass + + def print_pex_stats(): pass From 8603d3edd6ee0ce3a910de90ca2602628652f9e9 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 3 Apr 2020 11:37:06 -0700 Subject: [PATCH 227/521] PEP8 cleanup --- compiler/base/hierarchy_spice.py | 166 +++++++++++++++++-------------- 1 file changed, 89 insertions(+), 77 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 707e7bc8..ee8844c2 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -15,6 +15,7 @@ from wire_spice_model import * from power_data import * import logical_effort + class spice(): """ This provides a set of useful generic types for hierarchy @@ -30,19 +31,19 @@ class spice(): self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "POWER", "GROUND"] # Holds subckts/mods for this module - self.mods = [] + self.mods = [] # Holds the pins for this module self.pins = [] # The type map of each pin: INPUT, OUTPUT, INOUT, POWER, GROUND # for each instance, this is the set of nets/nodes that map to the pins for this instance - self.pin_type = {} + self.pin_type = {} # THE CONNECTIONS MUST MATCH THE ORDER OF THE PINS (restriction imposed by the # Spice format) self.conns = [] # Keep track of any comments to add the the spice try: self.commments - except: + except NameError: self.comments = [] self.sp_read() @@ -56,7 +57,7 @@ class spice(): try: self.commments - except: + except NameError: self.comments = [] self.comments.append(comment) @@ -65,7 +66,9 @@ class spice(): """ Adds a pin to the pins list. Default type is INOUT signal. """ self.pins.append(name) self.pin_type[name]=pin_type - debug.check(pin_type in self.valid_signal_types, "Invalid signaltype for {0}: {1}".format(name,pin_type)) + debug.check(pin_type in self.valid_signal_types, + "Invalid signaltype for {0}: {1}".format(name, + pin_type)) def add_pin_list(self, pin_list, pin_type="INOUT"): """ Adds a pin_list to the pins list """ @@ -73,36 +76,43 @@ class spice(): # or a list that is the same length as the pin list. if type(pin_type)==str: for pin in pin_list: - debug.check(pin_type in self.valid_signal_types, "Invalid signaltype for {0}: {1}".format(pin,pin_type)) - self.add_pin(pin,pin_type) + debug.check(pin_type in self.valid_signal_types, + "Invalid signaltype for {0}: {1}".format(pin, + pin_type)) + self.add_pin(pin, pin_type) elif len(pin_type)==len(pin_list): - for (pin,ptype) in zip(pin_list, pin_type): - debug.check(ptype in self.valid_signal_types, "Invalid signaltype for {0}: {1}".format(pin,ptype)) - self.add_pin(pin,ptype) + for (pin, ptype) in zip(pin_list, pin_type): + debug.check(ptype in self.valid_signal_types, + "Invalid signaltype for {0}: {1}".format(pin, + ptype)) + self.add_pin(pin, ptype) else: debug.error("Mismatch in type and pin list lengths.", -1) def add_pin_types(self, type_list): - """Add pin types for all the cell's pins. - Typically, should only be used for handmade cells.""" - #This only works if self.pins == bitcell.pin_names + """ + Add pin types for all the cell's pins. + Typically, should only be used for handmade cells. + """ + # This only works if self.pins == bitcell.pin_names if self.pin_names != self.pins: debug.error("{} spice subcircuit port names do not match pin_names\ \n SPICE names={}\ \n Module names={}\ - ".format(self.name, self.pin_names, self.pins),1) - self.pin_type = {pin:type for pin,type in zip(self.pin_names, type_list)} + ".format(self.name, self.pin_names, self.pins), 1) + self.pin_type = {pin: type for pin, type in zip(self.pin_names, type_list)} def get_pin_type(self, name): """ Returns the type of the signal pin. """ pin_type = self.pin_type[name] - debug.check(pin_type in self.valid_signal_types, "Invalid signaltype for {0}: {1}".format(name,pin_type)) + debug.check(pin_type in self.valid_signal_types, + "Invalid signaltype for {0}: {1}".format(name, pin_type)) return pin_type def get_pin_dir(self, name): """ Returns the direction of the pin. (Supply/ground are INOUT). """ - if self.pin_type[name] in ["POWER","GROUND"]: + if self.pin_type[name] in ["POWER", "GROUND"]: return "INOUT" else: return self.pin_type[name] @@ -125,11 +135,10 @@ class spice(): output_list.append(pin) return output_list - def copy_pins(self, other_module, suffix=""): """ This will copy all of the pins from the other module and add an optional suffix.""" for pin in other_module.pins: - self.add_pin(pin+suffix, other_module.get_pin_type(pin)) + self.add_pin(pin + suffix, other_module.get_pin_type(pin)) def get_inouts(self): """ These use pin types to determine pin lists. These @@ -144,7 +153,6 @@ class spice(): """Adds a subckt/submodule to the subckt hierarchy""" self.mods.append(mod) - def connect_inst(self, args, check=True): """Connects the pins of the last instance added It is preferred to use the function with the check to find if @@ -169,21 +177,23 @@ class spice(): debug.error("{0} : Not all instance pins ({1}) are connected ({2}).".format(self.name, len(self.insts), len(self.conns))) - debug.error("Instances: \n"+str(insts_string)) + debug.error("Instances: \n" + str(insts_string)) debug.error("-----") - debug.error("Connections: \n"+str(conns_string),1) + debug.error("Connections: \n" + str(conns_string), 1) def get_conns(self, inst): """Returns the connections of a given instance.""" for i in range(len(self.insts)): if inst is self.insts[i]: return self.conns[i] - #If not found, returns None + # If not found, returns None return None def sp_read(self): - """Reads the sp file (and parse the pins) from the library - Otherwise, initialize it to null for dynamic generation""" + """ + Reads the sp file (and parse the pins) from the library + Otherwise, initialize it to null for dynamic generation + """ if self.sp_file and os.path.isfile(self.sp_file): debug.info(3, "opening {0}".format(self.sp_file)) f = open(self.sp_file) @@ -202,13 +212,14 @@ class spice(): def check_net_in_spice(self, net_name): """Checks if a net name exists in the current. Intended to be check nets in hand-made cells.""" - #Remove spaces and lower case then add spaces. Nets are separated by spaces. - net_formatted = ' '+net_name.lstrip().rstrip().lower()+' ' + # Remove spaces and lower case then add spaces. + # Nets are separated by spaces. + net_formatted = ' ' + net_name.lstrip().rstrip().lower() + ' ' for line in self.spice: - #Lowercase the line and remove any part of the line that is a comment. + # Lowercase the line and remove any part of the line that is a comment. line = line.lower().split('*')[0] - #Skip .subckt or .ENDS lines + # Skip .subckt or .ENDS lines if line.find('.') == 0: continue if net_formatted in line: @@ -220,7 +231,7 @@ class spice(): nets_match = True for net in nets: nets_match = nets_match and self.check_net_in_spice(net) - return nets_match + return nets_match def contains(self, mod, modlist): for x in modlist: @@ -244,34 +255,31 @@ class spice(): if self.pins == []: return - # write out the first spice line (the subcircuit) sp.write("\n.SUBCKT {0} {1}\n".format(self.name, " ".join(self.pins))) for pin in self.pins: - sp.write("* {1:6}: {0} \n".format(pin,self.pin_type[pin])) + sp.write("* {1:6}: {0} \n".format(pin, self.pin_type[pin])) for line in self.comments: sp.write("* {}\n".format(line)) # every instance must have a set of connections, even if it is empty. - if len(self.insts)!=len(self.conns): + if len(self.insts) != len(self.conns): debug.error("{0} : Not all instance pins ({1}) are connected ({2}).".format(self.name, len(self.insts), len(self.conns))) - debug.error("Instances: \n"+str(self.insts)) + debug.error("Instances: \n" + str(self.insts)) debug.error("-----") - debug.error("Connections: \n"+str(self.conns),1) - - + debug.error("Connections: \n" + str(self.conns), 1) for i in range(len(self.insts)): # we don't need to output connections of empty instances. # these are wires and paths if self.conns[i] == []: continue - if hasattr(self.insts[i].mod,"spice_device"): + if hasattr(self.insts[i].mod, "spice_device"): sp.write(self.insts[i].mod.spice_device.format(self.insts[i].name, " ".join(self.conns[i]))) sp.write("\n") @@ -286,7 +294,7 @@ class spice(): else: # write the subcircuit itself # Including the file path makes the unit test fail for other users. - #if os.path.isfile(self.sp_file): + # if os.path.isfile(self.sp_file): # sp.write("\n* {0}\n".format(self.sp_file)) sp.write("\n".join(self.spice)) @@ -305,7 +313,8 @@ class spice(): def analytical_delay(self, corner, slew, load=0.0): """Inform users undefined delay module while building new modules""" - # FIXME: Slew is not used in the model right now. Can be added heuristically as linear factor + # FIXME: Slew is not used in the model right now. + # Can be added heuristically as linear factor relative_cap = logical_effort.convert_farad_to_relative_c(load) stage_effort = self.get_stage_effort(relative_cap) @@ -316,7 +325,7 @@ class spice(): abs_delay = stage_effort.get_absolute_delay() corner_delay = self.apply_corners_analytically(abs_delay, corner) SLEW_APPROXIMATION = 0.1 - corner_slew = SLEW_APPROXIMATION*corner_delay + corner_slew = SLEW_APPROXIMATION * corner_delay return delay_data(corner_delay, corner_slew) def get_stage_effort(self, cout, inp_is_rise=True): @@ -326,7 +335,7 @@ class spice(): debug.warning("Class {0} name {1}" .format(self.__class__.__name__, self.name)) - return None + return None def get_cin(self): """Returns input load in Femto-Farads. All values generated using @@ -342,35 +351,35 @@ class spice(): debug.warning("Design Class {0} input capacitance function needs to be defined" .format(self.__class__.__name__)) debug.warning("Class {0} name {1}" - .format(self.__class__.__name__, - self.name)) - return 0 + .format(self.__class__.__name__, + self.name)) + return 0 - def cal_delay_with_rc(self, corner, r, c ,slew, swing = 0.5): - """ - Calculate the delay of a mosfet by + def cal_delay_with_rc(self, corner, r, c, slew, swing=0.5): + """ + Calculate the delay of a mosfet by modeling it as a resistance driving a capacitance """ - swing_factor = abs(math.log(1-swing)) # time constant based on swing - delay = swing_factor * r * c #c is in ff and delay is in fs + swing_factor = abs(math.log(1 - swing)) # time constant based on swing + delay = swing_factor * r * c # c is in ff and delay is in fs delay = self.apply_corners_analytically(delay, corner) - delay = delay * 0.001 #make the unit to ps + delay = delay * 0.001 # make the unit to ps - # Output slew should be linear to input slew which is described + # Output slew should be linear to input slew which is described # as 0.005* slew. # The slew will be also influenced by the delay. - # If no input slew(or too small to make impact) - # The mimum slew should be the time to charge RC. + # If no input slew(or too small to make impact) + # The mimum slew should be the time to charge RC. # Delay * 2 is from 0 to 100% swing. 0.6*2*delay is from 20%-80%. slew = delay * 0.6 * 2 + 0.005 * slew - return delay_data(delay = delay, slew = slew) + return delay_data(delay=delay, slew=slew) def apply_corners_analytically(self, delay, corner): """Multiply delay by corner factors""" - proc,vdd,temp = corner - #FIXME: type of delay is needed to know which process to use. - proc_mult = max(self.get_process_delay_factor(proc)) + proc, vdd, temp = corner + # FIXME: type of delay is needed to know which process to use. + proc_mult = max(self.get_process_delay_factor(proc)) volt_mult = self.get_voltage_delay_factor(vdd) temp_mult = self.get_temp_delay_factor(temp) return delay * proc_mult * volt_mult * temp_mult @@ -385,48 +394,51 @@ class spice(): elif mos_proc == 'F': proc_factors.append(0.9) elif mos_proc == 'S': - proc_factors.append(1.1) + proc_factors.append(1.1) return proc_factors def get_voltage_delay_factor(self, voltage): """Returns delay increase due to voltage. Implemented as linear factor based off nominal voltage. """ - return tech.spice["nom_supply_voltage"]/voltage + return tech.spice["nom_supply_voltage"] / voltage def get_temp_delay_factor(self, temp): """Returns delay increase due to temperature (in C). Determines effect on threshold voltage and then linear factor is estimated. """ - #Some portions of equation condensed (phi_t = k*T/q for T in Kelvin) in mV - #(k/q)/100 = .008625, The division 100 simplifies the conversion from C to K and mV to V - thermal_voltage_nom = 0.008625*tech.spice["nom_temperature"] - thermal_voltage = 0.008625*temp - vthresh = (tech.spice["nom_threshold"]+2*(thermal_voltage-thermal_voltage_nom)) - #Calculate effect on Vdd-Vth. The current vdd is not used here. A separate vdd factor is calculated. - return (tech.spice["nom_supply_voltage"] - tech.spice["nom_threshold"])/(tech.spice["nom_supply_voltage"]-vthresh) + # Some portions of equation condensed (phi_t = k*T/q for T in Kelvin) in mV + # (k/q)/100 = .008625, The division 100 simplifies the conversion from C to K and mV to V + thermal_voltage_nom = 0.008625 * tech.spice["nom_temperature"] + thermal_voltage = 0.008625 * temp + vthresh = (tech.spice["nom_threshold"] + 2 * (thermal_voltage - thermal_voltage_nom)) + # Calculate effect on Vdd-Vth. + # The current vdd is not used here. + # A separate vdd factor is calculated. + return (tech.spice["nom_supply_voltage"] - tech.spice["nom_threshold"]) / (tech.spice["nom_supply_voltage"] - vthresh) def return_delay(self, delay, slew): return delay_data(delay, slew) - def generate_rc_net(self,lump_num, wire_length, wire_width): + def generate_rc_net(self, lump_num, wire_length, wire_width): return wire_spice_model(lump_num, wire_length, wire_width) def calc_dynamic_power(self, corner, c, freq, swing=1.0): - """ + """ Calculate dynamic power using effective capacitance, frequency, and corner (PVT) """ - proc,vdd,temp = corner - net_vswing = vdd*swing - power_dyn = c*vdd*net_vswing*freq + proc, vdd, temp = corner + net_vswing = vdd * swing + power_dyn = c * vdd * net_vswing * freq - #Apply process and temperature factors. Roughly, process and Vdd affect the delay which affects the power. - #No other estimations are currently used. Increased delay->slower freq.->less power - proc_div = max(self.get_process_delay_factor(proc)) + # A pply process and temperature factors. + # Roughly, process and Vdd affect the delay which affects the power. + # No other estimations are currently used. Increased delay->slower freq.->less power + proc_div = max(self.get_process_delay_factor(proc)) temp_div = self.get_temp_delay_factor(temp) - power_dyn = power_dyn/(proc_div*temp_div) + power_dyn = power_dyn / (proc_div * temp_div) - return power_dyn + return power_dyn def return_power(self, dynamic=0.0, leakage=0.0): return power_data(dynamic, leakage) From f358de78bb714d11859d147b7e9dc3984adf4e61 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 3 Apr 2020 13:39:54 -0700 Subject: [PATCH 228/521] Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation) --- compiler/base/hierarchy_design.py | 12 +++++-- compiler/base/hierarchy_spice.py | 47 +++++++++++++++++++++++---- compiler/sram/sram_base.py | 4 +-- compiler/tests/02_library_lvs_test.py | 4 ++- 4 files changed, 55 insertions(+), 12 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 82682b71..bb57ae3e 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -24,6 +24,14 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): self.gds_file = OPTS.openram_tech + "gds_lib/" + name + ".gds" self.sp_file = OPTS.openram_tech + "sp_lib/" + name + ".sp" + # If we have a separate lvs directory, then all the lvs files + # should be in there (all or nothing!) + lvs_dir = OPTS.openram_tech + "lvs_lib/" + if os.path.exists(lvs_dir): + self.lvs_file = lvs_dir + name + ".sp" + else: + self.lvs_file = self.sp_file + self.name = name hierarchy_spice.spice.__init__(self, name) hierarchy_layout.layout.__init__(self, name) @@ -56,7 +64,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) - self.sp_write(tempspice) + self.lvs_write(tempspice) self.gds_write(tempgds) # Final verification option does not allow nets to be connected by label. num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) @@ -114,7 +122,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) - self.sp_write(tempspice) + self.lvs_write(tempspice) self.gds_write(tempgds) num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) debug.check(num_errors == 0, diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index ee8844c2..b69888e4 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -43,7 +43,7 @@ class spice(): # Keep track of any comments to add the the spice try: self.commments - except NameError: + except AttributeError: self.comments = [] self.sp_read() @@ -57,7 +57,7 @@ class spice(): try: self.commments - except NameError: + except AttributeError: self.comments = [] self.comments.append(comment) @@ -210,6 +210,24 @@ class spice(): else: self.spice = [] + # We don't define self.lvs and will use self.spice if dynamically created + # or they are the same file + if self.lvs_file!=self.sp_file and os.path.isfile(self.lvs_file): + debug.info(3, "opening {0}".format(self.lvs_file)) + f = open(self.lvs_file) + self.lvs = f.readlines() + for i in range(len(self.lvs)): + self.lvs[i] = self.lvs[i].rstrip(" \n") + f.close() + + # pins and subckt should be the same + # find the correct subckt line in the file + subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE) + subckt_line = list(filter(subckt.search, self.lvs))[0] + # parses line into ports and remove subckt + lvs_pins = subckt_line.split(" ")[2:] + debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.", -1) + def check_net_in_spice(self, net_name): """Checks if a net name exists in the current. Intended to be check nets in hand-made cells.""" # Remove spaces and lower case then add spaces. @@ -239,16 +257,18 @@ class spice(): return True return False - def sp_write_file(self, sp, usedMODS): - """ Recursive spice subcircuit write; - Writes the spice subcircuit from the library or the dynamically generated one""" + def sp_write_file(self, sp, usedMODS, lvs_netlist=False): + """ + Recursive spice subcircuit write; + Writes the spice subcircuit from the library or the dynamically generated one + """ if not self.spice: # recursively write the modules for i in self.mods: if self.contains(i, usedMODS): continue usedMODS.append(i) - i.sp_write_file(sp, usedMODS) + i.sp_write_file(sp, usedMODS, lvs_netlist) if len(self.insts) == 0: return @@ -296,7 +316,10 @@ class spice(): # Including the file path makes the unit test fail for other users. # if os.path.isfile(self.sp_file): # sp.write("\n* {0}\n".format(self.sp_file)) - sp.write("\n".join(self.spice)) + if lvs_netlist: + sp.write("\n".join(self.lvs)) + else: + sp.write("\n".join(self.spice)) sp.write("\n") @@ -310,6 +333,16 @@ class spice(): del usedMODS spfile.close() + def lvs_write(self, spname): + """Writes the lvs to files""" + debug.info(3, "Writing to {0}".format(spname)) + spfile = open(spname, 'w') + spfile.write("*FIRST LINE IS A COMMENT\n") + usedMODS = list() + self.sp_write_file(spfile, usedMODS, True) + del usedMODS + spfile.close() + def analytical_delay(self, corner, slew, load=0.0): """Inform users undefined delay module while building new modules""" diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 563d128c..64e3f51b 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -574,11 +574,11 @@ class sram_base(design, verilog, lef): sp.write("* Data bits: {}\n".format(self.word_size)) sp.write("* Banks: {}\n".format(self.num_banks)) sp.write("* Column mux: {}:1\n".format(self.words_per_row)) - sp.write("**************************************************\n") + sp.write("**************************************************\n") # This causes unit test mismatch # sp.write("* Created: {0}\n".format(datetime.datetime.now())) # sp.write("* User: {0}\n".format(getpass.getuser())) - # sp.write(".global {0} {1}\n".format(spice["vdd_name"], + # sp.write(".global {0} {1}\n".format(spice["vdd_name"], # spice["gnd_name"])) usedMODS = list() self.sp_write_file(sp, usedMODS) diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 35ac5d76..0acc8926 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -45,7 +45,9 @@ class library_lvs_test(openram_test): def setup_files(): gds_dir = OPTS.openram_tech + "/gds_lib" - sp_dir = OPTS.openram_tech + "/sp_lib" + sp_dir = OPTS.openram_tech + "/lvs_lib" + if not os.path.exists(sp_dir): + sp_dir = OPTS.openram_tech + "/sp_lib" files = os.listdir(gds_dir) nametest = re.compile("\.gds$", re.IGNORECASE) gds_files = list(filter(nametest.search, files)) From ab5dd47182b59bef7941156d46fd66c9538adb88 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 3 Apr 2020 14:06:56 -0700 Subject: [PATCH 229/521] Ptx is in microns if lvs_lib exists --- compiler/base/hierarchy_spice.py | 7 +++++-- compiler/pgates/ptx.py | 12 +++++++++--- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index b69888e4..beb79ded 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -299,11 +299,14 @@ class spice(): # these are wires and paths if self.conns[i] == []: continue - if hasattr(self.insts[i].mod, "spice_device"): + if lvs_netlist and hasattr(self.insts[i].mod, "lvs_device"): + sp.write(self.insts[i].mod.lvs_device.format(self.insts[i].name, + " ".join(self.conns[i]))) + sp.write("\n") + elif hasattr(self.insts[i].mod, "spice_device"): sp.write(self.insts[i].mod.spice_device.format(self.insts[i].name, " ".join(self.conns[i]))) sp.write("\n") - else: sp.write("X{0} {1} {2}\n".format(self.insts[i].name, " ".join(self.conns[i]), diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index b9d04f32..3ed51651 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -11,6 +11,8 @@ from tech import layer, drc, spice from vector import vector from sram_factory import factory import contact +import os +from globals import OPTS class ptx(design.design): @@ -100,8 +102,6 @@ class ptx(design.design): dir_list = ['INOUT', 'INPUT', 'INOUT', body_dir] self.add_pin_list(pin_list, dir_list) - # self.spice.append("\n.SUBCKT {0} {1}".format(self.name, - # " ".join(self.pins))) # Just make a guess since these will actually # be decided in the layout later. area_sd = 2.5 * self.poly_width * self.tx_width @@ -114,7 +114,13 @@ class ptx(design.design): area_sd) self.spice_device = main_str + area_str self.spice.append("\n* ptx " + self.spice_device) - # self.spice.append(".ENDS {0}".format(self.name)) + + if os.path.exists(OPTS.openram_tech + "lvs_lib"): + self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly")) + def setup_layout_constants(self): """ From beef9441b72dc8ac045f806bbeb4c2711310be61 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 5 Apr 2020 02:55:15 -0700 Subject: [PATCH 230/521] fix pin check debug typo --- compiler/base/hierarchy_spice.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index beb79ded..7adfb4f7 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -226,7 +226,7 @@ class spice(): subckt_line = list(filter(subckt.search, self.lvs))[0] # parses line into ports and remove subckt lvs_pins = subckt_line.split(" ")[2:] - debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.", -1) + debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.") def check_net_in_spice(self, net_name): """Checks if a net name exists in the current. Intended to be check nets in hand-made cells.""" From b59c789dec692cee9843277f188486d621d3b35b Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 5 Apr 2020 03:58:26 -0700 Subject: [PATCH 231/521] remove whitespace --- compiler/modules/dff_buf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 8f581606..e42c01c0 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -91,7 +91,7 @@ class dff_buf(design.design): def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - #self.connect_inst(props.dff_buff.buf_ports) + self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1", From a12b5d9e6c2e8fa723a2b8ba93c3ebd780caa5ed Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 6 Apr 2020 13:31:31 -0700 Subject: [PATCH 232/521] Split decoder pbitcell tests --- ...hierarchical_predecode2x4_pbitcell_test.py | 41 +++++++++++++++++++ .../06_hierarchical_predecode2x4_test.py | 10 ----- ...hierarchical_predecode3x8_pbitcell_test.py | 41 +++++++++++++++++++ .../06_hierarchical_predecode3x8_test.py | 10 ----- 4 files changed, 82 insertions(+), 20 deletions(-) create mode 100755 compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py create mode 100755 compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py new file mode 100755 index 00000000..8afc45da --- /dev/null +++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py @@ -0,0 +1,41 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class hierarchical_predecode2x4_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # checking hierarchical precode 2x4 for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)") + a = factory.create(module_type="hierarchical_predecode2x4") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 2e55f5e9..8bb42253 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -26,16 +26,6 @@ class hierarchical_predecode2x4_test(openram_test): a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) - # checking hierarchical precode 2x4 for multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)") - a = factory.create(module_type="hierarchical_predecode2x4") - self.local_check(a) - globals.end_openram() # run the test from the command line diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py new file mode 100755 index 00000000..34d38ddf --- /dev/null +++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py @@ -0,0 +1,41 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class hierarchical_predecode3x8_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # checking hierarchical precode 3x8 for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)") + a = factory.create(module_type="hierarchical_predecode3x8") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index da7573e1..f01fae03 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -26,16 +26,6 @@ class hierarchical_predecode3x8_test(openram_test): a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) - # checking hierarchical precode 3x8 for multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)") - a = factory.create(module_type="hierarchical_predecode3x8") - self.local_check(a) - globals.end_openram() # run the test from the command line From cd8dc8e20b5431ad58bdb4cf762c8cadd17bd730 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 6 Apr 2020 14:08:38 -0700 Subject: [PATCH 233/521] Output lvs model instead of spice model --- compiler/base/hierarchy_spice.py | 4 ++-- compiler/tests/testutils.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index beb79ded..8091af63 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -226,7 +226,7 @@ class spice(): subckt_line = list(filter(subckt.search, self.lvs))[0] # parses line into ports and remove subckt lvs_pins = subckt_line.split(" ")[2:] - debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.", -1) + debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.") def check_net_in_spice(self, net_name): """Checks if a net name exists in the current. Intended to be check nets in hand-made cells.""" @@ -319,7 +319,7 @@ class spice(): # Including the file path makes the unit test fail for other users. # if os.path.isfile(self.sp_file): # sp.write("\n* {0}\n".format(self.sp_file)) - if lvs_netlist: + if lvs_netlist and hasattr(self, "lvs"): sp.write("\n".join(self.lvs)) else: sp.write("\n".join(self.spice)) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 95675c38..c4fd7cac 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -39,7 +39,7 @@ class openram_test(unittest.TestCase): tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name) tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name) - a.sp_write(tempspice) + a.lvs_write(tempspice) # cannot write gds in netlist_only mode if not OPTS.netlist_only: a.gds_write(tempgds) From c8c74e8b695a665a6d258ec1504a04f8e27c9f5d Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 6 Apr 2020 15:20:59 -0700 Subject: [PATCH 234/521] Fix lvs_write in sram class --- compiler/sram/sram.py | 3 +++ compiler/sram/sram_base.py | 9 ++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index 0efad5cc..8863c299 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -51,6 +51,9 @@ class sram(): def sp_write(self, name): self.s.sp_write(name) + def lvs_write(self, name): + self.s.lvs_write(name) + def lef_write(self, name): self.s.lef_write(name) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 64e3f51b..b9c4c909 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -561,7 +561,7 @@ class sram_base(design, verilog, lef): self.add_via_center(layers=self.m2_stack, offset=out_pos) - def sp_write(self, sp_name): + def sp_write(self, sp_name, lvs_netlist=False): # Write the entire spice of the object to the file ############################################################ # Spice circuit @@ -581,10 +581,13 @@ class sram_base(design, verilog, lef): # sp.write(".global {0} {1}\n".format(spice["vdd_name"], # spice["gnd_name"])) usedMODS = list() - self.sp_write_file(sp, usedMODS) + self.sp_write_file(sp, usedMODS, lvs_netlist=lvs_netlist) del usedMODS sp.close() - + + def lvs_write(self, sp_name): + self.sp_write(sp_name, lvs_netlist=True) + def get_wordline_stage_efforts(self, inp_is_rise=True): """Get the all the stage efforts for each stage in the path from clk_buf to a wordline""" stage_effort_list = [] From a3797094d0b4a29892097b8049cc8ed00aeae7bc Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 7 Apr 2020 10:37:49 -0700 Subject: [PATCH 235/521] Swap lvs and sp dimensions for s8 --- compiler/pgates/ptx.py | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 3ed51651..a555e832 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -106,20 +106,33 @@ class ptx(design.design): # be decided in the layout later. area_sd = 2.5 * self.poly_width * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width - main_str = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], - self.mults, - self.tx_width, - drc("minwidth_poly")) - area_str = "pd={0:.2f}u ps={0:.2f}u as={1:.2f}p ad={1:.2f}p".format(perimeter_sd, - area_sd) + if OPTS.tech_name == "s8": + print("here {0}".format(self.name)) + # s8 technology is in microns + main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly")) + # Perimeters are in microns + # Area is in u since it is microns square + area_str = "pd={0:.2f} ps={0:.2f} as={1:.2f}u ad={1:.2f}u".format(perimeter_sd, + area_sd) + else: + main_str = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly")) + area_str = "pd={0:.2f}u ps={0:.2f}u as={1:.2f}p ad={1:.2f}p".format(perimeter_sd, + area_sd) self.spice_device = main_str + area_str self.spice.append("\n* ptx " + self.spice_device) + # LVS lib is always in SI units if os.path.exists(OPTS.openram_tech + "lvs_lib"): - self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], - self.mults, - self.tx_width, - drc("minwidth_poly")) + self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly")) def setup_layout_constants(self): From 95363856e4429e1a8ebe7d97fa14adb7da15a887 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 8 Apr 2020 02:29:57 -0700 Subject: [PATCH 236/521] Added logical effort and input load for ptx module. --- compiler/pgates/ptx.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 8fbb94d8..a305f620 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -11,6 +11,7 @@ from tech import layer, drc, spice from vector import vector from sram_factory import factory import contact +import logical_effort class ptx(design.design): @@ -445,6 +446,26 @@ class ptx(design.design): if self.connect_active: self.connect_fingered_active(drain_positions, source_positions) + + def get_stage_effort(self, cout): + """Returns an object representing the parameters for delay in tau units.""" + + # FIXME: Using the same definition as the pinv.py. + parasitic_delay = 1 + size = self.mults*self.tx_width/drc("minwidth_tx") + return logical_effort.logical_effort(self.name, + size, + self.input_load(), + cout, + parasitic_delay) + + def input_load(self): + """ + Returns the relative gate cin of the tx + """ + + # FIXME: this will be applied for the loads of the drain/source + return self.mults*self.tx_width/drc("minwidth_tx") def add_diff_contact(self, label, pos): contact=self.add_via_center(layers=self.active_stack, From 0c27942bb2ca643f0c413f36d96c8b620c32202c Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 8 Apr 2020 16:45:28 -0700 Subject: [PATCH 237/521] Dynamically try and DRC decoder for height --- compiler/modules/hierarchical_decoder.py | 25 ++++++++++++++++------- compiler/pgates/pinv.py | 26 ++++++++++++++++-------- compiler/pgates/pnand3.py | 2 +- compiler/pgates/ptx.py | 1 - 4 files changed, 36 insertions(+), 18 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 0a54a401..8776810a 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -11,6 +11,7 @@ import math from sram_factory import factory from vector import vector from globals import OPTS +from errors import drc_error class hierarchical_decoder(design.design): @@ -37,18 +38,28 @@ class hierarchical_decoder(design.design): def find_decoder_height(self): b = factory.create(module_type="bitcell") # Old behavior - return (b.height, 1) + # return (b.height, 1) # Search for the smallest multiple that works cell_multiple = 1 - while cell_multiple < 3: + while cell_multiple < 5: cell_height = cell_multiple * b.height - and3 = factory.create(module_type="pand3", - height=cell_height) - (drc_errors, lvs_errors) = and3.DRC_LVS(force_check=True) - if drc_errors + lvs_errors == 0: - return (cell_height, cell_multiple) + # debug.info(2,"Trying mult = {0} height={1}".format(cell_multiple, cell_height)) + try: + and3 = factory.create(module_type="pand3", + height=cell_height) + except drc_error: + # debug.info(1, "Incrementing decoder height by 1 bitcell height {}".format(b.height)) + pass + else: + (drc_errors, lvs_errors) = and3.DRC_LVS(force_check=True) + total_errors = drc_errors + lvs_errors + if total_errors == 0: + debug.info(1, "Decoder height is multiple of {} bitcells.".format(cell_multiple)) + return (cell_height, cell_multiple) + cell_multiple += 1 + else: debug.error("Couldn't find a valid decoder height multiple.", -1) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 3c2e41a2..3ec3e23e 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -15,6 +15,7 @@ from globals import OPTS from utils import round_to_grid import logical_effort from sram_factory import factory +from errors import drc_error class pinv(pgate.pgate): @@ -105,11 +106,14 @@ class pinv(pgate.pgate): # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space, self.poly_extend_active + self.poly_space) - total_height = tx_height + min_channel + 2 * self.top_bottom_space - debug.check(self.height > total_height, - "Cell height {0} too small for simple min height {1}.".format(self.height, - total_height)) + total_height = tx_height + min_channel + 2 * self.top_bottom_space + # debug.check(self.height > total_height, + # "Cell height {0} too small for simple min height {1}.".format(self.height, + # total_height)) + if total_height > self.height: + msg = "Cell height {0} too small for simple min height {1}.".format(self.height, total_height) + raise drc_error(msg) # Determine the height left to the transistors to determine # the number of fingers @@ -141,12 +145,16 @@ class pinv(pgate.pgate): # with LVS property mismatch errors when fingers are not a grid # length and get rounded in the offset geometry. self.nmos_width = round_to_grid(self.nmos_width / self.tx_mults) - debug.check(self.nmos_width >= drc("minwidth_tx"), - "Cannot finger NMOS transistors to fit cell height.") - self.pmos_width = round_to_grid(self.pmos_width / self.tx_mults) - debug.check(self.pmos_width >= drc("minwidth_tx"), - "Cannot finger PMOS transistors to fit cell height.") + # debug.check(self.nmos_width >= drc("minwidth_tx"), + # "Cannot finger NMOS transistors to fit cell height.") + if self.nmos_width < drc("minwidth_tx"): + raise drc_error("Cannot finger NMOS transistors to fit cell height.") + self.pmos_width = round_to_grid(self.pmos_width / self.tx_mults) + #debug.check(self.pmos_width >= drc("minwidth_tx"), + # "Cannot finger PMOS transistors to fit cell height.") + if self.pmos_width < drc("minwidth_tx"): + raise drc_error("Cannot finger NMOS transistors to fit cell height.") def add_ptx(self): """ Create the PMOS and NMOS transistors. """ diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index cc6fd0f8..3eeba41e 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -223,7 +223,7 @@ class pnand3(pgate.pgate): position="center") # FIXME: constant hack - self.inputA_yoffset = self.inputB_yoffset + 1.12 * m1_pitch + self.inputA_yoffset = self.inputB_yoffset + 1.15 * m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 357e1ce4..f07f4b29 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -108,7 +108,6 @@ class ptx(design.design): area_sd = 2.5 * self.poly_width * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width if OPTS.tech_name == "s8": - print("here {0}".format(self.name)) # s8 technology is in microns main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], self.mults, From ade3b78711ae56f56ac72afa39438a4e839303c9 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 8 Apr 2020 16:55:45 -0700 Subject: [PATCH 238/521] Add exception errors file --- compiler/base/errors.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 compiler/base/errors.py diff --git a/compiler/base/errors.py b/compiler/base/errors.py new file mode 100644 index 00000000..e2b9e5ec --- /dev/null +++ b/compiler/base/errors.py @@ -0,0 +1,15 @@ + + +class drc_error(Exception): + """Exception raised for DRC errors. + + Attributes: + expression -- input expression in which the error occurred + message -- explanation of the error + """ + + # def __init__(self, expression, message): + # self.expression = expression + # self.message = message + def __init__(self, message): + self.message = message From cddfaa0dc8d0e2820a3e806ea30ffde9af9febb3 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 8 Apr 2020 17:04:14 -0700 Subject: [PATCH 239/521] Tech dependent fudge factor --- compiler/pgates/pnand3.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 3eeba41e..eb28ba08 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -223,7 +223,10 @@ class pnand3(pgate.pgate): position="center") # FIXME: constant hack - self.inputA_yoffset = self.inputB_yoffset + 1.15 * m1_pitch + if OPTS.tech_name == "s8": + self.inputA_yoffset = self.inputB_yoffset + 1.15 * m1_pitch + else: + self.inputA_yoffset = self.inputB_yoffset + 1.12 * m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, From 745450fadcbd3700cadc0dcf8552e23207a5597c Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 8 Apr 2020 17:04:50 -0700 Subject: [PATCH 240/521] Syntax error --- compiler/pgates/pnand3.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index eb28ba08..e7cc02e8 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -12,6 +12,7 @@ from tech import drc, parameter, spice from vector import vector import logical_effort from sram_factory import factory +from globals import OPTS class pnand3(pgate.pgate): @@ -226,7 +227,7 @@ class pnand3(pgate.pgate): if OPTS.tech_name == "s8": self.inputA_yoffset = self.inputB_yoffset + 1.15 * m1_pitch else: - self.inputA_yoffset = self.inputB_yoffset + 1.12 * m1_pitch + self.inputA_yoffset = self.inputB_yoffset + 1.12 * m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, From 58fbc5351a7d1a5e95a26e2929aa9569d6bd16fc Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 8 Apr 2020 17:05:16 -0700 Subject: [PATCH 241/521] Change rows to outputs in hierarchical decoder --- compiler/modules/hierarchical_decoder.py | 26 ++++++++++--------- compiler/modules/port_address.py | 12 +++------ .../06_hierarchical_decoder_pbitcell_test.py | 16 ++++++------ .../tests/06_hierarchical_decoder_test.py | 20 +++++++------- 4 files changed, 36 insertions(+), 38 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 8776810a..36097269 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -18,7 +18,7 @@ class hierarchical_decoder(design.design): """ Dynamically generated hierarchical decoder. """ - def __init__(self, name, rows): + def __init__(self, name, num_outputs): design.design.__init__(self, name) self.AND_FORMAT = "DEC_AND_{0}" @@ -27,8 +27,10 @@ class hierarchical_decoder(design.design): self.pre3x8_inst = [] (self.cell_height, self.cell_multiple) = self.find_decoder_height() - self.rows = rows - self.num_inputs = math.ceil(math.log(self.rows, 2)) + self.num_outputs = num_outputs + # We may have more than one bitcell per decoder row + self.rows = math.ceil(num_outputs / self.cell_multiple) + self.num_inputs = math.ceil(math.log(self.num_outputs, 2)) (self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) self.create_netlist() @@ -176,7 +178,7 @@ class hierarchical_decoder(design.design): self.internal_routing_width = self.m2_pitch * self.total_number_of_predecoder_outputs self.row_decoder_height = self.inv.height * self.rows - self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch + self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch # Calculates height and width of hierarchical decoder self.height = self.row_decoder_height self.width = self.input_routing_width + self.predecoder_width \ @@ -253,7 +255,7 @@ class hierarchical_decoder(design.design): for i in range(self.num_inputs): self.add_pin("addr_{0}".format(i), "INPUT") - for j in range(self.rows): + for j in range(self.num_outputs): self.add_pin("decode_{0}".format(j), "OUTPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -351,7 +353,7 @@ class hierarchical_decoder(design.design): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): row = len(self.predec_groups[0]) * j + i - if (row < self.rows): + if (row < self.num_outputs): name = self.AND_FORMAT.format(row) self.and_inst.append(self.add_inst(name=name, mod=self.and2)) @@ -369,7 +371,7 @@ class hierarchical_decoder(design.design): row = (len(self.predec_groups[0]) * len(self.predec_groups[1])) * k \ + len(self.predec_groups[0]) * j + i - if (row < self.rows): + if (row < self.num_outputs): name = self.AND_FORMAT.format(row) self.and_inst.append(self.add_inst(name=name, mod=self.and3)) @@ -405,7 +407,7 @@ class hierarchical_decoder(design.design): def place_and_array(self, and_mod): """ Add a column of AND gates for the decoder above the predecoders.""" - for row in range(self.rows): + for row in range(self.num_outputs): if ((row % 2) == 0): y_off = and_mod.height * row mirror = "R0" @@ -419,7 +421,7 @@ class hierarchical_decoder(design.design): def route_decoder(self): """ Add the pins. """ - for row in range(self.rows): + for row in range(self.num_outputs): z_pin = self.and_inst[row].get_pin("Z") self.add_layout_pin(text="decode_{0}".format(row), layer="m1", @@ -475,7 +477,7 @@ class hierarchical_decoder(design.design): for index_B in self.predec_groups[1]: for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? - if (row_index < self.rows): + if (row_index < self.num_outputs): predecode_name = "predecode_{}".format(index_A) self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("A")) predecode_name = "predecode_{}".format(index_B) @@ -487,7 +489,7 @@ class hierarchical_decoder(design.design): for index_B in self.predec_groups[1]: for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? - if (row_index < self.rows): + if (row_index < self.num_outputs): predecode_name = "predecode_{}".format(index_A) self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("A")) predecode_name = "predecode_{}".format(index_B) @@ -501,7 +503,7 @@ class hierarchical_decoder(design.design): # The vias will be placed in the center and right of the cells, respectively. xoffset = self.and_inst[0].rx() - for num in range(0, self.rows): + for num in range(0, self.num_outputs): for pin_name in ["vdd", "gnd"]: # The nand and inv are the same height rows... supply_pin = self.and_inst[num].get_pin(pin_name) diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 44b0d5a5..6938219a 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -90,17 +90,14 @@ class port_address(design.design): # The pre/post is to access the pin from "outside" the cell to avoid DRCs decoder_out_pos = self.row_decoder_inst.get_pin("decode_{}".format(row)).rc() driver_in_pos = self.wordline_driver_inst.get_pin("in_{}".format(row)).lc() - mid1 = decoder_out_pos.scale(0.5,1)+driver_in_pos.scale(0.5,0) - mid2 = decoder_out_pos.scale(0.5,0)+driver_in_pos.scale(0.5,1) + mid1 = decoder_out_pos.scale(0.5, 1) + driver_in_pos.scale(0.5, 0) + mid2 = decoder_out_pos.scale(0.5, 0) + driver_in_pos.scale(0.5, 1) self.add_path("m1", [decoder_out_pos, mid1, mid2, driver_in_pos]) - - - def add_modules(self): self.row_decoder = factory.create(module_type="decoder", - rows=self.num_rows) + num_outputs=self.num_rows) self.add_mod(self.row_decoder) self.wordline_driver = factory.create(module_type="wordline_driver", @@ -108,11 +105,10 @@ class port_address(design.design): cols=self.num_cols) self.add_mod(self.wordline_driver) - def create_row_decoder(self): """ Create the hierarchical row decoder """ - self.row_decoder_inst = self.add_inst(name="row_decoder", + self.row_decoder_inst = self.add_inst(name="row_decoder", mod=self.row_decoder) temp = [] diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py index 1fb3a3f6..ec8f4efe 100755 --- a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py @@ -28,39 +28,39 @@ class hierarchical_decoder_test(openram_test): factory.reset() debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=16) + a = factory.create(module_type="hierarchical_decoder", num_outputs=16) self.local_check(a) factory.reset() debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=17) + a = factory.create(module_type="hierarchical_decoder", num_outputs=17) self.local_check(a) factory.reset() debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=23) + a = factory.create(module_type="hierarchical_decoder", num_outputs=23) self.local_check(a) debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=32) + a = factory.create(module_type="hierarchical_decoder", num_outputs=32) self.local_check(a) factory.reset() debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=65) + a = factory.create(module_type="hierarchical_decoder", num_outputs=65) self.local_check(a) debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=128) + a = factory.create(module_type="hierarchical_decoder", num_outputs=128) self.local_check(a) factory.reset() debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=341) + a = factory.create(module_type="hierarchical_decoder", num_outputs=341) self.local_check(a) debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)") - a = factory.create(module_type="hierarchical_decoder", rows=512) + a = factory.create(module_type="hierarchical_decoder", num_outputs=512) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index ab7e844f..df979657 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -22,45 +22,45 @@ class hierarchical_decoder_test(openram_test): globals.init_openram(config_file) # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") - # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4) + # a = hierarchical_decoder.hierarchical_decoder(name="hd1, num_outputs=4) # self.local_check(a) # Doesn't require hierarchical decoder # debug.info(1, "Testing 8 row sample for hierarchical_decoder") - # a = hierarchical_decoder.hierarchical_decoder(name="hd2", rows=8) + # a = hierarchical_decoder.hierarchical_decoder(name="hd2", num_outputs=8) # self.local_check(a) # check hierarchical decoder for single port debug.info(1, "Testing 16 row sample for hierarchical_decoder") - a = factory.create(module_type="hierarchical_decoder", rows=16) + a = factory.create(module_type="hierarchical_decoder", num_outputs=16) self.local_check(a) debug.info(1, "Testing 17 row sample for hierarchical_decoder") - a = factory.create(module_type="hierarchical_decoder", rows=17) + a = factory.create(module_type="hierarchical_decoder", num_outputs=17) self.local_check(a) debug.info(1, "Testing 23 row sample for hierarchical_decoder") - a = factory.create(module_type="hierarchical_decoder", rows=23) + a = factory.create(module_type="hierarchical_decoder", num_outputs=23) self.local_check(a) debug.info(1, "Testing 32 row sample for hierarchical_decoder") - a = factory.create(module_type="hierarchical_decoder", rows=32) + a = factory.create(module_type="hierarchical_decoder", num_outputs=32) self.local_check(a) debug.info(1, "Testing 65 row sample for hierarchical_decoder") - a = factory.create(module_type="hierarchical_decoder", rows=65) + a = factory.create(module_type="hierarchical_decoder", num_outputs=65) self.local_check(a) debug.info(1, "Testing 128 row sample for hierarchical_decoder") - a = factory.create(module_type="hierarchical_decoder", rows=128) + a = factory.create(module_type="hierarchical_decoder", num_outputs=128) self.local_check(a) debug.info(1, "Testing 341 row sample for hierarchical_decoder") - a = factory.create(module_type="hierarchical_decoder", rows=341) + a = factory.create(module_type="hierarchical_decoder", num_outputs=341) self.local_check(a) debug.info(1, "Testing 512 row sample for hierarchical_decoder") - a = factory.create(module_type="hierarchical_decoder", rows=512) + a = factory.create(module_type="hierarchical_decoder", num_outputs=512) self.local_check(a) globals.end_openram() From 8a55c223dfa6475322c1f2940d13aed0d1232076 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 9 Apr 2020 09:48:54 -0700 Subject: [PATCH 242/521] Use single height for netlist_only mode --- compiler/modules/hierarchical_decoder.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 36097269..982d9583 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -38,9 +38,11 @@ class hierarchical_decoder(design.design): self.create_layout() def find_decoder_height(self): + b = factory.create(module_type="bitcell") # Old behavior - # return (b.height, 1) + if OPTS.netlist_only: + return (b.height, 1) # Search for the smallest multiple that works cell_multiple = 1 From 75bd2b46a548b888eeade14fdfa27895ab337e2f Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 9 Apr 2020 10:02:15 -0700 Subject: [PATCH 243/521] OpenRAM v1.1.5 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 3277ab1d..dbb1f962 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.4" +VERSION = "1.1.5" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From 7888e54fc4e6b652e98339d3775d40c523e27952 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 9 Apr 2020 11:38:18 -0700 Subject: [PATCH 244/521] Remove dynamic bitcell multiple detection. Check for decoder bitcell multiple in tech file or assume 1. PEP8 fixes. --- compiler/globals.py | 2 +- compiler/modules/hierarchical_decoder.py | 18 +++++++++++++----- compiler/tests/30_openram_back_end_test.py | 19 +++++++++---------- compiler/tests/30_openram_front_end_test.py | 21 ++++++++++----------- 4 files changed, 33 insertions(+), 27 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index 3277ab1d..4e6253ad 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -589,4 +589,4 @@ def report_status(): if OPTS.trim_netlist: debug.print_raw("Trimming netlist to speed up characterization (trim_netlist=False to disable).") if OPTS.nominal_corner_only: - debug.print_raw("Only characterizing nominal corner.") + debug.print_raw("Only characterizing nominal corner.") diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 982d9583..be062acf 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -12,6 +12,7 @@ from sram_factory import factory from vector import vector from globals import OPTS from errors import drc_error +from tech import cell_properties class hierarchical_decoder(design.design): @@ -26,7 +27,13 @@ class hierarchical_decoder(design.design): self.pre2x4_inst = [] self.pre3x8_inst = [] - (self.cell_height, self.cell_multiple) = self.find_decoder_height() + b = factory.create(module_type="bitcell") + try: + self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple + except AttributeError: + self.cell_multiple = 1 + self.cell_height = self.cell_multiple * b.height + self.num_outputs = num_outputs # We may have more than one bitcell per decoder row self.rows = math.ceil(num_outputs / self.cell_multiple) @@ -38,11 +45,12 @@ class hierarchical_decoder(design.design): self.create_layout() def find_decoder_height(self): - + """ + Dead code. This would dynamically determine the bitcell multiple, + but I just decided to hard code it in the tech file if it is not 1 + because a DRC tool would be required even to run in front-end mode. + """ b = factory.create(module_type="bitcell") - # Old behavior - if OPTS.netlist_only: - return (b.height, 1) # Search for the smallest multiple that works cell_multiple = 1 diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index 73d201b1..591d03ac 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -51,7 +51,7 @@ class openram_back_end_test(openram_test): debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: - exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) + exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) config_name = "{0}/tests/configs/config_back_end.py".format(OPENRAM_HOME) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, @@ -64,33 +64,32 @@ class openram_back_end_test(openram_test): # assert an error until we actually check a resul for extension in ["gds", "v", "lef", "sp"]: - filename = "{0}/{1}.{2}".format(out_path,out_file,extension) - debug.info(1,"Checking for file: " + filename) - self.assertEqual(os.path.exists(filename),True) + filename = "{0}/{1}.{2}".format(out_path, out_file, extension) + debug.info(1, "Checking for file: " + filename) + self.assertEqual(os.path.exists(filename), True) # Make sure there is any .lib file import glob files = glob.glob('{0}/*.lib'.format(out_path)) self.assertTrue(len(files)>0) - # Make sure there is any .html file + # Make sure there is any .html file if os.path.exists(out_path): datasheets = glob.glob('{0}/*html'.format(out_path)) self.assertTrue(len(datasheets)>0) # grep any errors from the output - output_log = open("{0}/output.log".format(out_path),"r") + output_log = open("{0}/output.log".format(out_path), "r") output = output_log.read() output_log.close() - self.assertEqual(len(re.findall('ERROR',output)),0) - self.assertEqual(len(re.findall('WARNING',output)),0) - + self.assertEqual(len(re.findall('ERROR', output)), 0) + self.assertEqual(len(re.findall('WARNING', output)), 0) # now clean up the directory if OPTS.purge_temp: if os.path.exists(out_path): shutil.rmtree(out_path, ignore_errors=True) - self.assertEqual(os.path.exists(out_path),False) + self.assertEqual(os.path.exists(out_path), False) globals.end_openram() diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 3aec10f9..127df6c2 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -51,7 +51,7 @@ class openram_front_end_test(openram_test): debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: - exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) + exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) config_name = "{0}/tests/configs/config_front_end.py".format(OPENRAM_HOME) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, @@ -64,33 +64,32 @@ class openram_front_end_test(openram_test): # assert an error until we actually check a result for extension in ["v", "lef", "sp", "gds"]: - filename = "{0}/{1}.{2}".format(out_path,out_file,extension) - debug.info(1,"Checking for file: " + filename) - self.assertEqual(os.path.exists(filename),True) + filename = "{0}/{1}.{2}".format(out_path, out_file, extension) + debug.info(1, "Checking for file: " + filename) + self.assertEqual(os.path.exists(filename), True) # Make sure there is any .lib file import glob files = glob.glob('{0}/*.lib'.format(out_path)) self.assertTrue(len(files)>0) - # Make sure there is any .html file + # Make sure there is any .html file if os.path.exists(out_path): datasheets = glob.glob('{0}/*html'.format(out_path)) self.assertTrue(len(datasheets)>0) # grep any errors from the output - output_log = open("{0}/output.log".format(out_path),"r") + output_log = open("{0}/output.log".format(out_path), "r") output = output_log.read() output_log.close() - self.assertEqual(len(re.findall('ERROR',output)),0) - self.assertEqual(len(re.findall('WARNING',output)),0) + self.assertEqual(len(re.findall('ERROR', output)), 0) + self.assertEqual(len(re.findall('WARNING', output)), 0) - - # now clean up the directory + # now clean up the directory if OPTS.purge_temp: if os.path.exists(out_path): shutil.rmtree(out_path, ignore_errors=True) - self.assertEqual(os.path.exists(out_path),False) + self.assertEqual(os.path.exists(out_path), False) globals.end_openram() From a0eb9839ad55e33fdbf76d8c5fda0da528104b06 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Thu, 9 Apr 2020 19:39:21 -0700 Subject: [PATCH 245/521] revert units on sp_lib, begin discrete tx simulation --- compiler/characterizer/stimuli.py | 11 +++++++ compiler/pgates/pgate.py | 49 ++++++++++++++++++++++++++++++- compiler/pgates/pinv.py | 3 ++ compiler/pgates/precharge.py | 5 ++++ compiler/pgates/ptx.py | 4 ++- 5 files changed, 70 insertions(+), 2 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 58a9e3ed..fc2a106f 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -34,6 +34,10 @@ class stimuli(): self.sf = stim_file (self.process, self.voltage, self.temperature) = corner + try: + self.device_libraries = tech.spice["fet_libraries"][self.process] + except: + debug.info(2, "Not using spice library") self.device_models = tech.spice["fet_models"][self.process] self.sram_name = "Xsram" @@ -247,8 +251,15 @@ class stimuli(): def write_include(self, circuit): """Writes include statements, inputs are lists of model files""" + libraries = self.device_libraries includes = self.device_models + [circuit] self.sf.write("* {} process corner\n".format(self.process)) + for item in list(libraries): + if os.path.isfile(item[0]): + self.sf.write(".lib \"{0}\" {1}\n".format(item[0], item[1])) + else: + debug.error("Could not find spice library: {0}\nSet SPICE_MODEL_DIR to over-ride path.\n".format(item[0])) + for item in list(includes): if os.path.isfile(item): self.sf.write(".include \"{0}\"\n".format(item)) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index d83825ea..ba5fef75 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -8,10 +8,14 @@ import contact import design import debug -from tech import layer +import math +from bisect import bisect_left +from tech import layer, drc from vector import vector from globals import OPTS +if(OPTS.tech_name == "s8"): + from tech import nmos_bins, pmos_bins class pgate(design.design): """ @@ -282,5 +286,48 @@ class pgate(design.design): self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width self.well_width = self.width + 2 * self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. + + def bin_width(self, tx_type, target_width): + + if tx_type == "nmos": + bins = nmos_bins[drc("minwidth_poly")] + elif tx_type == "pmos": + bins = pmos_bins[drc("minwidth_poly")] + else: + debug.error("invalid tx type") + + + bins = bins[0:bisect_left(bins, target_width) + 1] + if len(bins) == 1: + selected_bin = bins[0] + scaling_factor = 1 + scaled_bin = bins[0] + + else: + scaled_bins = [] + scaling_factors = [] + for width in bins[0:-1]: + m = math.ceil(target_width / width) + scaling_factors.append(m) + scaled_bins.append(m * width) + + scaled_bins.append(bins[-1]) + scaling_factors.append(1) + select = bisect_left(scaled_bins, target_width) + + selected_bin = bins[select] + scaling_factor = scaling_factors[select] + scaled_bin = scaled_bins[select] + + debug.info(2, "binning {0} tx, target: {4}, found {1} x {2} = {3}".format(tx_type, selected_bin, scaling_factor, scaled_bin, target_width)) + + return(selected_bin, scaling_factor) + + + + + + + diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 3c2e41a2..1ccad6ca 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -81,6 +81,9 @@ class pinv(pgate.pgate): self.tx_mults = 1 self.nmos_width = self.nmos_size * drc("minwidth_tx") self.pmos_width = self.pmos_size * drc("minwidth_tx") + if OPTS.tech_name == "s8": + (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) + (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) return # Do a quick sanity check and bail if unlikely feasible height diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index afe14a05..45128421 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -8,6 +8,7 @@ import contact import design import debug +from pgate import pgate from tech import parameter from vector import vector from globals import OPTS @@ -28,6 +29,7 @@ class precharge(design.design): self.bitcell = factory.create(module_type="bitcell") self.beta = parameter["beta"] self.ptx_width = self.beta * parameter["min_tx_size"] + self.ptx_mults = 1 self.width = self.bitcell.width self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br @@ -77,8 +79,11 @@ class precharge(design.design): """ Initializes the upper and lower pmos """ + if(OPTS.tech_name == "s8"): + (self.ptx_width, self.ptx_mults) = pgate.bin_width(self, "pmos", self.ptx_width) self.pmos = factory.create(module_type="ptx", width=self.ptx_width, + mults=self.ptx_mults, tx_type="pmos") self.add_mod(self.pmos) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 357e1ce4..ffd61a48 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -107,7 +107,9 @@ class ptx(design.design): # be decided in the layout later. area_sd = 2.5 * self.poly_width * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width - if OPTS.tech_name == "s8": + + + if OPTS.tech_name == None: print("here {0}".format(self.name)) # s8 technology is in microns main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], From 2e67d44cd7e09acf733acc40fc2f599757d9089c Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 10 Apr 2020 13:29:41 -0700 Subject: [PATCH 246/521] First pass of multiple bitcells per decoder row --- compiler/modules/hierarchical_decoder.py | 245 +++++++++++------- compiler/pgates/pnand3.py | 8 +- .../tests/06_hierarchical_decoder_test.py | 9 - 3 files changed, 159 insertions(+), 103 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index be062acf..0e5b3606 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -32,11 +32,11 @@ class hierarchical_decoder(design.design): self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple except AttributeError: self.cell_multiple = 1 + # For debugging + # self.cell_multiple = 2 self.cell_height = self.cell_multiple * b.height self.num_outputs = num_outputs - # We may have more than one bitcell per decoder row - self.rows = math.ceil(num_outputs / self.cell_multiple) self.num_inputs = math.ceil(math.log(self.num_outputs, 2)) (self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) @@ -51,6 +51,10 @@ class hierarchical_decoder(design.design): because a DRC tool would be required even to run in front-end mode. """ b = factory.create(module_type="bitcell") + + # Old behavior + if OPTS.netlist_only: + return (b.height, 1) # Search for the smallest multiple that works cell_multiple = 1 @@ -86,8 +90,8 @@ class hierarchical_decoder(design.design): self.setup_layout_constants() self.place_pre_decoder() self.place_row_decoder() - self.route_input_rails() - self.route_predecode_rails() + self.route_inputs() + self.route_decoder_bus() self.route_vdd_gnd() self.offset_all_coordinates() self.add_boundary() @@ -141,7 +145,7 @@ class hierarchical_decoder(design.design): def setup_netlist_constants(self): self.predec_groups = [] # This array is a 2D array. - # Distributing vertical rails to different groups. One group belongs to one pre-decoder. + # Distributing vertical bus to different groups. One group belongs to one pre-decoder. # For example, for two 2:4 pre-decoder and one 3:8 pre-decoder, we will # have total 16 output lines out of these 3 pre-decoders and they will # be distributed as [ [0,1,2,3] ,[4,5,6,7], [8,9,10,11,12,13,14,15] ] @@ -180,39 +184,45 @@ class hierarchical_decoder(design.design): self.predecoder_height = self.pre2_4.height * self.no_of_pre2x4 + self.pre3_8.height * self.no_of_pre3x8 + # We may have more than one bitcell per decoder row + self.num_rows = math.ceil(self.num_outputs / self.cell_multiple) + # We will place this many final decoders per row + self.decoders_per_row = math.ceil(self.num_outputs / self.num_rows) + # Calculates height and width of row-decoder if (self.num_inputs == 4 or self.num_inputs == 5): nand_width = self.and2.width else: nand_width = self.and3.width - self.internal_routing_width = self.m2_pitch * self.total_number_of_predecoder_outputs - self.row_decoder_height = self.inv.height * self.rows + self.internal_routing_width = self.m2_pitch * (self.total_number_of_predecoder_outputs + 1) + self.row_decoder_height = self.inv.height * self.num_rows self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch # Calculates height and width of hierarchical decoder - self.height = self.row_decoder_height + self.height = max(self.predecoder_height, self.row_decoder_height) self.width = self.input_routing_width + self.predecoder_width \ - + self.internal_routing_width + nand_width + self.inv.width + + self.internal_routing_width \ + + self.decoders_per_row * nand_width + self.inv.width - def route_input_rails(self): - """ Create input rails for the predecoders """ + def route_inputs(self): + """ Create input bus for the predecoders """ # inputs should be as high as the decoders input_height = self.no_of_pre2x4 * self.pre2_4.height + self.no_of_pre3x8 * self.pre3_8.height # Find the left-most predecoder min_x = 0 if self.no_of_pre2x4 > 0: - min_x = min(min_x, -self.pre2_4.width) + min_x = min(min_x, self.pre2x4_inst[0].lx()) if self.no_of_pre3x8 > 0: - min_x = min(min_x, -self.pre3_8.width) + min_x = min(min_x, self.pre3x8_inst[0].lx()) input_offset=vector(min_x - self.input_routing_width, 0) input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)] - self.input_rails = self.create_vertical_pin_bus(layer="m2", - pitch=self.m2_pitch, - offset=input_offset, - names=input_bus_names, - length=input_height) + self.input_bus = self.create_vertical_pin_bus(layer="m2", + pitch=self.m2_pitch, + offset=input_offset, + names=input_bus_names, + length=input_height) self.route_input_to_predecodes() @@ -222,7 +232,7 @@ class hierarchical_decoder(design.design): for i in range(2): index = pre_num * 2 + i - input_pos = self.input_rails["addr_{}".format(index)] + input_pos = self.input_bus["addr_{}".format(index)] in_name = "in_{}".format(i) decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name) @@ -232,13 +242,13 @@ class hierarchical_decoder(design.design): decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height) input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1) - self.route_input_rail(decoder_offset, input_offset) + self.route_input_bus(decoder_offset, input_offset) for pre_num in range(self.no_of_pre3x8): for i in range(3): index = pre_num * 3 + i + self.no_of_pre2x4 * 2 - input_pos = self.input_rails["addr_{}".format(index)] + input_pos = self.input_bus["addr_{}".format(index)] in_name = "in_{}".format(i) decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name) @@ -248,9 +258,9 @@ class hierarchical_decoder(design.design): decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height) input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1) - self.route_input_rail(decoder_offset, input_offset) + self.route_input_bus(decoder_offset, input_offset) - def route_input_rail(self, input_offset, output_offset): + def route_input_bus(self, input_offset, output_offset): """ Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """ self.add_via_center(layers=self.m2_stack, @@ -334,18 +344,17 @@ class hierarchical_decoder(design.design): else: base= vector(-self.pre2_4.width, num * self.pre2_4.height) - self.pre2x4_inst[num].place(base) + self.pre2x4_inst[num].place(base - vector(2 * self.m2_pitch, 0)) def place_pre3x8(self, num): """ Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """ if (self.num_inputs == 3): offset = vector(-self.pre_3_8.width, 0) - mirror = "R0" else: height = self.no_of_pre2x4 * self.pre2_4.height + num * self.pre3_8.height offset = vector(-self.pre3_8.width, height) - self.pre3x8_inst[num].place(offset) + self.pre3x8_inst[num].place(offset - vector(2 * self.m2_pitch, 0)) def create_row_decoder(self): """ Create the row-decoder by placing AND2/AND3 and Inverters @@ -362,14 +371,14 @@ class hierarchical_decoder(design.design): if (self.num_inputs == 4 or self.num_inputs == 5): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): - row = len(self.predec_groups[0]) * j + i - if (row < self.num_outputs): - name = self.AND_FORMAT.format(row) + output = len(self.predec_groups[0]) * j + i + if (output < self.num_outputs): + name = self.AND_FORMAT.format(output) self.and_inst.append(self.add_inst(name=name, mod=self.and2)) pins =["out_{0}".format(i), "out_{0}".format(j + len(self.predec_groups[0])), - "decode_{0}".format(row), + "decode_{0}".format(output), "vdd", "gnd"] self.connect_inst(pins) @@ -378,18 +387,18 @@ class hierarchical_decoder(design.design): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): for k in range(len(self.predec_groups[2])): - row = (len(self.predec_groups[0]) * len(self.predec_groups[1])) * k \ - + len(self.predec_groups[0]) * j + i + output = (len(self.predec_groups[0]) * len(self.predec_groups[1])) * k \ + + len(self.predec_groups[0]) * j + i - if (row < self.num_outputs): - name = self.AND_FORMAT.format(row) + if (output < self.num_outputs): + name = self.AND_FORMAT.format(output) self.and_inst.append(self.add_inst(name=name, mod=self.and3)) pins = ["out_{0}".format(i), "out_{0}".format(j + len(self.predec_groups[0])), "out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])), - "decode_{0}".format(row), + "decode_{0}".format(output), "vdd", "gnd"] self.connect_inst(pins) @@ -403,7 +412,10 @@ class hierarchical_decoder(design.design): self.route_decoder() def place_decoder_and_array(self): - """ Add a column of AND gates for final decode """ + """ + Add a column of AND gates for final decode. + This may have more than one decoder per row to match the bitcell height. + """ # Row Decoder AND GATE array for address inputs <5. if (self.num_inputs == 4 or self.num_inputs == 5): @@ -415,9 +427,13 @@ class hierarchical_decoder(design.design): self.place_and_array(and_mod=self.and3) def place_and_array(self, and_mod): - """ Add a column of AND gates for the decoder above the predecoders.""" - - for row in range(self.num_outputs): + """ + Add a column of AND gates for the decoder above the predecoders. + """ + + for inst_index in range(self.num_outputs): + row = math.floor(inst_index / self.decoders_per_row) + dec = inst_index % self.decoders_per_row if ((row % 2) == 0): y_off = and_mod.height * row mirror = "R0" @@ -425,46 +441,52 @@ class hierarchical_decoder(design.design): y_off = and_mod.height * (row + 1) mirror = "MX" - self.and_inst[row].place(offset=[self.internal_routing_width, y_off], - mirror=mirror) + x_off = self.internal_routing_width + dec * and_mod.width + self.and_inst[inst_index].place(offset=vector(x_off, y_off), + mirror=mirror) def route_decoder(self): """ Add the pins. """ - for row in range(self.num_outputs): - z_pin = self.and_inst[row].get_pin("Z") - self.add_layout_pin(text="decode_{0}".format(row), + for output in range(self.num_outputs): + z_pin = self.and_inst[output].get_pin("Z") + self.add_layout_pin(text="decode_{0}".format(output), layer="m1", offset=z_pin.ll(), width=z_pin.width(), height=z_pin.height()) - def route_predecode_rails(self): - """ Creates vertical metal 2 rails to connect predecoder and decoder stages.""" + def route_decoder_bus(self): + """ + Creates vertical metal 2 bus to connect predecoder and decoder stages. + """ # This is not needed for inputs <4 since they have no pre/decode stages. if (self.num_inputs >= 4): - input_offset = vector(0.5 * self.m2_width, 0) + # This leaves an offset for the predecoder output jogs input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)] - self.predecode_rails = self.create_vertical_pin_bus(layer="m2", - pitch=self.m2_pitch, - offset=input_offset, - names=input_bus_names, - length=self.height) + self.predecode_bus = self.create_vertical_pin_bus(layer="m2", + pitch=self.m2_pitch, + offset=vector(0, 0), + names=input_bus_names, + length=self.height) - self.route_rails_to_predecodes() - self.route_rails_to_decoder() - - def route_rails_to_predecodes(self): - """ Iterates through all of the predecodes and connects to the rails including the offsets """ + self.route_bus_to_predecodes() + self.route_bus_to_decoder() + def route_bus_to_predecodes(self): + """ + Iterates through all of the predecodes + and connects to the rails including the offsets + """ # FIXME: convert to connect_bus for pre_num in range(self.no_of_pre2x4): for i in range(4): predecode_name = "predecode_{}".format(pre_num * 4 + i) out_name = "out_{}".format(i) pin = self.pre2x4_inst[pre_num].get_pin(out_name) - self.route_predecode_rail_m3(predecode_name, pin) + x_offset = self.pre2x4_inst[pre_num].rx() + self.m2_pitch + self.route_predecode_bus_inputs(predecode_name, pin, x_offset) # FIXME: convert to connect_bus for pre_num in range(self.no_of_pre3x8): @@ -472,44 +494,68 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(pre_num * 8 + i + self.no_of_pre2x4 * 4) out_name = "out_{}".format(i) pin = self.pre3x8_inst[pre_num].get_pin(out_name) - self.route_predecode_rail_m3(predecode_name, pin) + x_offset = self.pre3x8_inst[pre_num].rx() + self.m2_pitch + self.route_predecode_bus_inputs(predecode_name, pin, x_offset) - def route_rails_to_decoder(self): - """ Use the self.predec_groups to determine the connections to the decoder AND gates. - Inputs of AND2/AND3 gates come from different groups. - For example for these groups [ [0,1,2,3] ,[4,5,6,7], - [8,9,10,11,12,13,14,15] ] the first AND3 inputs are connected to - [0,4,8] and second AND3 is connected to [0,4,9] ........... and the - 128th AND3 is connected to [3,7,15] + def route_bus_to_decoder(self): """ - row_index = 0 + Use the self.predec_groups to determine the connections to the decoder AND gates. + Inputs of AND2/AND3 gates come from different groups. + For example for these groups + [ [0,1,2,3] ,[4,5,6,7], [8,9,10,11,12,13,14,15] ] + the first AND3 inputs are connected to [0,4,8], + second AND3 is connected to [0,4,9], + ... + and the 128th AND3 is connected to [3,7,15] + """ + output_index = 0 + if (self.num_inputs == 4 or self.num_inputs == 5): for index_B in self.predec_groups[1]: for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? - if (row_index < self.num_outputs): + if (output_index < self.num_outputs): + row_index = math.floor(output_index / self.decoders_per_row) + row_remainder = (output_index % self.decoders_per_row) + row_offset = row_index * self.and_inst[0].height + (2 * row_remainder + 4) * self.m1_pitch predecode_name = "predecode_{}".format(index_A) - self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("A")) + self.route_predecode_bus_outputs(predecode_name, + self.and_inst[output_index].get_pin("A"), + row_offset) predecode_name = "predecode_{}".format(index_B) - self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("B")) - row_index = row_index + 1 + self.route_predecode_bus_outputs(predecode_name, + self.and_inst[output_index].get_pin("B"), + row_offset + self.m1_pitch) + output_index = output_index + 1 elif (self.num_inputs > 5): for index_C in self.predec_groups[2]: for index_B in self.predec_groups[1]: for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? - if (row_index < self.num_outputs): + if (output_index < self.num_outputs): + row_index = math.floor(output_index / self.decoders_per_row) + row_remainder = (output_index % self.decoders_per_row) + row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 4) * self.m1_pitch predecode_name = "predecode_{}".format(index_A) - self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("A")) + self.route_predecode_bus_outputs(predecode_name, + self.and_inst[output_index].get_pin("A"), + row_offset) predecode_name = "predecode_{}".format(index_B) - self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("B")) + self.route_predecode_bus_outputs(predecode_name, + self.and_inst[output_index].get_pin("B"), + row_offset + self.m1_pitch) predecode_name = "predecode_{}".format(index_C) - self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("C")) - row_index = row_index + 1 + self.route_predecode_bus_outputs(predecode_name, + self.and_inst[output_index].get_pin("C"), + row_offset + 2 * self.m1_pitch) + output_index = output_index + 1 def route_vdd_gnd(self): - """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ + """ + Add a pin for each row of vdd/gnd which are + must-connects next level up. + """ # The vias will be placed in the center and right of the cells, respectively. xoffset = self.and_inst[0].rx() @@ -526,23 +572,42 @@ class hierarchical_decoder(design.design): self.copy_layout_pin(pre, "vdd") self.copy_layout_pin(pre, "gnd") - def route_predecode_rail(self, rail_name, pin): - """ Connect the routing rail to the given metal1 pin """ - rail_pos = vector(self.predecode_rails[rail_name].x, pin.lc().y) - self.add_path("m1", [rail_pos, pin.lc()]) - self.add_via_center(layers=self.m1_stack, - offset=rail_pos) + def route_predecode_bus_outputs(self, rail_name, pin, y_offset): + """ + Connect the routing rail to the given metal1 pin + using a routing track at the given y_offset + + """ + pin_pos = pin.center() + # If we have a single decoder per row, we can route on M1 + if self.decoders_per_row == 1: + rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y) + self.add_path("m1", [rail_pos, pin_pos]) + self.add_via_center(layers=self.m1_stack, + offset=rail_pos) + # If not, we must route over the decoder cells on M3 + else: + rail_pos = vector(self.predecode_bus[rail_name].x, y_offset) + mid_pos = vector(pin_pos.x, rail_pos.y) + self.add_wire(self.m2_stack[::-1], [rail_pos, mid_pos, pin_pos]) + self.add_via_center(layers=self.m2_stack, + offset=rail_pos) + self.add_via_center(layers=self.m1_stack, + offset=pin_pos) - def route_predecode_rail_m3(self, rail_name, pin): - """ Connect the routing rail to the given metal1 pin """ + def route_predecode_bus_inputs(self, rail_name, pin, x_offset): + """ + Connect the routing rail to the given metal1 pin using a jog + to the right of the cell at the given x_offset. + """ # This routes the pin up to the rail, basically, to avoid conflicts. # It would be fixed with a channel router. - mid_point = vector(pin.cx(), pin.cy() + self.inv.height / 2) - rail_pos = vector(self.predecode_rails[rail_name].x, mid_point.y) + pin_pos = pin.center() + mid_point1 = vector(x_offset, pin_pos.y) + mid_point2 = vector(x_offset, pin_pos.y + self.inv.height / 2) + rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y) + self.add_wire(self.m1_stack, [pin_pos, mid_point1, mid_point2, rail_pos]) self.add_via_center(layers=self.m1_stack, - offset=pin.center()) - self.add_wire(("m3", "via2", "m2"), [rail_pos, mid_point, pin.uc()]) - self.add_via_center(layers=self.m2_stack, offset=rail_pos) def input_load(self): diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index e7cc02e8..58894ccf 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -221,7 +221,7 @@ class pnand3(pgate.pgate): self.nmos3_inst, self.inputC_yoffset, "C", - position="center") + position="left") # FIXME: constant hack if OPTS.tech_name == "s8": @@ -232,7 +232,7 @@ class pnand3(pgate.pgate): self.nmos1_inst, self.inputA_yoffset, "A", - position="center") + position="left") def route_output(self): """ Route the Z output """ @@ -255,10 +255,10 @@ class pnand3(pgate.pgate): directions=("V", "V")) # PMOS3 and NMOS3 are drain aligned - self.add_path("m2", [pmos3_pin.center(), nmos3_pin.center()]) + self.add_path("m1", [pmos3_pin.center(), nmos3_pin.center()]) # Route in the A input track (top track) mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset) - self.add_path("m2", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()]) + self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()]) # This extends the output to the edge of the cell self.add_via_center(layers=self.m1_stack, diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index df979657..7b77c6d9 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -20,15 +20,6 @@ class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - # Doesn't require hierarchical decoder - # debug.info(1, "Testing 4 row sample for hierarchical_decoder") - # a = hierarchical_decoder.hierarchical_decoder(name="hd1, num_outputs=4) - # self.local_check(a) - - # Doesn't require hierarchical decoder - # debug.info(1, "Testing 8 row sample for hierarchical_decoder") - # a = hierarchical_decoder.hierarchical_decoder(name="hd2", num_outputs=8) - # self.local_check(a) # check hierarchical decoder for single port debug.info(1, "Testing 16 row sample for hierarchical_decoder") From afcb5174ac877ae66e6844c2a20ec08bb04acee8 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sat, 11 Apr 2020 01:19:04 -0700 Subject: [PATCH 247/521] discrete dff tests working --- compiler/characterizer/stimuli.py | 14 ++++++++------ compiler/pgates/ptx.py | 2 +- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index fc2a106f..b5a143cf 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -251,14 +251,16 @@ class stimuli(): def write_include(self, circuit): """Writes include statements, inputs are lists of model files""" - libraries = self.device_libraries + includes = self.device_models + [circuit] self.sf.write("* {} process corner\n".format(self.process)) - for item in list(libraries): - if os.path.isfile(item[0]): - self.sf.write(".lib \"{0}\" {1}\n".format(item[0], item[1])) - else: - debug.error("Could not find spice library: {0}\nSet SPICE_MODEL_DIR to over-ride path.\n".format(item[0])) + if OPTS.tech_name == "s8": + libraries = self.device_libraries + for item in list(libraries): + if os.path.isfile(item[0]): + self.sf.write(".lib \"{0}\" {1}\n".format(item[0], item[1])) + else: + debug.error("Could not find spice library: {0}\nSet SPICE_MODEL_DIR to over-ride path.\n".format(item[0])) for item in list(includes): if os.path.isfile(item): diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index ffd61a48..d51f42be 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -109,7 +109,7 @@ class ptx(design.design): perimeter_sd = 2 * self.poly_width + 2 * self.tx_width - if OPTS.tech_name == None: + if OPTS.tech_name == "s8": print("here {0}".format(self.name)) # s8 technology is in microns main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], From 2661a427260ab00be56d446eb10759519069fc26 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Tue, 14 Apr 2020 03:09:10 +0000 Subject: [PATCH 248/521] changes to support spare columns --- compiler/modules/port_data.py | 140 ++++++++++++++---- compiler/modules/sense_amp_array.py | 43 ++++-- compiler/modules/write_driver_array.py | 74 ++++++++- compiler/options.py | 1 + compiler/sram/sram_config.py | 7 +- .../09_sense_amp_array_spare_cols_test.py | 55 +++++++ .../10_write_driver_array_spare_cols_test.py | 55 +++++++ .../tests/18_port_data_spare_cols_test.py | 115 ++++++++++++++ 8 files changed, 439 insertions(+), 51 deletions(-) create mode 100755 compiler/tests/09_sense_amp_array_spare_cols_test.py create mode 100755 compiler/tests/10_write_driver_array_spare_cols_test.py create mode 100755 compiler/tests/18_port_data_spare_cols_test.py diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index fbf5223a..5fad35ae 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -27,6 +27,10 @@ class port_data(design.design): else: self.num_wmasks = 0 + if self.num_spare_cols is None: + self.num_spare_cols = 0 + + if name == "": name = "port_data_{0}".format(self.port) design.design.__init__(self, name) @@ -102,7 +106,7 @@ class port_data(design.design): self.DRC_LVS() def add_pins(self): - """ Adding pins for port address module""" + """ Adding pins for port data module""" self.add_pin("rbl_bl", "INOUT") self.add_pin("rbl_br", "INOUT") @@ -111,11 +115,18 @@ class port_data(design.design): br_name = self.get_br_name(self.port) self.add_pin("{0}_{1}".format(bl_name, bit), "INOUT") self.add_pin("{0}_{1}".format(br_name, bit), "INOUT") + + for bit in range(self.num_spare_cols): + bl_name = self.get_bl_name(self.port) + br_name = self.get_br_name(self.port) + self.add_pin("spare{0}_{1}".format(bl_name, bit), "INOUT") + self.add_pin("spare{0}_{1}".format(br_name, bit), "INOUT") + if self.port in self.read_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout_{}".format(bit), "OUTPUT") if self.port in self.write_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): self.add_pin("din_{}".format(bit), "INPUT") # Will be empty if no col addr lines sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)] @@ -128,6 +139,8 @@ class port_data(design.design): self.add_pin("w_en", "INPUT") for bit in range(self.num_wmasks): self.add_pin("bank_wmask_{}".format(bit), "INPUT") + for bit in range(self.num_spare_cols): + self.add_pin("spare_wen{}".format(bit), "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -179,7 +192,7 @@ class port_data(design.design): # Extra column +1 is for RBL # Precharge will be shifted left if needed self.precharge_array = factory.create(module_type="precharge_array", - columns=self.num_cols + 1, + columns=self.num_cols + self.num_spare_cols + 1, bitcell_bl=self.bl_names[self.port], bitcell_br=self.br_names[self.port]) self.add_mod(self.precharge_array) @@ -187,7 +200,8 @@ class port_data(design.design): if self.port in self.read_ports: self.sense_amp_array = factory.create(module_type="sense_amp_array", word_size=self.word_size, - words_per_row=self.words_per_row) + words_per_row=self.words_per_row, + num_spare_cols=self.num_spare_cols) self.add_mod(self.sense_amp_array) else: self.sense_amp_array = None @@ -206,7 +220,8 @@ class port_data(design.design): self.write_driver_array = factory.create(module_type="write_driver_array", columns=self.num_cols, word_size=self.word_size, - write_size=self.write_size) + write_size=self.write_size, + num_spare_cols=self.num_spare_cols) self.add_mod(self.write_driver_array) if self.write_size is not None: self.write_mask_and_array = factory.create(module_type="write_mask_and_array", @@ -249,7 +264,7 @@ class port_data(design.design): # We create a dummy here to get bl/br names to add those pins to this # module, which happens before we create the real precharge_array self.precharge_array = factory.create(module_type="precharge_array", - columns=self.num_cols + 1, + columns=self.num_cols + self.num_spare_cols + 1, bitcell_bl=self.bl_names[self.port], bitcell_br=self.br_names[self.port]) @@ -272,6 +287,10 @@ class port_data(design.design): for bit in range(self.num_cols): temp.append("{0}_{1}".format(bl_name, bit)) temp.append("{0}_{1}".format(br_name, bit)) + + for bit in range(self.num_spare_cols): + temp.append("sparebl{0}_{1}".format(self.port, bit)) + temp.append("sparebr{0}_{1}".format(self.port, bit)) # Use right BLs for RBL if self.port==1: @@ -297,7 +316,6 @@ class port_data(design.design): for col in range(self.num_cols): temp.append("{0}_{1}".format(bl_name, col)) temp.append("{0}_{1}".format(br_name, col)) - for word in range(self.words_per_row): temp.append("sel_{}".format(word)) for bit in range(self.word_size): @@ -330,8 +348,14 @@ class port_data(design.design): else: temp.append("{0}_out_{1}".format(bl_name, bit)) temp.append("{0}_out_{1}".format(br_name, bit)) - - temp.extend(["s_en", "vdd", "gnd"]) + + for bit in range(self.num_spare_cols): + temp.append("dout_{}".format(self.word_size + bit)) + temp.append("sparebl{0}_{1}".format(self.port, bit)) + temp.append("sparebr{0}_{1}".format(self.port, bit)) + + temp.append("s_en") + temp.extend(["vdd", "gnd"]) self.connect_inst(temp) def place_sense_amp_array(self, offset): @@ -346,7 +370,7 @@ class port_data(design.design): br_name = self.get_br_name(self.port) temp = [] - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): temp.append("din_{}".format(bit)) for bit in range(self.word_size): @@ -355,11 +379,20 @@ class port_data(design.design): temp.append("{0}_{1}".format(br_name, bit)) else: temp.append("{0}_out_{1}".format(bl_name, bit)) - temp.append("{0}_out_{1}".format(br_name, bit)) + temp.append("{0}_out_{1}".format(br_name, bit)) + + for bit in range(self.num_spare_cols): + temp.append("sparebl{0}_{1}".format(self.port, bit)) + temp.append("sparebr{0}_{1}".format(self.port, bit)) if self.write_size is not None: for i in range(self.num_wmasks): temp.append("wdriver_sel_{}".format(i)) + + elif self.num_spare_cols: + temp.append("w_en") + for i in range(self.num_spare_cols): + temp.append("spare_wen{}".format(i)) else: temp.append("w_en") temp.extend(["vdd", "gnd"]) @@ -445,7 +478,7 @@ class port_data(design.design): def route_sense_amp_out(self, port): """ Add pins for the sense amp output """ - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): data_pin = self.sense_amp_array_inst.get_pin("data_{}".format(bit)) self.add_layout_pin_rect_center(text="dout_{0}".format(bit), layer=data_pin.layer, @@ -456,7 +489,7 @@ class port_data(design.design): def route_write_driver_in(self, port): """ Connecting write driver """ - for row in range(self.word_size): + for row in range(self.word_size + self.num_spare_cols): data_name = "data_{}".format(row) din_name = "din_{}".format(row) self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name) @@ -545,12 +578,36 @@ class port_data(design.design): else: start_bit=0 - self.channel_route_bitlines(inst1=inst1, - inst1_bls_template=inst1_bls_templ, - inst2=inst2, - num_bits=self.word_size, - inst1_start_bit=start_bit) + if self.port==0: + off = 1 + else: + off = 0 + + if self.num_spare_cols != 0 and self.col_addr_size>0: + self.channel_route_bitlines(inst1=self.column_mux_array_inst, + inst1_bls_template="{inst}_out_{bit}", + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) + + self.channel_route_bitlines(inst1=self.precharge_array_inst, + inst1_bls_template="{inst}_{bit}", + inst2=inst2, + num_bits=self.num_spare_cols, + inst1_start_bit=self.num_cols + off, + inst2_start_bit=self.word_size) + + else: + self.channel_route_bitlines(inst1=inst1, + inst1_bls_template=inst1_bls_templ, + inst2=inst2, + num_bits=self.word_size + self.num_spare_cols, + inst1_start_bit=start_bit) + + + # spare cols connected to precharge array since they are read independently + def route_write_driver_to_column_mux_or_precharge_array(self, port): """ Routing of BL and BR between sense_amp and column mux or precharge array """ inst2 = self.write_driver_array_inst @@ -569,10 +626,33 @@ class port_data(design.design): else: start_bit=0 - self.channel_route_bitlines(inst1=inst1, inst2=inst2, - num_bits=self.word_size, - inst1_bls_template=inst1_bls_templ, - inst1_start_bit=start_bit) + if self.port==0: + off=1 + else: + off=0 + + + if self.num_spare_cols != 0 and self.col_addr_size>0: + self.channel_route_bitlines(inst1=self.column_mux_array_inst, + inst1_bls_template="{inst}_out_{bit}", + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) + + self.channel_route_bitlines(inst1=self.precharge_array_inst, + inst1_bls_template="{inst}_{bit}", + inst2=inst2, + num_bits=self.num_spare_cols, + inst1_start_bit=self.num_cols + off, + inst2_start_bit=self.word_size) + + else: + self.channel_route_bitlines(inst1=inst1, + inst1_bls_template=inst1_bls_templ, + inst2=inst2, + num_bits=self.word_size + self.num_spare_cols, + inst1_start_bit=start_bit) + def route_write_driver_to_sense_amp(self, port): """ Routing of BL and BR between write driver and sense amp """ @@ -584,7 +664,7 @@ class port_data(design.design): # but just in case, do a channel route. self.channel_route_bitlines(inst1=inst1, inst2=inst2, - num_bits=self.word_size) + num_bits=self.word_size + self.num_spare_cols) def route_bitline_pins(self): """ Add the bitline pins for the given port """ @@ -595,13 +675,13 @@ class port_data(design.design): self.copy_layout_pin(self.precharge_array_inst, "br_0", "rbl_br") bit_offset=1 elif self.port==1: - self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(self.num_cols), "rbl_bl") - self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(self.num_cols), "rbl_br") + self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(self.num_cols + self.num_spare_cols), "rbl_bl") + self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(self.num_cols + self.num_spare_cols), "rbl_br") bit_offset=0 else: bit_offset=0 - for bit in range(self.num_cols): + for bit in range(self.num_cols + self.num_spare_cols): if self.precharge_array_inst: self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(bit + bit_offset), @@ -621,12 +701,16 @@ class port_data(design.design): for pin_name in sel_names: self.copy_layout_pin(self.column_mux_array_inst, pin_name) if self.sense_amp_array_inst: - self.copy_layout_pin(self.sense_amp_array_inst, "en", "s_en") + self.copy_layout_pin(self.sense_amp_array_inst, "en", "s_en") if self.write_driver_array_inst: if self.write_mask_and_array_inst: for bit in range(self.num_wmasks): # Add write driver's en_{} pins self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit), "wdriver_sel_{}".format(bit)) + elif self.num_spare_cols: + self.copy_layout_pin(self.write_driver_array_inst, "en_0", "w_en") + for bit in range(self.num_spare_cols): + self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + 1), "spare_wen{}".format(bit)) else: self.copy_layout_pin(self.write_driver_array_inst, "en", "w_en") if self.write_mask_and_array_inst: diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 322cc1b3..8640e033 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -19,7 +19,7 @@ class sense_amp_array(design.design): Dynamically generated sense amp array for all bitlines. """ - def __init__(self, name, word_size, words_per_row): + def __init__(self, name, word_size, words_per_row, num_spare_cols=None): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("word_size {0}".format(word_size)) @@ -27,8 +27,12 @@ class sense_amp_array(design.design): self.word_size = word_size self.words_per_row = words_per_row - self.row_size = self.word_size * self.words_per_row - + + if not num_spare_cols: + self.num_spare_cols = 0 + else: + self.num_spare_cols = num_spare_cols + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -58,9 +62,9 @@ class sense_amp_array(design.design): self.height = self.amp.height if self.bitcell.width > self.amp.width: - self.width = self.bitcell.width * self.word_size * self.words_per_row + self.width = self.bitcell.width * (self.word_size * self.words_per_row + self.num_spare_cols) else: - self.width = self.amp.width * self.word_size * self.words_per_row + self.width = self.amp.width * (self.word_size * self.words_per_row + self.num_spare_cols) self.place_sense_amp_array() self.add_layout_pins() @@ -69,7 +73,7 @@ class sense_amp_array(design.design): self.DRC_LVS() def add_pins(self): - for i in range(0,self.word_size): + for i in range(0,self.word_size + self.num_spare_cols): self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT") self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT") self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT") @@ -88,8 +92,7 @@ class sense_amp_array(design.design): def create_sense_amp_array(self): self.local_insts = [] - for i in range(0,self.word_size): - + for i in range(0,self.word_size + self.num_spare_cols): name = "sa_d{0}".format(i) self.local_insts.append(self.add_inst(name=name, mod=self.amp)) @@ -102,13 +105,14 @@ class sense_amp_array(design.design): from tech import cell_properties if self.bitcell.width > self.amp.width: amp_spacing = self.bitcell.width * self.words_per_row + spare_cols_spacing = self.bitcell.width else: amp_spacing = self.amp.width * self.words_per_row + spare_cols_spacing = self.amp.width for i in range(0,self.word_size): xoffset = amp_spacing * i - - # align the xoffset to the grid of bitcells. This way we + # align the xoffset to the grid of bitcells. This way we # know when to do the mirroring. grid_x = int(xoffset / self.amp.width) @@ -120,6 +124,23 @@ class sense_amp_array(design.design): amp_position = vector(xoffset, 0) self.local_insts[i].place(offset=amp_position,mirror=mirror) + + # place spare sense amps (will share the same enable as regular sense amps) + for i in range(0,self.num_spare_cols): + index = self.word_size + i + xoffset = ((self.word_size * self.words_per_row) + i) * spare_cols_spacing + # align the xoffset to the grid of bitcells. This way we + # know when to do the mirroring. + grid_x = int(xoffset / self.amp.width) + + if cell_properties.bitcell.mirror.y and grid_x % 2: + mirror = "MY" + xoffset = xoffset + self.amp.width + else: + mirror = "" + + amp_position = vector(xoffset, 0) + self.local_insts[index].place(offset=amp_position,mirror=mirror) def add_layout_pins(self): @@ -173,7 +194,7 @@ class sense_amp_array(design.design): def get_en_cin(self): """Get the relative capacitance of all the sense amp enable connections in the array""" sense_amp_en_cin = self.amp.get_en_cin() - return sense_amp_en_cin * self.word_size + return sense_amp_en_cin * (self.word_size + self.num_spare_cols) def get_drain_cin(self): """Get the relative capacitance of the drain of the PMOS isolation TX""" diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 08a2e007..f56c5e49 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -19,7 +19,7 @@ class write_driver_array(design.design): Dynamically generated write driver array of all bitlines. """ - def __init__(self, name, columns, word_size,write_size=None): + def __init__(self, name, columns, word_size, num_spare_cols=None, write_size=None): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) @@ -29,6 +29,10 @@ class write_driver_array(design.design): self.word_size = word_size self.write_size = write_size self.words_per_row = int(columns / word_size) + if not num_spare_cols: + self.num_spare_cols = 0 + else: + self.num_spare_cols = num_spare_cols if self.write_size: self.num_wmasks = int(self.word_size/self.write_size) @@ -61,9 +65,13 @@ class write_driver_array(design.design): def create_layout(self): if self.bitcell.width > self.driver.width: - self.width = self.columns * self.bitcell.width + self.width = (self.columns + self.num_spare_cols) * self.bitcell.width + self.width_regular_cols = self.columns * self.bitcell.width + self.single_col_width = self.bitcell.width else: - self.width = self.columns * self.driver.width + self.width = (self.columns + self.num_spare_cols) * self.driver.width + self.width_regular_cols = self.columns * self.driver.width + self.single_col_width = self.driver.width self.height = self.driver.height self.place_write_array() @@ -72,14 +80,17 @@ class write_driver_array(design.design): self.DRC_LVS() def add_pins(self): - for i in range(self.word_size): + for i in range(self.word_size + self.num_spare_cols): self.add_pin(self.data_name + "_{0}".format(i), "INPUT") - for i in range(self.word_size): + for i in range(self.word_size + self.num_spare_cols): self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT") self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT") if self.write_size: for i in range(self.num_wmasks): self.add_pin(self.en_name + "_{0}".format(i), "INPUT") + elif self.num_spare_cols: + for i in range(self.num_spare_cols + 1): + self.add_pin(self.en_name + "_{0}".format(i), "INPUT") else: self.add_pin(self.en_name, "INPUT") self.add_pin("vdd", "POWER") @@ -113,12 +124,30 @@ class write_driver_array(design.design): if w == self.write_size: w = 0 windex+=1 + + elif self.num_spare_cols: + self.connect_inst([self.data_name + "_{0}".format(index), + self.get_bl_name() + "_{0}".format(index), + self.get_br_name() + "_{0}".format(index), + self.en_name + "_{0}".format(0), "vdd", "gnd"]) + else: self.connect_inst([self.data_name + "_{0}".format(index), self.get_bl_name() + "_{0}".format(index), self.get_br_name() + "_{0}".format(index), self.en_name, "vdd", "gnd"]) + for i in range(self.num_spare_cols): + index = self.word_size + i + name = "write_driver{}".format(index) + self.driver_insts[index]=self.add_inst(name=name, + mod=self.driver) + + self.connect_inst([self.data_name + "_{0}".format(index), + self.get_bl_name() + "_{0}".format(index), + self.get_br_name() + "_{0}".format(index), + self.en_name + "_{0}".format(i + 1), "vdd", "gnd"]) + def place_write_array(self): from tech import cell_properties @@ -139,9 +168,23 @@ class write_driver_array(design.design): base = vector(xoffset, 0) self.driver_insts[index].place(offset=base, mirror=mirror) + # place spare write drivers (if spare columns are specified) + for i in range(self.num_spare_cols): + index = self.word_size + i + xoffset = (self.columns + i) * self.driver_spacing + + if cell_properties.bitcell.mirror.y and i % 2: + mirror = "MY" + xoffset = xoffset + self.driver.width + else: + mirror = "" + + base = vector(xoffset, 0) + self.driver_insts[index].place(offset=base, mirror=mirror) + def add_layout_pins(self): - for i in range(self.word_size): + for i in range(self.word_size + self.num_spare_cols): inst = self.driver_insts[i] din_pin = inst.get_pin(inst.mod.din_name) self.add_layout_pin(text=self.data_name + "_{0}".format(i), @@ -186,14 +229,29 @@ class write_driver_array(design.design): offset=en_pin.ll(), width=wmask_en_len-en_gap, height=en_pin.height()) + + elif self.num_spare_cols: + # shorten enable rail to accomodate those for spare write drivers + inst = self.driver_insts[0] + self.add_layout_pin(text=self.en_name + "_{0}".format(0), + layer="m1", + offset=inst.get_pin(inst.mod.en_name).ll(), + width=self.width_regular_cols - (self.words_per_row * inst.get_pin(inst.mod.en_name).width())) + + # individual enables for every spare write driver + for i in range(self.num_spare_cols): + inst = self.driver_insts[self.word_size + i] + self.add_layout_pin(text=self.en_name + "_{0}".format(i + 1), + layer="m1", + offset=inst.get_pin(inst.mod.en_name).ll(), + width=self.single_col_width - inst.get_pin(inst.mod.en_name).width()) + else: inst = self.driver_insts[0] self.add_layout_pin(text=self.en_name, layer="m1", offset=inst.get_pin(inst.mod.en_name).ll().scale(0,1), width=self.width) - - def get_w_en_cin(self): diff --git a/compiler/options.py b/compiler/options.py index 1c5d3e6a..5a35b173 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -45,6 +45,7 @@ class options(optparse.Values): # You can manually specify banks, but it is better to auto-detect it. num_banks = 1 num_spare_rows = 0 + # num_spare_cols = 0 ################### # Optimization options diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index e5d9c8dc..3af2fd9c 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -14,19 +14,18 @@ from sram_factory import factory class sram_config: """ This is a structure that is used to hold the SRAM configuration options. """ - def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None, num_spare_rows=0): + def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None, num_spare_rows=0, num_spare_cols=None): self.word_size = word_size self.num_words = num_words self.write_size = write_size self.num_banks = num_banks self.num_spare_rows = num_spare_rows + self.num_spare_cols = num_spare_cols # This will get over-written when we determine the organization self.words_per_row = words_per_row - self.compute_sizes() - - + self.compute_sizes() def set_local_config(self, module): """ Copy all of the member variables to the given module for convenience """ diff --git a/compiler/tests/09_sense_amp_array_spare_cols_test.py b/compiler/tests/09_sense_amp_array_spare_cols_test.py new file mode 100755 index 00000000..1eabe196 --- /dev/null +++ b/compiler/tests/09_sense_amp_array_spare_cols_test.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class sense_amp_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check sense amp array for single port + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1, num_spare_cols=3) + self.local_check(a) + + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=2) + self.local_check(a) + + # check sense amp array for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + factory.reset() + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2, num_spare_cols=2) + self.local_check(a) + + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=3) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_spare_cols_test.py b/compiler/tests/10_write_driver_array_spare_cols_test.py new file mode 100755 index 00000000..c5e7132f --- /dev/null +++ b/compiler/tests/10_write_driver_array_spare_cols_test.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class write_driver_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check write driver array for single port + debug.info(2, "Testing write_driver_array for columns=8, word_size=8") + a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3) + self.local_check(a) + + debug.info(2, "Testing write_driver_array for columns=16, word_size=8") + a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3) + self.local_check(a) + + # check write driver array for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + factory.reset() + debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") + a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3) + self.local_check(a) + + debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") + a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py new file mode 100755 index 00000000..1695f861 --- /dev/null +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class port_data_spare_cols_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + c = sram_config(word_size=8, + num_words=16, + num_spare_rows=1, + num_spare_cols=1) + + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + c.num_spare_cols=3 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + c.num_spare_cols=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + OPTS.bitcell = "bitcell_1w_1r" + OPTS.num_rw_ports = 0 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + c.num_words=16 + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 5f4ed47c57e9ec62e4f25c6426664d0c26f68543 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Mon, 13 Apr 2020 20:48:34 -0700 Subject: [PATCH 249/521] netlist only discrete simulating --- compiler/pgates/pnand2.py | 5 +++++ compiler/pgates/pnand3.py | 6 +++++- compiler/pgates/pnor2.py | 4 ++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 4a813269..22a03b6d 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -9,6 +9,7 @@ import contact import pgate import debug from tech import drc, parameter, spice +from globals import OPTS from vector import vector import logical_effort from sram_factory import factory @@ -37,6 +38,10 @@ class pnand2(pgate.pgate): debug.check(size == 1, "Size 1 pnand2 is only supported now.") self.tx_mults = 1 + if OPTS.tech_name == "s8": + (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) + (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) + # Creates the netlist and layout pgate.pgate.__init__(self, name, height) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index cc6fd0f8..c93c867f 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -12,7 +12,7 @@ from tech import drc, parameter, spice from vector import vector import logical_effort from sram_factory import factory - +from globals import OPTS class pnand3(pgate.pgate): """ @@ -40,6 +40,10 @@ class pnand3(pgate.pgate): "Size 1 pnand3 is only supported now.") self.tx_mults = 1 + if OPTS.tech_name == "s8": + (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) + (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) + # Creates the netlist and layout pgate.pgate.__init__(self, name, height) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 75840f26..47c1cc16 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -36,6 +36,10 @@ class pnor2(pgate.pgate): debug.check(size==1, "Size 1 pnor2 is only supported now.") self.tx_mults = 1 + if OPTS.tech_name == "s8": + (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) + (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) + # Creates the netlist and layout pgate.pgate.__init__(self, name, height) From 43dcf675a10ec3797191218607ec8260fb0c5a54 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 14 Apr 2020 10:52:25 -0700 Subject: [PATCH 250/521] Move pnand outputs to M1. Debug hierarchical decoder multirow. --- compiler/modules/hierarchical_decoder.py | 32 +++++++---- compiler/pgates/pnand2.py | 66 ++++++++++++++-------- compiler/pgates/pnand3.py | 72 +++++++++++++++++------- compiler/pgates/ptx.py | 37 +++++++----- 4 files changed, 139 insertions(+), 68 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 0e5b3606..a805e635 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -199,7 +199,8 @@ class hierarchical_decoder(design.design): self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch # Calculates height and width of hierarchical decoder - self.height = max(self.predecoder_height, self.row_decoder_height) + # Add extra pitch for good measure + self.height = max(self.predecoder_height, self.row_decoder_height) + self.m3_pitch self.width = self.input_routing_width + self.predecoder_width \ + self.internal_routing_width \ + self.decoders_per_row * nand_width + self.inv.width @@ -261,7 +262,10 @@ class hierarchical_decoder(design.design): self.route_input_bus(decoder_offset, input_offset) def route_input_bus(self, input_offset, output_offset): - """ Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """ + """ + Route a vertical M2 coordinate to another + vertical M2 coordinate to the predecode inputs + """ self.add_via_center(layers=self.m2_stack, offset=input_offset) @@ -471,10 +475,10 @@ class hierarchical_decoder(design.design): names=input_bus_names, length=self.height) - self.route_bus_to_predecodes() + self.route_predecodes_to_bus() self.route_bus_to_decoder() - def route_bus_to_predecodes(self): + def route_predecodes_to_bus(self): """ Iterates through all of the predecodes and connects to the rails including the offsets @@ -517,7 +521,7 @@ class hierarchical_decoder(design.design): if (output_index < self.num_outputs): row_index = math.floor(output_index / self.decoders_per_row) row_remainder = (output_index % self.decoders_per_row) - row_offset = row_index * self.and_inst[0].height + (2 * row_remainder + 4) * self.m1_pitch + row_offset = row_index * self.and_inst[0].height + (2 * row_remainder + 1) * self.m3_pitch predecode_name = "predecode_{}".format(index_A) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("A"), @@ -525,7 +529,7 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(index_B) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("B"), - row_offset + self.m1_pitch) + row_offset + self.m3_pitch) output_index = output_index + 1 elif (self.num_inputs > 5): @@ -536,7 +540,7 @@ class hierarchical_decoder(design.design): if (output_index < self.num_outputs): row_index = math.floor(output_index / self.decoders_per_row) row_remainder = (output_index % self.decoders_per_row) - row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 4) * self.m1_pitch + row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 1) * self.m3_pitch predecode_name = "predecode_{}".format(index_A) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("A"), @@ -544,11 +548,11 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(index_B) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("B"), - row_offset + self.m1_pitch) + row_offset + self.m3_pitch) predecode_name = "predecode_{}".format(index_C) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("C"), - row_offset + 2 * self.m1_pitch) + row_offset + 2 * self.m3_pitch) output_index = output_index + 1 def route_vdd_gnd(self): @@ -557,13 +561,19 @@ class hierarchical_decoder(design.design): must-connects next level up. """ - # The vias will be placed in the center and right of the cells, respectively. - xoffset = self.and_inst[0].rx() + # The vias will be placed at the right of the cells. + xoffset = max(x.rx() for x in self.and_inst) for num in range(0, self.num_outputs): + # Only add the power pin for the 1st in each row + if num % self.decoders_per_row: + continue + for pin_name in ["vdd", "gnd"]: # The nand and inv are the same height rows... supply_pin = self.and_inst[num].get_pin(pin_name) pin_pos = vector(xoffset, supply_pin.cy()) + self.add_path("m1", + [supply_pin.lc(), vector(xoffset, supply_pin.cy())]) self.add_power_pin(name=pin_name, loc=pin_pos) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 4a813269..2f21c0bb 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -98,7 +98,7 @@ class pnand2(pgate.pgate): # metal spacing to allow contacts on any layer self.input_spacing = max(self.poly_space + contact.poly_contact.first_layer_width, self.m1_space + contact.m1_via.first_layer_width, - self.m2_space + contact.m2_via.first_layer_width, + self.m2_space + contact.m2_via.first_layer_width, self.m3_space + contact.m2_via.second_layer_width) @@ -173,13 +173,15 @@ class pnand2(pgate.pgate): 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos_nd.active_height)) def add_well_contacts(self): - """ + """ Add n/p well taps to the layout and connect to supplies AFTER the wells are created """ - self.add_nwell_contact(self.pmos, self.pmos2_pos) - self.add_pwell_contact(self.nmos_nd, self.nmos2_pos) + self.add_nwell_contact(self.pmos, + self.pmos2_pos + vector(self.m1_pitch, 0)) + self.add_pwell_contact(self.nmos_nd, + self.nmos2_pos + vector(self.m1_pitch, 0)) def connect_rails(self): """ Connect the nmos and pmos to its respective power rails """ @@ -197,7 +199,7 @@ class pnand2(pgate.pgate): self.nmos2_inst, inputB_yoffset, "B", - position="right") + position="center") # This will help with the wells and the input/output placement self.inputA_yoffset = self.pmos2_inst.by() - self.poly_extend_active \ @@ -209,6 +211,7 @@ class pnand2(pgate.pgate): def route_output(self): """ Route the Z output """ + # PMOS1 drain pmos_pin = self.pmos1_inst.get_pin("D") top_pin_offset = pmos_pin.center() @@ -217,29 +220,46 @@ class pnand2(pgate.pgate): bottom_pin_offset = nmos_pin.center() # Output pin - out_offset = vector(nmos_pin.center().x + self.m1_pitch, + c_pin = self.get_pin("B") + out_offset = vector(c_pin.cx() + self.m1_pitch, self.inputA_yoffset) - # Midpoints of the L routes go horizontal first then vertical - mid1_offset = vector(out_offset.x, top_pin_offset.y) + # This routes on M2 + # # Midpoints of the L routes go horizontal first then vertical + # mid1_offset = vector(out_offset.x, top_pin_offset.y) + # mid2_offset = vector(out_offset.x, bottom_pin_offset.y) + + # # Non-preferred active contacts + # self.add_via_center(layers=self.m1_stack, + # directions=("V", "H"), + # offset=pmos_pin.center()) + # # Non-preferred active contacts + # self.add_via_center(layers=self.m1_stack, + # directions=("V", "H"), + # offset=nmos_pin.center()) + # self.add_via_center(layers=self.m1_stack, + # offset=out_offset) + + # # PMOS1 to mid-drain to NMOS2 drain + # self.add_path("m2", + # [top_pin_offset, mid1_offset, out_offset, + # mid2_offset, bottom_pin_offset]) + + # This routes on M1 + # Midpoints of the L routes goes vertical first then horizontal + mid1_offset = vector(top_pin_offset.x, out_offset.y) + # Midpoints of the L routes goes horizontal first then vertical mid2_offset = vector(out_offset.x, bottom_pin_offset.y) - # Non-preferred active contacts - self.add_via_center(layers=self.m1_stack, - directions=("V", "H"), - offset=pmos_pin.center()) - # Non-preferred active contacts - self.add_via_center(layers=self.m1_stack, - directions=("V", "H"), - offset=nmos_pin.center()) - self.add_via_center(layers=self.m1_stack, - offset=out_offset) + self.add_path("m1", + [top_pin_offset, mid1_offset, out_offset]) + # Route in two segments to have the width rule + self.add_path("m1", + [bottom_pin_offset, mid2_offset + vector(0.5 * self.m1_width, 0)], + width=nmos_pin.height()) + self.add_path("m1", + [mid2_offset, out_offset]) - # PMOS1 to mid-drain to NMOS2 drain - self.add_path("m2", - [top_pin_offset, mid1_offset, out_offset, - mid2_offset, bottom_pin_offset]) - # This extends the output to the edge of the cell self.add_layout_pin_rect_center(text="Z", layer="m1", diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 58894ccf..83e57c0a 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -191,8 +191,10 @@ class pnand3(pgate.pgate): def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ - self.add_nwell_contact(self.pmos, self.pmos3_pos) - self.add_pwell_contact(self.nmos_ns, self.nmos3_pos) + self.add_nwell_contact(self.pmos, + self.pmos3_pos + vector(self.m1_pitch, 0)) + self.add_pwell_contact(self.nmos_ns, + self.nmos3_pos + vector(self.m1_pitch, 0)) def connect_rails(self): """ Connect the nmos and pmos to its respective power rails """ @@ -221,7 +223,7 @@ class pnand3(pgate.pgate): self.nmos3_inst, self.inputC_yoffset, "C", - position="left") + position="right") # FIXME: constant hack if OPTS.tech_name == "s8": @@ -236,6 +238,7 @@ class pnand3(pgate.pgate): def route_output(self): """ Route the Z output """ + # PMOS1 drain pmos1_pin = self.pmos1_inst.get_pin("D") # PMOS3 drain @@ -243,29 +246,56 @@ class pnand3(pgate.pgate): # NMOS3 drain nmos3_pin = self.nmos3_inst.get_pin("D") - # Go up to metal2 for ease on all output pins - self.add_via_center(layers=self.m1_stack, - offset=pmos1_pin.center(), - directions=("V", "V")) - self.add_via_center(layers=self.m1_stack, - offset=pmos3_pin.center(), - directions=("V", "V")) - self.add_via_center(layers=self.m1_stack, - offset=nmos3_pin.center(), - directions=("V", "V")) + # midpoint for routing + mid_offset = vector(nmos3_pin.cx() + self.m1_pitch, + self.inputA_yoffset) + + # Aligned with the well taps + out_offset = vector(self.nwell_contact.cx(), + self.inputA_yoffset) - # PMOS3 and NMOS3 are drain aligned - self.add_path("m1", [pmos3_pin.center(), nmos3_pin.center()]) - # Route in the A input track (top track) - mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset) - self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()]) + # Go up to metal2 for ease on all output pins + # self.add_via_center(layers=self.m1_stack, + # offset=pmos1_pin.center(), + # directions=("V", "V")) + # self.add_via_center(layers=self.m1_stack, + # offset=pmos3_pin.center(), + # directions=("V", "V")) + # self.add_via_center(layers=self.m1_stack, + # offset=nmos3_pin.center(), + # directions=("V", "V")) + + # # Route in the A input track (top track) + # mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset) + # self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()]) # This extends the output to the edge of the cell - self.add_via_center(layers=self.m1_stack, - offset=mid_offset) + # self.add_via_center(layers=self.m1_stack, + # offset=mid_offset) + + top_left_pin_offset = pmos1_pin.center() + top_right_pin_offset = pmos3_pin.center() + bottom_pin_offset = nmos3_pin.center() + + # PMOS1 to output + self.add_path("m1", [top_left_pin_offset, + vector(top_left_pin_offset.x, out_offset.y), + out_offset]) + # PMOS3 to output + self.add_path("m1", [top_right_pin_offset, + vector(top_right_pin_offset.x, mid_offset.y), + mid_offset]) + # NMOS3 to output + mid2_offset = vector(mid_offset.x, bottom_pin_offset.y) + self.add_path("m1", + [bottom_pin_offset, mid2_offset], + width=nmos3_pin.height()) + mid3_offset = vector(mid_offset.x, nmos3_pin.by()) + self.add_path("m1", [mid3_offset, mid_offset]) + self.add_layout_pin_rect_center(text="Z", layer="m1", - offset=mid_offset, + offset=out_offset, width=contact.m1_via.first_layer_width, height=contact.m1_via.first_layer_height) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index f07f4b29..b4b20381 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -471,13 +471,13 @@ class ptx(design.design): """Returns an object representing the parameters for delay in tau units.""" # FIXME: Using the same definition as the pinv.py. - parasitic_delay = 1 - size = self.mults*self.tx_width/drc("minwidth_tx") - return logical_effort.logical_effort(self.name, - size, - self.input_load(), - cout, - parasitic_delay) + parasitic_delay = 1 + size = self.mults * self.tx_width / drc("minwidth_tx") + return logical_effort.logical_effort(self.name, + size, + self.input_load(), + cout, + parasitic_delay) def input_load(self): """ @@ -485,7 +485,7 @@ class ptx(design.design): """ # FIXME: this will be applied for the loads of the drain/source - return self.mults*self.tx_width/drc("minwidth_tx") + return self.mults * self.tx_width / drc("minwidth_tx") def add_diff_contact(self, label, pos): contact=self.add_via_center(layers=self.active_stack, @@ -496,14 +496,25 @@ class ptx(design.design): well_type=self.well_type) if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=pos) - + contact=self.add_via_center(layers=self.li_stack, + offset=pos, + directions=("V", "V")) + + # contact_area = contact.mod.second_layer_width * contact.mod.second_layer_height + # min_area = drc("minarea_m1") + # width = contact.mod.second_layer_width + # if contact_area < min_area: + # height = min_area / width + # else: + # height = contact.mod.second_layer_height + width = contact.mod.second_layer_width + height = contact.mod.second_layer_height self.add_layout_pin_rect_center(text=label, layer="m1", offset=pos, - width=contact.mod.second_layer_width, - height=contact.mod.second_layer_height) + width=width, + height=height) + return(contact) def get_cin(self): From 32d190b8b1fe9f6e3a4fdd5174fda78e79af17dd Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 14 Apr 2020 12:15:56 -0700 Subject: [PATCH 251/521] Jog connection on M1 for bank select. --- compiler/modules/bank_select.py | 90 +++++++++++++++------------------ 1 file changed, 41 insertions(+), 49 deletions(-) diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index c3307ece..b717399f 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -45,11 +45,9 @@ class bank_select(design.design): self.height = max([x.uy() for x in self.inv_inst]) + self.m1_width self.width = max([x.rx() for x in self.inv_inst]) - self.add_boundary() self.DRC_LVS() - def add_pins(self): # Number of control lines in the bus @@ -65,19 +63,18 @@ class bank_select(design.design): if (self.port == "rw") or (self.port == "r"): self.input_control_signals.append("s_en") # These will be outputs of the gaters if this is multibank - self.control_signals = ["gated_"+str for str in self.input_control_signals] + self.control_signals = ["gated_" + str for str in self.input_control_signals] self.add_pin_list(self.input_control_signals, "INPUT") self.add_pin("bank_sel") self.add_pin_list(self.control_signals, "OUTPUT") - self.add_pin("vdd","POWER") - self.add_pin("gnd","GROUND") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): """ Create modules for later instantiation """ - self.bitcell = factory.create(module_type="bitcell") - - height = self.bitcell.height + drc("poly_to_active") + self.dff = factory.create(module_type="dff") + height = self.dff.height + drc("poly_to_active") # 1x Inverter self.inv_sel = factory.create(module_type="pinv", height=height) @@ -98,17 +95,15 @@ class bank_select(design.design): def calculate_module_offsets(self): - self.xoffset_nand = self.inv4x.width + 2*self.m2_pitch + drc("pwell_to_nwell") - self.xoffset_nor = self.inv4x.width + 2*self.m2_pitch + drc("pwell_to_nwell") - self.xoffset_bank_sel_inv = 0 + self.xoffset_nand = self.inv4x.width + 2 * self.m2_pitch + drc("pwell_to_nwell") + self.xoffset_nor = self.inv4x.width + 2 * self.m2_pitch + drc("pwell_to_nwell") + self.xoffset_bank_sel_inv = 0 self.xoffset_inputs = 0 - self.yoffset_maxpoint = self.num_control_lines * self.inv4x.height - def create_instances(self): - self.bank_sel_inv=self.add_inst(name="bank_sel_inv", + self.bank_sel_inv=self.add_inst(name="bank_sel_inv", mod=self.inv_sel) self.connect_inst(["bank_sel", "bank_sel_bar", "vdd", "gnd"]) @@ -125,36 +120,36 @@ class bank_select(design.design): # (writes occur on clk low) if input_name in ("clk_buf"): - self.logic_inst.append(self.add_inst(name=name_nor, - mod=self.nor2)) + self.logic_inst.append(self.add_inst(name=name_nor, + mod=self.nor2)) self.connect_inst([input_name, "bank_sel_bar", - gated_name+"_temp_bar", + gated_name + "_temp_bar", "vdd", "gnd"]) # They all get inverters on the output - self.inv_inst.append(self.add_inst(name=name_inv, + self.inv_inst.append(self.add_inst(name=name_inv, mod=self.inv4x_nor)) - self.connect_inst([gated_name+"_temp_bar", + self.connect_inst([gated_name + "_temp_bar", gated_name, "vdd", "gnd"]) # the rest are AND (nand2+inv) gates else: - self.logic_inst.append(self.add_inst(name=name_nand, + self.logic_inst.append(self.add_inst(name=name_nand, mod=self.nand2)) self.connect_inst([input_name, "bank_sel", - gated_name+"_temp_bar", + gated_name + "_temp_bar", "vdd", "gnd"]) # They all get inverters on the output - self.inv_inst.append(self.add_inst(name=name_inv, + self.inv_inst.append(self.add_inst(name=name_inv, mod=self.inv4x)) - self.connect_inst([gated_name+"_temp_bar", + self.connect_inst([gated_name + "_temp_bar", gated_name, "vdd", "gnd"]) @@ -177,9 +172,9 @@ class bank_select(design.design): if i == 0: y_offset = 0 else: - y_offset = self.inv4x_nor.height + self.inv4x.height * (i-1) + y_offset = self.inv4x_nor.height + self.inv4x.height * (i - 1) - if i%2: + if i % 2: y_offset += self.inv4x.height mirror = "MX" else: @@ -200,7 +195,6 @@ class bank_select(design.design): # They all get inverters on the output inv_inst.place(offset=[logic_inst.rx(), y_offset], mirror=mirror) - def route_instances(self): @@ -222,57 +216,56 @@ class bank_select(design.design): end=bank_sel_pin_end) self.add_via_center(layers=self.m2_stack, offset=bank_sel_pin_end, - directions=("H","H")) + directions=("H", "H")) # bank_sel_bar is vertical wire bank_sel_bar_pin = self.bank_sel_inv.get_pin("Z") xoffset_bank_sel_bar = bank_sel_bar_pin.rx() self.add_label_pin(text="bank_sel_bar", - layer="m2", - offset=vector(xoffset_bank_sel_bar, 0), + layer="m2", + offset=vector(xoffset_bank_sel_bar, 0), height=self.inv4x.height) self.add_via_center(layers=self.m1_stack, offset=bank_sel_bar_pin.rc()) - for i in range(self.num_control_lines): logic_inst = self.logic_inst[i] inv_inst = self.inv_inst[i] input_name = self.input_control_signals[i] - gated_name = self.control_signals[i] + gated_name = self.control_signals[i] if input_name in ("clk_buf"): xoffset_bank_signal = xoffset_bank_sel_bar else: xoffset_bank_signal = xoffset_bank_sel # Connect the logic output to inverter input - pre = logic_inst.get_pin("Z").lc() - out_position = logic_inst.get_pin("Z").rc() + vector(0.5*self.m1_width,0) - in_position = inv_inst.get_pin("A").lc() + vector(0.5*self.m1_width,0) - post = inv_inst.get_pin("A").rc() - self.add_path("m1", [pre, out_position, in_position, post]) + out_pin = logic_inst.get_pin("Z") + out_pos = out_pin.rc() + in_pin = inv_inst.get_pin("A") + in_pos = in_pin.lc() + mid1_pos = vector(0.5 * (out_pos.x + in_pos.x), out_pos.y) + mid2_pos = vector(0.5 * (out_pos.x + in_pos.x), in_pos.y) + self.add_path("m1", [out_pos, mid1_pos, mid2_pos, in_pos]) - - # Connect the logic B input to bank_sel/bank_sel_bar - logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1_via.height,0) + # Connect the logic B input to bank_sel / bank_sel_bar + logic_pos = logic_inst.get_pin("B").lc() - vector(0.5 * contact.m1_via.height, 0) input_pos = vector(xoffset_bank_signal, logic_pos.y) - self.add_path("m2",[logic_pos, input_pos]) + self.add_path("m2", [logic_pos, input_pos]) self.add_via_center(layers=self.m1_stack, offset=logic_pos, - directions=("H","H")) + directions=("H", "H")) - # Connect the logic A input to the input pin logic_pos = logic_inst.get_pin("A").lc() - input_pos = vector(0,logic_pos.y) + input_pos = vector(0, logic_pos.y) self.add_via_center(layers=self.m1_stack, offset=logic_pos, - directions=("H","H")) + directions=("H", "H")) self.add_via_center(layers=self.m2_stack, offset=logic_pos, - directions=("H","H")) + directions=("H", "H")) self.add_layout_pin_segment_center(text=input_name, layer="m3", start=input_pos, @@ -286,7 +279,6 @@ class bank_select(design.design): width=inv_inst.rx() - out_pin.lx(), height=out_pin.height()) - # Find the x offsets for where the vias/pins should be placed a_xoffset = self.logic_inst[0].lx() b_xoffset = self.inv_inst[0].lx() @@ -294,7 +286,7 @@ class bank_select(design.design): # Route both supplies for n in ["vdd", "gnd"]: supply_pin = self.inv_inst[num].get_pin(n) - supply_offset = supply_pin.ll().scale(0,1) + supply_offset = supply_pin.ll().scale(0, 1) self.add_rect(layer="m1", offset=supply_offset, width=self.width) @@ -304,10 +296,10 @@ class bank_select(design.design): pin_pos = vector(xoffset, supply_pin.cy()) self.add_via_center(layers=self.m1_stack, offset=pin_pos, - directions=("H","H")) + directions=("H", "H")) self.add_via_center(layers=self.m2_stack, offset=pin_pos, - directions=("H","H")) + directions=("H", "H")) self.add_layout_pin_rect_center(text=n, layer="m3", offset=pin_pos) From 0941ebc3da648ecf3779cdcab42ed04e0be684b5 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 14 Apr 2020 14:08:07 -0700 Subject: [PATCH 252/521] Fix well spacing issue --- compiler/modules/bank_select.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index b717399f..3be10d3e 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -95,8 +95,8 @@ class bank_select(design.design): def calculate_module_offsets(self): - self.xoffset_nand = self.inv4x.width + 2 * self.m2_pitch + drc("pwell_to_nwell") - self.xoffset_nor = self.inv4x.width + 2 * self.m2_pitch + drc("pwell_to_nwell") + self.xoffset_nand = self.inv4x.width + 3 * self.m2_pitch + drc("pwell_to_nwell") + self.xoffset_nor = self.inv4x.width + 3 * self.m2_pitch + drc("pwell_to_nwell") self.xoffset_bank_sel_inv = 0 self.xoffset_inputs = 0 self.yoffset_maxpoint = self.num_control_lines * self.inv4x.height From 6c1c72c520d096775ca784569329b9c269cf207c Mon Sep 17 00:00:00 2001 From: jcirimel Date: Wed, 15 Apr 2020 04:09:58 -0700 Subject: [PATCH 253/521] fix pgates binning off-by-one --- compiler/pgates/pgate.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index ba5fef75..de513cc3 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -300,24 +300,24 @@ class pgate(design.design): bins = bins[0:bisect_left(bins, target_width) + 1] if len(bins) == 1: selected_bin = bins[0] - scaling_factor = 1 - scaled_bin = bins[0] + scaling_factor = math.ceil(target_width / width) + scaled_bin = bins[0] * scaling_factor else: scaled_bins = [] scaling_factors = [] + scaled_bins.append(bins[-1]) + scaling_factors.append(1) for width in bins[0:-1]: m = math.ceil(target_width / width) scaling_factors.append(m) scaled_bins.append(m * width) - scaled_bins.append(bins[-1]) - scaling_factors.append(1) select = bisect_left(scaled_bins, target_width) - - selected_bin = bins[select] scaling_factor = scaling_factors[select] scaled_bin = scaled_bins[select] + select = (select + 1) % len(scaled_bins) + selected_bin = bins[select] debug.info(2, "binning {0} tx, target: {4}, found {1} x {2} = {3}".format(tx_type, selected_bin, scaling_factor, scaled_bin, target_width)) From 331a4f4606a7de3c0d1554e85ed9832e8a6eef67 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 15 Apr 2020 09:48:42 -0700 Subject: [PATCH 254/521] Fix wire width bug in short jogs. PEP8 cleanup. --- compiler/base/design.py | 2 +- compiler/base/wire.py | 56 ++++++++++++++++-------- compiler/modules/hierarchical_decoder.py | 1 - 3 files changed, 38 insertions(+), 21 deletions(-) diff --git a/compiler/base/design.py b/compiler/base/design.py index c2ef8340..73ace38e 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -74,7 +74,7 @@ class design(hierarchy_design): return pitch def setup_drc_constants(self): - """ + """ These are some DRC constants used in many places in the compiler. """ diff --git a/compiler/base/wire.py b/compiler/base/wire.py index bf1daa6a..250f2d87 100644 --- a/compiler/base/wire.py +++ b/compiler/base/wire.py @@ -6,18 +6,18 @@ # All rights reserved. # from tech import drc -import debug from wire_path import wire_path from sram_factory import factory + class wire(wire_path): - """ + """ Object metal wire; given the layer type - Add a wire of minimium metal width between a set of points. + Add a wire of minimium metal width between a set of points. The points should be rectilinear to control the bend points. If not, it will always go down first. The points are the center of the wire. - The layer stack is the vertical, contact/via, and horizontal layers, respectively. + The layer stack is the vertical, contact/via, and horizontal layers, respectively. """ def __init__(self, obj, layer_stack, position_list): self.obj = obj @@ -36,6 +36,7 @@ class wire(wire_path): # wires and wire_paths should not be offset to (0,0) def setup_layers(self): + (horiz_layer, via_layer, vert_layer) = self.layer_stack self.via_layer_name = via_layer @@ -47,8 +48,16 @@ class wire(wire_path): via_connect = factory.create(module_type="contact", layer_stack=self.layer_stack, dimensions=(1, 1)) + + # This is used for short connections to avoid via-to-via spacing errors + self.vert_layer_contact_width = max(via_connect.second_layer_width, + via_connect.first_layer_width) + self.horiz_layer_contact_width = max(via_connect.second_layer_height, + via_connect.first_layer_height) + self.node_to_node = [drc("minwidth_" + str(self.horiz_layer_name)) + via_connect.width, drc("minwidth_" + str(self.horiz_layer_name)) + via_connect.height] + self.pitch = max(self.node_to_node) # create a 1x1 contact def create_vias(self): @@ -56,12 +65,9 @@ class wire(wire_path): self.c=factory.create(module_type="contact", layer_stack=self.layer_stack, dimensions=(1, 1)) - c_width = self.c.width - c_height = self.c.height - - from itertools import tee,islice - nwise = lambda g,n=2: zip(*(islice(g,i,None) for i,g in enumerate(tee(g,n)))) - threewise=nwise(self.position_list,3) + from itertools import tee, islice + nwise = lambda g, n=2: zip(*(islice(g, i, None) for i, g in enumerate(tee(g, n)))) + threewise = nwise(self.position_list, 3) for (a, offset, c) in list(threewise): # add a exceptions to prevent a via when we don't change directions @@ -72,18 +78,23 @@ class wire(wire_path): self.obj.add_via_center(layers=self.layer_stack, offset=offset) - def create_rectangles(self): - """ + """ Create the actual rectangles on the appropriate layers - using the position list of the corners. + using the position list of the corners. """ pl = self.position_list # position list for index in range(len(pl) - 1): + # Horizontal wire segment if pl[index][0] != pl[index + 1][0]: line_length = pl[index + 1][0] - pl[index][0] + if abs(line_length) < self.pitch: + width = self.horiz_layer_contact_width + else: + width = self.horiz_layer_width temp_offset = [pl[index][0], - pl[index][1] - 0.5*self.horiz_layer_width] + pl[index][1] - 0.5 * width] + # If we go in the negative direction, move the offset if line_length < 0: temp_offset = [temp_offset[0] + line_length, temp_offset[1]] @@ -91,10 +102,15 @@ class wire(wire_path): length=abs(line_length), offset=temp_offset, orientation="horizontal", - layer_width=self.horiz_layer_width) + layer_width=width) + # Vertical wire segment elif pl[index][1] != pl[index + 1][1]: line_length = pl[index + 1][1] - pl[index][1] - temp_offset = [pl[index][0] - 0.5 * self.vert_layer_width, + if abs(line_length) < self.pitch: + width = self.vert_layer_contact_width + else: + width = self.vert_layer_width + temp_offset = [pl[index][0] - 0.5 * width, pl[index][1]] if line_length < 0: temp_offset = [temp_offset[0], @@ -103,11 +119,13 @@ class wire(wire_path): length=abs(line_length), offset=temp_offset, orientation="vertical", - layer_width=self.vert_layer_width) + layer_width=width) def assert_node(self, A, B): - """ Check if the node movements are not big enough for the - technology sizes.""" + """ + Check if the node movements are not big enough for the + technology sizes. + """ X_diff = abs(A[0] - B[0]) Y_diff = abs(A[1] - B[1]) [minX, minY] = self.node_to_node diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index a805e635..f46849c6 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -33,7 +33,6 @@ class hierarchical_decoder(design.design): except AttributeError: self.cell_multiple = 1 # For debugging - # self.cell_multiple = 2 self.cell_height = self.cell_multiple * b.height self.num_outputs = num_outputs From 43fe1ae023bda3a81408d2ccfd73442f0f8c1294 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 15 Apr 2020 11:16:45 -0700 Subject: [PATCH 255/521] Improve pitch computation --- compiler/base/wire.py | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/compiler/base/wire.py b/compiler/base/wire.py index 250f2d87..2044eb3a 100644 --- a/compiler/base/wire.py +++ b/compiler/base/wire.py @@ -6,6 +6,7 @@ # All rights reserved. # from tech import drc +import contact from wire_path import wire_path from sram_factory import factory @@ -57,8 +58,29 @@ class wire(wire_path): self.node_to_node = [drc("minwidth_" + str(self.horiz_layer_name)) + via_connect.width, drc("minwidth_" + str(self.horiz_layer_name)) + via_connect.height] - self.pitch = max(self.node_to_node) + self.pitch = self.compute_pitch(self.layer_stack) + def compute_pitch(self, layer_stack): + + """ + This is contact direction independent pitch, + i.e. we take the maximum contact dimension + """ + (layer1, via, layer2) = layer_stack + + if layer1 == "poly" or layer1 == "active": + contact1 = getattr(contact, layer1 + "_contact") + else: + contact1 = getattr(contact, layer1 + "_via") + max_contact = max(contact1.width, contact1.height) + + layer1_space = drc["{0}_to_{0}".format(layer1)] + layer2_space = drc["{0}_to_{0}".format(layer2)] + pitch = max_contact + max(layer1_space, layer2_space) + + return pitch + + # create a 1x1 contact def create_vias(self): """ Add a via and corner square at every corner of the path.""" From 1564d6e02b466a815fac7cc66b26bd615e4fb054 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 15 Apr 2020 11:24:28 -0700 Subject: [PATCH 256/521] PEP8 cleanup --- compiler/drc/design_rules.py | 5 +++-- compiler/drc/drc_lut.py | 10 +++++----- compiler/drc/drc_value.py | 3 ++- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/compiler/drc/design_rules.py b/compiler/drc/design_rules.py index 05168b77..b194d082 100644 --- a/compiler/drc/design_rules.py +++ b/compiler/drc/design_rules.py @@ -9,9 +9,10 @@ import debug from drc_value import * from drc_lut import * + class design_rules(dict): - """ - This is a class that implements the design rules structures. + """ + This is a class that implements the design rules structures. """ def __init__(self, name): self.tech_name = name diff --git a/compiler/drc/drc_lut.py b/compiler/drc/drc_lut.py index 0ad0fde4..8a7b49d2 100644 --- a/compiler/drc/drc_lut.py +++ b/compiler/drc/drc_lut.py @@ -7,9 +7,10 @@ # import debug + class drc_lut(): - """ - Implement a lookup table of rules. + """ + Implement a lookup table of rules. Each element is a tuple with the last value being the rule. It searches through backwards until all of the key values are met and returns the rule value. @@ -31,7 +32,6 @@ class drc_lut(): for table_key in sorted(self.table.keys(), reverse=True): if self.match(key, table_key): return self.table[table_key] - def match(self, key1, key2): """ @@ -39,8 +39,8 @@ class drc_lut(): (i.e. return false if key1 Date: Wed, 15 Apr 2020 14:29:43 -0700 Subject: [PATCH 257/521] PEP8 cleanup --- compiler/modules/control_logic.py | 353 +++++++++++++++--------------- 1 file changed, 180 insertions(+), 173 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 1612938d..b4c7402e 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -5,18 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from math import log import design -from tech import drc, parameter from tech import cell_properties as props import debug -import contact from sram_factory import factory import math from vector import vector from globals import OPTS import logical_effort + class control_logic(design.design): """ Dynamically generated Control logic for the total SRAM circuit. @@ -29,7 +27,7 @@ class control_logic(design.design): debug.info(1, "Creating {}".format(name)) self.add_comment("num_rows: {0}".format(num_rows)) self.add_comment("words_per_row: {0}".format(words_per_row)) - self.add_comment("word_size {0}".format(word_size)) + self.add_comment("word_size {0}".format(word_size)) self.sram=sram self.num_rows = num_rows @@ -37,14 +35,15 @@ class control_logic(design.design): self.word_size = word_size self.port_type = port_type - self.num_cols = word_size*words_per_row - self.num_words = num_rows*words_per_row + self.num_cols = word_size * words_per_row + self.num_words = num_rows * words_per_row self.enable_delay_chain_resizing = False self.inv_parasitic_delay = logical_effort.logical_effort.pinv # Determines how much larger the sen delay should be. Accounts for possible error in model. - self.wl_timing_tolerance = 1 + # FIXME: This should be made a parameter + self.wl_timing_tolerance = 1 self.wl_stage_efforts = None self.sen_stage_efforts = None @@ -67,17 +66,16 @@ class control_logic(design.design): """ Create layout and route between modules """ self.place_instances() self.route_all() - #self.add_lvs_correspondence_points() + # self.add_lvs_correspondence_points() self.add_boundary() self.DRC_LVS() - def add_pins(self): """ Add the pins to the control logic module. """ self.add_pin_list(self.input_list + ["clk"] + self.rbl_list, "INPUT") - self.add_pin_list(self.output_list,"OUTPUT") - self.add_pin("vdd","POWER") - self.add_pin("gnd","GROUND") + self.add_pin_list(self.output_list, "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): """ Add all the required modules """ @@ -101,14 +99,13 @@ class control_logic(design.design): height=dff_height) self.add_mod(self.rbl_driver) - - # clk_buf drives a flop for every address - addr_flops = math.log(self.num_words,2) + math.log(self.words_per_row,2) + # clk_buf drives a flop for every address + addr_flops = math.log(self.num_words, 2) + math.log(self.words_per_row, 2) # plus data flops and control flops num_flops = addr_flops + self.word_size + self.num_control_signals # each flop internally has a FO 5 approximately # plus about 5 fanouts for the control logic - clock_fanout = 5*num_flops + 5 + clock_fanout = 5 * num_flops + 5 self.clk_buf_driver = factory.create(module_type="pdriver", fanout=clock_fanout, height=dff_height) @@ -117,7 +114,7 @@ class control_logic(design.design): # We will use the maximum since this same value is used to size the wl_en # and the p_en_bar drivers - max_fanout = max(self.num_rows,self.num_cols) + max_fanout = max(self.num_rows, self.num_cols) # wl_en drives every row in the bank self.wl_en_driver = factory.create(module_type="pdriver", @@ -127,7 +124,7 @@ class control_logic(design.design): # w_en drives every write driver self.wen_and = factory.create(module_type="pand3", - size=self.word_size+8, + size=self.word_size + 8, height=dff_height) self.add_mod(self.wen_and) @@ -137,7 +134,7 @@ class control_logic(design.design): height=dff_height) self.add_mod(self.sen_and3) - # used to generate inverted signals with low fanout + # used to generate inverted signals with low fanout self.inv = factory.create(module_type="pinv", size=1, height=dff_height) @@ -151,7 +148,6 @@ class control_logic(design.design): height=dff_height) self.add_mod(self.p_en_bar_driver) - self.nand2 = factory.create(module_type="pnand2", height=dff_height) self.add_mod(self.nand2) @@ -179,14 +175,14 @@ class control_logic(design.design): # delay_fanout_list=[delay_fanout_heuristic]*delay_stages_heuristic, # bitcell_loads=bitcell_loads) # #Resize if necessary, condition depends on resizing method - # if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_rise_fall_timing_match(): + # if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_rise_fall_timing_match(): # #This resizes to match fall and rise delays, can make the delay chain weird sizes. # stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) # self.replica_bitline = factory.create(module_type="replica_bitline", # delay_fanout_list=stage_list, # bitcell_loads=bitcell_loads) - # #This resizes based on total delay. + # #This resizes based on total delay. # # delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) # # self.replica_bitline = factory.create(module_type="replica_bitline", # # delay_fanout_list=[delay_fanout]*delay_stages, @@ -195,9 +191,10 @@ class control_logic(design.design): # self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing # self.delay_chain_resized = True - debug.check(OPTS.delay_chain_stages%2, "Must use odd number of delay chain stages for inverting delay chain.") + debug.check(OPTS.delay_chain_stages % 2, + "Must use odd number of delay chain stages for inverting delay chain.") self.delay_chain=factory.create(module_type="delay_chain", - fanout_list = OPTS.delay_chain_stages*[OPTS.delay_chain_fanout_per_stage]) + fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ]) self.add_mod(self.delay_chain) def get_heuristic_delay_chain_size(self): @@ -219,17 +216,17 @@ class control_logic(design.design): def set_sen_wl_delays(self): """Set delays for wordline and sense amp enable""" - self.wl_delay_rise,self.wl_delay_fall = self.get_delays_to_wl() - self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() - self.wl_delay = self.wl_delay_rise+self.wl_delay_fall - self.sen_delay = self.sen_delay_rise+self.sen_delay_fall + self.wl_delay_rise, self.wl_delay_fall = self.get_delays_to_wl() + self.sen_delay_rise, self.sen_delay_fall = self.get_delays_to_sen() + self.wl_delay = self.wl_delay_rise + self.wl_delay_fall + self.sen_delay = self.sen_delay_rise + self.sen_delay_fall def does_sen_rise_fall_timing_match(self): """Compare the relative rise/fall delays of the sense amp enable and wordline""" self.set_sen_wl_delays() # This is not necessarily more reliable than total delay in some cases. - if (self.wl_delay_rise*self.wl_timing_tolerance >= self.sen_delay_rise or - self.wl_delay_fall*self.wl_timing_tolerance >= self.sen_delay_fall): + if (self.wl_delay_rise * self.wl_timing_tolerance >= self.sen_delay_rise or + self.wl_delay_fall * self.wl_timing_tolerance >= self.sen_delay_fall): return False else: return True @@ -240,91 +237,107 @@ class control_logic(design.design): # The sen delay must always be bigger than than the wl # delay. This decides how much larger the sen delay must be # before a re-size is warranted. - if self.wl_delay*self.wl_timing_tolerance >= self.sen_delay: + if self.wl_delay * self.wl_timing_tolerance >= self.sen_delay: return False else: - return True + return True def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" from math import ceil - previous_delay_chain_delay = (previous_fanout+1+self.inv_parasitic_delay)*previous_stages + previous_delay_chain_delay = (previous_fanout + 1 + self.inv_parasitic_delay) * previous_stages debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay)) - - delay_fanout = 3 # This can be anything >=2 + + # This can be anything >=2 + delay_fanout = 3 # The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each # inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value - required_delay = self.wl_delay*self.wl_timing_tolerance - (self.sen_delay-previous_delay_chain_delay) + required_delay = self.wl_delay * self.wl_timing_tolerance - (self.sen_delay - previous_delay_chain_delay) debug.check(required_delay > 0, "Cannot size delay chain to have negative delay") - delay_stages = ceil(required_delay/(delay_fanout+1+self.inv_parasitic_delay)) - if delay_stages%2 == 1: #force an even number of stages. - delay_stages+=1 + delay_per_stage = delay_fanout + 1 + self.inv_parasitic_delay + delay_stages = ceil(required_delay / delay_per_stage) + # force an even number of stages. + if delay_stages % 2 == 1: + delay_stages += 1 # Fanout can be varied as well but is a little more complicated but potentially optimal. debug.info(1, "Setting delay chain to {} stages with {} fanout to match {} delay".format(delay_stages, delay_fanout, required_delay)) return (delay_stages, delay_fanout) def get_dynamic_delay_fanout_list(self, previous_stages, previous_fanout): """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" - - previous_delay_chain_delay = (previous_fanout+1+self.inv_parasitic_delay)*previous_stages + + previous_delay_per_stage = previous_fanout + 1 + self.inv_parasitic_delay + previous_delay_chain_delay = previous_delay_per_stage * previous_stages debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay)) fanout_rise = fanout_fall = 2 # This can be anything >=2 # The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each # inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value - required_delay_fall = self.wl_delay_fall*self.wl_timing_tolerance - (self.sen_delay_fall-previous_delay_chain_delay/2) - required_delay_rise = self.wl_delay_rise*self.wl_timing_tolerance - (self.sen_delay_rise-previous_delay_chain_delay/2) - debug.info(2,"Required delays from chain: fall={}, rise={}".format(required_delay_fall,required_delay_rise)) + required_delay_fall = self.wl_delay_fall * self.wl_timing_tolerance - \ + (self.sen_delay_fall - previous_delay_chain_delay / 2) + required_delay_rise = self.wl_delay_rise * self.wl_timing_tolerance - \ + (self.sen_delay_rise - previous_delay_chain_delay / 2) + debug.info(2, + "Required delays from chain: fall={}, rise={}".format(required_delay_fall, + required_delay_rise)) # If the fanout is different between rise/fall by this amount. Stage algorithm is made more pessimistic. WARNING_FANOUT_DIFF = 5 stages_close = False # The stages need to be equal (or at least a even number of stages with matching rise/fall delays) while True: - stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall,fanout_fall) - stages_rise = self.calculate_stages_with_fixed_fanout(required_delay_rise,fanout_rise) - debug.info(1,"Fall stages={}, rise stages={}".format(stages_fall,stages_rise)) - if abs(stages_fall-stages_rise) == 1 and not stages_close: + stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall, + fanout_fall) + stages_rise = self.calculate_stages_with_fixed_fanout(required_delay_rise, + fanout_rise) + debug.info(1, + "Fall stages={}, rise stages={}".format(stages_fall, + stages_rise)) + if abs(stages_fall - stages_rise) == 1 and not stages_close: stages_close = True safe_fanout_rise = fanout_rise safe_fanout_fall = fanout_fall - if stages_fall == stages_rise: + if stages_fall == stages_rise: break - elif abs(stages_fall-stages_rise) == 1 and WARNING_FANOUT_DIFF < abs(fanout_fall-fanout_rise): + elif abs(stages_fall - stages_rise) == 1 and WARNING_FANOUT_DIFF < abs(fanout_fall - fanout_rise): debug.info(1, "Delay chain fanouts between stages are large. Making chain size larger for safety.") fanout_rise = safe_fanout_rise fanout_fall = safe_fanout_fall break - # There should also be a condition to make sure the fanout does not get too large. + # There should also be a condition to make sure the fanout does not get too large. # Otherwise, increase the fanout of delay with the most stages, calculate new stages elif stages_fall>stages_rise: fanout_fall+=1 else: fanout_rise+=1 - total_stages = max(stages_fall,stages_rise)*2 + total_stages = max(stages_fall, stages_rise) * 2 debug.info(1, "New Delay chain: stages={}, fanout_rise={}, fanout_fall={}".format(total_stages, fanout_rise, fanout_fall)) # Creates interleaved fanout list of rise/fall delays. Assumes fall is the first stage. - stage_list = [fanout_fall if i%2==0 else fanout_rise for i in range(total_stages)] + stage_list = [fanout_fall if i % 2==0 else fanout_rise for i in range(total_stages)] return stage_list def calculate_stages_with_fixed_fanout(self, required_delay, fanout): from math import ceil # Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay - if required_delay <= 3+self.inv_parasitic_delay: #3 is the minimum delay per stage (with pinv=0). + # 3 is the minimum delay per stage (with pinv=0). + if required_delay <= 3 + self.inv_parasitic_delay: return 1 - delay_stages = ceil(required_delay/(fanout+1+self.inv_parasitic_delay)) + delay_per_stage = fanout + 1 + self.inv_parasitic_delay + delay_stages = ceil(required_delay / delay_per_stage) return delay_stages def calculate_stage_list(self, total_stages, fanout_rise, fanout_fall): - """Produces a list of fanouts which determine the size of the delay chain. List length is the number of stages. - Assumes the first stage is falling. + """ + Produces a list of fanouts which determine the size of the delay chain. + List length is the number of stages. + Assumes the first stage is falling. """ stage_list = [] for i in range(total_stages): - if i%2 == 0: + if i % 2 == 0: stage_list.append() def setup_signal_busses(self): @@ -351,7 +364,7 @@ class control_logic(design.design): else: self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] # leave space for the bus plus one extra space - self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch + self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch # Outputs to the bank if self.port_type == "rw": @@ -366,15 +379,13 @@ class control_logic(design.design): self.supply_list = ["vdd", "gnd"] - def route_rails(self): """ Add the input signal inverted tracks """ height = self.control_logic_center.y - self.m2_pitch - offset = vector(self.ctrl_dff_array.width,0) + offset = vector(self.ctrl_dff_array.width, 0) self.rail_offsets = self.create_vertical_bus("m2", self.m2_pitch, offset, self.internal_bus_list, height) - - + def create_instances(self): """ Create all the instances """ self.create_dffs() @@ -388,9 +399,7 @@ class control_logic(design.design): if (self.port_type == "rw") or (self.port_type == "r"): self.create_sen_row() self.create_delay() - self.create_pen_row() - - + self.create_pen_row() def place_instances(self): """ Place all the instances """ @@ -406,13 +415,13 @@ class control_logic(design.design): row = 0 # Add the logic on the right of the bus - self.place_clk_buf_row(row) + self.place_clk_buf_row(row) row += 1 - self.place_gated_clk_bar_row(row) + self.place_gated_clk_bar_row(row) row += 1 - self.place_gated_clk_buf_row(row) + self.place_gated_clk_buf_row(row) row += 1 - self.place_wlen_row(row) + self.place_wlen_row(row) row += 1 if (self.port_type == "rw") or (self.port_type == "w"): self.place_wen_row(row) @@ -421,10 +430,10 @@ class control_logic(design.design): row += 1 self.place_pen_row(row) row += 1 - if (self.port_type == "rw") or (self.port_type == "w"): + if (self.port_type == "rw") or (self.port_type == "w"): self.place_rbl_delay_row(row) row += 1 - if (self.port_type == "rw") or (self.port_type == "r"): + if (self.port_type == "rw") or (self.port_type == "r"): self.place_sen_row(row) row += 1 self.place_delay(row) @@ -435,11 +444,11 @@ class control_logic(design.design): self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y) # Extra pitch on top and right - self.height = height + 2*self.m1_pitch + self.height = height + 2 * self.m1_pitch # Max of modules or logic rows self.width = max([inst.rx() for inst in self.row_end_inst]) if (self.port_type == "rw") or (self.port_type == "r"): - self.width = max(self.delay_inst.rx() , self.width) + self.width = max(self.delay_inst.rx(), self.width) self.width += self.m2_pitch def route_all(self): @@ -459,7 +468,6 @@ class control_logic(design.design): self.route_gated_clk_buf() self.route_supply() - def create_delay(self): """ Create the replica bitline """ self.delay_inst=self.add_inst(name="delay_chain", @@ -467,9 +475,9 @@ class control_logic(design.design): # rbl_bl_delay is asserted (1) when the bitline has been discharged self.connect_inst(["rbl_bl", "rbl_bl_delay", "vdd", "gnd"]) - def place_delay(self,row): + def place_delay(self, row): """ Place the replica bitline """ - y_off = row * self.and2.height + 2*self.m1_pitch + y_off = row * self.and2.height + 2 * self.m1_pitch # Add the RBL above the rows # Add to the right of the control rows and routing channel @@ -482,24 +490,22 @@ class control_logic(design.design): # Connect to the rail level with the vdd rail # Use pen since it is in every type of control logic vdd_ypos = self.p_en_bar_nand_inst.get_pin("vdd").by() - in_pos = vector(self.rail_offsets["rbl_bl_delay"].x,vdd_ypos) - mid1 = vector(out_pos.x,in_pos.y) - self.add_wire(self.m1_stack,[out_pos, mid1, in_pos]) + in_pos = vector(self.rail_offsets["rbl_bl_delay"].x, vdd_ypos) + mid1 = vector(out_pos.x, in_pos.y) + self.add_wire(self.m1_stack, [out_pos, mid1, in_pos]) self.add_via_center(layers=self.m1_stack, offset=in_pos) - # Input from RBL goes to the delay line for futher delay self.copy_layout_pin(self.delay_inst, "in", "rbl_bl") - def create_clk_buf_row(self): """ Create the multistage and gated clock buffer """ self.clk_buf_inst = self.add_inst(name="clkbuf", mod=self.clk_buf_driver) - self.connect_inst(["clk","clk_buf","vdd","gnd"]) + self.connect_inst(["clk", "clk_buf", "vdd", "gnd"]) - def place_clk_buf_row(self,row): + def place_clk_buf_row(self, row): x_offset = self.control_x_offset x_offset = self.place_util(self.clk_buf_inst, x_offset, row) @@ -512,17 +518,16 @@ class control_logic(design.design): self.add_layout_pin_segment_center(text="clk", layer="m2", start=clk_pos, - end=clk_pos.scale(1,0)) + end=clk_pos.scale(1, 0)) self.add_via_center(layers=self.m1_stack, offset=clk_pos) - # Connect this at the bottom of the buffer out_pos = self.clk_buf_inst.get_pin("Z").center() - mid1 = vector(out_pos.x,2*self.m2_pitch) + mid1 = vector(out_pos.x, 2 * self.m2_pitch) mid2 = vector(self.rail_offsets["clk_buf"].x, mid1.y) bus_pos = self.rail_offsets["clk_buf"] - self.add_wire(("m3","via2","m2"),[out_pos, mid1, mid2, bus_pos]) + self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) # The pin is on M1, so we need another via as well self.add_via_center(layers=self.m1_stack, offset=self.clk_buf_inst.get_pin("Z").center()) @@ -532,40 +537,45 @@ class control_logic(design.design): def create_gated_clk_bar_row(self): self.clk_bar_inst = self.add_inst(name="inv_clk_bar", mod=self.inv) - self.connect_inst(["clk_buf","clk_bar","vdd","gnd"]) + self.connect_inst(["clk_buf", "clk_bar", "vdd", "gnd"]) self.gated_clk_bar_inst = self.add_inst(name="and2_gated_clk_bar", mod=self.and2) - self.connect_inst(["cs","clk_bar","gated_clk_bar","vdd","gnd"]) + self.connect_inst(["cs", "clk_bar", "gated_clk_bar", "vdd", "gnd"]) - def place_gated_clk_bar_row(self,row): + def place_gated_clk_bar_row(self, row): x_offset = self.control_x_offset x_offset = self.place_util(self.clk_bar_inst, x_offset, row) - x_offset = self.place_util(self.gated_clk_bar_inst, x_offset, row) + x_offset = self.place_util(self.gated_clk_bar_inst, x_offset, row) self.row_end_inst.append(self.gated_clk_bar_inst) def route_gated_clk_bar(self): clkbuf_map = zip(["A"], ["clk_buf"]) - self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets) + self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets) out_pos = self.clk_bar_inst.get_pin("Z").center() in_pos = self.gated_clk_bar_inst.get_pin("B").center() - mid1 = vector(in_pos.x,out_pos.y) - self.add_path("m1",[out_pos, mid1, in_pos]) + mid1 = vector(in_pos.x, out_pos.y) + self.add_path("m1", [out_pos, mid1, in_pos]) # This is the second gate over, so it needs to be on M3 clkbuf_map = zip(["A"], ["cs"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("m3", "via2", "m2")) + self.connect_vertical_bus(clkbuf_map, + self.gated_clk_bar_inst, + self.rail_offsets, + self.m2_stack[::-1]) # The pin is on M1, so we need another via as well self.add_via_center(layers=self.m1_stack, offset=self.gated_clk_bar_inst.get_pin("A").center()) - # This is the second gate over, so it needs to be on M3 clkbuf_map = zip(["Z"], ["gated_clk_bar"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("m3", "via2", "m2")) + self.connect_vertical_bus(clkbuf_map, + self.gated_clk_bar_inst, + self.rail_offsets, + self.m2_stack[::-1]) # The pin is on M1, so we need another via as well self.add_via_center(layers=self.m1_stack, offset=self.gated_clk_bar_inst.get_pin("Z").center()) @@ -573,9 +583,9 @@ class control_logic(design.design): def create_gated_clk_buf_row(self): self.gated_clk_buf_inst = self.add_inst(name="and2_gated_clk_buf", mod=self.and2) - self.connect_inst(["clk_buf", "cs","gated_clk_buf","vdd","gnd"]) + self.connect_inst(["clk_buf", "cs", "gated_clk_buf", "vdd", "gnd"]) - def place_gated_clk_buf_row(self,row): + def place_gated_clk_buf_row(self, row): x_offset = self.control_x_offset x_offset = self.place_util(self.gated_clk_buf_inst, x_offset, row) @@ -584,11 +594,13 @@ class control_logic(design.design): def route_gated_clk_buf(self): clkbuf_map = zip(["A", "B"], ["clk_buf", "cs"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets) - clkbuf_map = zip(["Z"], ["gated_clk_buf"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets, ("m3", "via2", "m2")) + self.connect_vertical_bus(clkbuf_map, + self.gated_clk_buf_inst, + self.rail_offsets, + self.m2_stack[::-1]) # The pin is on M1, so we need another via as well self.add_via_center(layers=self.m1_stack, offset=self.gated_clk_buf_inst.get_pin("Z").center()) @@ -602,7 +614,7 @@ class control_logic(design.design): def place_wlen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.wl_en_inst, x_offset, row) + x_offset = self.place_util(self.wl_en_inst, x_offset, row) self.row_end_inst.append(self.wl_en_inst) @@ -623,11 +635,11 @@ class control_logic(design.design): mod=self.p_en_bar_driver) self.connect_inst(["p_en_bar_unbuf", "p_en_bar", "vdd", "gnd"]) - def place_pen_row(self,row): + def place_pen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.p_en_bar_nand_inst, x_offset, row) - x_offset = self.place_util(self.p_en_bar_driver_inst, x_offset, row) + x_offset = self.place_util(self.p_en_bar_nand_inst, x_offset, row) + x_offset = self.place_util(self.p_en_bar_driver_inst, x_offset, row) self.row_end_inst.append(self.p_en_bar_driver_inst) @@ -637,8 +649,8 @@ class control_logic(design.design): out_pos = self.p_en_bar_nand_inst.get_pin("Z").rc() in_pos = self.p_en_bar_driver_inst.get_pin("A").lc() - mid1 = vector(out_pos.x,in_pos.y) - self.add_wire(self.m1_stack,[out_pos, mid1,in_pos]) + mid1 = vector(out_pos.x, in_pos.y) + self.add_wire(self.m1_stack, [out_pos, mid1, in_pos]) self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar") @@ -656,14 +668,12 @@ class control_logic(design.design): # hence we use rbl_bl_delay as well. self.connect_inst(["rbl_bl_delay", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) - - def place_sen_row(self,row): + def place_sen_row(self, row): x_offset = self.control_x_offset x_offset = self.place_util(self.s_en_gate_inst, x_offset, row) self.row_end_inst.append(self.s_en_gate_inst) - def route_sen(self): @@ -683,7 +693,7 @@ class control_logic(design.design): mod=self.inv) self.connect_inst(["rbl_bl_delay", "rbl_bl_delay_bar", "vdd", "gnd"]) - def place_rbl_delay_row(self,row): + def place_rbl_delay_row(self, row): x_offset = self.control_x_offset x_offset = self.place_util(self.rbl_bl_delay_inv_inst, x_offset, row) @@ -700,11 +710,9 @@ class control_logic(design.design): self.add_via_center(layers=self.m1_stack, offset=self.rbl_bl_delay_inv_inst.get_pin("Z").center()) - rbl_map = zip(["A"], ["rbl_bl_delay"]) self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets) - def create_wen_row(self): # input: we (or cs) output: w_en @@ -720,8 +728,7 @@ class control_logic(design.design): # Only drive the writes in the second half of the clock cycle during a write operation. self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"]) - - def place_wen_row(self,row): + def place_wen_row(self, row): x_offset = self.control_x_offset x_offset = self.place_util(self.w_en_gate_inst, x_offset, row) @@ -750,22 +757,22 @@ class control_logic(design.design): self.connect_inst(inst_pins) def place_dffs(self): - self.ctrl_dff_inst.place(vector(0,0)) + self.ctrl_dff_inst.place(vector(0, 0)) def route_dffs(self): if self.port_type == "rw": dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"]) elif self.port_type == "r": - dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) + dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) else: dff_out_map = zip(["dout_bar_0"], ["cs"]) self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets, ("m3", "via2", "m2")) # Connect the clock rail to the other clock rail in_pos = self.ctrl_dff_inst.get_pin("clk").uc() - mid_pos = in_pos + vector(0,2*self.m2_pitch) + mid_pos = in_pos + vector(0, 2 * self.m2_pitch) rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y) - self.add_wire(self.m1_stack,[in_pos, mid_pos, rail_pos]) + self.add_wire(self.m1_stack, [in_pos, mid_pos, rail_pos]) self.add_via_center(layers=self.m1_stack, offset=rail_pos) @@ -773,34 +780,31 @@ class control_logic(design.design): if (self.port_type == "rw"): self.copy_layout_pin(self.ctrl_dff_inst, "din_1", "web") - def get_offset(self,row): + def get_offset(self, row): """ Compute the y-offset and mirroring """ - y_off = row*self.and2.height + y_off = row * self.and2.height if row % 2: y_off += self.and2.height mirror="MX" else: mirror="R0" - return (y_off,mirror) - + return (y_off, mirror) def connect_output(self, inst, pin_name, out_name): """ Create an output pin on the right side from the pin of a given instance. """ out_pin = inst.get_pin(pin_name) - right_pos=out_pin.center() + vector(self.width-out_pin.cx(),0) + right_pos = out_pin.center() + vector(self.width - out_pin.cx(), 0) self.add_layout_pin_segment_center(text=out_name, layer="m1", start=out_pin.center(), end=right_pos) - - def route_supply(self): """ Add vdd and gnd to the instance cells """ - max_row_x_loc = max([inst.rx() for inst in self.row_end_inst]) + max_row_x_loc = max([inst.rx() for inst in self.row_end_inst]) for inst in self.row_end_inst: pins = inst.get_pins("vdd") for pin in pins: @@ -818,16 +822,14 @@ class control_logic(design.design): self.add_power_pin("gnd", pin_loc) self.add_path("m1", [row_loc, pin_loc]) - self.copy_layout_pin(self.delay_inst,"gnd") - self.copy_layout_pin(self.delay_inst,"vdd") + self.copy_layout_pin(self.delay_inst, "gnd") + self.copy_layout_pin(self.delay_inst, "vdd") - self.copy_layout_pin(self.ctrl_dff_inst,"gnd") - self.copy_layout_pin(self.ctrl_dff_inst,"vdd") + self.copy_layout_pin(self.ctrl_dff_inst, "gnd") + self.copy_layout_pin(self.ctrl_dff_inst, "vdd") - - def add_lvs_correspondence_points(self): - """ This adds some points for easier debugging if LVS goes wrong. + """ This adds some points for easier debugging if LVS goes wrong. These should probably be turned off by default though, since extraction will show these as ports in the extracted netlist. """ @@ -851,74 +853,79 @@ class control_logic(design.design): offset=pin.ll(), height=pin.height(), width=pin.width()) - def get_delays_to_wl(self): """Get the delay (in delay units) of the clk to a wordline in the bitcell array""" debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") self.wl_stage_efforts = self.get_wordline_stage_efforts() - clk_to_wl_rise,clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(self.wl_stage_efforts) - total_delay = clk_to_wl_rise + clk_to_wl_fall - debug.info(1, "Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise, clk_to_wl_fall,total_delay)) - return clk_to_wl_rise,clk_to_wl_fall + clk_to_wl_rise, clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(self.wl_stage_efforts) + total_delay = clk_to_wl_rise + clk_to_wl_fall + debug.info(1, + "Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise, + clk_to_wl_fall, + total_delay)) + return clk_to_wl_rise, clk_to_wl_fall - def get_wordline_stage_efforts(self): """Follows the gated_clk_bar -> wl_en -> wordline signal for the total path efforts""" stage_effort_list = [] - #Initial direction of gated_clk_bar signal for this path + # Initial direction of gated_clk_bar signal for this path is_clk_bar_rise = True - #Calculate the load on wl_en within the module and add it to external load + # Calculate the load on wl_en within the module and add it to external load external_cout = self.sram.get_wl_en_cin() - #First stage is the clock buffer + # First stage is the clock buffer stage_effort_list += self.clk_buf_driver.get_stage_efforts(external_cout, is_clk_bar_rise) last_stage_is_rise = stage_effort_list[-1].is_rise - #Then ask the sram for the other path delays (from the bank) + # Then ask the sram for the other path delays (from the bank) stage_effort_list += self.sram.get_wordline_stage_efforts(last_stage_is_rise) return stage_effort_list def get_delays_to_sen(self): - """Get the delay (in delay units) of the clk to a sense amp enable. - This does not incorporate the delay of the replica bitline. + """ + Get the delay (in delay units) of the clk to a sense amp enable. + This does not incorporate the delay of the replica bitline. """ debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") self.sen_stage_efforts = self.get_sa_enable_stage_efforts() clk_to_sen_rise, clk_to_sen_fall = logical_effort.calculate_relative_rise_fall_delays(self.sen_stage_efforts) - total_delay = clk_to_sen_rise + clk_to_sen_fall - debug.info(1, "Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise, clk_to_sen_fall,total_delay)) - return clk_to_sen_rise, clk_to_sen_fall + total_delay = clk_to_sen_rise + clk_to_sen_fall + debug.info(1, + "Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise, + clk_to_sen_fall, + total_delay)) + return clk_to_sen_rise, clk_to_sen_fall def get_sa_enable_stage_efforts(self): """Follows the gated_clk_bar signal to the sense amp enable signal adding each stages stage effort to a list""" stage_effort_list = [] - #Initial direction of clock signal for this path + # Initial direction of clock signal for this path last_stage_rise = True - #First stage, gated_clk_bar -(and2)-> rbl_in. Only for RW ports. + # First stage, gated_clk_bar -(and2)-> rbl_in. Only for RW ports. if self.port_type == "rw": stage1_cout = self.replica_bitline.get_en_cin() stage_effort_list += self.and2.get_stage_efforts(stage1_cout, last_stage_rise) last_stage_rise = stage_effort_list[-1].is_rise - #Replica bitline stage, rbl_in -(rbl)-> pre_s_en + # Replica bitline stage, rbl_in -(rbl)-> pre_s_en stage2_cout = self.sen_and2.get_cin() stage_effort_list += self.replica_bitline.determine_sen_stage_efforts(stage2_cout, last_stage_rise) last_stage_rise = stage_effort_list[-1].is_rise - #buffer stage, pre_s_en -(buffer)-> s_en + # buffer stage, pre_s_en -(buffer)-> s_en stage3_cout = self.sram.get_sen_cin() stage_effort_list += self.s_en_driver.get_stage_efforts(stage3_cout, last_stage_rise) last_stage_rise = stage_effort_list[-1].is_rise - return stage_effort_list + return stage_effort_list def get_wl_sen_delays(self): - """Gets a list of the stages and delays in order of their path.""" + """ Gets a list of the stages and delays in order of their path. """ if self.sen_stage_efforts == None or self.wl_stage_efforts == None: debug.error("Model delays not calculated for SRAM.", 1) @@ -927,45 +934,45 @@ class control_logic(design.design): return wl_delays, sen_delays def analytical_delay(self, corner, slew, load): - """Gets the analytical delay from clk input to wl_en output""" + """ Gets the analytical delay from clk input to wl_en output """ stage_effort_list = [] - #Calculate the load on clk_buf_bar - ext_clk_buf_cout = self.sram.get_clk_bar_cin() + # Calculate the load on clk_buf_bar + # ext_clk_buf_cout = self.sram.get_clk_bar_cin() - #Operations logic starts on negative edge - last_stage_rise = False + # Operations logic starts on negative edge + last_stage_rise = False - #First stage(s), clk -(pdriver)-> clk_buf. - #clk_buf_cout = self.replica_bitline.get_en_cin() + # First stage(s), clk -(pdriver)-> clk_buf. + # clk_buf_cout = self.replica_bitline.get_en_cin() clk_buf_cout = 0 stage_effort_list += self.clk_buf_driver.get_stage_efforts(clk_buf_cout, last_stage_rise) last_stage_rise = stage_effort_list[-1].is_rise - #Second stage, clk_buf -(inv)-> clk_bar + # Second stage, clk_buf -(inv)-> clk_bar clk_bar_cout = self.and2.get_cin() stage_effort_list += self.and2.get_stage_efforts(clk_bar_cout, last_stage_rise) last_stage_rise = stage_effort_list[-1].is_rise - #Third stage clk_bar -(and)-> gated_clk_bar + # Third stage clk_bar -(and)-> gated_clk_bar gated_clk_bar_cin = self.get_gated_clk_bar_cin() stage_effort_list.append(self.inv.get_stage_effort(gated_clk_bar_cin, last_stage_rise)) last_stage_rise = stage_effort_list[-1].is_rise - #Stages from gated_clk_bar -------> wordline + # Stages from gated_clk_bar -------> wordline stage_effort_list += self.get_wordline_stage_efforts() return stage_effort_list def get_clk_buf_cin(self): """ - Get the loads that are connected to the buffered clock. + Get the loads that are connected to the buffered clock. Includes all the DFFs and some logic. """ - #Control logic internal load + # Control logic internal load int_clk_buf_cap = self.inv.get_cin() + self.ctrl_dff_array.get_clk_cin() + self.and2.get_cin() - #Control logic external load (in the other parts of the SRAM) + # Control logic external load (in the other parts of the SRAM) ext_clk_buf_cap = self.sram.get_clk_bar_cin() return int_clk_buf_cap + ext_clk_buf_cap @@ -976,7 +983,7 @@ class control_logic(design.design): total_cin = 0 total_cin += self.wl_en_driver.get_cin() if self.port_type == 'rw': - total_cin +=self.and2.get_cin() + total_cin += self.and2.get_cin() return total_cin def graph_exclude_dffs(self): @@ -989,7 +996,7 @@ class control_logic(design.design): def place_util(self, inst, x_offset, row): """ Utility to place a row and compute the next offset """ - (y_offset,mirror)=self.get_offset(row) + (y_offset, mirror) = self.get_offset(row) offset = vector(x_offset, y_offset) inst.place(offset, mirror) - return x_offset+inst.width + return x_offset + inst.width From 94eb2afa36156afa193c38d1f47a206a10cf5de7 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 15 Apr 2020 15:29:55 -0700 Subject: [PATCH 258/521] Change to callable DRC rule. Use bottom coordinate for bus offsets. --- compiler/base/hierarchy_layout.py | 81 ++++++++++++++----------------- compiler/base/wire.py | 4 +- 2 files changed, 38 insertions(+), 47 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 63d53d39..e67f8d85 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -46,7 +46,6 @@ class layout(): except ImportError: self.pwr_grid_layer = "m3" - ############################################################ # GDS layout ############################################################ @@ -196,7 +195,7 @@ class layout(): self.insts.append(geometry.instance(name, mod, offset, mirror, rotate)) debug.info(3, "adding instance {}".format(self.insts[-1])) # This is commented out for runtime reasons - #debug.info(4, "instance list: " + ",".join(x.name for x in self.insts)) + # debug.info(4, "instance list: " + ",".join(x.name for x in self.insts)) return self.insts[-1] def get_inst(self, name): @@ -214,12 +213,14 @@ class layout(): width = drc["minwidth_{}".format(layer)] if not height: height = drc["minwidth_{}".format(layer)] - # negative layers indicate "unused" layers in a given technology lpp = techlayer[layer] - if lpp[0] >= 0: - self.objs.append(geometry.rectangle(lpp, offset, width, height)) - return self.objs[-1] - return None + if abs(offset[0]-5.16250)<0.01 and abs(offset[1]-8.70750)<0.01: + import pdb; pdb.set_trace() + self.objs.append(geometry.rectangle(lpp, + offset, + width, + height)) + return self.objs[-1] def add_rect_center(self, layer, offset, width=None, height=None): """ @@ -230,16 +231,13 @@ class layout(): width = drc["minwidth_{}".format(layer)] if not height: height = drc["minwidth_{}".format(layer)] - # negative layers indicate "unused" layers in a given technology lpp = techlayer[layer] corrected_offset = offset - vector(0.5 * width, 0.5 * height) - if lpp[0] >= 0: - self.objs.append(geometry.rectangle(lpp, - corrected_offset, - width, - height)) - return self.objs[-1] - return None + self.objs.append(geometry.rectangle(lpp, + corrected_offset, + width, + height)) + return self.objs[-1] def add_segment_center(self, layer, start, end): """ @@ -252,15 +250,15 @@ class layout(): elif start.x != end.x: offset = vector(0, 0.5 * minwidth_layer) return self.add_rect(layer, - start-offset, - end.x-start.x, + start - offset, + end.x - start.x, minwidth_layer) else: offset = vector(0.5 * minwidth_layer, 0) return self.add_rect(layer, - start-offset, + start - offset, minwidth_layer, - end.y-start.y) + end.y - start.y) def get_pin(self, text): """ @@ -268,14 +266,14 @@ class layout(): """ try: if len(self.pin_map[text]) > 1: - debug.error("Should use a pin iterator since more than one pin {}".format(text),-1) + debug.error("Should use a pin iterator since more than one pin {}".format(text), -1) # If we have one pin, return it and not the list. # Otherwise, should use get_pins() any_pin = next(iter(self.pin_map[text])) return any_pin except Exception: self.gds_write("missing_pin.gds") - debug.error("No pin found with name {0} on {1}. Saved as missing_pin.gds.".format(text,self.name),-1) + debug.error("No pin found with name {0} on {1}. Saved as missing_pin.gds.".format(text, self.name), -1) def get_pins(self, text): """ @@ -377,7 +375,7 @@ class layout(): height = drc["minwidth_{0}".format(layer)] new_pin = pin_layout(text, - [offset, offset+vector(width, height)], + [offset, offset + vector(width, height)], layer) try: @@ -413,23 +411,18 @@ class layout(): def add_label(self, text, layer, offset=[0, 0], zoom=-1): """Adds a text label on the given layer,offset, and zoom level""" - # negative layers indicate "unused" layers in a given technology debug.info(5, "add label " + str(text) + " " + layer + " " + str(offset)) lpp = techlayer[layer] - if lpp[0] >= 0: - self.objs.append(geometry.label(text, lpp, offset, zoom)) - return self.objs[-1] - return None + self.objs.append(geometry.label(text, lpp, offset, zoom)) + return self.objs[-1] def add_path(self, layer, coordinates, width=None): """Connects a routing path on given layer,coordinates,width.""" debug.info(4, "add path " + str(layer) + " " + str(coordinates)) import wire_path # NOTE: (UNTESTED) add_path(...) is currently not used - # negative layers indicate "unused" layers in a given technology # lpp = techlayer[layer] - # if lpp[0] >= 0: - # self.objs.append(geometry.path(lpp, coordinates, width)) + # self.objs.append(geometry.path(lpp, coordinates, width)) wire_path.wire_path(obj=self, layer=layer, @@ -465,7 +458,7 @@ class layout(): from tech import preferred_directions return preferred_directions[layer] - def add_via(self, layers, offset, size=[1,1], directions=None, implant_type=None, well_type=None): + def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None): """ Add a three layer via structure. """ if not directions: @@ -487,7 +480,7 @@ class layout(): self.connect_inst([]) return inst - def add_via_center(self, layers, offset, directions=None, size=[1,1], implant_type=None, well_type=None): + def add_via_center(self, layers, offset, directions=None, size=[1, 1], implant_type=None, well_type=None): """ Add a three layer via structure by the center coordinate accounting for mirroring and rotation. @@ -799,9 +792,7 @@ class layout(): self.add_rect(layer=layer, offset=line_offset, height=length) - # Make this the center of the rail - line_positions[names[i]] = line_offset + vector(half_minwidth, - 0.5 * length) + line_positions[names[i]] = line_offset + vector(half_minwidth, 0) else: for i in range(len(names)): line_offset = offset + vector(0, @@ -953,14 +944,14 @@ class layout(): min_y = min([pin.center().y for pin in pins]) # if we are less than a pitch, just create a non-preferred layer jog - if max_y-min_y <= pitch: + if max_y - min_y <= pitch: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)] # Add the vertical trunk on the horizontal layer! self.add_path(self.horizontal_layer, [vector(trunk_offset.x, min_y - half_layer_width), - vector(trunk_offset.x,max_y + half_layer_width)]) + vector(trunk_offset.x, max_y + half_layer_width)]) # Route each pin to the trunk for pin in pins: @@ -1000,7 +991,7 @@ class layout(): # Remove the pin from all conflicts # FIXME: This is O(n^2), so maybe optimize it. - for other_pin,conflicts in g.items(): + for other_pin, conflicts in g.items(): if pin in conflicts: conflicts.remove(pin) g[other_pin]=conflicts @@ -1151,8 +1142,8 @@ class layout(): else: self.bounding_box = self.add_rect(layer=boundary_layer, offset=ll, - height=ur.y-ll.y, - width=ur.x-ll.x) + height=ur.y - ll.y, + width=ur.x - ll.x) def add_enclosure(self, insts, layer="nwell"): """ Add a layer that surrounds the given instances. Useful @@ -1171,8 +1162,8 @@ class layout(): self.add_rect(layer=layer, offset=vector(xmin, ymin), - width=xmax-xmin, - height=ymax-ymin) + width=xmax - xmin, + height=ymax - ymin) def copy_power_pins(self, inst, name): """ @@ -1192,7 +1183,7 @@ class layout(): else: debug.warning("{0} pins of {1} should be on {2} or metal1 for "\ "supply router." - .format(name,inst.name,self.pwr_grid_layer)) + .format(name, inst.name, self.pwr_grid_layer)) def add_power_pin(self, name, loc, size=[1, 1], vertical=False, start_layer="m1"): """ @@ -1244,8 +1235,8 @@ class layout(): [ll, ur] = bbox supply_rail_spacing = self.supply_rail_pitch - self.supply_rail_width - height = (ur.y-ll.y) + 3 * self.supply_rail_pitch - supply_rail_spacing - width = (ur.x-ll.x) + 3 * self.supply_rail_pitch - supply_rail_spacing + height = (ur.y - ll.y) + 3 * self.supply_rail_pitch - supply_rail_spacing + width = (ur.x - ll.x) + 3 * self.supply_rail_pitch - supply_rail_spacing # LEFT vertical rails offset = ll + vector(-2 * self.supply_rail_pitch, diff --git a/compiler/base/wire.py b/compiler/base/wire.py index 2044eb3a..23cc1b41 100644 --- a/compiler/base/wire.py +++ b/compiler/base/wire.py @@ -74,8 +74,8 @@ class wire(wire_path): contact1 = getattr(contact, layer1 + "_via") max_contact = max(contact1.width, contact1.height) - layer1_space = drc["{0}_to_{0}".format(layer1)] - layer2_space = drc["{0}_to_{0}".format(layer2)] + layer1_space = drc("{0}_to_{0}".format(layer1)) + layer2_space = drc("{0}_to_{0}".format(layer2)) pitch = max_contact + max(layer1_space, layer2_space) return pitch From 9d2902de9ea6b1c5f575a434a798c30b860cd942 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 15 Apr 2020 15:55:49 -0700 Subject: [PATCH 259/521] Conditional well spacing --- compiler/modules/dff_buf.py | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index e42c01c0..c30f15b6 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -7,13 +7,13 @@ # import debug import design -from tech import drc,parameter +from tech import parameter from tech import cell_properties as props -from math import log from vector import vector from globals import OPTS from sram_factory import factory + class dff_buf(design.design): """ This is a simple buffered DFF. The output is buffered @@ -107,13 +107,23 @@ class dff_buf(design.design): self.dff_inst.place(vector(0,0)) # Add INV1 to the right - well_spacing = max(self.nwell_space, - self.pwell_space, - self.pwell_to_nwell) - self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing + self.well_extend_active,0)) + well_spacing = 0 + try: + well_spacing = max(well_spacing, self.nwell_space) + except AttributeError: + pass + try: + well_spacing = max(well_spacing, self.pwell_space) + except AttributeError: + pass + try: + well_spacing = max(well_spacing, self.pwell_to_nwell) + except AttributeError: + pass + self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing + self.well_extend_active, 0)) # Add INV2 to the right - self.inv2_inst.place(vector(self.inv1_inst.rx(),0)) + self.inv2_inst.place(vector(self.inv1_inst.rx(), 0)) def route_wires(self): # Route dff q to inv1 a From b347e3f7a8fdaa7289f12bbacbb982cd7e3199d4 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 15 Apr 2020 16:49:04 -0700 Subject: [PATCH 260/521] Try both layers for reversed layer stacks. --- compiler/base/wire.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler/base/wire.py b/compiler/base/wire.py index 23cc1b41..ddb10f43 100644 --- a/compiler/base/wire.py +++ b/compiler/base/wire.py @@ -71,7 +71,10 @@ class wire(wire_path): if layer1 == "poly" or layer1 == "active": contact1 = getattr(contact, layer1 + "_contact") else: - contact1 = getattr(contact, layer1 + "_via") + try: + contact1 = getattr(contact, layer1 + "_via") + except AttributeError: + contact1 = getattr(contact, layer2 + "_via") max_contact = max(contact1.width, contact1.height) layer1_space = drc("{0}_to_{0}".format(layer1)) From d1319d633d96f68d006e719afa72542cb336bb5f Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Apr 2020 11:02:54 -0700 Subject: [PATCH 261/521] Don't widen too short wires either --- compiler/base/wire.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/compiler/base/wire.py b/compiler/base/wire.py index ddb10f43..10272ede 100644 --- a/compiler/base/wire.py +++ b/compiler/base/wire.py @@ -83,7 +83,6 @@ class wire(wire_path): return pitch - # create a 1x1 contact def create_vias(self): """ Add a via and corner square at every corner of the path.""" @@ -113,7 +112,9 @@ class wire(wire_path): # Horizontal wire segment if pl[index][0] != pl[index + 1][0]: line_length = pl[index + 1][0] - pl[index][0] - if abs(line_length) < self.pitch: + # Make the wire wider to avoid via-to-via spacing problems + # But don't make it wider if it is shorter than one via + if abs(line_length) < self.pitch and abs(line_length) > self.horiz_layer_contact_width: width = self.horiz_layer_contact_width else: width = self.horiz_layer_width @@ -131,7 +132,9 @@ class wire(wire_path): # Vertical wire segment elif pl[index][1] != pl[index + 1][1]: line_length = pl[index + 1][1] - pl[index][1] - if abs(line_length) < self.pitch: + # Make the wire wider to avoid via-to-via spacing problems + # But don't make it wider if it is shorter than one via + if abs(line_length) < self.pitch and abs(line_length) > self.vert_layer_contact_width: width = self.vert_layer_contact_width else: width = self.vert_layer_width From 770533e7b1eab1e03bcbdbaaa1901d4cc2ae2de9 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Apr 2020 11:27:26 -0700 Subject: [PATCH 262/521] Parameterize vdd and gnd pin in sense amp array. --- compiler/modules/sense_amp_array.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index d8cb2869..c2f68f9b 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -126,14 +126,16 @@ class sense_amp_array(design.design): for i in range(len(self.local_insts)): inst = self.local_insts[i] + gnd_pin = inst.get_pin("gnd") self.add_power_pin(name="gnd", - loc=inst.get_pin("gnd").center(), - start_layer="m2", + loc=gnd_pin.center(), + start_layer=gnd_pin.layer, vertical=True) - + + vdd_pin = inst.get_pin("vdd") self.add_power_pin(name="vdd", - loc=inst.get_pin("vdd").center(), - start_layer="m2", + loc=vdd_pin.center(), + start_layer=vdd_pin.layer, vertical=True) bl_pin = inst.get_pin(inst.mod.get_bl_names()) From 843e9414df9fad170a6926e42b435c9e64928cd8 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Apr 2020 11:28:35 -0700 Subject: [PATCH 263/521] Parameterize vdd and gnd pin in write driver array. --- compiler/modules/write_driver_array.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index d1244aed..ab369dda 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -166,7 +166,7 @@ class write_driver_array(design.design): self.add_power_pin(name=n, loc=pin.center(), vertical=True, - start_layer="m2") + start_layer=pin.layer) if self.write_size: for bit in range(self.num_wmasks): inst = self.driver_insts[bit * self.write_size] From 75fce9894c13545fb4da4f681f04dc92bae4650c Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 17 Apr 2020 09:35:07 -0700 Subject: [PATCH 264/521] Allow LVS to run even if DRC fails. --- compiler/tests/testutils.py | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index c4fd7cac..96820e38 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -44,22 +44,30 @@ class openram_test(unittest.TestCase): if not OPTS.netlist_only: a.gds_write(tempgds) + # Run both DRC and LVS even if DRC might fail + # Magic can still extract despite DRC failing, so it might be ok in some techs + # if we ignore things like minimum metal area of pins import verify - result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification) - if result != 0: + drc_result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification) + lvs_result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification) + + if lvs_result != 0: + #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) + #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) + #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) + self.fail("LVS mismatch: {}".format(a.name)) + if lvs_result == 0 and drc_result != 0: + #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) + #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) + #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) + debug.warning("DRC failed but LVS passed: {}".format(a.name)) + elif drc_result != 0: #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) self.fail("DRC failed: {}".format(a.name)) - result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification) - if result != 0: - #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) - #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) - #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) - self.fail("LVS mismatch: {}".format(a.name)) - # For debug... #import pdb; pdb.set_trace() if OPTS.purge_temp: From f1925420cffd2336cc06ac843face6f5e6b28bc1 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 17 Apr 2020 10:30:26 -0700 Subject: [PATCH 265/521] Only allow DRC fail with LVS pass if using Magic. --- compiler/tests/testutils.py | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 96820e38..eaac38e2 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -44,19 +44,18 @@ class openram_test(unittest.TestCase): if not OPTS.netlist_only: a.gds_write(tempgds) + import verify # Run both DRC and LVS even if DRC might fail # Magic can still extract despite DRC failing, so it might be ok in some techs # if we ignore things like minimum metal area of pins - import verify drc_result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification) - lvs_result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification) + + # Always run LVS if we are using magic + if "magic" in OPTS.drc_exe: + lvs_result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification) - if lvs_result != 0: - #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) - #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) - #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) - self.fail("LVS mismatch: {}".format(a.name)) - if lvs_result == 0 and drc_result != 0: + # Only allow DRC to fail and LVS to pass if we are using magic + if "magic" in OPTS.drc_exe and lvs_result == 0 and drc_result != 0: #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) @@ -66,6 +65,12 @@ class openram_test(unittest.TestCase): #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) self.fail("DRC failed: {}".format(a.name)) + + if lvs_result != 0: + #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) + #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) + #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) + self.fail("LVS mismatch: {}".format(a.name)) # For debug... From fbc6dfdaac3688f3a18283646bd3f1e961a45dcd Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Fri, 17 Apr 2020 12:26:18 -0700 Subject: [PATCH 266/521] split pbitcell tests --- ...4_single_level_column_mux_pbitcell_test.py | 49 +++++++++++++++++ .../tests/04_single_level_column_mux_test.py | 20 +------ ...hierarchical_predecode2x4_pbitcell_test.py | 6 +- .../06_hierarchical_predecode2x4_test.py | 2 +- ...hierarchical_predecode3x8_pbitcell_test.py | 2 +- .../06_hierarchical_predecode3x8_test.py | 2 +- ...le_level_column_mux_array_pbitcell_test.py | 55 +++++++++++++++++++ .../07_single_level_column_mux_array_test.py | 27 +-------- .../tests/08_wordline_driver_pbitcell_test.py | 44 +++++++++++++++ compiler/tests/08_wordline_driver_test.py | 13 +---- compiler/tests/09_sense_amp_array_test.py | 15 ----- .../tests/09_sense_amp_array_test_pbitcell.py | 46 ++++++++++++++++ .../10_write_driver_array_pbitcell_test.py | 46 ++++++++++++++++ compiler/tests/10_write_driver_array_test.py | 15 ----- ..._write_driver_array_wmask_pbitcell_test.py | 49 +++++++++++++++++ .../tests/10_write_driver_array_wmask_test.py | 15 ----- .../10_write_mask_and_array_pbitcell_test.py | 49 +++++++++++++++++ .../tests/10_write_mask_and_array_test.py | 15 ----- .../tests/19_bank_select_pbitcell_test.py | 48 ++++++++++++++++ compiler/tests/19_bank_select_test.py | 19 +------ 20 files changed, 398 insertions(+), 139 deletions(-) create mode 100644 compiler/tests/04_single_level_column_mux_pbitcell_test.py create mode 100644 compiler/tests/07_single_level_column_mux_array_pbitcell_test.py create mode 100644 compiler/tests/08_wordline_driver_pbitcell_test.py create mode 100644 compiler/tests/09_sense_amp_array_test_pbitcell.py create mode 100644 compiler/tests/10_write_driver_array_pbitcell_test.py create mode 100644 compiler/tests/10_write_driver_array_wmask_pbitcell_test.py create mode 100644 compiler/tests/10_write_mask_and_array_pbitcell_test.py create mode 100644 compiler/tests/19_bank_select_pbitcell_test.py diff --git a/compiler/tests/04_single_level_column_mux_pbitcell_test.py b/compiler/tests/04_single_level_column_mux_pbitcell_test.py new file mode 100644 index 00000000..85f909e6 --- /dev/null +++ b/compiler/tests/04_single_level_column_mux_pbitcell_test.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +#@unittest.skip("SKIPPING 04_driver_test") + +class single_level_column_mux_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check single level column mux in multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + factory.reset() + debug.info(2, "Checking column mux for pbitcell (innermost connections)") + tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + factory.reset() + debug.info(2, "Checking column mux for pbitcell (outermost connections)") + tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index de5870fc..2b437987 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -22,30 +22,14 @@ class single_level_column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - + # check single level column mux in single port debug.info(2, "Checking column mux") tx = factory.create(module_type="single_level_column_mux", tx_size=8) self.local_check(tx) - - # check single level column mux in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - - factory.reset() - debug.info(2, "Checking column mux for pbitcell (innermost connections)") - tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(tx) - - factory.reset() - debug.info(2, "Checking column mux for pbitcell (outermost connections)") - tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(tx) globals.end_openram() - + # run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py index 8afc45da..bc4a153f 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py @@ -26,13 +26,13 @@ class hierarchical_predecode2x4_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - + debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)") a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) - + globals.end_openram() - + # run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 8bb42253..ebb06330 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -27,7 +27,7 @@ class hierarchical_predecode2x4_test(openram_test): self.local_check(a) globals.end_openram() - + # run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py index 34d38ddf..ffe68102 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py @@ -26,7 +26,7 @@ class hierarchical_predecode3x8_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - + debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)") a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index f01fae03..63acc416 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -25,7 +25,7 @@ class hierarchical_predecode3x8_test(openram_test): debug.info(1, "Testing sample for hierarchy_predecode3x8") a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) - + globals.end_openram() # run the test from the command line diff --git a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py b/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py new file mode 100644 index 00000000..d929b855 --- /dev/null +++ b/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class single_level_column_mux_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + import single_level_column_mux_array + + # check single level column mux array in multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + factory.reset() + debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 4-way column_mux_array in multi-port") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)") + a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)") + a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(a) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index ff6c51eb..c5d48689 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -20,7 +20,7 @@ class single_level_column_mux_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import single_level_column_mux_array - + # check single level column mux array in single port debug.info(1, "Testing sample for 2-way column_mux_array") a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8) @@ -33,32 +33,9 @@ class single_level_column_mux_test(openram_test): debug.info(1, "Testing sample for 8-way column_mux_array") a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4) self.local_check(a) - - # check single level column mux array in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - - factory.reset() - debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(a) - - debug.info(1, "Testing sample for 4-way column_mux_array in multi-port") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(a) - - debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)") - a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(a) - - debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)") - a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(a) globals.end_openram() - + # run the test from the command line if __name__ == "__main__": diff --git a/compiler/tests/08_wordline_driver_pbitcell_test.py b/compiler/tests/08_wordline_driver_pbitcell_test.py new file mode 100644 index 00000000..42de5c26 --- /dev/null +++ b/compiler/tests/08_wordline_driver_pbitcell_test.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +#@unittest.skip("SKIPPING 04_driver_test") + +class wordline_driver_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check wordline driver for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + factory.reset() + debug.info(2, "Checking driver (multi-port case)") + tx = factory.create(module_type="wordline_driver", rows=8, cols=64) + self.local_check(tx) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index f64503f8..8a18a59d 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -28,19 +28,8 @@ class wordline_driver_test(openram_test): tx = factory.create(module_type="wordline_driver", rows=8, cols=32) self.local_check(tx) - # check wordline driver for multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - factory.reset() - debug.info(2, "Checking driver (multi-port case)") - tx = factory.create(module_type="wordline_driver", rows=8, cols=64) - self.local_check(tx) - globals.end_openram() - + # run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index 88b5a9aa..459113f2 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -34,21 +34,6 @@ class sense_amp_test(openram_test): a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) self.local_check(a) - # check sense amp array for multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - factory.reset() - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") - a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2) - self.local_check(a) - - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") - a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) - self.local_check(a) - globals.end_openram() # run the test from the command line diff --git a/compiler/tests/09_sense_amp_array_test_pbitcell.py b/compiler/tests/09_sense_amp_array_test_pbitcell.py new file mode 100644 index 00000000..7c2fbd2d --- /dev/null +++ b/compiler/tests/09_sense_amp_array_test_pbitcell.py @@ -0,0 +1,46 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class sense_amp_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + #check sense amp array for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + factory.reset() + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2) + self.local_check(a) + + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_pbitcell_test.py b/compiler/tests/10_write_driver_array_pbitcell_test.py new file mode 100644 index 00000000..87849001 --- /dev/null +++ b/compiler/tests/10_write_driver_array_pbitcell_test.py @@ -0,0 +1,46 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class write_driver_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check write driver array for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + factory.reset() + debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") + a = factory.create(module_type="write_driver_array", columns=8, word_size=8) + self.local_check(a) + + debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") + a = factory.create(module_type="write_driver_array", columns=16, word_size=8) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 16e280ed..8db26a5a 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -29,22 +29,7 @@ class write_driver_test(openram_test): debug.info(2, "Testing write_driver_array for columns=16, word_size=8") a = factory.create(module_type="write_driver_array", columns=16, word_size=8) self.local_check(a) - - # check write driver array for multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - factory.reset() - debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") - a = factory.create(module_type="write_driver_array", columns=8, word_size=8) - self.local_check(a) - - debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") - a = factory.create(module_type="write_driver_array", columns=16, word_size=8) - self.local_check(a) - globals.end_openram() # run the test from the command line diff --git a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py new file mode 100644 index 00000000..046b4d22 --- /dev/null +++ b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os + +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class write_driver_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check write driver array for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + factory.reset() + debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)") + a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4) + self.local_check(a) + + debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)") + a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4) + self.local_check(a) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py index 743d331a..15e32b19 100755 --- a/compiler/tests/10_write_driver_array_wmask_test.py +++ b/compiler/tests/10_write_driver_array_wmask_test.py @@ -36,21 +36,6 @@ class write_driver_test(openram_test): a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4) self.local_check(a) - # check write driver array for multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - factory.reset() - debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)") - a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4) - self.local_check(a) - - debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)") - a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4) - self.local_check(a) - globals.end_openram() diff --git a/compiler/tests/10_write_mask_and_array_pbitcell_test.py b/compiler/tests/10_write_mask_and_array_pbitcell_test.py new file mode 100644 index 00000000..5068c119 --- /dev/null +++ b/compiler/tests/10_write_mask_and_array_pbitcell_test.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os + +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class write_mask_and_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check write driver array for multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + factory.reset() + debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)") + a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4) + self.local_check(a) + + debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)") + a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2) + self.local_check(a) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py index 303ce2f4..42d80fa4 100755 --- a/compiler/tests/10_write_mask_and_array_test.py +++ b/compiler/tests/10_write_mask_and_array_test.py @@ -36,21 +36,6 @@ class write_mask_and_array_test(openram_test): a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2) self.local_check(a) - # check write driver array for multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - factory.reset() - debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)") - a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4) - self.local_check(a) - - debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)") - a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2) - self.local_check(a) - globals.end_openram() diff --git a/compiler/tests/19_bank_select_pbitcell_test.py b/compiler/tests/19_bank_select_pbitcell_test.py new file mode 100644 index 00000000..6bf5929e --- /dev/null +++ b/compiler/tests/19_bank_select_pbitcell_test.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class bank_select_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + OPTS.bitcell = "pbitcell" + debug.info(1, "No column mux, rw control logic") + a = factory.create(module_type="bank_select", port="rw") + self.local_check(a) + + OPTS.num_rw_ports = 0 + OPTS.num_w_ports = 1 + OPTS.num_r_ports = 1 + + debug.info(1, "No column mux, w control logic") + a = factory.create(module_type="bank_select", port="w") + self.local_check(a) + + debug.info(1, "No column mux, r control logic") + a = factory.create(module_type="bank_select", port="r") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index adb2523e..afec4c3c 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -24,26 +24,9 @@ class bank_select_test(openram_test): debug.info(1, "No column mux, rw control logic") a = factory.create(module_type="bank_select", port="rw") self.local_check(a) - - OPTS.bitcell = "pbitcell" - debug.info(1, "No column mux, rw control logic") - a = factory.create(module_type="bank_select", port="rw") - self.local_check(a) - - OPTS.num_rw_ports = 0 - OPTS.num_w_ports = 1 - OPTS.num_r_ports = 1 - debug.info(1, "No column mux, w control logic") - a = factory.create(module_type="bank_select", port="w") - self.local_check(a) - - debug.info(1, "No column mux, r control logic") - a = factory.create(module_type="bank_select", port="r") - self.local_check(a) - globals.end_openram() - + # run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() From 7920b0cef99f0ece902a14c47fe5c37e9fa0f263 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Fri, 17 Apr 2020 12:36:48 -0700 Subject: [PATCH 267/521] m3 min area rounding fix --- compiler/base/hierarchy_layout.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e67f8d85..14136c9c 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -17,6 +17,7 @@ import os from globals import OPTS from vector import vector from pin_layout import pin_layout +from utils import round_to_grid class layout(): @@ -325,7 +326,7 @@ class layout(): file_name = "non_rectilinear.gds" self.gds_write(file_name) debug.error("Cannot have a non-manhatten layout pin: {}".format(file_name), -1) - + minwidth_layer = drc["minwidth_{}".format(layer)] # one of these will be zero @@ -1213,7 +1214,8 @@ class layout(): else: # Hack for min area if OPTS.tech_name == "s8": - height = width = sqrt(drc["minarea_m3"]) + width = round_to_grid(sqrt(drc["minarea_m3"])) + height = round_to_grid(drc["minarea_m3"]/width) else: width = via.width height = via.height From 7e36cd482855bfa5408ea0fb794be107adb6ada8 Mon Sep 17 00:00:00 2001 From: David Ratchkov Date: Fri, 17 Apr 2020 13:45:57 -0700 Subject: [PATCH 268/521] - Write voltage_map and pg_pin - Remove 'when' condition on leakage power - Remove 'clk*' from 'when' condition on internal_power on the same 'clk*' pin --- compiler/characterizer/lib.py | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 1e68fc2e..b0668ddc 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -181,17 +181,20 @@ class lib: self.lib.write(" dont_touch : true;\n") self.lib.write(" area : {};\n\n".format(self.sram.width * self.sram.height)) - #Build string of all control signals. + self.write_pg_pin() + + #Build string of all control signals. control_str = 'csb0' #assume at least 1 port for i in range(1, self.total_port_num): control_str += ' & csb{0}'.format(i) # Leakage is included in dynamic when macro is enabled self.lib.write(" leakage_power () {\n") - self.lib.write(" when : \"{0}\";\n".format(control_str)) + # 'when' condition unnecessary when cs pin does not turn power to devices + # self.lib.write(" when : \"{0}\";\n".format(control_str)) self.lib.write(" value : {};\n".format(self.char_sram_results["leakage_power"])) self.lib.write(" }\n") - self.lib.write(" cell_leakage_power : {};\n".format(0)) + self.lib.write(" cell_leakage_power : {};\n".format(self.char_sram_results["leakage_power"])) def write_units(self): @@ -240,6 +243,9 @@ class lib: self.lib.write(" default_max_fanout : 4.0 ;\n") self.lib.write(" default_connection_class : universal ;\n\n") + self.lib.write(" voltage_map ( vdd, {} );\n".format(tech.spice["nom_supply_voltage"])) + self.lib.write(" voltage_map ( gnd, 0 );\n\n") + def create_list(self,values): """ Helper function to create quoted, line wrapped list """ list_values = ", ".join(str(v) for v in values) @@ -518,7 +524,7 @@ class lib: web_name = " & !web{0}".format(port) avg_write_power = np.mean(self.char_port_results[port]["write1_power"] + self.char_port_results[port]["write0_power"]) self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"!csb{0} & clk{0}{1}\"; \n".format(port, web_name)) + self.lib.write(" when : \"!csb{0}{1}\"; \n".format(port, web_name)) self.lib.write(" rise_power(scalar){\n") self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) self.lib.write(" }\n") @@ -532,7 +538,7 @@ class lib: web_name = " & web{0}".format(port) avg_read_power = np.mean(self.char_port_results[port]["read1_power"] + self.char_port_results[port]["read0_power"]) self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"!csb{0} & !clk{0}{1}\"; \n".format(port, web_name)) + self.lib.write(" when : \"!csb{0}{1}\"; \n".format(port, web_name)) self.lib.write(" rise_power(scalar){\n") self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) self.lib.write(" }\n") @@ -552,6 +558,16 @@ class lib: self.lib.write(" }\n") self.lib.write(" }\n") + def write_pg_pin(self): + self.lib.write(" pg_pin(vdd) {\n") + self.lib.write(" voltage_name : VDD;\n") + self.lib.write(" pg_type : primary_power;\n") + self.lib.write(" }\n\n") + self.lib.write(" pg_pin(gnd) {\n") + self.lib.write(" voltage_name : GND;\n") + self.lib.write(" pg_type : primary_ground;\n") + self.lib.write(" }\n\n") + def compute_delay(self): """Compute SRAM delays for current corner""" self.d = delay(self.sram, self.sp_file, self.corner) From cbb67ad483fd6873d562e1d6f6a90711cf03c8a1 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 17 Apr 2020 13:57:52 -0700 Subject: [PATCH 269/521] Update to run LVS when no DRC errors too. --- compiler/tests/testutils.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index eaac38e2..99d534d0 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -51,9 +51,9 @@ class openram_test(unittest.TestCase): drc_result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification) # Always run LVS if we are using magic - if "magic" in OPTS.drc_exe: + if "magic" in OPTS.drc_exe or drc_result == 0: lvs_result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification) - + # Only allow DRC to fail and LVS to pass if we are using magic if "magic" in OPTS.drc_exe and lvs_result == 0 and drc_result != 0: #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) From a158ad1e81144c21c6b1e0b680cc38f58fdad01d Mon Sep 17 00:00:00 2001 From: jcirimel Date: Fri, 17 Apr 2020 14:24:52 -0700 Subject: [PATCH 270/521] add missing import --- compiler/pgates/pnor2.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 47c1cc16..b1899b4c 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -8,6 +8,7 @@ import contact import pgate import debug +from globals import OPTS from tech import drc, parameter, spice from vector import vector from sram_factory import factory From 1f816e2823b56c0c3f406d4f7424e7fb6311b236 Mon Sep 17 00:00:00 2001 From: David Ratchkov Date: Fri, 17 Apr 2020 14:55:17 -0700 Subject: [PATCH 271/521] - Characterize actual disabled power (read mode only) - Report rise/fall power individually --- .gitignore | 2 ++ compiler/characterizer/delay.py | 15 +++++++++++++-- compiler/characterizer/lib.py | 22 +++++++++++++--------- compiler/characterizer/simulation.py | 16 ++++++++++++++++ 4 files changed, 44 insertions(+), 11 deletions(-) diff --git a/.gitignore b/.gitignore index 948e7d19..3d6e4f92 100644 --- a/.gitignore +++ b/.gitignore @@ -8,3 +8,5 @@ *.toc *.synctex.gz **/model_data +outputs +technology/freepdk45/ncsu_basekit diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index a9f9542c..2823a415 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -59,7 +59,7 @@ class delay(simulation): """ Create measurement names. The names themselves currently define the type of measurement """ self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"] - self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power"] + self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power", "disabled_read0_power", "disabled_read1_power"] # self.voltage_when_names = ["volt_bl", "volt_br"] # self.bitline_delay_names = ["delay_bl", "delay_br"] @@ -108,6 +108,11 @@ class delay(simulation): self.read_lib_meas.append(power_measure("read0_power", "FALL", measure_scale=1e3)) self.read_lib_meas[-1].meta_str = sram_op.READ_ZERO + self.read_lib_meas.append(power_measure("disabled_read1_power", "RISE", measure_scale=1e3)) + self.read_lib_meas[-1].meta_str = "disabled_read1" + self.read_lib_meas.append(power_measure("disabled_read0_power", "FALL", measure_scale=1e3)) + self.read_lib_meas[-1].meta_str = "disabled_read0" + # This will later add a half-period to the spice time delay. Only for reading 0. for obj in self.read_lib_meas: if obj.meta_str is sram_op.READ_ZERO: @@ -665,7 +670,7 @@ class delay(simulation): if not success: feasible_period = 2 * feasible_period continue - + # Positions of measurements currently hardcoded. First 2 are delays, next 2 are slews feasible_delays = [results[port][mname] for mname in self.delay_meas_names if "delay" in mname] feasible_slews = [results[port][mname] for mname in self.delay_meas_names if "slew" in mname] @@ -1208,6 +1213,9 @@ class delay(simulation): read_port) self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times)-1 + self.add_nop(self.probe_address, data_zeros, read_port) + self.measure_cycles[write_port]["disabled_read0"] = len(self.cycle_times) - 1 + self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)") self.add_write("W data 1 address {} to write value".format(self.probe_address), @@ -1223,6 +1231,9 @@ class delay(simulation): wmask_ones, write_port) + self.add_nop(self.probe_address, data_zeros, read_port) + self.measure_cycles[write_port]["disabled_read1"] = len(self.cycle_times) - 1 + # This also ensures we will have a L->H transition on the next read self.add_read("R data 0 address {} to clear dout caps".format(inverse_address), inverse_address, diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index b0668ddc..9f3c12d3 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -522,39 +522,43 @@ class lib: if port in self.write_ports: if port in self.read_ports: web_name = " & !web{0}".format(port) - avg_write_power = np.mean(self.char_port_results[port]["write1_power"] + self.char_port_results[port]["write0_power"]) + write1_power = np.mean(self.char_port_results[port]["write1_power"]) + write0_power = np.mean(self.char_port_results[port]["write0_power"]) self.lib.write(" internal_power(){\n") self.lib.write(" when : \"!csb{0}{1}\"; \n".format(port, web_name)) self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) + self.lib.write(" values(\"{0:.6e}\");\n".format(write1_power)) self.lib.write(" }\n") self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) + self.lib.write(" values(\"{0:.6e}\");\n".format(write0_power)) self.lib.write(" }\n") self.lib.write(" }\n") if port in self.read_ports: if port in self.write_ports: web_name = " & web{0}".format(port) - avg_read_power = np.mean(self.char_port_results[port]["read1_power"] + self.char_port_results[port]["read0_power"]) + read1_power = np.mean(self.char_port_results[port]["read1_power"]) + read0_power = np.mean(self.char_port_results[port]["read0_power"]) self.lib.write(" internal_power(){\n") self.lib.write(" when : \"!csb{0}{1}\"; \n".format(port, web_name)) self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) + self.lib.write(" values(\"{0:.6e}\");\n".format(read1_power)) self.lib.write(" }\n") self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) + self.lib.write(" values(\"{0:.6e}\");\n".format(read0_power)) self.lib.write(" }\n") self.lib.write(" }\n") - # Have 0 internal power when disabled, this will be represented as leakage power. + # Disabled power. + disabled_read1_power = np.mean(self.char_port_results[port]["disabled_read1_power"]) + disabled_read0_power = np.mean(self.char_port_results[port]["disabled_read0_power"]) self.lib.write(" internal_power(){\n") self.lib.write(" when : \"csb{0}\"; \n".format(port)) self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"0\");\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read1_power)) self.lib.write(" }\n") self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"0\");\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read0_power)) self.lib.write(" }\n") self.lib.write(" }\n") diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index adbe5f5f..0cfc860f 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -210,6 +210,22 @@ class simulation(): if unselected_port != port: self.add_noop_one_port(unselected_port) + def add_nop(self, address, din_data, port): + """ Add the control values for a cycle with clock only. Does not increment the period. """ + debug.check(port in self.read_ports or port in self.write_ports, + "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_ports)) + debug.info(2, 'Clock only on port {}'.format(port)) + self.fn_cycle_comments.append('Clock only on port {}'.format(port)) + self.append_cycle_comment(port, 'Clock only on port {}'.format(port)) + + self.cycle_times.append(self.t_current) + self.t_current += self.period + self.add_control_one_port(port, "noop") + # If the port is also a readwrite then add data. + if port in self.write_ports: + self.add_data(din_data, port) + self.add_address(address, port) + def add_noop_all_ports(self, comment): """ Add the control values for a noop to all ports. """ debug.info(2, comment) From 486819ae0d1d11281e1f5544bc0a670c56632627 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Fri, 17 Apr 2020 15:27:36 -0700 Subject: [PATCH 272/521] fix width bin typo --- compiler/pgates/pgate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index de513cc3..d3084146 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -300,7 +300,7 @@ class pgate(design.design): bins = bins[0:bisect_left(bins, target_width) + 1] if len(bins) == 1: selected_bin = bins[0] - scaling_factor = math.ceil(target_width / width) + scaling_factor = math.ceil(target_width / selected_bin) scaled_bin = bins[0] * scaling_factor else: From 123cc371beabe50a21bdf4382ce332198cd20255 Mon Sep 17 00:00:00 2001 From: David Ratchkov Date: Fri, 17 Apr 2020 16:09:58 -0700 Subject: [PATCH 273/521] - Fix disabled power char --- compiler/characterizer/delay.py | 24 ++++++++++++++---- compiler/characterizer/lib.py | 37 +++++++++++++++++++--------- compiler/characterizer/simulation.py | 33 +++++++++++++------------ 3 files changed, 61 insertions(+), 33 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 2823a415..62367d72 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -59,7 +59,8 @@ class delay(simulation): """ Create measurement names. The names themselves currently define the type of measurement """ self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"] - self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power", "disabled_read0_power", "disabled_read1_power"] + self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power", + "disabled_read0_power", "disabled_read1_power", "disabled_write0_power", "disabled_write1_power"] # self.voltage_when_names = ["volt_bl", "volt_br"] # self.bitline_delay_names = ["delay_bl", "delay_br"] @@ -161,6 +162,11 @@ class delay(simulation): self.write_lib_meas.append(power_measure("write0_power", "FALL", measure_scale=1e3)) self.write_lib_meas[-1].meta_str = sram_op.WRITE_ZERO + self.write_lib_meas.append(power_measure("disabled_write1_power", "RISE", measure_scale=1e3)) + self.write_lib_meas[-1].meta_str = "disabled_write1" + self.write_lib_meas.append(power_measure("disabled_write0_power", "FALL", measure_scale=1e3)) + self.write_lib_meas[-1].meta_str = "disabled_write0" + write_measures = [] write_measures.append(self.write_lib_meas) write_measures.append(self.create_write_bit_measures()) @@ -1203,6 +1209,9 @@ class delay(simulation): write_port) self.measure_cycles[write_port][sram_op.WRITE_ZERO] = len(self.cycle_times)-1 + self.add_noop_clock_one_port(write_port) + self.measure_cycles[write_port]["disabled_write0"] = len(self.cycle_times)-1 + # This also ensures we will have a H->L transition on the next read self.add_read("R data 1 address {} to set dout caps".format(inverse_address), inverse_address, @@ -1213,8 +1222,9 @@ class delay(simulation): read_port) self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times)-1 - self.add_nop(self.probe_address, data_zeros, read_port) - self.measure_cycles[write_port]["disabled_read0"] = len(self.cycle_times) - 1 + self.add_noop_clock_one_port(read_port) + self.measure_cycles[read_port]["disabled_read0"] = len(self.cycle_times) - 1 + self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)") @@ -1225,14 +1235,18 @@ class delay(simulation): write_port) self.measure_cycles[write_port][sram_op.WRITE_ONE] = len(self.cycle_times)-1 + self.add_noop_clock_one_port(write_port) + self.measure_cycles[write_port]["disabled_write1"] = len(self.cycle_times)-1 + self.add_write("W data 0 address {} to clear din caps".format(inverse_address), inverse_address, data_zeros, wmask_ones, write_port) - self.add_nop(self.probe_address, data_zeros, read_port) - self.measure_cycles[write_port]["disabled_read1"] = len(self.cycle_times) - 1 + self.add_noop_clock_one_port(read_port) + self.measure_cycles[read_port]["disabled_read1"] = len(self.cycle_times) - 1 + # This also ensures we will have a L->H transition on the next read self.add_read("R data 0 address {} to clear dout caps".format(inverse_address), diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 9f3c12d3..57e21763 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -534,6 +534,19 @@ class lib: self.lib.write(" }\n") self.lib.write(" }\n") + # Disabled power. + disabled_read1_power = np.mean(self.char_port_results[port]["disabled_read1_power"]) + disabled_read0_power = np.mean(self.char_port_results[port]["disabled_raed0_power"]) + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"csb{0}{1}\"; \n".format(port, web_name)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read1_power)) + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read0_power)) + self.lib.write(" }\n") + self.lib.write(" }\n") + if port in self.read_ports: if port in self.write_ports: web_name = " & web{0}".format(port) @@ -549,18 +562,18 @@ class lib: self.lib.write(" }\n") self.lib.write(" }\n") - # Disabled power. - disabled_read1_power = np.mean(self.char_port_results[port]["disabled_read1_power"]) - disabled_read0_power = np.mean(self.char_port_results[port]["disabled_read0_power"]) - self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"csb{0}\"; \n".format(port)) - self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read1_power)) - self.lib.write(" }\n") - self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read0_power)) - self.lib.write(" }\n") - self.lib.write(" }\n") + # Disabled power. + disabled_write1_power = np.mean(self.char_port_results[port]["disabled_write1_power"]) + disabled_write0_power = np.mean(self.char_port_results[port]["disabled_write0_power"]) + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"csb{0}{1}\"; \n".format(port, web_name)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write1_power)) + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write0_power)) + self.lib.write(" }\n") + self.lib.write(" }\n") def write_pg_pin(self): self.lib.write(" pg_pin(vdd) {\n") diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 0cfc860f..0d5cfb25 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -210,22 +210,6 @@ class simulation(): if unselected_port != port: self.add_noop_one_port(unselected_port) - def add_nop(self, address, din_data, port): - """ Add the control values for a cycle with clock only. Does not increment the period. """ - debug.check(port in self.read_ports or port in self.write_ports, - "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_ports)) - debug.info(2, 'Clock only on port {}'.format(port)) - self.fn_cycle_comments.append('Clock only on port {}'.format(port)) - self.append_cycle_comment(port, 'Clock only on port {}'.format(port)) - - self.cycle_times.append(self.t_current) - self.t_current += self.period - self.add_control_one_port(port, "noop") - # If the port is also a readwrite then add data. - if port in self.write_ports: - self.add_data(din_data, port) - self.add_address(address, port) - def add_noop_all_ports(self, comment): """ Add the control values for a noop to all ports. """ debug.info(2, comment) @@ -295,6 +279,23 @@ class simulation(): except: self.add_wmask("0"*self.num_wmasks, port) + def add_noop_clock_one_port(self, port): + """ Add the control values for a noop to a single port. Increments the period. """ + debug.info(2, 'Clock only on port {}'.format(port)) + self.fn_cycle_comments.append('Clock only on port {}'.format(port)) + self.append_cycle_comment(port, 'Clock only on port {}'.format(port)) + + self.cycle_times.append(self.t_current) + self.t_current += self.period + + self.add_noop_one_port(port) + + #Add noops to all other ports. + for unselected_port in self.all_ports: + if unselected_port != port: + self.add_noop_one_port(unselected_port) + + def append_cycle_comment(self, port, comment): """Add comment to list to be printed in stimulus file""" #Clean up time before appending. Make spacing dynamic as well. From 5aea45ed690593e4e9b965f84639e12ea29731e9 Mon Sep 17 00:00:00 2001 From: David Ratchkov Date: Fri, 17 Apr 2020 16:23:06 -0700 Subject: [PATCH 274/521] - Fix switched disabled powers --- compiler/characterizer/lib.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 57e21763..276ea767 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -535,15 +535,15 @@ class lib: self.lib.write(" }\n") # Disabled power. - disabled_read1_power = np.mean(self.char_port_results[port]["disabled_read1_power"]) - disabled_read0_power = np.mean(self.char_port_results[port]["disabled_raed0_power"]) + disabled_write1_power = np.mean(self.char_port_results[port]["disabled_write1_power"]) + disabled_write0_power = np.mean(self.char_port_results[port]["disabled_write0_power"]) self.lib.write(" internal_power(){\n") self.lib.write(" when : \"csb{0}{1}\"; \n".format(port, web_name)) self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read1_power)) + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write1_power)) self.lib.write(" }\n") self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read0_power)) + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write0_power)) self.lib.write(" }\n") self.lib.write(" }\n") @@ -563,18 +563,18 @@ class lib: self.lib.write(" }\n") # Disabled power. - disabled_write1_power = np.mean(self.char_port_results[port]["disabled_write1_power"]) - disabled_write0_power = np.mean(self.char_port_results[port]["disabled_write0_power"]) + disabled_read1_power = np.mean(self.char_port_results[port]["disabled_read1_power"]) + disabled_read0_power = np.mean(self.char_port_results[port]["disabled_read0_power"]) self.lib.write(" internal_power(){\n") self.lib.write(" when : \"csb{0}{1}\"; \n".format(port, web_name)) self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write1_power)) + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read1_power)) self.lib.write(" }\n") self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write0_power)) + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read0_power)) self.lib.write(" }\n") self.lib.write(" }\n") - + def write_pg_pin(self): self.lib.write(" pg_pin(vdd) {\n") self.lib.write(" voltage_name : VDD;\n") From 1f094b03bc3f2d962ebd06138cfbade446eac82c Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sat, 18 Apr 2020 05:26:39 -0700 Subject: [PATCH 275/521] use more optimal discrete pinv sizing --- compiler/pgates/pgate.py | 29 +++++++++++---- compiler/pgates/pinv.py | 77 ++++++++++++++++++++++++++++------------ 2 files changed, 78 insertions(+), 28 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index d3084146..a49be6a0 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -15,7 +15,7 @@ from vector import vector from globals import OPTS if(OPTS.tech_name == "s8"): - from tech import nmos_bins, pmos_bins + from tech import nmos_bins, pmos_bins, accuracy_requirement class pgate(design.design): """ @@ -323,11 +323,28 @@ class pgate(design.design): return(selected_bin, scaling_factor) + def permute_widths(self, tx_type, target_width): - - - + if tx_type == "nmos": + bins = nmos_bins[drc("minwidth_poly")] + elif tx_type == "pmos": + bins = pmos_bins[drc("minwidth_poly")] + else: + debug.error("invalid tx type") - - + bins = bins[0:bisect_left(bins, target_width) + 1] + + if len(bins) == 1: + selected_bins = (bins[0], math.ceil(target_width / bins[0])) + else: + scaled_bins = [] + scaled_bins.append((bins[-1], 1)) + for width in bins[:-1]: + m = math.ceil(target_width / width) + scaled_bins.append((m * width, m)) + + return(scaled_bins) + + def bin_accuracy(self, ideal_width, width): + return abs(1-(ideal_width - width)/ideal_width) \ No newline at end of file diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 5e44ecff..07f724e0 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -8,15 +8,19 @@ import contact import pgate import debug +import operator from tech import drc, parameter, spice from vector import vector from math import ceil from globals import OPTS from utils import round_to_grid +from bisect import bisect_left import logical_effort from sram_factory import factory from errors import drc_error +if(OPTS.tech_name == "s8"): + from tech import nmos_bins, pmos_bins, accuracy_requirement class pinv(pgate.pgate): """ @@ -134,30 +138,59 @@ class pinv(pgate.pgate): # Determine the number of mults for each to fit width # into available space - self.nmos_width = self.nmos_size * drc("minwidth_tx") - self.pmos_width = self.pmos_size * drc("minwidth_tx") - nmos_required_mults = max(int(ceil(self.nmos_width / nmos_height_available)), 1) - pmos_required_mults = max(int(ceil(self.pmos_width / pmos_height_available)), 1) - # The mults must be the same for easy connection of poly - self.tx_mults = max(nmos_required_mults, pmos_required_mults) + if OPTS.tech_name != "s8": + self.nmos_width = self.nmos_size * drc("minwidth_tx") + self.pmos_width = self.pmos_size * drc("minwidth_tx") + nmos_required_mults = max(int(ceil(self.nmos_width / nmos_height_available)), 1) + pmos_required_mults = max(int(ceil(self.pmos_width / pmos_height_available)), 1) + # The mults must be the same for easy connection of poly + self.tx_mults = max(nmos_required_mults, pmos_required_mults) - # Recompute each mult width and check it isn't too small - # This could happen if the height is narrow and the size is small - # User should pick a bigger size to fix it... - # We also need to round the width to the grid or we will end up - # with LVS property mismatch errors when fingers are not a grid - # length and get rounded in the offset geometry. - self.nmos_width = round_to_grid(self.nmos_width / self.tx_mults) - # debug.check(self.nmos_width >= drc("minwidth_tx"), - # "Cannot finger NMOS transistors to fit cell height.") - if self.nmos_width < drc("minwidth_tx"): - raise drc_error("Cannot finger NMOS transistors to fit cell height.") + # Recompute each mult width and check it isn't too small + # This could happen if the height is narrow and the size is small + # User should pick a bigger size to fix it... + # We also need to round the width to the grid or we will end up + # with LVS property mismatch errors when fingers are not a grid + # length and get rounded in the offset geometry. + self.nmos_width = round_to_grid(self.nmos_width / self.tx_mults) + # debug.check(self.nmos_width >= drc("minwidth_tx"), + # "Cannot finger NMOS transistors to fit cell height.") + if self.nmos_width < drc("minwidth_tx"): + raise drc_error("Cannot finger NMOS transistors to fit cell height.") - self.pmos_width = round_to_grid(self.pmos_width / self.tx_mults) - #debug.check(self.pmos_width >= drc("minwidth_tx"), - # "Cannot finger PMOS transistors to fit cell height.") - if self.pmos_width < drc("minwidth_tx"): - raise drc_error("Cannot finger NMOS transistors to fit cell height.") + self.pmos_width = round_to_grid(self.pmos_width / self.tx_mults) + #debug.check(self.pmos_width >= drc("minwidth_tx"), + # "Cannot finger PMOS transistors to fit cell height.") + if self.pmos_width < drc("minwidth_tx"): + raise drc_error("Cannot finger NMOS transistors to fit cell height.") + else: + self.nmos_width = self.nmos_size * drc("minwidth_tx") + self.pmos_width = self.pmos_size * drc("minwidth_tx") + nmos_bins = self.permute_widths("nmos", self.nmos_width) + pmos_bins = self.permute_widths("pmos", self.pmos_width) + + valid_pmos = [] + for bin in pmos_bins: + if self.bin_accuracy(self.pmos_width, bin[0]) > accuracy_requirement: + valid_pmos.append(bin) + valid_pmos.sort(key = operator.itemgetter(1)) + + valid_nmos = [] + for bin in nmos_bins: + if self.bin_accuracy(self.nmos_width, bin[0]) > accuracy_requirement: + valid_nmos.append(bin) + valid_nmos.sort(key = operator.itemgetter(1)) + + for bin in valid_pmos: + if bin[0]/bin[1] < pmos_height_available: + self.pmos_width = valid_nmos[0][0] + self.tx_mults = valid_pmos[0][1] + break + + for bin in valid_nmos: + if bin[0]/bin[1] < nmos_height_available: + self.nmos_width = valid_nmos[0][0] + break def add_ptx(self): """ Create the PMOS and NMOS transistors. """ From 85bc801689a5afbdb5f79d59a6c6cda605df3159 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sat, 18 Apr 2020 05:34:55 -0700 Subject: [PATCH 276/521] fix pinv drc bug --- compiler/pgates/pinv.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 07f724e0..d3062cba 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -183,14 +183,17 @@ class pinv(pgate.pgate): for bin in valid_pmos: if bin[0]/bin[1] < pmos_height_available: - self.pmos_width = valid_nmos[0][0] - self.tx_mults = valid_pmos[0][1] + self.pmos_width = bin[0]/bin[1] + pmos_mults = valid_pmos[0][1] break for bin in valid_nmos: if bin[0]/bin[1] < nmos_height_available: - self.nmos_width = valid_nmos[0][0] + self.nmos_width = bin[0]/bin[1] + nmos_mults = valid_pmos[0][1] break + + self.tx_mults = max(pmos_mults, nmos_mults) def add_ptx(self): """ Create the PMOS and NMOS transistors. """ From add9ec7b2836677ba46e296d48f6bf4fe2837608 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sat, 18 Apr 2020 05:42:23 -0700 Subject: [PATCH 277/521] remove excess newlines --- compiler/pgates/pgate.py | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index a49be6a0..f3fc9abc 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -296,7 +296,6 @@ class pgate(design.design): else: debug.error("invalid tx type") - bins = bins[0:bisect_left(bins, target_width) + 1] if len(bins) == 1: selected_bin = bins[0] @@ -330,11 +329,8 @@ class pgate(design.design): elif tx_type == "pmos": bins = pmos_bins[drc("minwidth_poly")] else: - debug.error("invalid tx type") - - + debug.error("invalid tx type") bins = bins[0:bisect_left(bins, target_width) + 1] - if len(bins) == 1: selected_bins = (bins[0], math.ceil(target_width / bins[0])) else: From f590ecf83c2f1f318982a3152771e51cc9edef71 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sat, 18 Apr 2020 05:51:21 -0700 Subject: [PATCH 278/521] fix minimum pinv sizing --- compiler/pgates/pgate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index f3fc9abc..a942b35f 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -332,7 +332,7 @@ class pgate(design.design): debug.error("invalid tx type") bins = bins[0:bisect_left(bins, target_width) + 1] if len(bins) == 1: - selected_bins = (bins[0], math.ceil(target_width / bins[0])) + scaled_bins = [(bins[0], math.ceil(target_width / bins[0]))] else: scaled_bins = [] scaled_bins.append((bins[-1], 1)) From 7f65176908ec460b3229c897a3cfd93bb7100e64 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 20 Apr 2020 14:23:40 -0700 Subject: [PATCH 279/521] Configured bitline directions into prot_data --- compiler/base/hierarchy_layout.py | 36 +++++++++++++++++++++---------- compiler/modules/bitcell_array.py | 24 ++++++++++----------- compiler/modules/port_data.py | 7 +++++- 3 files changed, 42 insertions(+), 25 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e67f8d85..3cf3e727 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -974,6 +974,7 @@ class layout(): def create_channel_route(self, netlist, offset, layer_stack, + layer_dirs=None, vertical=False): """ The net list is a list of the nets. Each net is a list of pins @@ -1012,25 +1013,38 @@ class layout(): def vcg_pin_overlap(pin1, pin2, vertical, pitch): """ Check for vertical or horizontal overlap of the two pins """ + # FIXME: If the pins are not in a row, this may break. # However, a top pin shouldn't overlap another top pin, # for example, so the # extra comparison *shouldn't* matter. # Pin 1 must be in the "BOTTOM" set - x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x-pin2.center().x) Date: Mon, 20 Apr 2020 14:26:44 -0700 Subject: [PATCH 280/521] Split port data test into single and multi-port. --- compiler/tests/18_port_data_1rw_1r_test.py | 78 ++++++++++++++++++++++ compiler/tests/18_port_data_test.py | 46 ------------- 2 files changed, 78 insertions(+), 46 deletions(-) create mode 100755 compiler/tests/18_port_data_1rw_1r_test.py diff --git a/compiler/tests/18_port_data_1rw_1r_test.py b/compiler/tests/18_port_data_1rw_1r_test.py new file mode 100755 index 00000000..3e1dbded --- /dev/null +++ b/compiler/tests/18_port_data_1rw_1r_test.py @@ -0,0 +1,78 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class port_data_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + OPTS.bitcell = "bitcell_1w_1r" + OPTS.num_rw_ports = 0 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + c = sram_config(word_size=4, + num_words=16) + + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py index 71681056..57e19846 100755 --- a/compiler/tests/18_port_data_test.py +++ b/compiler/tests/18_port_data_test.py @@ -55,52 +55,6 @@ class port_data_test(openram_test): a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) - OPTS.bitcell = "bitcell_1w_1r" - OPTS.num_rw_ports = 0 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - - c.num_words=16 - c.words_per_row=1 - factory.reset() - c.recompute_sizes() - debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) - self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) - self.local_check(a) - - c.num_words=32 - c.words_per_row=2 - factory.reset() - c.recompute_sizes() - debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) - self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) - self.local_check(a) - - c.num_words=64 - c.words_per_row=4 - factory.reset() - c.recompute_sizes() - debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) - self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) - self.local_check(a) - - c.word_size=2 - c.num_words=128 - c.words_per_row=8 - factory.reset() - c.recompute_sizes() - debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) - self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) - self.local_check(a) - globals.end_openram() # run the test from the command line From 7995451cbb669cd346fca33cb8f4a9889e5434ce Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 20 Apr 2020 14:45:18 -0700 Subject: [PATCH 281/521] PEP8 formatting --- .../modules/single_level_column_mux_array.py | 63 ++++++++----------- 1 file changed, 26 insertions(+), 37 deletions(-) diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 324b7415..d1c08e18 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -5,17 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from math import log import design -import contact -from tech import drc import debug -import math from vector import vector from sram_factory import factory from globals import OPTS import logical_effort + class single_level_column_mux_array(design.design): """ Dynamically generated column mux array. @@ -56,7 +53,7 @@ class single_level_column_mux_array(design.design): self.add_routing() # Find the highest shapes to determine height before adding well highest = self.find_highest_coords() - self.height = highest.y + self.height = highest.y self.add_layout_pins() self.add_enclosure(self.mux_inst, "pwell") @@ -74,22 +71,18 @@ class single_level_column_mux_array(design.design): self.add_pin("br_out_{}".format(i)) self.add_pin("gnd") - def add_modules(self): self.mux = factory.create(module_type="single_level_column_mux", bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) self.add_mod(self.mux) - def setup_layout_constants(self): - self.column_addr_size = num_of_inputs = int(self.words_per_row / 2) + self.column_addr_size = int(self.words_per_row / 2) self.width = self.columns * self.mux.width # one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br # one extra route pitch is to space from the sense amp - self.route_height = (self.words_per_row + 3)*self.m1_pitch - - + self.route_height = (self.words_per_row + 3) * self.m1_pitch def create_array(self): self.mux_inst = [] @@ -101,8 +94,8 @@ class single_level_column_mux_array(design.design): self.connect_inst(["bl_{}".format(col_num), "br_{}".format(col_num), - "bl_out_{}".format(int(col_num/self.words_per_row)), - "br_out_{}".format(int(col_num/self.words_per_row)), + "bl_out_{}".format(int(col_num / self.words_per_row)), + "br_out_{}".format(int(col_num / self.words_per_row)), "sel_{}".format(col_num % self.words_per_row), "gnd"]) @@ -117,11 +110,9 @@ class single_level_column_mux_array(design.design): else: mirror = "" - name = "XMUX{0}".format(col_num) offset = vector(xoffset, self.route_height) self.mux_inst[col_num].place(offset=offset, mirror=mirror) - def add_layout_pins(self): """ Add the pins after we determine the height. """ # For every column, add a pass gate @@ -131,18 +122,17 @@ class single_level_column_mux_array(design.design): self.add_layout_pin(text="bl_{}".format(col_num), layer="m2", offset=offset, - height=self.height-offset.y) + height=self.height - offset.y) offset = mux_inst.get_pin("br").ll() self.add_layout_pin(text="br_{}".format(col_num), layer="m2", offset=offset, - height=self.height-offset.y) + height=self.height - offset.y) for inst in self.mux_inst: self.copy_layout_pin(inst, "gnd") - def add_routing(self): self.add_horizontal_input_rail() self.add_vertical_poly_rail() @@ -151,7 +141,7 @@ class single_level_column_mux_array(design.design): def add_horizontal_input_rail(self): """ Create address input rails on M1 below the mux transistors """ for j in range(self.words_per_row): - offset = vector(0, self.route_height + (j-self.words_per_row)*self.m1_pitch) + offset = vector(0, self.route_height + (j - self.words_per_row) * self.m1_pitch) self.add_layout_pin(text="sel_{}".format(j), layer="m1", offset=offset, @@ -167,9 +157,10 @@ class single_level_column_mux_array(design.design): # Add the column x offset to find the right select bit gate_offset = self.mux_inst[col].get_pin("sel").bc() # height to connect the gate to the correct horizontal row - sel_height = self.get_pin("sel_{}".format(sel_index)).by() + # sel_height = self.get_pin("sel_{}".format(sel_index)).by() # use the y offset from the sel pin and the x offset from the gate - offset = vector(gate_offset.x,self.get_pin("sel_{}".format(sel_index)).cy()) + offset = vector(gate_offset.x, + self.get_pin("sel_{}".format(sel_index)).cy()) # Add the poly contact with a shift to account for the rotation self.add_via_center(layers=("m1", "contact", "poly"), offset=offset) @@ -182,11 +173,11 @@ class single_level_column_mux_array(design.design): bl_offset = self.mux_inst[j].get_pin("bl_out").bc() br_offset = self.mux_inst[j].get_pin("br_out").bc() - bl_out_offset = bl_offset - vector(0,(self.words_per_row+1)*self.m1_pitch) - br_out_offset = br_offset - vector(0,(self.words_per_row+2)*self.m1_pitch) + bl_out_offset = bl_offset - vector(0, (self.words_per_row + 1) * self.m1_pitch) + br_out_offset = br_offset - vector(0, (self.words_per_row + 2) * self.m1_pitch) - bl_out_offset_end = bl_out_offset + vector(0,self.route_height) - br_out_offset_end = br_out_offset + vector(0,self.route_height) + bl_out_offset_end = bl_out_offset + vector(0, self.route_height) + br_out_offset_end = br_out_offset + vector(0, self.route_height) if cell_properties.bitcell.mirror.y and j % 2: tmp_bl_out_end = br_out_offset_end @@ -208,21 +199,20 @@ class single_level_column_mux_array(design.design): else: dist = 0 - self.add_path("m1", [bl_out_offset, bl_out_offset+vector(width+dist,0)]) - self.add_path("m1", [br_out_offset, br_out_offset+vector(width-dist,0)]) + self.add_path("m1", [bl_out_offset, bl_out_offset + vector(width + dist, 0)]) + self.add_path("m1", [br_out_offset, br_out_offset + vector(width - dist, 0)]) # Extend the bitline output rails and gnd downward on the first bit of each n-way mux - self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j/self.words_per_row)), + self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j / self.words_per_row)), layer="m2", start=bl_out_offset, end=tmp_bl_out_end) - self.add_layout_pin_segment_center(text="br_out_{}".format(int(j/self.words_per_row)), + self.add_layout_pin_segment_center(text="br_out_{}".format(int(j / self.words_per_row)), layer="m2", start=br_out_offset, end=tmp_br_out_end) - - # This via is on the right of the wire + # This via is on the right of the wire self.add_via_center(layers=self.m1_stack, offset=bl_out_offset) @@ -231,20 +221,19 @@ class single_level_column_mux_array(design.design): offset=br_out_offset) else: - - self.add_path("m2", [ bl_out_offset, tmp_bl_out_end]) - self.add_path("m2", [ br_out_offset, tmp_br_out_end]) + self.add_path("m2", [bl_out_offset, tmp_bl_out_end]) + self.add_path("m2", [br_out_offset, tmp_br_out_end]) # This via is on the right of the wire self.add_via_center(layers=self.m1_stack, offset=bl_out_offset) - # This via is on the left of the wire + # This via is on the left of the wire self.add_via_center(layers=self.m1_stack, offset=br_out_offset) def get_drain_cin(self): """Get the relative capacitance of the drain of the NMOS pass TX""" from tech import parameter - #Bitcell drain load being used to estimate mux NMOS drain load + # Bitcell drain load being used to estimate mux NMOS drain load drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap']) - return drain_load + return drain_load From 8c177f9947e6c1f98977cad5b8a6ab87ddfa0ea7 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 20 Apr 2020 15:03:32 -0700 Subject: [PATCH 282/521] Split col mux test --- ...4_single_level_column_mux_pbitcell_test.py | 49 +++++++++++++++++++ .../tests/04_single_level_column_mux_test.py | 16 ------ compiler/tests/18_port_data_1rw_1r_test.py | 2 +- 3 files changed, 50 insertions(+), 17 deletions(-) create mode 100755 compiler/tests/04_single_level_column_mux_pbitcell_test.py diff --git a/compiler/tests/04_single_level_column_mux_pbitcell_test.py b/compiler/tests/04_single_level_column_mux_pbitcell_test.py new file mode 100755 index 00000000..6fe55736 --- /dev/null +++ b/compiler/tests/04_single_level_column_mux_pbitcell_test.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +#@unittest.skip("SKIPPING 04_driver_test") + +class single_level_column_mux_pbitcell_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check single level column mux in multi-port + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + factory.reset() + debug.info(2, "Checking column mux for pbitcell (innermost connections)") + tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + factory.reset() + debug.info(2, "Checking column mux for pbitcell (outermost connections)") + tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index de5870fc..9f1d03f9 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -28,22 +28,6 @@ class single_level_column_mux_test(openram_test): tx = factory.create(module_type="single_level_column_mux", tx_size=8) self.local_check(tx) - # check single level column mux in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - - factory.reset() - debug.info(2, "Checking column mux for pbitcell (innermost connections)") - tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(tx) - - factory.reset() - debug.info(2, "Checking column mux for pbitcell (outermost connections)") - tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(tx) - globals.end_openram() # run the test from the command line diff --git a/compiler/tests/18_port_data_1rw_1r_test.py b/compiler/tests/18_port_data_1rw_1r_test.py index 3e1dbded..6201de6a 100755 --- a/compiler/tests/18_port_data_1rw_1r_test.py +++ b/compiler/tests/18_port_data_1rw_1r_test.py @@ -13,7 +13,7 @@ from globals import OPTS from sram_factory import factory import debug -class port_data_test(openram_test): +class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) From dfbf6fe45c4115ec79b96a9880433c51ac1ca770 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 20 Apr 2020 15:33:53 -0700 Subject: [PATCH 283/521] Default is to use preferred layer directions --- compiler/base/hierarchy_layout.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 3cf3e727..b970666d 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1127,13 +1127,13 @@ class layout(): self.horizontal_pitch) offset += vector(0, self.horizontal_pitch) - def create_vertical_channel_route(self, netlist, offset, layer_stack, layer_dirs): + def create_vertical_channel_route(self, netlist, offset, layer_stack, layer_dirs=None): """ Wrapper to create a vertical channel route """ self.create_channel_route(netlist, offset, layer_stack, layer_dirs, vertical=True) - def create_horizontal_channel_route(self, netlist, offset, layer_stack, layer_dirs): + def create_horizontal_channel_route(self, netlist, offset, layer_stack, layer_dirs=None): """ Wrapper to create a horizontal channel route """ From f6135f34711e755ab80c6a3891506a3fc8e380f0 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 20 Apr 2020 16:38:30 -0700 Subject: [PATCH 284/521] PEP8 formatting --- compiler/modules/dff_buf_array.py | 96 +++++++++++++++---------------- 1 file changed, 46 insertions(+), 50 deletions(-) diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 1735a7a1..f95bf576 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -7,13 +7,12 @@ # import debug import design -from tech import drc from tech import cell_properties as props -from math import log from vector import vector from globals import OPTS from sram_factory import factory + class dff_buf_array(design.design): """ This is a simple row (or multiple rows) of flops. @@ -54,13 +53,13 @@ class dff_buf_array(design.design): self.DRC_LVS() def add_pins(self): - for row in range(self.rows): + for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_din_name(row,col), "INPUT") - for row in range(self.rows): + self.add_pin(self.get_din_name(row, col), "INPUT") + for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_dout_name(row,col), "OUTPUT") - self.add_pin(self.get_dout_bar_name(row,col), "OUTPUT") + self.add_pin(self.get_dout_name(row, col), "OUTPUT") + self.add_pin(self.get_dout_bar_name(row, col), "OUTPUT") self.add_pin("clk", "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -75,17 +74,16 @@ class dff_buf_array(design.design): inv2_size=self.inv2_size) self.add_mod(self.dff) - def create_dff_array(self): self.dff_insts={} - for row in range(self.rows): + for row in range(self.rows): for col in range(self.columns): - name = "dff_r{0}_c{1}".format(row,col) - self.dff_insts[row,col]=self.add_inst(name=name, - mod=self.dff) - inst_ports = [self.get_din_name(row,col), - self.get_dout_name(row,col), - self.get_dout_bar_name(row,col), + name = "dff_r{0}_c{1}".format(row, col) + self.dff_insts[row, col]=self.add_inst(name=name, + mod=self.dff) + inst_ports = [self.get_din_name(row, col), + self.get_dout_name(row, col), + self.get_dout_bar_name(row, col), "clk", "vdd", "gnd"] @@ -102,17 +100,17 @@ class dff_buf_array(design.design): dff_pitch = self.dff.width + well_spacing + self.well_extend_active - for row in range(self.rows): + for row in range(self.rows): for col in range(self.columns): - name = "Xdff_r{0}_c{1}".format(row,col) + name = "Xdff_r{0}_c{1}".format(row, col) if (row % 2 == 0): - base = vector(col*dff_pitch,row*self.dff.height) + base = vector(col * dff_pitch, row * self.dff.height) mirror = "R0" else: - base = vector(col*dff_pitch,(row+1)*self.dff.height) + base = vector(col * dff_pitch, (row + 1) * self.dff.height) mirror = "MX" - self.dff_insts[row,col].place(offset=base, - mirror=mirror) + self.dff_insts[row, col].place(offset=base, + mirror=mirror) def get_din_name(self, row, col): if self.columns == 1: @@ -120,7 +118,7 @@ class dff_buf_array(design.design): elif self.rows == 1: din_name = "din_{0}".format(col) else: - din_name = "din_{0}_{1}".format(row,col) + din_name = "din_{0}_{1}".format(row, col) return din_name @@ -130,7 +128,7 @@ class dff_buf_array(design.design): elif self.rows == 1: dout_name = "dout_{0}".format(col) else: - dout_name = "dout_{0}_{1}".format(row,col) + dout_name = "dout_{0}_{1}".format(row, col) return dout_name @@ -140,75 +138,73 @@ class dff_buf_array(design.design): elif self.rows == 1: dout_bar_name = "dout_bar_{0}".format(col) else: - dout_bar_name = "dout_bar_{0}_{1}".format(row,col) + dout_bar_name = "dout_bar_{0}_{1}".format(row, col) return dout_bar_name def add_layout_pins(self): for row in range(self.rows): - for col in range(self.columns): + for col in range(self.columns): # Continous vdd rail along with label. - vdd_pin=self.dff_insts[row,col].get_pin("vdd") + vdd_pin=self.dff_insts[row, col].get_pin("vdd") self.add_power_pin("vdd", vdd_pin.lc()) # Continous gnd rail along with label. - gnd_pin=self.dff_insts[row,col].get_pin("gnd") + gnd_pin=self.dff_insts[row, col].get_pin("gnd") self.add_power_pin("gnd", gnd_pin.lc()) - - for row in range(self.rows): - for col in range(self.columns): - din_pin = self.dff_insts[row,col].get_pin("D") - debug.check(din_pin.layer=="m2","DFF D pin not on metal2") - self.add_layout_pin(text=self.get_din_name(row,col), + for row in range(self.rows): + for col in range(self.columns): + din_pin = self.dff_insts[row, col].get_pin("D") + debug.check(din_pin.layer=="m2", "DFF D pin not on metal2") + self.add_layout_pin(text=self.get_din_name(row, col), layer=din_pin.layer, offset=din_pin.ll(), width=din_pin.width(), height=din_pin.height()) - dout_pin = self.dff_insts[row,col].get_pin("Q") - debug.check(dout_pin.layer=="m2","DFF Q pin not on metal2") - self.add_layout_pin(text=self.get_dout_name(row,col), + dout_pin = self.dff_insts[row, col].get_pin("Q") + debug.check(dout_pin.layer=="m2", "DFF Q pin not on metal2") + self.add_layout_pin(text=self.get_dout_name(row, col), layer=dout_pin.layer, offset=dout_pin.ll(), width=dout_pin.width(), height=dout_pin.height()) - dout_bar_pin = self.dff_insts[row,col].get_pin("Qb") - debug.check(dout_bar_pin.layer=="m2","DFF Qb pin not on metal2") - self.add_layout_pin(text=self.get_dout_bar_name(row,col), + dout_bar_pin = self.dff_insts[row, col].get_pin("Qb") + debug.check(dout_bar_pin.layer=="m2", "DFF Qb pin not on metal2") + self.add_layout_pin(text=self.get_dout_bar_name(row, col), layer=dout_bar_pin.layer, offset=dout_bar_pin.ll(), width=dout_bar_pin.width(), height=dout_bar_pin.height()) - # Create vertical spines to a single horizontal rail - clk_pin = self.dff_insts[0,0].get_pin("clk") - clk_ypos = 2*self.m3_pitch+self.m3_width - debug.check(clk_pin.layer=="m2","DFF clk pin not on metal2") + clk_pin = self.dff_insts[0, 0].get_pin("clk") + clk_ypos = 2 * self.m3_pitch + self.m3_width + debug.check(clk_pin.layer=="m2", "DFF clk pin not on metal2") if self.columns==1: self.add_layout_pin(text="clk", layer="m2", - offset=clk_pin.ll().scale(1,0), + offset=clk_pin.ll().scale(1, 0), width=self.m2_width, height=self.height) else: self.add_layout_pin_segment_center(text="clk", - layer="m3", - start=vector(0,clk_ypos), - end=vector(self.width,clk_ypos)) + layer="m3", + start=vector(0, clk_ypos), + end=vector(self.width, clk_ypos)) for col in range(self.columns): - clk_pin = self.dff_insts[0,col].get_pin("clk") + clk_pin = self.dff_insts[0, col].get_pin("clk") # Make a vertical strip for each column self.add_rect(layer="m2", - offset=clk_pin.ll().scale(1,0), + offset=clk_pin.ll().scale(1, 0), width=self.m2_width, height=self.height) # Drop a via to the M3 pin self.add_via_center(layers=self.m2_stack, - offset=vector(clk_pin.cx(),clk_ypos)) + offset=vector(clk_pin.cx(), clk_ypos)) def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" From 63bea67fb5700f5a7110ceab4faae542e07d00e5 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Mon, 20 Apr 2020 20:22:46 -0700 Subject: [PATCH 285/521] col_mux.py changes --- compiler/pgates/single_level_column_mux.py | 86 ++++++++++++---------- 1 file changed, 47 insertions(+), 39 deletions(-) diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 90645326..9d21211e 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -7,7 +7,7 @@ # import pgate import debug -from tech import drc +from tech import drc, layer from vector import vector from sram_factory import factory import logical_effort @@ -22,13 +22,13 @@ class single_level_column_mux(pgate.pgate): for optimal speed """ def __init__(self, name, tx_size=8, bitcell_bl="bl", bitcell_br="br"): - + debug.info(2, "creating single column mux cell: {0}".format(name)) self.tx_size = int(tx_size) self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br - + pgate.pgate.__init__(self, name) def get_bl_names(self): @@ -41,9 +41,9 @@ class single_level_column_mux(pgate.pgate): self.add_modules() self.add_pins() self.add_ptx() - + def create_layout(self): - + self.pin_height = 2 * self.m2_width self.width = self.bitcell.width self.height = self.nmos_upper.uy() + self.pin_height @@ -59,39 +59,42 @@ class single_level_column_mux(pgate.pgate): self.ptx_width = self.tx_size * drc("minwidth_tx") self.nmos = factory.create(module_type="ptx", width=self.ptx_width) self.add_mod(self.nmos) - + def add_pins(self): self.add_pin_list(["bl", "br", "bl_out", "br_out", "sel", "gnd"]) def add_bitline_pins(self): """ Add the top and bottom pins to this cell """ - bl_pos = vector(self.bitcell.get_pin(self.bitcell_bl).lx(), 0) - br_pos = vector(self.bitcell.get_pin(self.bitcell_br).lx(), 0) + bl_pin=self.bitcell.get_pin(self.bitcell_bl) + br_pin=self.bitcell.get_pin(self.bitcell_br) + + bl_pos = vector(bl_pin.lx(), 0) + br_pos = vector(br_pin.lx(), 0) # bl and br self.add_layout_pin(text="bl", - layer="m2", + layer=bl_pin.layer, offset=bl_pos + vector(0, self.height - self.pin_height), height=self.pin_height) self.add_layout_pin(text="br", - layer="m2", + layer=br_pin.layer, offset=br_pos + vector(0, self.height - self.pin_height), height=self.pin_height) - + # bl_out and br_out self.add_layout_pin(text="bl_out", - layer="m2", + layer=bl_pin.layer, offset=bl_pos, height=self.pin_height) self.add_layout_pin(text="br_out", - layer="m2", + layer=br_pin.layer, offset=br_pos, height=self.pin_height) def add_ptx(self): """ Create the two pass gate NMOS transistors to switch the bitlines""" - + # Space it in the center nmos_lower_position = self.nmos.active_offset.scale(0,1) \ + vector(0.5 * self.bitcell.width- 0.5 * self.nmos.active_width, 0) @@ -102,7 +105,7 @@ class single_level_column_mux(pgate.pgate): # This aligns it directly above the other tx with gates abutting nmos_upper_position = nmos_lower_position \ - + vector(0, self.nmos.active_height + self.poly_space) + + vector(0, self.nmos.active_height + self.active_space) self.nmos_upper = self.add_inst(name="mux_tx2", mod=self.nmos, offset=nmos_upper_position) @@ -110,12 +113,11 @@ class single_level_column_mux(pgate.pgate): def connect_poly(self): """ Connect the poly gate of the two pass transistors """ - - height = self.nmos_upper.get_pin("G").uy() - self.nmos_lower.get_pin("G").by() + self.add_layout_pin(text="sel", layer="poly", - offset=self.nmos_lower.get_pin("G").ll(), - height=height) + offset=self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active), + height=self.active_space) def connect_bitlines(self): """ Connect the bitlines to the mux transistors """ @@ -131,36 +133,42 @@ class single_level_column_mux(pgate.pgate): nmos_upper_s_pin = self.nmos_upper.get_pin("S") nmos_upper_d_pin = self.nmos_upper.get_pin("D") + # If li exists, use li and m1 for the mux, otherwise use m1 and m2 + if "li" in layer: + col_mux_stack = self.li_stack + else: + col_mux_stack = self.m1_stack + # Add vias to bl, br_out, nmos_upper/S, nmos_lower/D - self.add_via_center(layers=self.m1_stack, + self.add_via_center(layers=col_mux_stack, offset=bl_pin.bc(), directions=("V", "V")) - self.add_via_center(layers=self.m1_stack, + self.add_via_center(layers=col_mux_stack, offset=br_out_pin.uc(), directions=("V", "V")) - self.add_via_center(layers=self.m1_stack, + self.add_via_center(layers=col_mux_stack, offset=nmos_upper_s_pin.center(), directions=("V", "V")) - self.add_via_center(layers=self.m1_stack, + self.add_via_center(layers=col_mux_stack, offset=nmos_lower_d_pin.center(), directions=("V", "V")) - + # bl -> nmos_upper/D on metal1 # bl_out -> nmos_upper/S on metal2 - self.add_path("m1", + self.add_path(col_mux_stack[0], [bl_pin.ll(), vector(nmos_upper_d_pin.cx(), bl_pin.by()), nmos_upper_d_pin.center()]) # halfway up, move over mid1 = bl_out_pin.uc().scale(1, 0.4) \ + nmos_upper_s_pin.bc().scale(0, 0.4) mid2 = bl_out_pin.uc().scale(0, 0.4) \ - + nmos_upper_s_pin.bc().scale(1, 0.4) - self.add_path("m2", - [bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.bc()]) - + + nmos_upper_s_pin.bc().scale(1, 0.4) + self.add_path(col_mux_stack[2], + [bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.center()]) + # br -> nmos_lower/D on metal2 # br_out -> nmos_lower/S on metal1 - self.add_path("m1", + self.add_path(col_mux_stack[0], [br_out_pin.uc(), vector(nmos_lower_s_pin.cx(), br_out_pin.uy()), nmos_lower_s_pin.center()]) @@ -169,9 +177,9 @@ class single_level_column_mux(pgate.pgate): + nmos_lower_d_pin.uc().scale(0,0.5) mid2 = br_pin.bc().scale(0,0.5) \ + nmos_lower_d_pin.uc().scale(1,0.5) - self.add_path("m2", - [br_pin.bc(), mid1, mid2, nmos_lower_d_pin.uc()]) - + self.add_path(col_mux_stack[2], + [br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()]) + def add_wells(self): """ Add a well and implant over the whole cell. Also, add the @@ -192,11 +200,12 @@ class single_level_column_mux(pgate.pgate): start_layer="m1") # Add well enclosure over all the tx and contact - self.add_rect(layer="pwell", - offset=vector(0, 0), - width=self.bitcell.width, - height=self.height) - + if "pwell" in layer: + self.add_rect(layer="pwell", + offset=vector(0, 0), + width=self.bitcell.width, + height=self.height) + def get_stage_effort(self, corner, slew, load): """ Returns relative delay that the column mux. @@ -211,4 +220,3 @@ class single_level_column_mux(pgate.pgate): load, parasitic_delay, False) - From 829f3e03fa08da37cfdfb22d01018237bbe753f5 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Mon, 20 Apr 2020 22:08:29 -0700 Subject: [PATCH 286/521] col_mux.py update with correct contacts --- compiler/pgates/single_level_column_mux.py | 29 +++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 9d21211e..e84469db 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -57,7 +57,10 @@ class single_level_column_mux(pgate.pgate): # Adds nmos_lower,nmos_upper to the module self.ptx_width = self.tx_size * drc("minwidth_tx") - self.nmos = factory.create(module_type="ptx", width=self.ptx_width) + self.nmos = factory.create(module_type="ptx", + width=self.ptx_width, + add_source_contact=False, + add_drain_contact=False) self.add_mod(self.nmos) def add_pins(self): @@ -153,6 +156,30 @@ class single_level_column_mux(pgate.pgate): offset=nmos_lower_d_pin.center(), directions=("V", "V")) + # Add diffusion contacts + # These were previously omitted with the options: add_source_contact=False, add_drain_contact=False + # They are added now and not previously due to a s8 tech special case in which the contacts intersected the mux intraconnect + self.add_via_center(layers=self.active_stack, + offset=nmos_upper_d_pin.center(), + directions=("V", "V"), + implant_type="n", + well_type="nwell") + self.add_via_center(layers=self.active_stack, + offset=nmos_lower_s_pin.center(), + directions=("V", "V"), + implant_type="n", + well_type="nwell") + self.add_via_center(layers=self.active_stack, + offset=nmos_upper_s_pin.center(), + directions=("V", "V"), + implant_type="n", + well_type="nwell") + self.add_via_center(layers=self.active_stack, + offset=nmos_lower_d_pin.center(), + directions=("V", "V"), + implant_type="n", + well_type="nwell") + # bl -> nmos_upper/D on metal1 # bl_out -> nmos_upper/S on metal2 self.add_path(col_mux_stack[0], From ab91d0ab1d86afb4d9f73b22c613cbe6cc7c0853 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 21 Apr 2020 15:20:30 -0700 Subject: [PATCH 287/521] Add purpose to string output --- compiler/base/geometry.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 5d7f8d76..cfcfa73a 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -296,11 +296,11 @@ class path(geometry): def __str__(self): """ override print function output """ - return "path: layer=" + self.layerNumber + " w=" + self.width + return "path: layer=" + self.layerNumber + " purpose=" + str(self.layerPurpose) + " w=" + self.width def __repr__(self): """ override print function output """ - return "( path: layer=" + self.layerNumber + " w=" + self.width + " coords=" + str(self.coordinates) + " )" + return "( path: layer=" + self.layerNumber + " purpose=" + str(self.layerPurpose) + " w=" + self.width + " coords=" + str(self.coordinates) + " )" class label(geometry): @@ -340,11 +340,11 @@ class label(geometry): def __str__(self): """ override print function output """ - return "label: " + self.text + " layer=" + str(self.layerNumber) + return "label: " + self.text + " layer=" + str(self.layerNumber) + " purpose=" + str(self.layerPurpose) def __repr__(self): """ override print function output """ - return "( label: " + self.text + " @" + str(self.offset) + " layer=" + str(self.layerNumber) + " )" + return "( label: " + self.text + " @" + str(self.offset) + " layer=" + str(self.layerNumber) + " purpose=" + str(self.layerPurpose) + " )" class rectangle(geometry): @@ -391,4 +391,4 @@ class rectangle(geometry): def __repr__(self): """ override print function output """ - return "( rect: @" + str(self.offset) + " WxH=" + str(self.width) + "x" + str(self.height) + " layer=" + str(self.layerNumber) + " )" + return "( rect: @" + str(self.offset) + " WxH=" + str(self.width) + "x" + str(self.height) + " layer=" + str(self.layerNumber) + " purpose=" + str(self.layerPurpose) + " )" From 5f76514cf09844936e3929106cc089c3317e1f9c Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 21 Apr 2020 15:20:51 -0700 Subject: [PATCH 288/521] Remove end of line whitespace --- technology/scn4m_subm/tech/tech.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 7c360d38..d8384d7f 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -89,7 +89,7 @@ power_grid = m3_stack ################################################### # create the GDS layer map -layer={} +layer={} layer["pwell"] = (41, 0) layer["nwell"] = (42, 0) layer["active"] = (43, 0) @@ -98,9 +98,9 @@ layer["nimplant"] = (45, 0) layer["poly"] = (46, 0) layer["poly_contact"] = (47, 0) layer["active_contact"] = (48, 0) -layer["m1"] = (49, 0) +layer["m1"] = (49, 0) layer["via1"] = (50, 0) -layer["m2"] = (51, 0) +layer["m2"] = (51, 0) layer["via2"] = (61, 0) layer["m3"] = (62, 0) layer["via3"] = (30, 0) From cd66ddb37c9af43e56a679aadb3ff0b1805d92d1 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 21 Apr 2020 15:21:29 -0700 Subject: [PATCH 289/521] Add supply rails to dff array. PEP8 cleanup. --- compiler/modules/dff_buf.py | 33 +++++++++++++++--------------- compiler/modules/dff_buf_array.py | 34 +++++++++++++++++++++++++------ 2 files changed, 44 insertions(+), 23 deletions(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index c30f15b6..500767d8 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -35,7 +35,7 @@ class dff_buf(design.design): # This causes a DRC in the pinv which assumes min width rails. This ensures the output # contact does not violate spacing to the rail in the NMOS. debug.check(inv1_size>=2, "Inverter must be greater than two for rail spacing DRC rules.") - debug.check(inv2_size>=2, "Inverter must be greater than two for rail spacing DRC rules.") + debug.check(inv2_size>=2, "Inverter must be greater than two for rail spacing DRC rules.") self.inv1_size=inv1_size self.inv2_size=inv2_size @@ -52,14 +52,13 @@ class dff_buf(design.design): def create_layout(self): self.place_instances() self.width = self.inv2_inst.rx() + self.height = self.dff.height - - self.route_wires() self.add_layout_pins() self.add_boundary() self.DRC_LVS() - + def add_modules(self): self.dff = factory.create(module_type="dff") self.add_mod(self.dff) @@ -73,8 +72,6 @@ class dff_buf(design.design): size=self.inv2_size, height=self.dff.height) self.add_mod(self.inv2) - - def add_pins(self): self.add_pin("D", "INPUT") @@ -96,17 +93,19 @@ class dff_buf(design.design): self.inv1_inst=self.add_inst(name="dff_buf_inv1", mod=self.inv1) - self.connect_inst(["qint", "Qb", "vdd", "gnd"]) + self.connect_inst(["qint", "Qb", "vdd", "gnd"]) self.inv2_inst=self.add_inst(name="dff_buf_inv2", mod=self.inv2) - self.connect_inst(["Qb", "Q", "vdd", "gnd"]) + self.connect_inst(["Qb", "Q", "vdd", "gnd"]) def place_instances(self): # Add the DFF - self.dff_inst.place(vector(0,0)) + self.dff_inst.place(vector(0, 0)) # Add INV1 to the right + # The INV needs well spacing because the DFF is likely from a library + # with different well construction rules well_spacing = 0 try: well_spacing = max(well_spacing, self.nwell_space) @@ -129,7 +128,7 @@ class dff_buf(design.design): # Route dff q to inv1 a q_pin = self.dff_inst.get_pin("Q") a1_pin = self.inv1_inst.get_pin("A") - mid_x_offset = 0.5*(a1_pin.cx() + q_pin.cx()) + mid_x_offset = 0.5 * (a1_pin.cx() + q_pin.cx()) mid1 = vector(mid_x_offset, q_pin.cy()) mid2 = vector(mid_x_offset, a1_pin.cy()) self.add_path("m3", [q_pin.center(), mid1, mid2, a1_pin.center()]) @@ -143,7 +142,7 @@ class dff_buf(design.design): # Route inv1 z to inv2 a z1_pin = self.inv1_inst.get_pin("Z") a2_pin = self.inv2_inst.get_pin("A") - mid_x_offset = 0.5*(z1_pin.cx() + a2_pin.cx()) + mid_x_offset = 0.5 * (z1_pin.cx() + a2_pin.cx()) self.mid_qb_pos = vector(mid_x_offset, z1_pin.cy()) mid2 = vector(mid_x_offset, a2_pin.cy()) self.add_path("m1", [z1_pin.center(), self.mid_qb_pos, mid2, a2_pin.center()]) @@ -181,8 +180,8 @@ class dff_buf(design.design): height=din_pin.height()) dout_pin = self.inv2_inst.get_pin("Z") - mid_pos = dout_pin.center() + vector(self.m1_pitch,0) - q_pos = mid_pos - vector(0,self.m2_pitch) + mid_pos = dout_pin.center() + vector(self.m1_pitch, 0) + q_pos = mid_pos - vector(0, self.m2_pitch) self.add_layout_pin_rect_center(text="Q", layer="m2", offset=q_pos) @@ -190,7 +189,7 @@ class dff_buf(design.design): self.add_via_center(layers=self.m1_stack, offset=q_pos) - qb_pos = self.mid_qb_pos + vector(0,self.m2_pitch) + qb_pos = self.mid_qb_pos + vector(0, self.m2_pitch) self.add_layout_pin_rect_center(text="Qb", layer="m2", offset=qb_pos) @@ -200,7 +199,7 @@ class dff_buf(design.design): def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" - #This is a handmade cell so the value must be entered in the tech.py file or estimated. - #Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width. - #FIXME: Dff changed in a past commit. The parameter need to be updated. + # This is a handmade cell so the value must be entered in the tech.py file or estimated. + # Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width. + # FIXME: Dff changed in a past commit. The parameter need to be updated. return parameter["dff_clk_cin"] diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index f95bf576..b608cdeb 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -48,6 +48,7 @@ class dff_buf_array(design.design): self.width = self.columns * self.dff.width self.height = self.rows * self.dff.height self.place_dff_array() + self.route_supplies() self.add_layout_pins() self.add_boundary() self.DRC_LVS() @@ -94,15 +95,25 @@ class dff_buf_array(design.design): def place_dff_array(self): - well_spacing = max(self.nwell_space, - self.pwell_space, - self.pwell_to_nwell) + well_spacing = 0 + try: + well_spacing = max(self.nwell_space, well_spacing) + except AttributeError: + pass + try: + well_spacing = max(self.pwell_space, well_spacing) + except AttributeError: + pass + try: + well_spacing = max(self.pwell_to_nwell, well_spacing) + except AttributeError: + pass dff_pitch = self.dff.width + well_spacing + self.well_extend_active for row in range(self.rows): for col in range(self.columns): - name = "Xdff_r{0}_c{1}".format(row, col) + # name = "Xdff_r{0}_c{1}".format(row, col) if (row % 2 == 0): base = vector(col * dff_pitch, row * self.dff.height) mirror = "R0" @@ -141,8 +152,17 @@ class dff_buf_array(design.design): dout_bar_name = "dout_bar_{0}_{1}".format(row, col) return dout_bar_name - - def add_layout_pins(self): + + def route_supplies(self): + for row in range(self.rows): + vdd0_pin=self.dff_insts[row, 0].get_pin("vdd") + vddn_pin=self.dff_insts[row, self.columns - 1].get_pin("vdd") + self.add_path(vdd0_pin.layer, [vdd0_pin.lc(), vddn_pin.rc()], width=vdd0_pin.height()) + + gnd0_pin=self.dff_insts[row, 0].get_pin("gnd") + gndn_pin=self.dff_insts[row, self.columns - 1].get_pin("gnd") + self.add_path(gnd0_pin.layer, [gnd0_pin.lc(), gndn_pin.rc()], width=gnd0_pin.height()) + for row in range(self.rows): for col in range(self.columns): # Continous vdd rail along with label. @@ -152,6 +172,8 @@ class dff_buf_array(design.design): # Continous gnd rail along with label. gnd_pin=self.dff_insts[row, col].get_pin("gnd") self.add_power_pin("gnd", gnd_pin.lc()) + + def add_layout_pins(self): for row in range(self.rows): for col in range(self.columns): From fc85dfe29fd27b02b19a3c6d37631297abf6bf5b Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 21 Apr 2020 15:21:57 -0700 Subject: [PATCH 290/521] Add boundary to all pgates --- compiler/pgates/pand2.py | 1 + compiler/pgates/pand3.py | 1 + compiler/pgates/pbuf.py | 1 + compiler/pgates/pdriver.py | 1 + compiler/pgates/pinv.py | 1 + compiler/pgates/pinvbuf.py | 1 + compiler/pgates/pnand2.py | 3 ++- compiler/pgates/pnand3.py | 1 + compiler/pgates/pnor2.py | 1 + compiler/pgates/precharge.py | 3 ++- compiler/pgates/ptristate_inv.py | 1 + compiler/pgates/pwrite_driver.py | 1 + 12 files changed, 14 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 23fd5e5b..995296b6 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -45,6 +45,7 @@ class pand2(pgate.pgate): self.place_insts() self.add_wires() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index dd1d87f7..f8cc2ac3 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -44,6 +44,7 @@ class pand3(pgate.pgate): self.place_insts() self.add_wires() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 3171324b..6f9719eb 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -37,6 +37,7 @@ class pbuf(pgate.pgate): self.place_insts() self.add_wires() self.add_layout_pins() + self.add_boundary() def add_pins(self): self.add_pin("A", "INPUT") diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 5aa5393e..4bf654a4 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -76,6 +76,7 @@ class pdriver(pgate.pgate): self.width = self.inv_inst_list[-1].rx() self.height = self.inv_inst_list[0].height + self.add_boundary() def add_pins(self): self.add_pin("A", "INPUT") diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 3ec3e23e..d5a26a7a 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -64,6 +64,7 @@ class pinv(pgate.pgate): "A", position="farleft") self.route_outputs() + self.add_boundary() def add_pins(self): """ Adds pins for spice netlist """ diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index b8ecb3bf..fe376bc4 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -47,6 +47,7 @@ class pinvbuf(pgate.pgate): self.place_modules() self.route_wires() self.add_layout_pins() + self.add_boundary() self.offset_all_coordinates() diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 2f21c0bb..8398abbc 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -57,7 +57,8 @@ class pnand2(pgate.pgate): self.extend_wells() self.route_inputs() self.route_output() - + self.add_boundary() + def add_pins(self): """ Adds pins for spice netlist """ pin_list = ["A", "B", "Z", "vdd", "gnd"] diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 83e57c0a..fd563145 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -67,6 +67,7 @@ class pnand3(pgate.pgate): self.extend_wells() self.route_inputs() self.route_output() + self.add_boundary() def add_ptx(self): """ Create the PMOS and NMOS transistors. """ diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 75840f26..9dbc0c52 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -56,6 +56,7 @@ class pnor2(pgate.pgate): self.extend_wells() self.route_inputs() self.route_output() + self.add_boundary() def add_pins(self): """ Adds pins for spice netlist """ diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index afe14a05..7adec605 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -68,7 +68,8 @@ class precharge(design.design): self.route_vdd_rail() self.route_bitlines() self.connect_to_bitlines() - + self.add_boundary() + def add_pins(self): self.add_pin_list(["bl", "br", "en_bar", "vdd"], ["OUTPUT", "OUTPUT", "INPUT", "POWER"]) diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index 9586e72b..22f6b164 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -56,6 +56,7 @@ class ptristate_inv(pgate.pgate): self.connect_rails() self.route_inputs() self.route_outputs() + self.add_boundary() def add_pins(self): """ Adds pins for spice netlist """ diff --git a/compiler/pgates/pwrite_driver.py b/compiler/pgates/pwrite_driver.py index 16830e62..da5eacdc 100644 --- a/compiler/pgates/pwrite_driver.py +++ b/compiler/pgates/pwrite_driver.py @@ -52,6 +52,7 @@ class pwrite_driver(design.design): self.place_modules() self.route_wires() self.route_supplies() + self.add_boundary() def add_pins(self): self.add_pin("din", "INPUT") From 0f6998a1c5dca33abb6b0604b84709688d0ae6bf Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 21 Apr 2020 15:36:38 -0700 Subject: [PATCH 291/521] PEP8 cleanup --- compiler/modules/delay_chain.py | 72 +++++++++++++++------------------ 1 file changed, 33 insertions(+), 39 deletions(-) diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index a07576d4..4e421d0a 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -7,12 +7,11 @@ # import debug import design -from tech import drc -from contact import contact from vector import vector from globals import OPTS from sram_factory import factory + class delay_chain(design.design): """ Generate a delay chain with the given number of stages and fanout. @@ -28,7 +27,7 @@ class delay_chain(design.design): # Two fanouts are needed so that we can route the vdd/gnd connections for f in fanout_list: - debug.check(f>=2,"Must have >=2 fanouts for each stage.") + debug.check(f>=2, "Must have >=2 fanouts for each stage.") # number of inverters including any fanout loads. self.fanout_list = fanout_list @@ -36,7 +35,6 @@ class delay_chain(design.design): self.create_netlist() if not OPTS.netlist_only: self.create_layout() - def create_netlist(self): self.add_modules() @@ -45,9 +43,9 @@ class delay_chain(design.design): def create_layout(self): # Each stage is a a row - self.height = len(self.fanout_list)*self.inv.height + self.height = len(self.fanout_list) * self.inv.height # The width is determined by the largest fanout plus the driver - self.width = (max(self.fanout_list)+1) * self.inv.width + self.width = (max(self.fanout_list) + 1) * self.inv.width self.place_inverters() self.route_inverters() @@ -71,7 +69,7 @@ class delay_chain(design.design): self.driver_inst_list = [] self.rightest_load_inst = {} self.load_inst_map = {} - for stage_num,fanout_size in zip(range(len(self.fanout_list)),self.fanout_list): + for stage_num, fanout_size in zip(range(len(self.fanout_list)), self.fanout_list): # Add the inverter cur_driver=self.add_inst(name="dinv{}".format(stage_num), mod=self.inv) @@ -79,23 +77,23 @@ class delay_chain(design.design): self.driver_inst_list.append(cur_driver) # Hook up the driver - if stage_num+1==len(self.fanout_list): + if stage_num + 1 == len(self.fanout_list): stageout_name = "out" else: - stageout_name = "dout_{}".format(stage_num+1) + stageout_name = "dout_{}".format(stage_num + 1) if stage_num == 0: stagein_name = "in" else: - stagein_name = "dout_{}".format(stage_num) + stagein_name = "dout_{}".format(stage_num) self.connect_inst([stagein_name, stageout_name, "vdd", "gnd"]) # Now add the dummy loads to the right self.load_inst_map[cur_driver]=[] for i in range(fanout_size): - cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num,i), + cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num, i), mod=self.inv) # Fanout stage is always driven by driver and output is disconnected - disconnect_name = "n_{0}_{1}".format(stage_num,i) + disconnect_name = "n_{0}_{1}".format(stage_num, i) self.connect_inst([stageout_name, disconnect_name, "vdd", "gnd"]) # Keep track of all the loads to connect their inputs as a load @@ -106,13 +104,13 @@ class delay_chain(design.design): def place_inverters(self): """ Place the inverters and connect them based on the stage list """ - for stage_num,fanout_size in zip(range(len(self.fanout_list)),self.fanout_list): + for stage_num, fanout_size in zip(range(len(self.fanout_list)), self.fanout_list): if stage_num % 2: inv_mirror = "MX" - inv_offset = vector(0, (stage_num+1)* self.inv.height) + inv_offset = vector(0, (stage_num + 1) * self.inv.height) else: inv_mirror = "R0" - inv_offset = vector(0, stage_num * self.inv.height) + inv_offset = vector(0, stage_num * self.inv.height) # Add the inverter cur_driver=self.driver_inst_list[stage_num] @@ -122,10 +120,9 @@ class delay_chain(design.design): # Now add the dummy loads to the right load_list = self.load_inst_map[cur_driver] for i in range(fanout_size): - inv_offset += vector(self.inv.width,0) + inv_offset += vector(self.inv.width, 0) load_list[i].place(offset=inv_offset, mirror=inv_mirror) - def add_route(self, pin1, pin2): """ This guarantees that we route from the top to bottom row correctly. """ @@ -134,9 +131,9 @@ class delay_chain(design.design): if pin1_pos.y == pin2_pos.y: self.add_path("m2", [pin1_pos, pin2_pos]) else: - mid_point = vector(pin2_pos.x, 0.5*(pin1_pos.y+pin2_pos.y)) + mid_point = vector(pin2_pos.x, 0.5 * (pin1_pos.y + pin2_pos.y)) # Written this way to guarantee it goes right first if we are switching rows - self.add_path("m2", [pin1_pos, vector(pin1_pos.x,mid_point.y), mid_point, vector(mid_point.x,pin2_pos.y), pin2_pos]) + self.add_path("m2", [pin1_pos, vector(pin1_pos.x, mid_point.y), mid_point, vector(mid_point.x, pin2_pos.y), pin2_pos]) def route_inverters(self): """ Add metal routing for each of the fanout stages """ @@ -145,7 +142,7 @@ class delay_chain(design.design): inv = self.driver_inst_list[i] for load in self.load_inst_map[inv]: # Drop a via on each A pin - a_pin = load.get_pin("A") + a_pin = load.get_pin("A") self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) self.add_via_center(layers=self.m2_stack, @@ -161,19 +158,17 @@ class delay_chain(design.design): offset=z_pin.center()) self.add_via_center(layers=self.m2_stack, offset=z_pin.center()) - self.add_path("m3",[z_pin.center(), a_max.center()]) + self.add_path("m3", [z_pin.center(), a_max.center()]) - # Route Z to the A of the next stage - if i+1 < len(self.driver_inst_list): + if i + 1 < len(self.driver_inst_list): z_pin = inv.get_pin("Z") - next_inv = self.driver_inst_list[i+1] + next_inv = self.driver_inst_list[i + 1] next_a_pin = next_inv.get_pin("A") - y_mid = (z_pin.cy() + next_a_pin.cy())/2 + y_mid = (z_pin.cy() + next_a_pin.cy()) / 2 mid1_point = vector(z_pin.cx(), y_mid) mid2_point = vector(next_a_pin.cx(), y_mid) - self.add_path("m2",[z_pin.center(), mid1_point, mid2_point, next_a_pin.center()]) - + self.add_path("m2", [z_pin.center(), mid1_point, mid2_point, next_a_pin.center()]) def add_layout_pins(self): """ Add vdd and gnd rails and the input/output. Connect the gnd rails internally on @@ -184,7 +179,7 @@ class delay_chain(design.design): # The routing to connect the loads is over the first and last cells # We have an even number of drivers and must only do every other # supply rail - for i in range(0,len(self.driver_inst_list),2): + for i in range(0, len(self.driver_inst_list), 2): inv = self.driver_inst_list[i] for load in self.load_inst_map[inv]: if load==self.rightest_load_inst[inv]: @@ -202,43 +197,42 @@ class delay_chain(design.design): pin = load.get_pin(pin_name) self.add_power_pin(pin_name, pin.rc()) - # input is A pin of first inverter a_pin = self.driver_inst_list[0].get_pin("A") self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) self.add_layout_pin(text="in", layer="m2", - offset=a_pin.ll().scale(1,0), + offset=a_pin.ll().scale(1, 0), height=a_pin.cy()) - # output is A pin of last load inverter last_driver_inst = self.driver_inst_list[-1] a_pin = self.rightest_load_inst[last_driver_inst].get_pin("A") self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) - mid_point = vector(a_pin.cx()+3*self.m2_width,a_pin.cy()) - self.add_path("m2",[a_pin.center(), mid_point, mid_point.scale(1,0)]) + mid_point = vector(a_pin.cx() + 3 * self.m2_width, a_pin.cy()) + self.add_path("m2", [a_pin.center(), mid_point, mid_point.scale(1, 0)]) self.add_layout_pin_segment_center(text="out", layer="m2", start=mid_point, - end=mid_point.scale(1,0)) + end=mid_point.scale(1, 0)) def get_cin(self): """Get the enable input ralative capacitance""" - #Only 1 input to the delay chain which is connected to an inverter. + # Only 1 input to the delay chain which is connected to an inverter. dc_cin = self.inv.get_cin() - return dc_cin + return dc_cin def determine_delayed_en_stage_efforts(self, ext_delayed_en_cout, inp_is_rise=True): """Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load.""" stage_effort_list = [] - #Add a stage to the list for every stage in delay chain. Stages only differ in fanout except the last which has an external cout. + # Add a stage to the list for every stage in delay chain. + # Stages only differ in fanout except the last which has an external cout. last_stage_is_rise = inp_is_rise for stage_fanout in self.fanout_list: - stage_cout = self.inv.get_cin()*(stage_fanout+1) - if len(stage_effort_list) == len(self.fanout_list)-1: #last stage + stage_cout = self.inv.get_cin() * (stage_fanout + 1) + if len(stage_effort_list) == len(self.fanout_list) - 1: stage_cout+=ext_delayed_en_cout stage = self.inv.get_stage_effort(stage_cout, last_stage_is_rise) stage_effort_list.append(stage) From 3d4a40b338f2cc196cb48f780e15b776db5b3e4c Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Tue, 21 Apr 2020 15:38:19 -0700 Subject: [PATCH 292/521] freepdk45 col_mux fix --- compiler/pgates/single_level_column_mux.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index e84469db..288894aa 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -108,7 +108,7 @@ class single_level_column_mux(pgate.pgate): # This aligns it directly above the other tx with gates abutting nmos_upper_position = nmos_lower_position \ - + vector(0, self.nmos.active_height + self.active_space) + + vector(0, self.nmos.active_height + max(self.active_space,self.poly_space)) self.nmos_upper = self.add_inst(name="mux_tx2", mod=self.nmos, offset=nmos_upper_position) @@ -117,10 +117,14 @@ class single_level_column_mux(pgate.pgate): def connect_poly(self): """ Connect the poly gate of the two pass transistors """ + # offset is the top of the lower nmos' diffusion + # height is the distance between the nmos' diffusions, which depends on max(self.active_space,self.poly_space) + offset = self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active) + height = self.nmos_upper.get_pin("G").by() + self.poly_extend_active - offset.y self.add_layout_pin(text="sel", layer="poly", - offset=self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active), - height=self.active_space) + offset=offset, + height=height) def connect_bitlines(self): """ Connect the bitlines to the mux transistors """ From f1c1adc9bd0aeac481d8cf011ad018971b469c6e Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 21 Apr 2020 16:12:54 -0700 Subject: [PATCH 293/521] Simplify supply contacts in delay chain. --- compiler/modules/delay_chain.py | 42 ++++++++++++--------------------- 1 file changed, 15 insertions(+), 27 deletions(-) diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index 4e421d0a..b34974e5 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -49,6 +49,7 @@ class delay_chain(design.design): self.place_inverters() self.route_inverters() + self.route_supplies() self.add_layout_pins() self.add_boundary() self.DRC_LVS() @@ -67,7 +68,6 @@ class delay_chain(design.design): def create_inverters(self): """ Create the inverters and connect them based on the stage list """ self.driver_inst_list = [] - self.rightest_load_inst = {} self.load_inst_map = {} for stage_num, fanout_size in zip(range(len(self.fanout_list)), self.fanout_list): # Add the inverter @@ -98,9 +98,6 @@ class delay_chain(design.design): # Keep track of all the loads to connect their inputs as a load self.load_inst_map[cur_driver].append(cur_load) - else: - # Keep track of the last one so we can add the the wire later - self.rightest_load_inst[cur_driver]=cur_load def place_inverters(self): """ Place the inverters and connect them based on the stage list """ @@ -151,7 +148,7 @@ class delay_chain(design.design): # Route an M3 horizontal wire to the furthest z_pin = inv.get_pin("Z") a_pin = inv.get_pin("A") - a_max = self.rightest_load_inst[inv].get_pin("A") + a_max = self.load_inst_map[inv][-1].get_pin("A") self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) self.add_via_center(layers=self.m1_stack, @@ -169,33 +166,24 @@ class delay_chain(design.design): mid1_point = vector(z_pin.cx(), y_mid) mid2_point = vector(next_a_pin.cx(), y_mid) self.add_path("m2", [z_pin.center(), mid1_point, mid2_point, next_a_pin.center()]) - - def add_layout_pins(self): - """ Add vdd and gnd rails and the input/output. Connect the gnd rails internally on - the top end with no input/output to obstruct. """ + def route_supplies(self): # Add power and ground to all the cells except: # the fanout driver, the right-most load # The routing to connect the loads is over the first and last cells # We have an even number of drivers and must only do every other # supply rail - for i in range(0, len(self.driver_inst_list), 2): - inv = self.driver_inst_list[i] - for load in self.load_inst_map[inv]: - if load==self.rightest_load_inst[inv]: - continue - for pin_name in ["vdd", "gnd"]: - pin = load.get_pin(pin_name) - self.add_power_pin(pin_name, pin.rc()) - else: - # We have an even number of rows, so need to get the last gnd rail - inv = self.driver_inst_list[-1] - for load in self.load_inst_map[inv]: - if load==self.rightest_load_inst[inv]: - continue - pin_name = "gnd" - pin = load.get_pin(pin_name) - self.add_power_pin(pin_name, pin.rc()) + + for inst in self.driver_inst_list: + load_list = self.load_inst_map[inst] + for pin_name in ["vdd", "gnd"]: + pin = load_list[0].get_pin(pin_name) + self.add_power_pin(pin_name, pin.rc() - vector(self.m1_pitch, 0)) + + pin = load_list[-1].get_pin(pin_name) + self.add_power_pin(pin_name, pin.rc() - vector(0.5 * self.m1_pitch, 0)) + + def add_layout_pins(self): # input is A pin of first inverter a_pin = self.driver_inst_list[0].get_pin("A") @@ -208,7 +196,7 @@ class delay_chain(design.design): # output is A pin of last load inverter last_driver_inst = self.driver_inst_list[-1] - a_pin = self.rightest_load_inst[last_driver_inst].get_pin("A") + a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A") self.add_via_center(layers=self.m1_stack, offset=a_pin.center()) mid_point = vector(a_pin.cx() + 3 * self.m2_width, a_pin.cy()) From 60ba2c1aa55ebf664deeaec919530d2ab6917e64 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Tue, 21 Apr 2020 17:20:29 -0700 Subject: [PATCH 294/521] updated pbitcell test names --- compiler/tests/04_precharge_pbitcell_test.py | 8 ++++---- .../tests/04_single_level_column_mux_pbitcell_test.py | 2 +- compiler/tests/05_replica_pbitcell_array_test.py | 6 +++--- compiler/tests/06_hierarchical_decoder_pbitcell_test.py | 4 ++-- .../tests/06_hierarchical_predecode2x4_pbitcell_test.py | 2 +- .../tests/06_hierarchical_predecode3x8_pbitcell_test.py | 2 +- .../07_single_level_column_mux_array_pbitcell_test.py | 2 +- compiler/tests/08_wordline_driver_pbitcell_test.py | 2 +- compiler/tests/09_sense_amp_array_test_pbitcell.py | 2 +- compiler/tests/10_write_driver_array_pbitcell_test.py | 2 +- .../tests/10_write_driver_array_wmask_pbitcell_test.py | 2 +- compiler/tests/10_write_mask_and_array_pbitcell_test.py | 2 +- 12 files changed, 18 insertions(+), 18 deletions(-) diff --git a/compiler/tests/04_precharge_pbitcell_test.py b/compiler/tests/04_precharge_pbitcell_test.py index fd2f8283..3eb7628d 100755 --- a/compiler/tests/04_precharge_pbitcell_test.py +++ b/compiler/tests/04_precharge_pbitcell_test.py @@ -15,12 +15,12 @@ from globals import OPTS from sram_factory import factory import debug -class precharge_test(openram_test): +class precharge_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - + # check precharge in multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 @@ -36,14 +36,14 @@ class precharge_test(openram_test): debug.info(2, "Checking precharge for pbitcell (innermost connections)") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) - + factory.reset() debug.info(2, "Checking precharge for pbitcell (outermost connections)") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) globals.end_openram() - + # run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/compiler/tests/04_single_level_column_mux_pbitcell_test.py b/compiler/tests/04_single_level_column_mux_pbitcell_test.py index 85f909e6..18ab631f 100644 --- a/compiler/tests/04_single_level_column_mux_pbitcell_test.py +++ b/compiler/tests/04_single_level_column_mux_pbitcell_test.py @@ -17,7 +17,7 @@ import debug #@unittest.skip("SKIPPING 04_driver_test") -class single_level_column_mux_test(openram_test): +class single_level_column_mux_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/05_replica_pbitcell_array_test.py b/compiler/tests/05_replica_pbitcell_array_test.py index 34bdbee7..6a87f408 100755 --- a/compiler/tests/05_replica_pbitcell_array_test.py +++ b/compiler/tests/05_replica_pbitcell_array_test.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California +# Copyright (c) 2016-2019 Regents of the University of California # All rights reserved. # import unittest @@ -13,7 +13,7 @@ from globals import OPTS from sram_factory import factory import debug -class replica_bitcell_array_test(openram_test): +class replica_pbitcell_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -41,7 +41,7 @@ class replica_bitcell_array_test(openram_test): debug.info(2, "Testing 4x4 array for pbitcell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) self.local_check(a) - + globals.end_openram() # run the test from the command line diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py index ec8f4efe..094e8b2e 100755 --- a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class hierarchical_decoder_test(openram_test): +class hierarchical_decoder_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -64,7 +64,7 @@ class hierarchical_decoder_test(openram_test): self.local_check(a) globals.end_openram() - + # run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py index bc4a153f..b5532891 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class hierarchical_predecode2x4_test(openram_test): +class hierarchical_predecode2x4_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py index ffe68102..1d5ab41b 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class hierarchical_predecode3x8_test(openram_test): +class hierarchical_predecode3x8_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py b/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py index d929b855..84e62a96 100644 --- a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py +++ b/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py @@ -14,7 +14,7 @@ from globals import OPTS from sram_factory import factory import debug -class single_level_column_mux_test(openram_test): +class single_level_column_mux_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/08_wordline_driver_pbitcell_test.py b/compiler/tests/08_wordline_driver_pbitcell_test.py index 42de5c26..3dd5933d 100644 --- a/compiler/tests/08_wordline_driver_pbitcell_test.py +++ b/compiler/tests/08_wordline_driver_pbitcell_test.py @@ -17,7 +17,7 @@ import debug #@unittest.skip("SKIPPING 04_driver_test") -class wordline_driver_test(openram_test): +class wordline_driver_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/09_sense_amp_array_test_pbitcell.py b/compiler/tests/09_sense_amp_array_test_pbitcell.py index 7c2fbd2d..a0fe256f 100644 --- a/compiler/tests/09_sense_amp_array_test_pbitcell.py +++ b/compiler/tests/09_sense_amp_array_test_pbitcell.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class sense_amp_test(openram_test): +class sense_amp_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/10_write_driver_array_pbitcell_test.py b/compiler/tests/10_write_driver_array_pbitcell_test.py index 87849001..397b3762 100644 --- a/compiler/tests/10_write_driver_array_pbitcell_test.py +++ b/compiler/tests/10_write_driver_array_pbitcell_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class write_driver_test(openram_test): +class write_driver_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py index 046b4d22..b6593eb0 100644 --- a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py +++ b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py @@ -17,7 +17,7 @@ from sram_factory import factory import debug -class write_driver_test(openram_test): +class write_driver_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/10_write_mask_and_array_pbitcell_test.py b/compiler/tests/10_write_mask_and_array_pbitcell_test.py index 5068c119..448ee8b1 100644 --- a/compiler/tests/10_write_mask_and_array_pbitcell_test.py +++ b/compiler/tests/10_write_mask_and_array_pbitcell_test.py @@ -17,7 +17,7 @@ from sram_factory import factory import debug -class write_mask_and_array_test(openram_test): +class write_mask_and_array_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) From c2419af2e2a61e4caa821ca04abcb90007a0ca0e Mon Sep 17 00:00:00 2001 From: David Ratchkov Date: Mon, 20 Apr 2020 13:36:47 -0700 Subject: [PATCH 295/521] Fix voltage_map names (these do not need to match pg_pin names) --- compiler/characterizer/lib.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 276ea767..e6befc2b 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -243,8 +243,8 @@ class lib: self.lib.write(" default_max_fanout : 4.0 ;\n") self.lib.write(" default_connection_class : universal ;\n\n") - self.lib.write(" voltage_map ( vdd, {} );\n".format(tech.spice["nom_supply_voltage"])) - self.lib.write(" voltage_map ( gnd, 0 );\n\n") + self.lib.write(" voltage_map ( VDD, {} );\n".format(tech.spice["nom_supply_voltage"])) + self.lib.write(" voltage_map ( GND, 0 );\n\n") def create_list(self,values): """ Helper function to create quoted, line wrapped list """ From 14f440df7360f3b799b3ba1448fac9ccb580097e Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 22 Apr 2020 10:40:04 -0700 Subject: [PATCH 296/521] Update golden results with new lib syntax --- compiler/tests/21_hspice_delay_test.py | 47 +++-- compiler/tests/21_ngspice_delay_test.py | 44 ++-- ..._16_1_freepdk45_FF_1p0V_25C_analytical.lib | 83 +++++--- ..._16_1_freepdk45_SS_1p0V_25C_analytical.lib | 83 +++++--- .../sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 167 ++++++++------- ..._16_1_freepdk45_TT_1p0V_25C_analytical.lib | 83 +++++--- ...16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 95 +++++---- ...16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 95 +++++---- .../sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 191 ++++++++++-------- ...16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 95 +++++---- 10 files changed, 583 insertions(+), 400 deletions(-) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 832a6308..a602f9d2 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -60,29 +60,36 @@ class timing_sram_test(openram_test): data, port_data = d.analyze(probe_address, probe_data, slews, loads) #Combine info about port into all data data.update(port_data[0]) - + if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.2383338], - 'delay_lh': [0.2383338], - 'leakage_power': 0.0014532999999999998, - 'min_period': 0.898, - 'read0_power': [0.30059800000000003], - 'read1_power': [0.30061810000000005], - 'slew_hl': [0.25358420000000004], - 'slew_lh': [0.25358420000000004], - 'write0_power': [0.34616749999999996], - 'write1_power': [0.2792924]} + golden_data = {'min_period': 0.898, + 'write1_power': [0.2659137999999999], + 'disabled_write0_power': [0.1782495], + 'disabled_read0_power': [0.14490679999999997], + 'write0_power': [0.3330119], + 'disabled_write1_power': [0.1865223], + 'leakage_power': 0.0014532, + 'disabled_read1_power': [0.1627516], + 'slew_lh': [0.25367799999999996], + 'slew_hl': [0.25367799999999996], + 'delay_lh': [0.23820930000000004], + 'delay_hl': [0.23820930000000004], + 'read1_power': [0.3005756], + 'read0_power': [0.3005888]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.7448], - 'delay_lh': [1.7448], - 'leakage_power': 0.0006356744000000001, + golden_data = {'leakage_power': 0.0006356576000000001, + 'write1_power': [11.292700000000002], + 'read0_power': [12.98], + 'disabled_write1_power': [8.3707], + 'write0_power': [14.4447], 'delay_hl': [1.7445000000000002], + 'disabled_read0_power': [6.4325], + 'slew_hl': [1.7437], + 'disabled_write0_power': [8.1307], + 'slew_lh': [1.7437], + 'read1_power': [12.9869], + 'disabled_read1_power': [7.706], 'min_period': 6.25, - 'read0_power': [12.9846], - 'read1_power': [12.9722], - 'slew_hl': [1.7433], - 'slew_lh': [1.7433], - 'write0_power': [14.8772], - 'write1_power': [11.7217]} + 'delay_lh': [1.7445000000000002]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index fb72a57d..c944b3ce 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -55,27 +55,35 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.2264205], - 'delay_lh': [0.2264205], - 'leakage_power': 0.0021017429999999997, - 'min_period': 0.859, - 'read0_power': [0.3339161], - 'read1_power': [0.31329440000000003], - 'slew_hl': [0.2590786], - 'slew_lh': [0.2590786], - 'write0_power': [0.36360849999999995], - 'write1_power': [0.3486931]} + golden_data = {'slew_lh': [0.2592187], + 'slew_hl': [0.2592187], + 'delay_lh': [0.2465583], + 'disabled_write0_power': [0.1924678], + 'disabled_read0_power': [0.152483], + 'write0_power': [0.3409064], + 'disabled_read1_power': [0.1737818], + 'read0_power': [0.3096708], + 'read1_power': [0.3107916], + 'delay_hl': [0.2465583], + 'write1_power': [0.26915849999999997], + 'leakage_power': 0.002044307, + 'min_period': 0.898, + 'disabled_write1_power': [0.201411]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.85985], - 'delay_lh': [1.85985], + golden_data = {'read1_power': [12.11658], + 'write1_power': [10.52653], + 'read0_power': [11.956710000000001], + 'disabled_write0_power': [7.673665], + 'disabled_write1_power': [7.981922000000001], + 'slew_lh': [1.868836], + 'slew_hl': [1.868836], + 'delay_hl': [1.8598510000000001], + 'delay_lh': [1.8598510000000001], 'leakage_power': 0.008613619, + 'disabled_read0_power': [5.904712], 'min_period': 6.875, - 'read0_power': [12.656310000000001], - 'read1_power': [12.11682], - 'slew_hl': [1.868942], - 'slew_lh': [1.868942], - 'write0_power': [13.978110000000001], - 'write1_power': [11.437930000000001]} + 'disabled_read1_power': [7.132159], + 'write0_power': [13.406400000000001]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index a1c5a04b..b3ef0e0a 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ default_max_fanout : 4.0 ; default_connection_class : universal ; + voltage_map ( VDD, 1.0 ); + voltage_map ( GND, 0 ); + lu_table_template(CELL_TABLE){ variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.00125, 0.005, 0.04"); - index_2("0.052275, 0.2091, 1.6728"); + index_2("5.2275e-05, 0.0002091, 0.0008364"); } lu_table_template(CONSTRAINT_TABLE){ @@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){ dont_use : true; map_only : true; dont_touch : true; - area : 1124.88; + area : 0; + + pg_pin(vdd) { + voltage_name : VDD; + pg_type : primary_power; + } + + pg_pin(gnd) { + voltage_name : GND; + pg_type : primary_ground; + } leakage_power () { - when : "csb0"; - value : 0.000167; + value : 0.000198; } - cell_leakage_power : 0; + cell_leakage_power : 0.000198; bus(din0){ bus_type : data; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; memory_write(){ address : addr0; clocked_on : clk0; @@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){ bus(dout0){ bus_type : data; direction : output; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + max_capacitance : 0.0008364000000000001; + min_capacitance : 5.2275000000000003e-05; memory_read(){ address : addr0; } @@ -138,14 +150,14 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk0"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.088, 0.088, 0.088",\ - "0.088, 0.088, 0.088",\ - "0.088, 0.088, 0.088"); + values("0.193, 0.193, 0.194",\ + "0.193, 0.193, 0.194",\ + "0.193, 0.193, 0.194"); } cell_fall(CELL_TABLE) { - values("0.088, 0.088, 0.088",\ - "0.088, 0.088, 0.088",\ - "0.088, 0.088, 0.088"); + values("0.193, 0.193, 0.194",\ + "0.193, 0.193, 0.194",\ + "0.193, 0.193, 0.194"); } rise_transition(CELL_TABLE) { values("0.001, 0.001, 0.001",\ @@ -164,7 +176,7 @@ cell (sram_2_16_1_freepdk45){ bus(addr0){ bus_type : addr; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; max_transition : 0.04; pin(addr0[3:0]){ timing(){ @@ -200,7 +212,7 @@ cell (sram_2_16_1_freepdk45){ pin(csb0){ direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -233,7 +245,7 @@ cell (sram_2_16_1_freepdk45){ pin(web0){ direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){ pin(clk0){ clock : true; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; internal_power(){ - when : "!csb0 & clk0 & !web0"; + when : "!csb0 & !web0"; rise_power(scalar){ - values("0.033101244168888884"); + values("9.240667e-02"); } fall_power(scalar){ - values("0.033101244168888884"); + values("9.240667e-02"); } } internal_power(){ - when : "!csb0 & !clk0 & web0"; + when : "csb0 & !web0"; rise_power(scalar){ - values("0.033101244168888884"); + values("9.240667e-02"); } fall_power(scalar){ - values("0.033101244168888884"); + values("9.240667e-02"); } } internal_power(){ - when : "csb0"; + when : "!csb0 & web0"; rise_power(scalar){ - values("0"); + values("9.240667e-02"); } fall_power(scalar){ - values("0"); + values("9.240667e-02"); + } + } + internal_power(){ + when : "csb0 & web0"; + rise_power(scalar){ + values("9.240667e-02"); + } + fall_power(scalar){ + values("9.240667e-02"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk0; rise_constraint(scalar) { - values("0.009"); + values("0.0195"); } fall_constraint(scalar) { - values("0.009"); + values("0.0195"); } } timing(){ timing_type :"minimum_period"; related_pin : clk0; rise_constraint(scalar) { - values("0.018"); + values("0.039"); } fall_constraint(scalar) { - values("0.018"); + values("0.039"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 865daada..34be4fe4 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ default_max_fanout : 4.0 ; default_connection_class : universal ; + voltage_map ( VDD, 1.0 ); + voltage_map ( GND, 0 ); + lu_table_template(CELL_TABLE){ variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.00125, 0.005, 0.04"); - index_2("0.052275, 0.2091, 1.6728"); + index_2("5.2275e-05, 0.0002091, 0.0008364"); } lu_table_template(CONSTRAINT_TABLE){ @@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){ dont_use : true; map_only : true; dont_touch : true; - area : 1124.88; + area : 0; + + pg_pin(vdd) { + voltage_name : VDD; + pg_type : primary_power; + } + + pg_pin(gnd) { + voltage_name : GND; + pg_type : primary_ground; + } leakage_power () { - when : "csb0"; - value : 0.000167; + value : 0.000198; } - cell_leakage_power : 0; + cell_leakage_power : 0.000198; bus(din0){ bus_type : data; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; memory_write(){ address : addr0; clocked_on : clk0; @@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){ bus(dout0){ bus_type : data; direction : output; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + max_capacitance : 0.0008364000000000001; + min_capacitance : 5.2275000000000003e-05; memory_read(){ address : addr0; } @@ -138,14 +150,14 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk0"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.107, 0.107, 0.107",\ - "0.107, 0.107, 0.107",\ - "0.107, 0.107, 0.107"); + values("0.236, 0.236, 0.237",\ + "0.236, 0.236, 0.237",\ + "0.236, 0.236, 0.237"); } cell_fall(CELL_TABLE) { - values("0.107, 0.107, 0.107",\ - "0.107, 0.107, 0.107",\ - "0.107, 0.107, 0.107"); + values("0.236, 0.236, 0.237",\ + "0.236, 0.236, 0.237",\ + "0.236, 0.236, 0.237"); } rise_transition(CELL_TABLE) { values("0.001, 0.001, 0.001",\ @@ -164,7 +176,7 @@ cell (sram_2_16_1_freepdk45){ bus(addr0){ bus_type : addr; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; max_transition : 0.04; pin(addr0[3:0]){ timing(){ @@ -200,7 +212,7 @@ cell (sram_2_16_1_freepdk45){ pin(csb0){ direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -233,7 +245,7 @@ cell (sram_2_16_1_freepdk45){ pin(web0){ direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){ pin(clk0){ clock : true; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; internal_power(){ - when : "!csb0 & clk0 & !web0"; + when : "!csb0 & !web0"; rise_power(scalar){ - values("0.033101244168888884"); + values("7.560546e-02"); } fall_power(scalar){ - values("0.033101244168888884"); + values("7.560546e-02"); } } internal_power(){ - when : "!csb0 & !clk0 & web0"; + when : "csb0 & !web0"; rise_power(scalar){ - values("0.033101244168888884"); + values("7.560546e-02"); } fall_power(scalar){ - values("0.033101244168888884"); + values("7.560546e-02"); } } internal_power(){ - when : "csb0"; + when : "!csb0 & web0"; rise_power(scalar){ - values("0"); + values("7.560546e-02"); } fall_power(scalar){ - values("0"); + values("7.560546e-02"); + } + } + internal_power(){ + when : "csb0 & web0"; + rise_power(scalar){ + values("7.560546e-02"); + } + fall_power(scalar){ + values("7.560546e-02"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk0; rise_constraint(scalar) { - values("0.0105"); + values("0.0235"); } fall_constraint(scalar) { - values("0.0105"); + values("0.0235"); } } timing(){ timing_type :"minimum_period"; related_pin : clk0; rise_constraint(scalar) { - values("0.021"); + values("0.047"); } fall_constraint(scalar) { - values("0.021"); + values("0.047"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index 72d01a0f..cca9c1ed 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ default_max_fanout : 4.0 ; default_connection_class : universal ; + voltage_map ( VDD, 1.0 ); + voltage_map ( GND, 0 ); + lu_table_template(CELL_TABLE){ variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.00125, 0.005, 0.04"); - index_2("0.052275, 0.2091, 1.6728"); + index_2("5.2275e-05, 0.0002091, 0.0008364"); } lu_table_template(CONSTRAINT_TABLE){ @@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){ dont_use : true; map_only : true; dont_touch : true; - area : 977.4951374999999; + area : 0; + + pg_pin(vdd) { + voltage_name : VDD; + pg_type : primary_power; + } + + pg_pin(gnd) { + voltage_name : GND; + pg_type : primary_ground; + } leakage_power () { - when : "csb0"; - value : 0.0011164579999999999; + value : 0.00163; } - cell_leakage_power : 0; + cell_leakage_power : 0.00163; bus(din0){ bus_type : data; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; memory_write(){ address : addr0; clocked_on : clk0; @@ -98,9 +110,9 @@ cell (sram_2_16_1_freepdk45){ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.033, 0.033, 0.039",\ - "0.033, 0.033, 0.039",\ - "0.033, 0.033, 0.039"); + values("0.033, 0.033, 0.033",\ + "0.033, 0.033, 0.033",\ + "0.033, 0.033, 0.033"); } fall_constraint(CONSTRAINT_TABLE) { values("0.027, 0.027, 0.033",\ @@ -112,14 +124,14 @@ cell (sram_2_16_1_freepdk45){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.01, -0.016, -0.022",\ - "-0.01, -0.016, -0.022",\ - "-0.01, -0.016, -0.022"); + values("-0.01, -0.01, 0.021",\ + "-0.01, -0.01, 0.021",\ + "-0.01, -0.01, 0.021"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.016, -0.016, -0.016",\ - "-0.016, -0.016, -0.016",\ - "-0.016, -0.016, -0.016"); + values("-0.016, -0.01, -0.016",\ + "-0.016, -0.01, -0.016",\ + "-0.016, -0.01, -0.016"); } } } @@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){ bus(dout0){ bus_type : data; direction : output; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + max_capacitance : 0.0008364000000000001; + min_capacitance : 5.2275000000000003e-05; memory_read(){ address : addr0; } @@ -138,24 +150,24 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk0"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.235, 0.235, 0.239",\ - "0.235, 0.236, 0.24",\ - "0.241, 0.242, 0.246"); + values("0.226, 0.227, 0.232",\ + "0.227, 0.228, 0.233",\ + "0.232, 0.234, 0.238"); } cell_fall(CELL_TABLE) { - values("2.583, 2.585, 2.612",\ - "2.584, 2.585, 2.613",\ - "2.59, 2.592, 2.62"); + values("0.226, 0.227, 0.232",\ + "0.227, 0.228, 0.233",\ + "0.232, 0.234, 0.238"); } rise_transition(CELL_TABLE) { - values("0.022, 0.022, 0.03",\ - "0.022, 0.023, 0.03",\ - "0.022, 0.022, 0.03"); + values("0.256, 0.256, 0.257",\ + "0.256, 0.256, 0.257",\ + "0.256, 0.256, 0.257"); } fall_transition(CELL_TABLE) { - values("0.078, 0.079, 0.083",\ - "0.078, 0.079, 0.083",\ - "0.079, 0.079, 0.083"); + values("0.256, 0.256, 0.257",\ + "0.256, 0.256, 0.257",\ + "0.256, 0.256, 0.257"); } } } @@ -164,16 +176,16 @@ cell (sram_2_16_1_freepdk45){ bus(addr0){ bus_type : addr; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; max_transition : 0.04; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.033, 0.033, 0.039",\ - "0.033, 0.033, 0.039",\ - "0.033, 0.033, 0.039"); + values("0.033, 0.033, 0.033",\ + "0.033, 0.033, 0.033",\ + "0.033, 0.033, 0.033"); } fall_constraint(CONSTRAINT_TABLE) { values("0.027, 0.027, 0.033",\ @@ -185,14 +197,14 @@ cell (sram_2_16_1_freepdk45){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.01, -0.016, -0.022",\ - "-0.01, -0.016, -0.022",\ - "-0.01, -0.016, -0.022"); + values("-0.01, -0.01, 0.021",\ + "-0.01, -0.01, 0.021",\ + "-0.01, -0.01, 0.021"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.016, -0.016, -0.016",\ - "-0.016, -0.016, -0.016",\ - "-0.016, -0.016, -0.016"); + values("-0.016, -0.01, -0.016",\ + "-0.016, -0.01, -0.016",\ + "-0.016, -0.01, -0.016"); } } } @@ -200,14 +212,14 @@ cell (sram_2_16_1_freepdk45){ pin(csb0){ direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; timing(){ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.033, 0.033, 0.039",\ - "0.033, 0.033, 0.039",\ - "0.033, 0.033, 0.039"); + values("0.033, 0.033, 0.033",\ + "0.033, 0.033, 0.033",\ + "0.033, 0.033, 0.033"); } fall_constraint(CONSTRAINT_TABLE) { values("0.027, 0.027, 0.033",\ @@ -219,28 +231,28 @@ cell (sram_2_16_1_freepdk45){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.01, -0.016, -0.022",\ - "-0.01, -0.016, -0.022",\ - "-0.01, -0.016, -0.022"); + values("-0.01, -0.01, 0.021",\ + "-0.01, -0.01, 0.021",\ + "-0.01, -0.01, 0.021"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.016, -0.016, -0.016",\ - "-0.016, -0.016, -0.016",\ - "-0.016, -0.016, -0.016"); + values("-0.016, -0.01, -0.016",\ + "-0.016, -0.01, -0.016",\ + "-0.016, -0.01, -0.016"); } } } pin(web0){ direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; timing(){ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.033, 0.033, 0.039",\ - "0.033, 0.033, 0.039",\ - "0.033, 0.033, 0.039"); + values("0.033, 0.033, 0.033",\ + "0.033, 0.033, 0.033",\ + "0.033, 0.033, 0.033"); } fall_constraint(CONSTRAINT_TABLE) { values("0.027, 0.027, 0.033",\ @@ -252,14 +264,14 @@ cell (sram_2_16_1_freepdk45){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.01, -0.016, -0.022",\ - "-0.01, -0.016, -0.022",\ - "-0.01, -0.016, -0.022"); + values("-0.01, -0.01, 0.021",\ + "-0.01, -0.01, 0.021",\ + "-0.01, -0.01, 0.021"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.016, -0.016, -0.016",\ - "-0.016, -0.016, -0.016",\ - "-0.016, -0.016, -0.016"); + values("-0.016, -0.01, -0.016",\ + "-0.016, -0.01, -0.016",\ + "-0.016, -0.01, -0.016"); } } } @@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){ pin(clk0){ clock : true; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; internal_power(){ - when : "!csb0 & clk0 & !web0"; + when : "!csb0 & !web0"; rise_power(scalar){ - values("0.03599689694444445"); + values("3.069977e-01"); } fall_power(scalar){ - values("0.03599689694444445"); + values("3.686680e-01"); } } internal_power(){ - when : "!csb0 & !clk0 & web0"; + when : "csb0 & !web0"; rise_power(scalar){ - values("0.029906643888888886"); + values("2.055845e-01"); } fall_power(scalar){ - values("0.029906643888888886"); + values("1.933561e-01"); } } internal_power(){ - when : "csb0"; + when : "!csb0 & web0"; rise_power(scalar){ - values("0"); + values("3.315565e-01"); } fall_power(scalar){ - values("0"); + values("3.314553e-01"); + } + } + internal_power(){ + when : "csb0 & web0"; + rise_power(scalar){ + values("1.777355e-01"); + } + fall_power(scalar){ + values("1.615044e-01"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk0; rise_constraint(scalar) { - values("2.422"); + values("0.449"); } fall_constraint(scalar) { - values("2.422"); + values("0.449"); } } timing(){ timing_type :"minimum_period"; related_pin : clk0; rise_constraint(scalar) { - values("4.844"); + values("0.898"); } fall_constraint(scalar) { - values("4.844"); + values("0.898"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 33587063..26028892 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ default_max_fanout : 4.0 ; default_connection_class : universal ; + voltage_map ( VDD, 1.0 ); + voltage_map ( GND, 0 ); + lu_table_template(CELL_TABLE){ variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.00125, 0.005, 0.04"); - index_2("0.052275, 0.2091, 1.6728"); + index_2("5.2275e-05, 0.0002091, 0.0008364"); } lu_table_template(CONSTRAINT_TABLE){ @@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){ dont_use : true; map_only : true; dont_touch : true; - area : 977.4951374999999; + area : 0; + + pg_pin(vdd) { + voltage_name : VDD; + pg_type : primary_power; + } + + pg_pin(gnd) { + voltage_name : GND; + pg_type : primary_ground; + } leakage_power () { - when : "csb0"; - value : 0.000179; + value : 0.000198; } - cell_leakage_power : 0; + cell_leakage_power : 0.000198; bus(din0){ bus_type : data; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; memory_write(){ address : addr0; clocked_on : clk0; @@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){ bus(dout0){ bus_type : data; direction : output; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + max_capacitance : 0.0008364000000000001; + min_capacitance : 5.2275000000000003e-05; memory_read(){ address : addr0; } @@ -138,14 +150,14 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk0"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.098, 0.098, 0.098",\ - "0.098, 0.098, 0.098",\ - "0.098, 0.098, 0.098"); + values("0.215, 0.215, 0.216",\ + "0.215, 0.215, 0.216",\ + "0.215, 0.215, 0.216"); } cell_fall(CELL_TABLE) { - values("0.098, 0.098, 0.098",\ - "0.098, 0.098, 0.098",\ - "0.098, 0.098, 0.098"); + values("0.215, 0.215, 0.216",\ + "0.215, 0.215, 0.216",\ + "0.215, 0.215, 0.216"); } rise_transition(CELL_TABLE) { values("0.001, 0.001, 0.001",\ @@ -164,7 +176,7 @@ cell (sram_2_16_1_freepdk45){ bus(addr0){ bus_type : addr; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; max_transition : 0.04; pin(addr0[3:0]){ timing(){ @@ -200,7 +212,7 @@ cell (sram_2_16_1_freepdk45){ pin(csb0){ direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -233,7 +245,7 @@ cell (sram_2_16_1_freepdk45){ pin(web0){ direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){ pin(clk0){ clock : true; direction : input; - capacitance : 0.2091; + capacitance : 0.00020910000000000001; internal_power(){ - when : "!csb0 & clk0 & !web0"; + when : "!csb0 & !web0"; rise_power(scalar){ - values("0.0747594982142222"); + values("8.316600e-02"); } fall_power(scalar){ - values("0.0747594982142222"); + values("8.316600e-02"); } } internal_power(){ - when : "!csb0 & !clk0 & web0"; + when : "csb0 & !web0"; rise_power(scalar){ - values("0.0747594982142222"); + values("8.316600e-02"); } fall_power(scalar){ - values("0.0747594982142222"); + values("8.316600e-02"); } } internal_power(){ - when : "csb0"; + when : "!csb0 & web0"; rise_power(scalar){ - values("0"); + values("8.316600e-02"); } fall_power(scalar){ - values("0"); + values("8.316600e-02"); + } + } + internal_power(){ + when : "csb0 & web0"; + rise_power(scalar){ + values("8.316600e-02"); + } + fall_power(scalar){ + values("8.316600e-02"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk0; rise_constraint(scalar) { - values("0.0"); + values("0.0215"); } fall_constraint(scalar) { - values("0.0"); + values("0.0215"); } } timing(){ timing_type :"minimum_period"; related_pin : clk0; rise_constraint(scalar) { - values("0"); + values("0.043"); } fall_constraint(scalar) { - values("0"); + values("0.043"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index c370f993..6912aec7 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ default_max_fanout : 4.0 ; default_connection_class : universal ; + voltage_map ( VDD, 5.0 ); + voltage_map ( GND, 0 ); + lu_table_template(CELL_TABLE){ variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.0125, 0.05, 0.4"); - index_2("2.45605, 9.8242, 78.5936"); + index_2("0.00245605, 0.0098242, 0.0392968"); } lu_table_template(CONSTRAINT_TABLE){ @@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){ dont_use : true; map_only : true; dont_touch : true; - area : 73068.14000000001; + area : 0; + + pg_pin(vdd) { + voltage_name : VDD; + pg_type : primary_power; + } + + pg_pin(gnd) { + voltage_name : GND; + pg_type : primary_ground; + } leakage_power () { - when : "csb0"; - value : 0.000167; + value : 0.000198; } - cell_leakage_power : 0; + cell_leakage_power : 0.000198; bus(din0){ bus_type : data; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; memory_write(){ address : addr0; clocked_on : clk0; @@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){ bus(dout0){ bus_type : data; direction : output; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + max_capacitance : 0.0392968; + min_capacitance : 0.00245605; memory_read(){ address : addr0; } @@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){ related_pin : "clk0"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.241, 0.241, 0.241",\ - "0.241, 0.241, 0.241",\ - "0.241, 0.241, 0.241"); + values("1.183, 1.199, 1.264",\ + "1.183, 1.199, 1.264",\ + "1.183, 1.199, 1.264"); } cell_fall(CELL_TABLE) { - values("0.241, 0.241, 0.241",\ - "0.241, 0.241, 0.241",\ - "0.241, 0.241, 0.241"); + values("1.183, 1.199, 1.264",\ + "1.183, 1.199, 1.264",\ + "1.183, 1.199, 1.264"); } rise_transition(CELL_TABLE) { - values("0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004"); + values("0.006, 0.007, 0.014",\ + "0.006, 0.007, 0.014",\ + "0.006, 0.007, 0.014"); } fall_transition(CELL_TABLE) { - values("0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004"); + values("0.006, 0.007, 0.014",\ + "0.006, 0.007, 0.014",\ + "0.006, 0.007, 0.014"); } } } @@ -164,7 +176,7 @@ cell (sram_2_16_1_scn4m_subm){ bus(addr0){ bus_type : addr; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; max_transition : 0.4; pin(addr0[3:0]){ timing(){ @@ -200,7 +212,7 @@ cell (sram_2_16_1_scn4m_subm){ pin(csb0){ direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -233,7 +245,7 @@ cell (sram_2_16_1_scn4m_subm){ pin(web0){ direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){ pin(clk0){ clock : true; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; internal_power(){ - when : "!csb0 & clk0 & !web0"; + when : "!csb0 & !web0"; rise_power(scalar){ - values("4.99880645"); + values("7.797263e+00"); } fall_power(scalar){ - values("4.99880645"); + values("7.797263e+00"); } } internal_power(){ - when : "!csb0 & !clk0 & web0"; + when : "csb0 & !web0"; rise_power(scalar){ - values("4.99880645"); + values("7.797263e+00"); } fall_power(scalar){ - values("4.99880645"); + values("7.797263e+00"); } } internal_power(){ - when : "csb0"; + when : "!csb0 & web0"; rise_power(scalar){ - values("0"); + values("7.797263e+00"); } fall_power(scalar){ - values("0"); + values("7.797263e+00"); + } + } + internal_power(){ + when : "csb0 & web0"; + rise_power(scalar){ + values("7.797263e+00"); + } + fall_power(scalar){ + values("7.797263e+00"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk0; rise_constraint(scalar) { - values("0.024"); + values("0.1265"); } fall_constraint(scalar) { - values("0.024"); + values("0.1265"); } } timing(){ timing_type :"minimum_period"; related_pin : clk0; rise_constraint(scalar) { - values("0.048"); + values("0.253"); } fall_constraint(scalar) { - values("0.048"); + values("0.253"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index f52de676..a7605cb3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ default_max_fanout : 4.0 ; default_connection_class : universal ; + voltage_map ( VDD, 5.0 ); + voltage_map ( GND, 0 ); + lu_table_template(CELL_TABLE){ variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.0125, 0.05, 0.4"); - index_2("2.45605, 9.8242, 78.5936"); + index_2("0.00245605, 0.0098242, 0.0392968"); } lu_table_template(CONSTRAINT_TABLE){ @@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){ dont_use : true; map_only : true; dont_touch : true; - area : 73068.14000000001; + area : 0; + + pg_pin(vdd) { + voltage_name : VDD; + pg_type : primary_power; + } + + pg_pin(gnd) { + voltage_name : GND; + pg_type : primary_ground; + } leakage_power () { - when : "csb0"; - value : 0.000167; + value : 0.000198; } - cell_leakage_power : 0; + cell_leakage_power : 0.000198; bus(din0){ bus_type : data; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; memory_write(){ address : addr0; clocked_on : clk0; @@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){ bus(dout0){ bus_type : data; direction : output; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + max_capacitance : 0.0392968; + min_capacitance : 0.00245605; memory_read(){ address : addr0; } @@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){ related_pin : "clk0"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.294, 0.294, 0.294",\ - "0.294, 0.294, 0.294",\ - "0.294, 0.294, 0.294"); + values("1.446, 1.466, 1.545",\ + "1.446, 1.466, 1.545",\ + "1.446, 1.466, 1.545"); } cell_fall(CELL_TABLE) { - values("0.294, 0.294, 0.294",\ - "0.294, 0.294, 0.294",\ - "0.294, 0.294, 0.294"); + values("1.446, 1.466, 1.545",\ + "1.446, 1.466, 1.545",\ + "1.446, 1.466, 1.545"); } rise_transition(CELL_TABLE) { - values("0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004"); + values("0.007, 0.009, 0.017",\ + "0.007, 0.009, 0.017",\ + "0.007, 0.009, 0.017"); } fall_transition(CELL_TABLE) { - values("0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004"); + values("0.007, 0.009, 0.017",\ + "0.007, 0.009, 0.017",\ + "0.007, 0.009, 0.017"); } } } @@ -164,7 +176,7 @@ cell (sram_2_16_1_scn4m_subm){ bus(addr0){ bus_type : addr; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; max_transition : 0.4; pin(addr0[3:0]){ timing(){ @@ -200,7 +212,7 @@ cell (sram_2_16_1_scn4m_subm){ pin(csb0){ direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -233,7 +245,7 @@ cell (sram_2_16_1_scn4m_subm){ pin(web0){ direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){ pin(clk0){ clock : true; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; internal_power(){ - when : "!csb0 & clk0 & !web0"; + when : "!csb0 & !web0"; rise_power(scalar){ - values("4.99880645"); + values("6.379579e+00"); } fall_power(scalar){ - values("4.99880645"); + values("6.379579e+00"); } } internal_power(){ - when : "!csb0 & !clk0 & web0"; + when : "csb0 & !web0"; rise_power(scalar){ - values("4.99880645"); + values("6.379579e+00"); } fall_power(scalar){ - values("4.99880645"); + values("6.379579e+00"); } } internal_power(){ - when : "csb0"; + when : "!csb0 & web0"; rise_power(scalar){ - values("0"); + values("6.379579e+00"); } fall_power(scalar){ - values("0"); + values("6.379579e+00"); + } + } + internal_power(){ + when : "csb0 & web0"; + rise_power(scalar){ + values("6.379579e+00"); + } + fall_power(scalar){ + values("6.379579e+00"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk0; rise_constraint(scalar) { - values("0.0295"); + values("0.1545"); } fall_constraint(scalar) { - values("0.0295"); + values("0.1545"); } } timing(){ timing_type :"minimum_period"; related_pin : clk0; rise_constraint(scalar) { - values("0.059"); + values("0.309"); } fall_constraint(scalar) { - values("0.059"); + values("0.309"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index 7447a1e2..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ default_max_fanout : 4.0 ; default_connection_class : universal ; + voltage_map ( VDD, 5.0 ); + voltage_map ( GND, 0 ); + lu_table_template(CELL_TABLE){ variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.0125, 0.05, 0.4"); - index_2("2.45605, 9.8242, 78.5936"); + index_2("0.00245605, 0.0098242, 0.0392968"); } lu_table_template(CONSTRAINT_TABLE){ @@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){ dont_use : true; map_only : true; dont_touch : true; - area : 60774.3; + area : 0; + + pg_pin(vdd) { + voltage_name : VDD; + pg_type : primary_power; + } + + pg_pin(gnd) { + voltage_name : GND; + pg_type : primary_ground; + } leakage_power () { - when : "csb0"; - value : 0.0009813788999999999; + value : 0.000198; } - cell_leakage_power : 0; + cell_leakage_power : 0.000198; bus(din0){ bus_type : data; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; memory_write(){ address : addr0; clocked_on : clk0; @@ -98,28 +110,28 @@ cell (sram_2_16_1_scn4m_subm){ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.167, 0.167, 0.228",\ - "0.167, 0.167, 0.228",\ - "0.167, 0.167, 0.228"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.131, 0.125, 0.137",\ - "0.131, 0.125, 0.137",\ - "0.131, 0.125, 0.137"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } } timing(){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.065, -0.071, -0.114",\ - "-0.065, -0.071, -0.114",\ - "-0.065, -0.071, -0.114"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.089, -0.089, -0.089",\ - "-0.089, -0.089, -0.089",\ - "-0.089, -0.089, -0.089"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } } } @@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){ bus(dout0){ bus_type : data; direction : output; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + max_capacitance : 0.0392968; + min_capacitance : 0.00245605; memory_read(){ address : addr0; } @@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){ related_pin : "clk0"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("1.556, 1.576, 1.751",\ - "1.559, 1.579, 1.754",\ - "1.624, 1.643, 1.819"); + values("1.314, 1.332, 1.404",\ + "1.314, 1.332, 1.404",\ + "1.314, 1.332, 1.404"); } cell_fall(CELL_TABLE) { - values("3.445, 3.504, 3.926",\ - "3.448, 3.507, 3.93",\ - "3.49, 3.549, 3.972"); + values("1.314, 1.332, 1.404",\ + "1.314, 1.332, 1.404",\ + "1.314, 1.332, 1.404"); } rise_transition(CELL_TABLE) { - values("0.13, 0.169, 0.574",\ - "0.13, 0.169, 0.574",\ - "0.13, 0.169, 0.574"); + values("0.006, 0.008, 0.015",\ + "0.006, 0.008, 0.015",\ + "0.006, 0.008, 0.015"); } fall_transition(CELL_TABLE) { - values("0.467, 0.49, 0.959",\ - "0.467, 0.49, 0.959",\ - "0.47, 0.493, 0.96"); + values("0.006, 0.008, 0.015",\ + "0.006, 0.008, 0.015",\ + "0.006, 0.008, 0.015"); } } } @@ -164,35 +176,35 @@ cell (sram_2_16_1_scn4m_subm){ bus(addr0){ bus_type : addr; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; max_transition : 0.4; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.167, 0.167, 0.228",\ - "0.167, 0.167, 0.228",\ - "0.167, 0.167, 0.228"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.131, 0.125, 0.137",\ - "0.131, 0.125, 0.137",\ - "0.131, 0.125, 0.137"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } } timing(){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.065, -0.071, -0.114",\ - "-0.065, -0.071, -0.114",\ - "-0.065, -0.071, -0.114"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.089, -0.089, -0.089",\ - "-0.089, -0.089, -0.089",\ - "-0.089, -0.089, -0.089"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } } } @@ -200,66 +212,66 @@ cell (sram_2_16_1_scn4m_subm){ pin(csb0){ direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; timing(){ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.167, 0.167, 0.228",\ - "0.167, 0.167, 0.228",\ - "0.167, 0.167, 0.228"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.131, 0.125, 0.137",\ - "0.131, 0.125, 0.137",\ - "0.131, 0.125, 0.137"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } } timing(){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.065, -0.071, -0.114",\ - "-0.065, -0.071, -0.114",\ - "-0.065, -0.071, -0.114"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.089, -0.089, -0.089",\ - "-0.089, -0.089, -0.089",\ - "-0.089, -0.089, -0.089"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } } } pin(web0){ direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; timing(){ timing_type : setup_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("0.167, 0.167, 0.228",\ - "0.167, 0.167, 0.228",\ - "0.167, 0.167, 0.228"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.131, 0.125, 0.137",\ - "0.131, 0.125, 0.137",\ - "0.131, 0.125, 0.137"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } } timing(){ timing_type : hold_rising; related_pin : "clk0"; rise_constraint(CONSTRAINT_TABLE) { - values("-0.065, -0.071, -0.114",\ - "-0.065, -0.071, -0.114",\ - "-0.065, -0.071, -0.114"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.089, -0.089, -0.089",\ - "-0.089, -0.089, -0.089",\ - "-0.089, -0.089, -0.089"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } } } @@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){ pin(clk0){ clock : true; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; internal_power(){ - when : "!csb0 & clk0 & !web0"; + when : "!csb0 & !web0"; rise_power(scalar){ - values("9.972790277777777"); + values("7.017537e+00"); } fall_power(scalar){ - values("9.972790277777777"); + values("7.017537e+00"); } } internal_power(){ - when : "!csb0 & !clk0 & web0"; + when : "csb0 & !web0"; rise_power(scalar){ - values("8.899322499999998"); + values("7.017537e+00"); } fall_power(scalar){ - values("8.899322499999998"); + values("7.017537e+00"); } } internal_power(){ - when : "csb0"; + when : "!csb0 & web0"; rise_power(scalar){ - values("0"); + values("7.017537e+00"); } fall_power(scalar){ - values("0"); + values("7.017537e+00"); + } + } + internal_power(){ + when : "csb0 & web0"; + rise_power(scalar){ + values("7.017537e+00"); + } + fall_power(scalar){ + values("7.017537e+00"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk0; rise_constraint(scalar) { - values("2.344"); + values("0.1405"); } fall_constraint(scalar) { - values("2.344"); + values("0.1405"); } } timing(){ timing_type :"minimum_period"; related_pin : clk0; rise_constraint(scalar) { - values("4.688"); + values("0.281"); } fall_constraint(scalar) { - values("4.688"); + values("0.281"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index 4248b986..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ default_max_fanout : 4.0 ; default_connection_class : universal ; + voltage_map ( VDD, 5.0 ); + voltage_map ( GND, 0 ); + lu_table_template(CELL_TABLE){ variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.0125, 0.05, 0.4"); - index_2("2.45605, 9.8242, 78.5936"); + index_2("0.00245605, 0.0098242, 0.0392968"); } lu_table_template(CONSTRAINT_TABLE){ @@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){ dont_use : true; map_only : true; dont_touch : true; - area : 60774.3; + area : 0; + + pg_pin(vdd) { + voltage_name : VDD; + pg_type : primary_power; + } + + pg_pin(gnd) { + voltage_name : GND; + pg_type : primary_ground; + } leakage_power () { - when : "csb0"; - value : 0.000179; + value : 0.000198; } - cell_leakage_power : 0; + cell_leakage_power : 0.000198; bus(din0){ bus_type : data; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; memory_write(){ address : addr0; clocked_on : clk0; @@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){ bus(dout0){ bus_type : data; direction : output; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + max_capacitance : 0.0392968; + min_capacitance : 0.00245605; memory_read(){ address : addr0; } @@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){ related_pin : "clk0"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.268, 0.268, 0.268",\ - "0.268, 0.268, 0.268",\ - "0.268, 0.268, 0.268"); + values("1.314, 1.332, 1.404",\ + "1.314, 1.332, 1.404",\ + "1.314, 1.332, 1.404"); } cell_fall(CELL_TABLE) { - values("0.268, 0.268, 0.268",\ - "0.268, 0.268, 0.268",\ - "0.268, 0.268, 0.268"); + values("1.314, 1.332, 1.404",\ + "1.314, 1.332, 1.404",\ + "1.314, 1.332, 1.404"); } rise_transition(CELL_TABLE) { - values("0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004"); + values("0.006, 0.008, 0.015",\ + "0.006, 0.008, 0.015",\ + "0.006, 0.008, 0.015"); } fall_transition(CELL_TABLE) { - values("0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004",\ - "0.004, 0.004, 0.004"); + values("0.006, 0.008, 0.015",\ + "0.006, 0.008, 0.015",\ + "0.006, 0.008, 0.015"); } } } @@ -164,7 +176,7 @@ cell (sram_2_16_1_scn4m_subm){ bus(addr0){ bus_type : addr; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; max_transition : 0.4; pin(addr0[3:0]){ timing(){ @@ -200,7 +212,7 @@ cell (sram_2_16_1_scn4m_subm){ pin(csb0){ direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -233,7 +245,7 @@ cell (sram_2_16_1_scn4m_subm){ pin(web0){ direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){ pin(clk0){ clock : true; direction : input; - capacitance : 9.8242; + capacitance : 0.0098242; internal_power(){ - when : "!csb0 & clk0 & !web0"; + when : "!csb0 & !web0"; rise_power(scalar){ - values("11.3049604371"); + values("7.017537e+00"); } fall_power(scalar){ - values("11.3049604371"); + values("7.017537e+00"); } } internal_power(){ - when : "!csb0 & !clk0 & web0"; + when : "csb0 & !web0"; rise_power(scalar){ - values("11.3049604371"); + values("7.017537e+00"); } fall_power(scalar){ - values("11.3049604371"); + values("7.017537e+00"); } } internal_power(){ - when : "csb0"; + when : "!csb0 & web0"; rise_power(scalar){ - values("0"); + values("7.017537e+00"); } fall_power(scalar){ - values("0"); + values("7.017537e+00"); + } + } + internal_power(){ + when : "csb0 & web0"; + rise_power(scalar){ + values("7.017537e+00"); + } + fall_power(scalar){ + values("7.017537e+00"); } } timing(){ timing_type :"min_pulse_width"; related_pin : clk0; rise_constraint(scalar) { - values("0.0"); + values("0.1405"); } fall_constraint(scalar) { - values("0.0"); + values("0.1405"); } } timing(){ timing_type :"minimum_period"; related_pin : clk0; rise_constraint(scalar) { - values("0"); + values("0.281"); } fall_constraint(scalar) { - values("0"); + values("0.281"); } } } From 32576fb62c9ac7a69518f7fe1714eeb1de42d912 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 22 Apr 2020 13:27:50 -0700 Subject: [PATCH 297/521] Convert wordline driver to pand2 rather than pnand2+pdriver --- compiler/modules/control_logic.py | 2 +- compiler/modules/hierarchical_decoder.py | 1 - compiler/modules/wordline_driver.py | 119 ++++++++++------------- compiler/pgates/pand2.py | 3 +- 4 files changed, 54 insertions(+), 71 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index b4c7402e..5dd8182e 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -90,7 +90,7 @@ class control_logic(design.design): self.add_mod(self.ctrl_dff_array) self.and2 = factory.create(module_type="pand2", - size=4, + size=12, height=dff_height) self.add_mod(self.and2) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index f46849c6..69822149 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -32,7 +32,6 @@ class hierarchical_decoder(design.design): self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple except AttributeError: self.cell_multiple = 1 - # For debugging self.cell_height = self.cell_multiple * b.height self.num_outputs = num_outputs diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index d84457ba..76a31074 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -7,10 +7,12 @@ # import debug import design +import math import contact from vector import vector from sram_factory import factory from globals import OPTS +from tech import cell_properties class wordline_driver(design.design): @@ -26,6 +28,13 @@ class wordline_driver(design.design): self.rows = rows self.cols = cols + + b = factory.create(module_type="bitcell") + try: + self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple + except AttributeError: + self.cell_multiple = 1 + self.cell_height = self.cell_multiple * b.height self.create_netlist() if not OPTS.netlist_only: @@ -37,6 +46,7 @@ class wordline_driver(design.design): self.create_drivers() def create_layout(self): + self.setup_layout_constants() self.place_drivers() self.route_layout() self.route_vdd_gnd() @@ -56,17 +66,10 @@ class wordline_driver(design.design): self.add_pin("gnd", "GROUND") def add_modules(self): - b = factory.create(module_type="bitcell") - - self.inv = factory.create(module_type="pdriver", - fanout=self.cols, - neg_polarity=True, - height=b.height) - self.add_mod(self.inv) - - self.nand2 = factory.create(module_type="pnand2", - height=b.height) - self.add_mod(self.nand2) + self.and2 = factory.create(module_type="pand2", + height=self.cell_height, + size=self.cols) + self.add_mod(self.and2) def route_vdd_gnd(self): """ @@ -75,68 +78,64 @@ class wordline_driver(design.design): """ # Find the x offsets for where the vias/pins should be placed - a_xoffset = self.nand_inst[0].lx() + xoffset_list = [self.and_inst[0].lx()] for num in range(self.rows): # this will result in duplicate polygons for rails, but who cares - # use the inverter offset even though it will be the nand's too + # use the inverter offset even though it will be the and's too (gate_offset, y_dir) = self.get_gate_offset(0, - self.inv.height, + self.and2.height, num) - # Route both supplies for name in ["vdd", "gnd"]: - supply_pin = self.inv2_inst[num].get_pin(name) + supply_pin = self.and_inst[num].get_pin(name) # Add pins in two locations - for xoffset in [a_xoffset]: + for xoffset in xoffset_list: pin_pos = vector(xoffset, supply_pin.cy()) self.add_power_pin(name, pin_pos) def create_drivers(self): - self.nand_inst = [] - self.inv2_inst = [] + self.and_inst = [] for row in range(self.rows): - name_nand = "wl_driver_nand{}".format(row) - name_inv2 = "wl_driver_inv{}".format(row) + name_and = "wl_driver_and{}".format(row) - # add nand 2 - self.nand_inst.append(self.add_inst(name=name_nand, - mod=self.nand2)) + # add and2 + self.and_inst.append(self.add_inst(name=name_and, + mod=self.and2)) self.connect_inst(["en", "in_{0}".format(row), - "wl_bar_{0}".format(row), - "vdd", "gnd"]) - # add inv2 - self.inv2_inst.append(self.add_inst(name=name_inv2, - mod=self.inv)) - self.connect_inst(["wl_bar_{0}".format(row), "wl_{0}".format(row), "vdd", "gnd"]) + + def setup_layout_constants(self): + # We may have more than one bitcell per decoder row + self.num_rows = math.ceil(self.rows / self.cell_multiple) + # We will place this many final decoders per row + self.decoders_per_row = math.ceil(self.rows / self.num_rows) def place_drivers(self): - nand2_xoffset = 2 * self.m1_width + 5 * self.m1_space - inv2_xoffset = nand2_xoffset + self.nand2.width + and2_xoffset = 2 * self.m1_width + 5 * self.m1_space - self.width = inv2_xoffset + self.inv.width - self.height = self.inv.height * self.rows + self.width = and2_xoffset + self.and2.width + self.height = self.and2.height * self.num_rows for row in range(self.rows): + #row = math.floor(inst_index / self.decoders_per_row) + #dec = inst_index % self.decoders_per_row + if (row % 2): - y_offset = self.inv.height * (row + 1) + y_offset = self.and2.height * (row + 1) inst_mirror = "MX" else: - y_offset = self.inv.height * row + y_offset = self.and2.height * row inst_mirror = "R0" - nand2_offset = [nand2_xoffset, y_offset] - inv2_offset = [inv2_xoffset, y_offset] + # x_off = self.internal_routing_width + dec * and_mod.width + and2_offset = [and2_xoffset, y_offset] - # add nand 2 - self.nand_inst[row].place(offset=nand2_offset, - mirror=inst_mirror) - # add inv2 - self.inv2_inst[row].place(offset=inv2_offset, + # add and2 + self.and_inst[row].place(offset=and2_offset, mirror=inst_mirror) def route_layout(self): @@ -151,11 +150,10 @@ class wordline_driver(design.design): height=self.height) for row in range(self.rows): - nand_inst = self.nand_inst[row] - inv2_inst = self.inv2_inst[row] + and_inst = self.and_inst[row] # en connection - a_pin = nand_inst.get_pin("A") + a_pin = and_inst.get_pin("A") a_pos = a_pin.lc() clk_offset = vector(en_pin.bc().x, a_pos.y) self.add_segment_center(layer="m1", @@ -164,18 +162,10 @@ class wordline_driver(design.design): self.add_via_center(layers=self.m1_stack, offset=clk_offset) - # Nand2 out to 2nd inv - zr_pos = nand_inst.get_pin("Z").rc() - al_pos = inv2_inst.get_pin("A").lc() - # ensure the bend is in the middle - mid1_pos = vector(0.5 * (zr_pos.x + al_pos.x), zr_pos.y) - mid2_pos = vector(0.5 * (zr_pos.x + al_pos.x), al_pos.y) - self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos]) - - # connect the decoder input pin to nand2 B - b_pin = nand_inst.get_pin("B") + # connect the decoder input pin to and2 B + b_pin = and_inst.get_pin("B") b_pos = b_pin.lc() - # needs to move down since B nand input is + # needs to move down since B and input is # nearly aligned with A inv input up_or_down = self.m2_space if row % 2 else -self.m2_space input_offset = vector(0, b_pos.y + up_or_down) @@ -192,7 +182,7 @@ class wordline_driver(design.design): offset=mid_via_offset, directions=("V", "V")) - # now connect to the nand2 B + # now connect to the and2 B self.add_path("m2", [mid_via_offset, b_pos]) contact_offset = b_pos - vector(0.5 * contact.m1_via.height, 0) self.add_via_center(layers=self.m1_stack, @@ -200,7 +190,7 @@ class wordline_driver(design.design): directions=("H", "H")) # output each WL on the right - wl_offset = inv2_inst.get_pin("Z").rc() + wl_offset = and_inst.get_pin("Z").rc() self.add_layout_pin_segment_center(text="wl_{0}".format(row), layer="m1", start=wl_offset, @@ -213,13 +203,8 @@ class wordline_driver(design.design): """ stage_effort_list = [] - stage1_cout = self.inv.get_cin() - stage1 = self.nand2.get_stage_effort(stage1_cout, inp_is_rise) + stage1 = self.and2.get_stage_effort(external_cout, inp_is_rise) stage_effort_list.append(stage1) - last_stage_is_rise = stage1.is_rise - - stage2 = self.inv.get_stage_efforts(external_cout, last_stage_is_rise) - stage_effort_list.extend(stage2) return stage_effort_list @@ -228,6 +213,6 @@ class wordline_driver(design.design): Get the relative capacitance of all the enable connections in the bank """ - # The enable is connected to a nand2 for every row. - total_cin = self.nand2.get_cin() * self.rows + # The enable is connected to a and2 for every row. + total_cin = self.and2.get_cin() * self.rows return total_cin diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 995296b6..4c044f1c 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -30,13 +30,12 @@ class pand2(pgate.pgate): self.create_insts() def create_modules(self): - # Shield the cap, but have at least a stage effort of 4 self.nand = factory.create(module_type="pnand2", height=self.height) self.add_mod(self.nand) self.inv = factory.create(module_type="pdriver", neg_polarity=True, - fanout=3*self.size, + fanout=self.size, height=self.height) self.add_mod(self.inv) From fed1c0bbe10c43425bae1dd46c16775c1714e1e3 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Wed, 22 Apr 2020 16:22:34 -0700 Subject: [PATCH 298/521] s8 col mux array --- .../modules/single_level_column_mux_array.py | 115 +++++++++--------- compiler/pgates/single_level_column_mux.py | 45 ++++--- 2 files changed, 85 insertions(+), 75 deletions(-) diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 324b7415..581e20b0 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -5,17 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from math import log import design -import contact -from tech import drc import debug -import math +from tech import layer from vector import vector from sram_factory import factory from globals import OPTS import logical_effort + class single_level_column_mux_array(design.design): """ Dynamically generated column mux array. @@ -26,13 +24,20 @@ class single_level_column_mux_array(design.design): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("cols: {0} word_size: {1} bl: {2} br: {3}".format(columns, word_size, bitcell_bl, bitcell_br)) - + self.columns = columns self.word_size = word_size self.words_per_row = int(self.columns / self.word_size) self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br - + + if "li" in layer: + self.col_mux_stack = self.li_stack + self.col_mux_stack_pitch = self.li_pitch + else: + self.col_mux_stack = self.m1_stack + self.col_mux_stack_pitch = self.m1_pitch + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -49,20 +54,20 @@ class single_level_column_mux_array(design.design): self.add_modules() self.add_pins() self.create_array() - + def create_layout(self): self.setup_layout_constants() self.place_array() self.add_routing() # Find the highest shapes to determine height before adding well highest = self.find_highest_coords() - self.height = highest.y + self.height = highest.y self.add_layout_pins() - self.add_enclosure(self.mux_inst, "pwell") - + if "pwell" in layer: + self.add_enclosure(self.mux_inst, "pwell") self.add_boundary() self.DRC_LVS() - + def add_pins(self): for i in range(self.columns): self.add_pin("bl_{}".format(i)) @@ -74,23 +79,19 @@ class single_level_column_mux_array(design.design): self.add_pin("br_out_{}".format(i)) self.add_pin("gnd") - def add_modules(self): self.mux = factory.create(module_type="single_level_column_mux", bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) self.add_mod(self.mux) - def setup_layout_constants(self): - self.column_addr_size = num_of_inputs = int(self.words_per_row / 2) + self.column_addr_size = int(self.words_per_row / 2) self.width = self.columns * self.mux.width # one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br # one extra route pitch is to space from the sense amp - self.route_height = (self.words_per_row + 3)*self.m1_pitch - + self.route_height = (self.words_per_row + 3) * self.col_mux_stack_pitch - def create_array(self): self.mux_inst = [] # For every column, add a pass gate @@ -98,11 +99,11 @@ class single_level_column_mux_array(design.design): name = "XMUX{0}".format(col_num) self.mux_inst.append(self.add_inst(name=name, mod=self.mux)) - + self.connect_inst(["bl_{}".format(col_num), "br_{}".format(col_num), - "bl_out_{}".format(int(col_num/self.words_per_row)), - "br_out_{}".format(int(col_num/self.words_per_row)), + "bl_out_{}".format(int(col_num / self.words_per_row)), + "br_out_{}".format(int(col_num / self.words_per_row)), "sel_{}".format(col_num % self.words_per_row), "gnd"]) @@ -117,32 +118,31 @@ class single_level_column_mux_array(design.design): else: mirror = "" - name = "XMUX{0}".format(col_num) offset = vector(xoffset, self.route_height) self.mux_inst[col_num].place(offset=offset, mirror=mirror) - def add_layout_pins(self): """ Add the pins after we determine the height. """ # For every column, add a pass gate for col_num in range(self.columns): mux_inst = self.mux_inst[col_num] - offset = mux_inst.get_pin("bl").ll() + bl_pin = mux_inst.get_pin("bl") + offset = bl_pin.ll() self.add_layout_pin(text="bl_{}".format(col_num), - layer="m2", + layer=bl_pin.layer, offset=offset, - height=self.height-offset.y) + height=self.height - offset.y) - offset = mux_inst.get_pin("br").ll() + br_pin = mux_inst.get_pin("br") + offset = br_pin.ll() self.add_layout_pin(text="br_{}".format(col_num), - layer="m2", + layer=br_pin.layer, offset=offset, - height=self.height-offset.y) + height=self.height - offset.y) for inst in self.mux_inst: self.copy_layout_pin(inst, "gnd") - def add_routing(self): self.add_horizontal_input_rail() self.add_vertical_poly_rail() @@ -151,15 +151,15 @@ class single_level_column_mux_array(design.design): def add_horizontal_input_rail(self): """ Create address input rails on M1 below the mux transistors """ for j in range(self.words_per_row): - offset = vector(0, self.route_height + (j-self.words_per_row)*self.m1_pitch) + offset = vector(0, self.route_height + (j - self.words_per_row) * self.col_mux_stack_pitch) #edit self.add_layout_pin(text="sel_{}".format(j), - layer="m1", + layer=self.col_mux_stack[0], offset=offset, width=self.mux.width * self.columns) def add_vertical_poly_rail(self): """ Connect the poly to the address rails """ - + # Offset to the first transistor gate in the pass gate for col in range(self.columns): # which select bit should this column connect to depends on the position in the word @@ -167,11 +167,12 @@ class single_level_column_mux_array(design.design): # Add the column x offset to find the right select bit gate_offset = self.mux_inst[col].get_pin("sel").bc() # height to connect the gate to the correct horizontal row - sel_height = self.get_pin("sel_{}".format(sel_index)).by() + # sel_height = self.get_pin("sel_{}".format(sel_index)).by() # use the y offset from the sel pin and the x offset from the gate - offset = vector(gate_offset.x,self.get_pin("sel_{}".format(sel_index)).cy()) + offset = vector(gate_offset.x, + self.get_pin("sel_{}".format(sel_index)).cy()) # Add the poly contact with a shift to account for the rotation - self.add_via_center(layers=("m1", "contact", "poly"), + self.add_via_center(layers=self.poly_stack, offset=offset) self.add_path("poly", [offset, gate_offset]) @@ -182,11 +183,11 @@ class single_level_column_mux_array(design.design): bl_offset = self.mux_inst[j].get_pin("bl_out").bc() br_offset = self.mux_inst[j].get_pin("br_out").bc() - bl_out_offset = bl_offset - vector(0,(self.words_per_row+1)*self.m1_pitch) - br_out_offset = br_offset - vector(0,(self.words_per_row+2)*self.m1_pitch) + bl_out_offset = bl_offset - vector(0, (self.words_per_row + 1) * self.col_mux_stack_pitch) + br_out_offset = br_offset - vector(0, (self.words_per_row + 2) * self.col_mux_stack_pitch) - bl_out_offset_end = bl_out_offset + vector(0,self.route_height) - br_out_offset_end = br_out_offset + vector(0,self.route_height) + bl_out_offset_end = bl_out_offset + vector(0, self.route_height) + br_out_offset_end = br_out_offset + vector(0, self.route_height) if cell_properties.bitcell.mirror.y and j % 2: tmp_bl_out_end = br_out_offset_end @@ -208,43 +209,41 @@ class single_level_column_mux_array(design.design): else: dist = 0 - self.add_path("m1", [bl_out_offset, bl_out_offset+vector(width+dist,0)]) - self.add_path("m1", [br_out_offset, br_out_offset+vector(width-dist,0)]) + self.add_path(self.col_mux_stack[0], [bl_out_offset, bl_out_offset + vector(width + dist, 0)]) + self.add_path(self.col_mux_stack[0], [br_out_offset, br_out_offset + vector(width - dist, 0)]) # Extend the bitline output rails and gnd downward on the first bit of each n-way mux - self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j/self.words_per_row)), - layer="m2", + self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j / self.words_per_row)), + layer=self.col_mux_stack[2], start=bl_out_offset, end=tmp_bl_out_end) - self.add_layout_pin_segment_center(text="br_out_{}".format(int(j/self.words_per_row)), - layer="m2", + self.add_layout_pin_segment_center(text="br_out_{}".format(int(j / self.words_per_row)), + layer=self.col_mux_stack[2], start=br_out_offset, end=tmp_br_out_end) - - # This via is on the right of the wire - self.add_via_center(layers=self.m1_stack, + # This via is on the right of the wire + self.add_via_center(layers=self.col_mux_stack, offset=bl_out_offset) # This via is on the left of the wire - self.add_via_center(layers=self.m1_stack, + self.add_via_center(layers=self.col_mux_stack, offset=br_out_offset) else: - - self.add_path("m2", [ bl_out_offset, tmp_bl_out_end]) - self.add_path("m2", [ br_out_offset, tmp_br_out_end]) - + self.add_path(self.col_mux_stack[2], [bl_out_offset, bl_offset]) + self.add_path(self.col_mux_stack[2], [br_out_offset, br_offset]) + # This via is on the right of the wire - self.add_via_center(layers=self.m1_stack, + self.add_via_center(layers=self.col_mux_stack, offset=bl_out_offset) - # This via is on the left of the wire - self.add_via_center(layers=self.m1_stack, + # This via is on the left of the wire + self.add_via_center(layers=self.col_mux_stack, offset=br_out_offset) def get_drain_cin(self): """Get the relative capacitance of the drain of the NMOS pass TX""" from tech import parameter - #Bitcell drain load being used to estimate mux NMOS drain load + # Bitcell drain load being used to estimate mux NMOS drain load drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap']) - return drain_load + return drain_load diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 288894aa..9e38287f 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -121,13 +121,25 @@ class single_level_column_mux(pgate.pgate): # height is the distance between the nmos' diffusions, which depends on max(self.active_space,self.poly_space) offset = self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active) height = self.nmos_upper.get_pin("G").by() + self.poly_extend_active - offset.y - self.add_layout_pin(text="sel", - layer="poly", + self.add_rect(layer="poly", offset=offset, height=height) + # Add the sel pin to the bottom of the mux + self.add_layout_pin(text="sel", + layer="poly", + offset=self.nmos_lower.get_pin("G").ll(), + height=self.poly_extend_active) + def connect_bitlines(self): """ Connect the bitlines to the mux transistors """ + + # If li exists, use li and m1 for the mux, otherwise use m1 and m2 + if "li" in layer: + self.col_mux_stack = self.li_stack + else: + self.col_mux_stack = self.m1_stack + # These are on metal2 bl_pin = self.get_pin("bl") br_pin = self.get_pin("br") @@ -140,29 +152,24 @@ class single_level_column_mux(pgate.pgate): nmos_upper_s_pin = self.nmos_upper.get_pin("S") nmos_upper_d_pin = self.nmos_upper.get_pin("D") - # If li exists, use li and m1 for the mux, otherwise use m1 and m2 - if "li" in layer: - col_mux_stack = self.li_stack - else: - col_mux_stack = self.m1_stack - # Add vias to bl, br_out, nmos_upper/S, nmos_lower/D - self.add_via_center(layers=col_mux_stack, + self.add_via_center(layers=self.col_mux_stack, offset=bl_pin.bc(), directions=("V", "V")) - self.add_via_center(layers=col_mux_stack, + self.add_via_center(layers=self.col_mux_stack, offset=br_out_pin.uc(), directions=("V", "V")) - self.add_via_center(layers=col_mux_stack, + self.add_via_center(layers=self.col_mux_stack, offset=nmos_upper_s_pin.center(), directions=("V", "V")) - self.add_via_center(layers=col_mux_stack, + self.add_via_center(layers=self.col_mux_stack, offset=nmos_lower_d_pin.center(), directions=("V", "V")) # Add diffusion contacts # These were previously omitted with the options: add_source_contact=False, add_drain_contact=False - # They are added now and not previously due to a s8 tech special case in which the contacts intersected the mux intraconnect + # They are added now and not previously so that they do not include m1 (which is usually included by default) + # This is only a concern when the local interconnect (li) layer is being used self.add_via_center(layers=self.active_stack, offset=nmos_upper_d_pin.center(), directions=("V", "V"), @@ -186,7 +193,7 @@ class single_level_column_mux(pgate.pgate): # bl -> nmos_upper/D on metal1 # bl_out -> nmos_upper/S on metal2 - self.add_path(col_mux_stack[0], + self.add_path(self.col_mux_stack[0], [bl_pin.ll(), vector(nmos_upper_d_pin.cx(), bl_pin.by()), nmos_upper_d_pin.center()]) # halfway up, move over @@ -194,12 +201,12 @@ class single_level_column_mux(pgate.pgate): + nmos_upper_s_pin.bc().scale(0, 0.4) mid2 = bl_out_pin.uc().scale(0, 0.4) \ + nmos_upper_s_pin.bc().scale(1, 0.4) - self.add_path(col_mux_stack[2], + self.add_path(self.col_mux_stack[2], [bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.center()]) # br -> nmos_lower/D on metal2 # br_out -> nmos_lower/S on metal1 - self.add_path(col_mux_stack[0], + self.add_path(self.col_mux_stack[0], [br_out_pin.uc(), vector(nmos_lower_s_pin.cx(), br_out_pin.uy()), nmos_lower_s_pin.center()]) @@ -208,7 +215,7 @@ class single_level_column_mux(pgate.pgate): + nmos_lower_d_pin.uc().scale(0,0.5) mid2 = br_pin.bc().scale(0,0.5) \ + nmos_lower_d_pin.uc().scale(1,0.5) - self.add_path(col_mux_stack[2], + self.add_path(self.col_mux_stack[2], [br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()]) def add_wells(self): @@ -225,6 +232,10 @@ class single_level_column_mux(pgate.pgate): implant_type="p", well_type="p") + # If there is a li layer, include it in the power stack + self.add_via_center(layers=self.col_mux_stack, + offset=active_pos) + # Add the M1->..->power_grid_layer stack self.add_power_pin(name = "gnd", loc = active_pos, From 1b6634bb9742ebc3be700e93d1fe6d50033f2d21 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Wed, 29 Apr 2020 15:48:15 -0700 Subject: [PATCH 299/521] port data routing fix --- compiler/base/hierarchy_layout.py | 19 +++++++++++++++---- compiler/modules/port_data.py | 19 +++++++++---------- 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e6f9ac9f..03d0116e 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -905,8 +905,11 @@ class layout(): max_x = max([pin.center().x for pin in pins]) min_x = min([pin.center().x for pin in pins]) + max_x_lc = max([pin.lc().x for pin in pins]) + min_x_rc = min([pin.rc().x for pin in pins]) + # if we are less than a pitch, just create a non-preferred layer jog - if max_x-min_x <= pitch: + if max_x - min_x <= pitch: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)] # Add the horizontal trunk on the vertical layer! @@ -927,7 +930,15 @@ class layout(): # Route each pin to the trunk for pin in pins: - mid = vector(pin.center().x, trunk_offset.y) + # If there is sufficient space, Route from the edge of the pins + # Otherwise, route from the center of the pins + if max_x_lc - min_x_rc > pitch: + if pin.center().x == max_x: + mid = vector(pin.lc().x, trunk_offset.y) + else: + mid = vector(pin.rc().x, trunk_offset.y) + else: + mid = vector(pin.center().x, trunk_offset.y) self.add_path(self.vertical_layer, [pin.center(), mid]) self.add_via_center(layers=layer_stack, offset=mid) @@ -1014,7 +1025,7 @@ class layout(): def vcg_pin_overlap(pin1, pin2, vertical, pitch): """ Check for vertical or horizontal overlap of the two pins """ - + # FIXME: If the pins are not in a row, this may break. # However, a top pin shouldn't overlap another top pin, # for example, so the @@ -1095,7 +1106,7 @@ class layout(): # list of routes to do while vcg: # from pprint import pformat - # print("VCG:\n",pformat(vcg)) + # print("VCG:\n", pformat(vcg)) # get a route from conflict graph with empty fanout set net_name = None for net_name, conflicts in vcg.items(): diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index bdf10f39..641a1349 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -19,7 +19,7 @@ class port_data(design.design): """ def __init__(self, sram_config, port, name=""): - + sram_config.set_local_config(self) self.port = port if self.write_size is not None: @@ -444,7 +444,7 @@ class port_data(design.design): def route_sense_amp_out(self, port): """ Add pins for the sense amp output """ - + for bit in range(self.word_size): data_pin = self.sense_amp_array_inst.get_pin("data_{}".format(bit)) self.add_layout_pin_rect_center(text="dout_{0}".format(bit), @@ -521,10 +521,10 @@ class port_data(design.design): insn2_start_bit = 1 if self.port == 0 else 0 - self.connect_bitlines(inst1=inst1, - inst2=inst2, - num_bits=self.num_cols, - inst2_start_bit=insn2_start_bit) + self.channel_route_bitlines(inst1=inst1, + inst2=inst2, + num_bits=self.num_cols, + inst2_start_bit=insn2_start_bit) def route_sense_amp_to_column_mux_or_precharge_array(self, port): """ Routing of BL and BR between sense_amp and column mux or precharge array """ @@ -703,7 +703,7 @@ class port_data(design.design): bitline_dirs = ("H", "V") elif bottom_names[0].layer == "m1": bitline_dirs = ("V", "H") - + route_map = list(zip(bottom_names, top_names)) self.create_horizontal_channel_route(route_map, offset, self.m1_stack, bitline_dirs) @@ -717,7 +717,7 @@ class port_data(design.design): This assumes that they have sufficient space to create a jog in the middle between the two modules (if needed). """ - + bot_inst_group, top_inst_group = self._group_bitline_instances( inst1, inst2, num_bits, inst1_bls_template, inst1_start_bit, @@ -738,9 +738,8 @@ class port_data(design.design): vector(bot_br.x, yoffset), vector(top_br.x, yoffset), top_br]) - + def graph_exclude_precharge(self): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" if self.precharge_array_inst: self.graph_inst_exclude.add(self.precharge_array_inst) - From 49918b0716d8d403e1b47e412a356db3c9c51a90 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Sat, 2 May 2020 09:44:56 +0000 Subject: [PATCH 300/521] New lib syntax for golden results --- .../tests/21_ngspice_delay_extra_rows_test.py | 46 +++++++++++-------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py index 66827ef5..22812d52 100755 --- a/compiler/tests/21_ngspice_delay_extra_rows_test.py +++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py @@ -56,27 +56,35 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.2264205], - 'delay_lh': [0.2264205], - 'leakage_power': 0.0021017429999999997, - 'min_period': 0.859, - 'read0_power': [0.3339161], - 'read1_power': [0.31329440000000003], - 'slew_hl': [0.2590786], - 'slew_lh': [0.2590786], - 'write0_power': [0.36360849999999995], - 'write1_power': [0.3486931]} + golden_data = {'slew_lh': [0.2592187], + 'slew_hl': [0.2592187], + 'delay_lh': [0.2465583], + 'disabled_write0_power': [0.1924678], + 'disabled_read0_power': [0.152483], + 'write0_power': [0.3409064], + 'disabled_read1_power': [0.1737818], + 'read0_power': [0.3096708], + 'read1_power': [0.3107916], + 'delay_hl': [0.2465583], + 'write1_power': [0.26915849999999997], + 'leakage_power': 0.002044307, + 'min_period': 0.898, + 'disabled_write1_power': [0.201411]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.85985], - 'delay_lh': [1.85985], - 'leakage_power': 0.006418553, + golden_data = {'read1_power': [12.11658], + 'write1_power': [10.52653], + 'read0_power': [11.956710000000001], + 'disabled_write0_power': [7.673665], + 'disabled_write1_power': [7.981922000000001], + 'slew_lh': [1.868836], + 'slew_hl': [1.868836], + 'delay_hl': [1.8598510000000001], + 'delay_lh': [1.8598510000000001], + 'leakage_power': 0.005457728, + 'disabled_read0_power': [5.904712], 'min_period': 6.875, - 'read0_power': [12.656310000000001], - 'read1_power': [12.11682], - 'slew_hl': [1.868942], - 'slew_lh': [1.868942], - 'write0_power': [13.978110000000001], - 'write1_power': [11.437930000000001]} + 'disabled_read1_power': [7.132159], + 'write0_power': [13.406400000000001]} else: self.assertTrue(False) # other techs fail From e30938fb66db62ed06340f45e235659f610471c8 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Sun, 3 May 2020 15:23:30 +0000 Subject: [PATCH 301/521] Spare columns working at bank level --- compiler/modules/bank.py | 34 +++++++--- compiler/modules/port_data.py | 8 +-- .../tests/19_single_bank_spare_cols_test.py | 68 +++++++++++++++++++ 3 files changed, 92 insertions(+), 18 deletions(-) create mode 100755 compiler/tests/19_single_bank_spare_cols_test.py diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 252f0945..379e03d7 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -31,6 +31,9 @@ class bank(design.design): else: self.num_wmasks = 0 + if not self.num_spare_cols: + self.num_spare_cols = 0 + if name == "": name = "bank_{0}_{1}".format(self.word_size, self.num_words) design.design.__init__(self, name) @@ -77,12 +80,12 @@ class bank(design.design): def add_pins(self): """ Adding pins for Bank module""" for port in self.read_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout{0}_{1}".format(port, bit), "OUTPUT") for port in self.all_ports: self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]), "OUTPUT") for port in self.write_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): self.add_pin("din{0}_{1}".format(port,bit), "INPUT") for port in self.all_ports: for bit in range(self.addr_size): @@ -101,6 +104,8 @@ class bank(design.design): self.add_pin("w_en{0}".format(port), "INPUT") for bit in range(self.num_wmasks): self.add_pin("bank_wmask{0}_{1}".format(port, bit), "INPUT") + for bit in range(self.num_spare_cols): + self.add_pin("spare_wen{0}_{1}".format(port, bit), "INPUT") for port in self.all_ports: self.add_pin("wl_en{0}".format(port), "INPUT") self.add_pin("vdd", "POWER") @@ -359,7 +364,7 @@ class bank(design.design): self.add_mod(self.port_data[port]) self.port_address = factory.create(module_type="port_address", - cols=self.num_cols, + cols=self.num_cols + self.num_spare_cols, rows=self.num_rows) self.add_mod(self.port_address) @@ -367,7 +372,7 @@ class bank(design.design): self.num_rbl = len(self.all_ports) self.bitcell_array = factory.create(module_type="replica_bitcell_array", - cols=self.num_cols, + cols=self.num_cols + self.num_spare_cols, rows=self.num_rows, left_rbl=1, right_rbl=1 if len(self.all_ports)>1 else 0, @@ -385,7 +390,7 @@ class bank(design.design): mod=self.bitcell_array) temp = [] - for col in range(self.num_cols): + for col in range(self.num_cols + self.num_spare_cols): for bitline in self.bitline_names: temp.append("{0}_{1}".format(bitline, col)) for rbl in range(self.num_rbl): @@ -419,14 +424,14 @@ class bank(design.design): rbl_br_name=self.bitcell_array.get_rbl_br_name(self.port_rbl_map[port]) temp.append(rbl_bl_name) temp.append(rbl_br_name) - for col in range(self.num_cols): + for col in range(self.num_cols + self.num_spare_cols): temp.append("{0}_{1}".format(self.bl_names[port], col)) temp.append("{0}_{1}".format(self.br_names[port], col)) if port in self.read_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): temp.append("dout{0}_{1}".format(port, bit)) if port in self.write_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): temp.append("din{0}_{1}".format(port, bit)) # Will be empty if no col addr lines sel_names = ["sel{0}_{1}".format(port, x) for x in range(self.num_col_addr_lines)] @@ -438,6 +443,8 @@ class bank(design.design): temp.append("w_en{0}".format(port)) for bit in range(self.num_wmasks): temp.append("bank_wmask{0}_{1}".format(port, bit)) + for bit in range(self.num_spare_cols): + temp.append("spare_wen{0}_{1}".format(port, bit)) temp.extend(["vdd", "gnd"]) self.connect_inst(temp) @@ -676,7 +683,7 @@ class bank(design.design): self.connect_bitlines(inst1=inst1, inst2=inst2, - num_bits=self.num_cols, + num_bits=self.num_cols + self.num_spare_cols, inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst2_bl_name=inst2_bl_name, @@ -691,7 +698,7 @@ class bank(design.design): def route_port_data_out(self, port): """ Add pins for the port data out """ - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): data_pin = self.port_data_inst[port].get_pin("dout_{0}".format(bit)) self.add_layout_pin_rect_center(text="dout{0}_{1}".format(port, bit), layer=data_pin.layer, @@ -712,7 +719,7 @@ class bank(design.design): def route_port_data_in(self, port): """ Connecting port data in """ - for row in range(self.word_size): + for row in range(self.word_size + self.num_spare_cols): data_name = "din_{}".format(row) din_name = "din{0}_{1}".format(port, row) self.copy_layout_pin(self.port_data_inst[port], data_name, din_name) @@ -722,6 +729,11 @@ class bank(design.design): wmask_name = "bank_wmask_{}".format(row) bank_wmask_name = "bank_wmask{0}_{1}".format(port, row) self.copy_layout_pin(self.port_data_inst[port], wmask_name, bank_wmask_name) + + for col in range(self.num_spare_cols): + sparecol_name = "spare_wen{}".format(col) + bank_sparecol_name = "spare_wen{0}_{1}".format(port, col) + self.copy_layout_pin(self.port_data_inst[port], sparecol_name, bank_sparecol_name) def channel_route_bitlines(self, inst1, inst2, num_bits, inst1_bl_name="bl_{}", inst1_br_name="br_{}", diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index c33b7639..dc551f7e 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -110,18 +110,12 @@ class port_data(design.design): self.add_pin("rbl_bl", "INOUT") self.add_pin("rbl_br", "INOUT") - for bit in range(self.num_cols): + for bit in range(self.num_cols + self.num_spare_cols): bl_name = self.get_bl_name(self.port) br_name = self.get_br_name(self.port) self.add_pin("{0}_{1}".format(bl_name, bit), "INOUT") self.add_pin("{0}_{1}".format(br_name, bit), "INOUT") - for bit in range(self.num_spare_cols): - bl_name = self.get_bl_name(self.port) - br_name = self.get_br_name(self.port) - self.add_pin("spare{0}_{1}".format(bl_name, bit), "INOUT") - self.add_pin("spare{0}_{1}".format(br_name, bit), "INOUT") - if self.port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout_{}".format(bit), "OUTPUT") diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py new file mode 100755 index 00000000..fc247bcd --- /dev/null +++ b/compiler/tests/19_single_bank_spare_cols_test.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class single_bank_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + c = sram_config(word_size=4, + num_words=16, + num_spare_cols=3) + + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) + + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 91dbbed9ba404bc951711d51f59023821e034508 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Tue, 5 May 2020 12:18:26 -0700 Subject: [PATCH 302/521] added horizontal trunk route edit to vertical trunk route --- compiler/base/hierarchy_layout.py | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 03d0116e..4f74185b 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -955,6 +955,9 @@ class layout(): max_y = max([pin.center().y for pin in pins]) min_y = min([pin.center().y for pin in pins]) + max_y_uc = max([pin.uc().y for pin in pins]) + min_y_bc = min([pin.bc().y for pin in pins]) + # if we are less than a pitch, just create a non-preferred layer jog if max_y - min_y <= pitch: @@ -978,7 +981,15 @@ class layout(): # Route each pin to the trunk for pin in pins: - mid = vector(trunk_offset.x, pin.center().y) + # If there is sufficient space, Route from the edge of the pins + # Otherwise, route from the center of the pins + if max_y_uc - min_y_bc > pitch: + if pin.center().y == max_y: + mid = vector(trunk_offset.x, pin.bc().y) + else: + mid = vector(trunk_offset.x, pin.uc().y) + else: + mid = vector(trunk_offset.x, pin.center().y) self.add_path(self.horizontal_layer, [pin.center(), mid]) self.add_via_center(layers=layer_stack, offset=mid) From 71a1dd8f38471016ef59702fea2ad90bad199ace Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 5 May 2020 16:35:51 -0700 Subject: [PATCH 303/521] fix tx binning in col mux for memories with >1 word per row --- compiler/pgates/pgate.py | 5 +++-- compiler/pgates/precharge.py | 2 +- compiler/pgates/ptx.py | 3 ++- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index a942b35f..e845f018 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -286,9 +286,10 @@ class pgate(design.design): self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width self.well_width = self.width + 2 * self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. - - def bin_width(self, tx_type, target_width): + @staticmethod + def bin_width(tx_type, target_width): + if tx_type == "nmos": bins = nmos_bins[drc("minwidth_poly")] elif tx_type == "pmos": diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 45128421..73edaa99 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -80,7 +80,7 @@ class precharge(design.design): Initializes the upper and lower pmos """ if(OPTS.tech_name == "s8"): - (self.ptx_width, self.ptx_mults) = pgate.bin_width(self, "pmos", self.ptx_width) + (self.ptx_width, self.ptx_mults) = pgate.bin_width("pmos", self.ptx_width) self.pmos = factory.create(module_type="ptx", width=self.ptx_width, mults=self.ptx_mults, diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index b4b20381..0cc3f951 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -14,7 +14,7 @@ import contact import logical_effort import os from globals import OPTS - +from pgate import pgate class ptx(design.design): """ @@ -109,6 +109,7 @@ class ptx(design.design): perimeter_sd = 2 * self.poly_width + 2 * self.tx_width if OPTS.tech_name == "s8": # s8 technology is in microns + (self.width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], self.mults, self.tx_width, From d8a51ecafb3c30b3407ae7408bd4f5b325d32b96 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 5 May 2020 21:59:28 -0700 Subject: [PATCH 304/521] remove prints, scaling bug fix --- compiler/pgates/pgate.py | 8 +++++--- compiler/pgates/ptx.py | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index e845f018..918cd17b 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -304,22 +304,24 @@ class pgate(design.design): scaled_bin = bins[0] * scaling_factor else: + base_bins = [] scaled_bins = [] scaling_factors = [] scaled_bins.append(bins[-1]) + base_bins.append(bins[-1]) scaling_factors.append(1) for width in bins[0:-1]: m = math.ceil(target_width / width) + base_bins.append(width) scaling_factors.append(m) scaled_bins.append(m * width) select = bisect_left(scaled_bins, target_width) scaling_factor = scaling_factors[select] scaled_bin = scaled_bins[select] - select = (select + 1) % len(scaled_bins) - selected_bin = bins[select] + selected_bin = base_bins[select] - debug.info(2, "binning {0} tx, target: {4}, found {1} x {2} = {3}".format(tx_type, selected_bin, scaling_factor, scaled_bin, target_width)) + debug.info(2, "binning {0} tx, target: {4}, found {1} x {2} = {3}".format(tx_type, selected_bin, scaling_factor, selected_bin * scaling_factor, target_width)) return(selected_bin, scaling_factor) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 0cc3f951..a5d9c3b5 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -109,7 +109,7 @@ class ptx(design.design): perimeter_sd = 2 * self.poly_width + 2 * self.tx_width if OPTS.tech_name == "s8": # s8 technology is in microns - (self.width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) + (self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], self.mults, self.tx_width, From e642b8521b01df689d9a55a5e6de4e72f4820d7a Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Wed, 6 May 2020 13:02:33 -0700 Subject: [PATCH 305/521] increase col_mux bitline spacing to fix cyclic vcg --- compiler/base/hierarchy_layout.py | 14 +++++++++----- compiler/pgates/single_level_column_mux.py | 15 +++++++++++++-- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 4f74185b..ffb35151 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -905,11 +905,13 @@ class layout(): max_x = max([pin.center().x for pin in pins]) min_x = min([pin.center().x for pin in pins]) + # max_x_lc & min_x_rc are for routing to/from the edge of the pins + # to increase spacing between contacts of different nets max_x_lc = max([pin.lc().x for pin in pins]) min_x_rc = min([pin.rc().x for pin in pins]) # if we are less than a pitch, just create a non-preferred layer jog - if max_x - min_x <= pitch: + if max_x_lc - min_x_rc <= pitch: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)] # Add the horizontal trunk on the vertical layer! @@ -955,11 +957,13 @@ class layout(): max_y = max([pin.center().y for pin in pins]) min_y = min([pin.center().y for pin in pins]) - max_y_uc = max([pin.uc().y for pin in pins]) - min_y_bc = min([pin.bc().y for pin in pins]) + # max_y_bc & min_y_uc are for routing to/from the edge of the pins + # to reduce spacing between contacts of different nets + max_y_bc = max([pin.bc().y for pin in pins]) + min_y_uc = min([pin.uc().y for pin in pins]) # if we are less than a pitch, just create a non-preferred layer jog - if max_y - min_y <= pitch: + if max_y_bc - min_y_uc <= pitch: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)] @@ -983,7 +987,7 @@ class layout(): for pin in pins: # If there is sufficient space, Route from the edge of the pins # Otherwise, route from the center of the pins - if max_y_uc - min_y_bc > pitch: + if max_y_bc - min_y_uc > pitch: if pin.center().y == max_y: mid = vector(trunk_offset.x, pin.bc().y) else: diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 9e38287f..0629a96c 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -11,7 +11,7 @@ from tech import drc, layer from vector import vector from sram_factory import factory import logical_effort - +from utils import round_to_grid class single_level_column_mux(pgate.pgate): """ @@ -75,6 +75,17 @@ class single_level_column_mux(pgate.pgate): bl_pos = vector(bl_pin.lx(), 0) br_pos = vector(br_pin.lx(), 0) + # The bitline input/output pins must be a least as wide as the metal pitch + # so that there is enough space to route to/from the pins. + # FIXME: bitline_metal_pitch should be greater than the horizontal metal pitch used in port_data + bitline_metal_pitch = self.width / 2 + bitline_width = br_pos.x - bl_pos.x + if bitline_width < bitline_metal_pitch: + bitline_width_increase_bl = round_to_grid((bitline_metal_pitch - bitline_width) / 2) + bitline_width_increase_br = round_to_grid((bitline_metal_pitch - bitline_width) - bitline_width_increase_bl) + bl_pos = bl_pos + vector(-bitline_width_increase_bl, 0) + br_pos = br_pos + vector( bitline_width_increase_br, 0) + # bl and br self.add_layout_pin(text="bl", layer=bl_pin.layer, @@ -133,7 +144,7 @@ class single_level_column_mux(pgate.pgate): def connect_bitlines(self): """ Connect the bitlines to the mux transistors """ - + # If li exists, use li and m1 for the mux, otherwise use m1 and m2 if "li" in layer: self.col_mux_stack = self.li_stack From 5c50cf234bade52c321bcfb502f0de6654ef2dcf Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Sat, 9 May 2020 07:56:19 +0000 Subject: [PATCH 306/521] Fixed lvs errors for spare columns --- compiler/modules/bank.py | 7 ++++++- compiler/modules/port_data.py | 37 +++++++++++++++++++++++++---------- 2 files changed, 33 insertions(+), 11 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 379e03d7..597d2fc0 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -683,11 +683,16 @@ class bank(design.design): self.connect_bitlines(inst1=inst1, inst2=inst2, - num_bits=self.num_cols + self.num_spare_cols, + num_bits=self.num_cols, inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst2_bl_name=inst2_bl_name, inst2_br_name=inst2_br_name) + + # connect spare bitlines + for i in range(self.num_spare_cols): + self.connect_bitline(inst1, inst2, inst1_bl_name.format(self.num_cols+i), "spare" + inst2_bl_name.format(i)) + self.connect_bitline(inst1, inst2, inst1_br_name.format(self.num_cols+i), "spare" + inst2_br_name.format(i)) # Connect the replica bitlines rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index dc551f7e..1d434929 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -30,7 +30,6 @@ class port_data(design.design): if self.num_spare_cols is None: self.num_spare_cols = 0 - if name == "": name = "port_data_{0}".format(self.port) design.design.__init__(self, name) @@ -110,12 +109,17 @@ class port_data(design.design): self.add_pin("rbl_bl", "INOUT") self.add_pin("rbl_br", "INOUT") - for bit in range(self.num_cols + self.num_spare_cols): + for bit in range(self.num_cols): bl_name = self.get_bl_name(self.port) br_name = self.get_br_name(self.port) self.add_pin("{0}_{1}".format(bl_name, bit), "INOUT") self.add_pin("{0}_{1}".format(br_name, bit), "INOUT") - + for bit in range(self.num_spare_cols): + bl_name = self.get_bl_name(self.port) + br_name = self.get_br_name(self.port) + self.add_pin("spare{0}_{1}".format(bl_name, bit), "INOUT") + self.add_pin("spare{0}_{1}".format(br_name, bit), "INOUT") + if self.port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout_{}".format(bit), "OUTPUT") @@ -283,8 +287,8 @@ class port_data(design.design): temp.append("{0}_{1}".format(br_name, bit)) for bit in range(self.num_spare_cols): - temp.append("sparebl{0}_{1}".format(self.port, bit)) - temp.append("sparebr{0}_{1}".format(self.port, bit)) + temp.append("spare{0}_{1}".format(bl_name, bit)) + temp.append("spare{0}_{1}".format(br_name, bit)) # Use right BLs for RBL if self.port==1: @@ -345,8 +349,8 @@ class port_data(design.design): for bit in range(self.num_spare_cols): temp.append("dout_{}".format(self.word_size + bit)) - temp.append("sparebl{0}_{1}".format(self.port, bit)) - temp.append("sparebr{0}_{1}".format(self.port, bit)) + temp.append("spare{0}_{1}".format(bl_name, bit)) + temp.append("spare{0}_{1}".format(br_name, bit)) temp.append("s_en") temp.extend(["vdd", "gnd"]) @@ -376,8 +380,8 @@ class port_data(design.design): temp.append("{0}_out_{1}".format(br_name, bit)) for bit in range(self.num_spare_cols): - temp.append("sparebl{0}_{1}".format(self.port, bit)) - temp.append("sparebr{0}_{1}".format(self.port, bit)) + temp.append("spare{0}_{1}".format(bl_name, bit)) + temp.append("spare{0}_{1}".format(br_name, bit)) if self.write_size is not None: for i in range(self.num_wmasks): @@ -675,7 +679,7 @@ class port_data(design.design): else: bit_offset=0 - for bit in range(self.num_cols + self.num_spare_cols): + for bit in range(self.num_cols): if self.precharge_array_inst: self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(bit + bit_offset), @@ -685,6 +689,19 @@ class port_data(design.design): "br_{}".format(bit)) else: debug.error("Didn't find precharge array.") + + # Copy layout pins of spare columns + for bit in range(self.num_spare_cols): + if self.precharge_array_inst: + self.copy_layout_pin(self.precharge_array_inst, + "bl_{}".format(self.num_cols + bit + bit_offset), + "sparebl_{}".format(bit)) + self.copy_layout_pin(self.precharge_array_inst, + "br_{}".format(self.num_cols + bit + bit_offset), + "sparebr_{}".format(bit)) + else: + debug.error("Didn't find precharge array.") + def route_control_pins(self): """ Add the control pins: s_en, p_en_bar, w_en """ From dd73afc983951603788246d0bb578942f68409c2 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 23 Apr 2020 14:43:54 -0700 Subject: [PATCH 307/521] Changes to allow decoder height to be a 2x multiple of bitcell height. Convert to use li layer in pgates. Fix multifinger devices with li layers. Simplify wordline driver input routing. Fix power pin direction option update. PEP8 cleanup Changes to simplify metal preferred directions and pitches. Split of control logic tests. --- compiler/base/hierarchy_layout.py | 117 +++++++---- compiler/modules/bitcell_base_array.py | 9 +- compiler/modules/delay_chain.py | 2 +- compiler/modules/hierarchical_decoder.py | 75 ++++--- compiler/modules/hierarchical_predecode.py | 83 ++++---- compiler/modules/wordline_driver.py | 94 ++++----- compiler/pgates/pand2.py | 2 +- compiler/pgates/pand3.py | 2 +- compiler/pgates/pdriver.py | 2 +- compiler/pgates/pgate.py | 37 ++-- compiler/pgates/pinv.py | 39 ++-- compiler/pgates/pnand2.py | 114 +++++------ compiler/pgates/pnand3.py | 132 +++++++------ compiler/pgates/pnor2.py | 121 ++++++------ compiler/pgates/precharge.py | 2 +- compiler/pgates/ptx.py | 186 ++++++++++-------- compiler/router/supply_grid_router.py | 110 +++++------ compiler/tests/03_ptx_3finger_nmos_test.py | 3 +- compiler/tests/03_ptx_3finger_pmos_test.py | 3 +- compiler/tests/03_ptx_4finger_nmos_test.py | 5 +- compiler/tests/03_ptx_4finger_pmos_test.py | 5 +- compiler/tests/03_ptx_no_contacts_test.py | 60 ++++++ compiler/tests/04_pinv_100x_test.py | 36 ++++ compiler/tests/16_control_logic_r_test.py | 36 ++++ ...ic_test.py => 16_control_logic_rw_test.py} | 0 compiler/tests/16_control_logic_w_test.py | 35 ++++ 26 files changed, 770 insertions(+), 540 deletions(-) create mode 100755 compiler/tests/03_ptx_no_contacts_test.py create mode 100755 compiler/tests/04_pinv_100x_test.py create mode 100755 compiler/tests/16_control_logic_r_test.py rename compiler/tests/{16_control_logic_test.py => 16_control_logic_rw_test.py} (100%) create mode 100755 compiler/tests/16_control_logic_w_test.py diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e6f9ac9f..a2761084 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -41,11 +41,18 @@ class layout(): self.visited = [] # List of modules we have already visited self.is_library_cell = False # Flag for library cells self.gds_read() + try: from tech import power_grid self.pwr_grid_layer = power_grid[0] except ImportError: self.pwr_grid_layer = "m3" + + if "li" in techlayer: + self.layer_indices = ["active", "li", "m1", "m2", "m3", "m4"] + else: + self.layer_indices = ["active", "m1", "m2", "m3", "m4"] + ############################################################ # GDS layout @@ -462,7 +469,12 @@ class layout(): def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None): """ Add a three layer via structure. """ - if not directions: + # Non-preferred directions + if directions == "nonpref": + directions = (self.get_preferred_direction(layers[2]), + self.get_preferred_direction(layers[0])) + # Preferred if not specified + elif not directions or directions == "pref": directions = (self.get_preferred_direction(layers[0]), self.get_preferred_direction(layers[2])) @@ -487,7 +499,12 @@ class layout(): accounting for mirroring and rotation. """ - if not directions: + # Non-preferred directions + if directions == "nonpref": + directions = (self.get_preferred_direction(layers[2]), + self.get_preferred_direction(layers[0])) + # Preferred if not specified + elif not directions or directions == "pref": directions = (self.get_preferred_direction(layers[0]), self.get_preferred_direction(layers[2])) @@ -513,36 +530,54 @@ class layout(): return inst def add_via_stack(self, offset, from_layer, to_layer, - direction=None, - size=[1, 1]): + directions=None, + size=[1, 1], + implant_type=None, + well_type=None): """ Punch a stack of vias from a start layer to a target layer. """ return self.__add_via_stack_internal(offset=offset, - direction=direction, + directions=directions, from_layer=from_layer, to_layer=to_layer, via_func=self.add_via, last_via=None, - size=size) + size=size, + implant_type=implant_type, + well_type=well_type) - def add_via_stack_center(self, offset, from_layer, to_layer, - direction=None, - size=[1, 1]): + def get_layer_index(self, layer_name): + """ + Return a layer index from bottom up in this tech. + """ + + return self.layer_indices.index(layer_name) + + def add_via_stack_center(self, + offset, + from_layer, + to_layer, + directions=None, + size=[1, 1], + implant_type=None, + well_type=None): """ Punch a stack of vias from a start layer to a target layer by the center coordinate accounting for mirroring and rotation. """ return self.__add_via_stack_internal(offset=offset, - direction=direction, + directions=directions, from_layer=from_layer, to_layer=to_layer, via_func=self.add_via_center, last_via=None, - size=size) + size=size, + implant_type=implant_type, + well_type=well_type) - def __add_via_stack_internal(self, offset, direction, from_layer, to_layer, - via_func, last_via, size): + def __add_via_stack_internal(self, offset, directions, from_layer, to_layer, + via_func, last_via, size, implant_type=None, well_type=None): """ Punch a stack of vias from a start layer to a target layer. Here we figure out whether to punch it up or down the stack. @@ -551,8 +586,8 @@ class layout(): if from_layer == to_layer: return last_via - from_id = int(from_layer[1]) - to_id = int(to_layer[1]) + from_id = self.get_layer_index(from_layer) + to_id = self.get_layer_index(to_layer) if from_id < to_id: # grow the stack up search_id = 0 @@ -563,19 +598,36 @@ class layout(): curr_stack = next(filter(lambda stack: stack[search_id] == from_layer, layer_stacks), None) if curr_stack is None: - raise ValueError("Cannot create via from '{0}' to '{1}'." \ - "Layer '{0}' not defined" - .format(from_layer, to_layer)) + raise ValueError("Cannot create via from '{0}' to '{1}'." + "Layer '{0}' not defined".format(from_layer, to_layer)) - via = via_func(layers=curr_stack, size=size, offset=offset, directions=direction) - return self.__add_via_stack_internal(offset=offset, - direction=direction, - from_layer=curr_stack[next_id], - to_layer=to_layer, - via_func=via_func, - last_via=via, - size=size) + via = via_func(layers=curr_stack, + size=size, + offset=offset, + directions=directions, + implant_type=implant_type, + well_type=well_type) + if from_layer == "active": + via = self.__add_via_stack_internal(offset=offset, + directions=directions, + from_layer=curr_stack[next_id], + to_layer=to_layer, + via_func=via_func, + last_via=via, + size=size, + implant_type=implant_type, + well_type=well_type) + else: + via = self.__add_via_stack_internal(offset=offset, + directions=directions, + from_layer=curr_stack[next_id], + to_layer=to_layer, + via_func=via_func, + last_via=via, + size=size) + return via + def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"): """Adds a ptx module to the design.""" import ptx @@ -1200,27 +1252,18 @@ class layout(): "supply router." .format(name, inst.name, self.pwr_grid_layer)) - def add_power_pin(self, name, loc, size=[1, 1], vertical=False, start_layer="m1"): + def add_power_pin(self, name, loc, size=[1, 1], directions=None, start_layer="m1"): """ Add a single power pin from the lowest power_grid layer down to M1 (or li) at the given center location. The starting layer is specified to determine which vias are needed. """ - # Force vdd/gnd via stack to be vertically or horizontally oriented - # Default: None, uses prefered metal directions - if vertical: - direction = ("V", "V") - elif not vertical and vertical is not None: - direction = ("H", "H") - else: - direction = None - via = self.add_via_stack_center(from_layer=start_layer, to_layer=self.pwr_grid_layer, size=size, offset=loc, - direction=direction) + directions=directions) if start_layer == self.pwr_grid_layer: self.add_layout_pin_rect_center(text=name, layer=self.pwr_grid_layer, diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 8ee9336b..a8829fc3 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -104,9 +104,9 @@ class bitcell_base_array(design.design): # For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space # Default uses prefered directions for each layer; this cell property is only currently used by s8 tech (03/20) try: - force_power_pins_vertical = cell_properties.bitcell_force_power_pins_vertical + bitcell_power_pin_directions = cell_properties.bitcell_power_pin_directions except AttributeError: - force_power_pins_vertical = None + bitcell_power_pin_directions = None # Add vdd/gnd via stacks for row in range(self.row_size): @@ -114,7 +114,10 @@ class bitcell_base_array(design.design): inst = self.cell_inst[row,col] for pin_name in ["vdd", "gnd"]: for pin in inst.get_pins(pin_name): - self.add_power_pin(name=pin_name, loc=pin.center(), vertical=force_power_pins_vertical, start_layer=pin.layer) + self.add_power_pin(name=pin_name, + loc=pin.center(), + directions=bitcell_power_pin_directions, + start_layer=pin.layer) def _adjust_x_offset(self, xoffset, col, col_offset): tempx = xoffset diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index b34974e5..ad9bc1cc 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -62,7 +62,7 @@ class delay_chain(design.design): self.add_pin("gnd", "GROUND") def add_modules(self): - self.inv = factory.create(module_type="pinv", route_output=False) + self.inv = factory.create(module_type="pinv") self.add_mod(self.inv) def create_inverters(self): diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 69822149..be3ba9c1 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -186,16 +186,25 @@ class hierarchical_decoder(design.design): self.num_rows = math.ceil(self.num_outputs / self.cell_multiple) # We will place this many final decoders per row self.decoders_per_row = math.ceil(self.num_outputs / self.num_rows) - + # Calculates height and width of row-decoder if (self.num_inputs == 4 or self.num_inputs == 5): nand_width = self.and2.width + nand_inputs = 2 else: nand_width = self.and3.width - self.internal_routing_width = self.m2_pitch * (self.total_number_of_predecoder_outputs + 1) + nand_inputs = 3 + self.internal_routing_width = self.m3_pitch * (self.total_number_of_predecoder_outputs + 1) self.row_decoder_height = self.inv.height * self.num_rows + + decoder_input_wire_height = self.decoders_per_row * nand_inputs * self.m3_pitch + #print(self.decoders_per_row, nand_inputs) + #print(decoder_input_wire_height, self.cell_height) + if decoder_input_wire_height > self.cell_height: + debug.warning("Cannot fit multi-bit decoder routes per row.") + #debug.check(decoder_input_wire_height < self.cell_height, "Cannot fit multi-bit decoder routes per row.") - self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch + self.input_routing_width = (self.num_inputs + 1) * self.m3_pitch # Calculates height and width of hierarchical decoder # Add extra pitch for good measure self.height = max(self.predecoder_height, self.row_decoder_height) + self.m3_pitch @@ -217,8 +226,8 @@ class hierarchical_decoder(design.design): input_offset=vector(min_x - self.input_routing_width, 0) input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)] - self.input_bus = self.create_vertical_pin_bus(layer="m2", - pitch=self.m2_pitch, + self.input_bus = self.create_vertical_pin_bus(layer="m3", + pitch=self.m3_pitch, offset=input_offset, names=input_bus_names, length=input_height) @@ -238,7 +247,7 @@ class hierarchical_decoder(design.design): # To prevent conflicts, we will offset each input connect so # that it aligns with the vdd/gnd rails - decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height) + decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * (self.inv.height + self.m1_pitch)) input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1) self.route_input_bus(decoder_offset, input_offset) @@ -254,7 +263,7 @@ class hierarchical_decoder(design.design): # To prevent conflicts, we will offset each input connect so # that it aligns with the vdd/gnd rails - decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height) + decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * (self.inv.height + self.m1_pitch)) input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1) self.route_input_bus(decoder_offset, input_offset) @@ -265,11 +274,15 @@ class hierarchical_decoder(design.design): vertical M2 coordinate to the predecode inputs """ - self.add_via_center(layers=self.m2_stack, - offset=input_offset) - self.add_via_center(layers=self.m2_stack, - offset=output_offset) - self.add_path(("m3"), [input_offset, output_offset]) + self.add_via_stack_center(from_layer="m2", + to_layer="m3", + offset=input_offset, + directions="nonpref") + self.add_via_stack_center(from_layer="m2", + to_layer="m3", + offset=output_offset, + directions="nonpref") + self.add_path(("m2"), [input_offset, output_offset]) def add_pins(self): """ Add the module pins """ @@ -467,8 +480,8 @@ class hierarchical_decoder(design.design): if (self.num_inputs >= 4): # This leaves an offset for the predecoder output jogs input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)] - self.predecode_bus = self.create_vertical_pin_bus(layer="m2", - pitch=self.m2_pitch, + self.predecode_bus = self.create_vertical_pin_bus(layer="m3", + pitch=self.m3_pitch, offset=vector(0, 0), names=input_bus_names, length=self.height) @@ -538,7 +551,7 @@ class hierarchical_decoder(design.design): if (output_index < self.num_outputs): row_index = math.floor(output_index / self.decoders_per_row) row_remainder = (output_index % self.decoders_per_row) - row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 1) * self.m3_pitch + row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 1) * self.m2_pitch predecode_name = "predecode_{}".format(index_A) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("A"), @@ -546,11 +559,11 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(index_B) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("B"), - row_offset + self.m3_pitch) + row_offset + self.m2_pitch) predecode_name = "predecode_{}".format(index_C) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("C"), - row_offset + 2 * self.m3_pitch) + row_offset + 2 * self.m2_pitch) output_index = output_index + 1 def route_vdd_gnd(self): @@ -590,18 +603,26 @@ class hierarchical_decoder(design.design): # If we have a single decoder per row, we can route on M1 if self.decoders_per_row == 1: rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y) - self.add_path("m1", [rail_pos, pin_pos]) - self.add_via_center(layers=self.m1_stack, - offset=rail_pos) + self.add_path("m2", [rail_pos, pin_pos]) + self.add_via_stack_center(from_layer=pin.layer, + to_layer="m2", + offset=pin_pos, + directions=("H", "H")) + self.add_via_stack_center(from_layer="m2", + to_layer="m3", + offset=rail_pos, + directions="nonpref") # If not, we must route over the decoder cells on M3 else: rail_pos = vector(self.predecode_bus[rail_name].x, y_offset) mid_pos = vector(pin_pos.x, rail_pos.y) - self.add_wire(self.m2_stack[::-1], [rail_pos, mid_pos, pin_pos]) + self.add_wire(self.m2_stack, [rail_pos, mid_pos, pin_pos]) self.add_via_center(layers=self.m2_stack, offset=rail_pos) - self.add_via_center(layers=self.m1_stack, - offset=pin_pos) + self.add_via_stack_center(from_layer=pin_pos.layer, + to_layer="m3", + offset=pin_pos, + directions="nonpref") def route_predecode_bus_inputs(self, rail_name, pin, x_offset): """ @@ -614,9 +635,11 @@ class hierarchical_decoder(design.design): mid_point1 = vector(x_offset, pin_pos.y) mid_point2 = vector(x_offset, pin_pos.y + self.inv.height / 2) rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y) - self.add_wire(self.m1_stack, [pin_pos, mid_point1, mid_point2, rail_pos]) - self.add_via_center(layers=self.m1_stack, - offset=rail_pos) + self.add_path("m1", [pin_pos, mid_point1, mid_point2, rail_pos]) + self.add_via_stack_center(from_layer="m1", + to_layer="m3", + offset=rail_pos, + directions="nonpref") def input_load(self): if self.determine_predecodes(self.num_inputs)[1]==0: diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index ccee34a9..c5fd1777 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -57,10 +57,10 @@ class hierarchical_predecode(design.design): self.height = self.number_of_outputs * self.and_mod.height # x offset for input inverters - self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch + self.x_off_inv_1 = self.number_of_inputs*self.m3_pitch # x offset to AND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches - self.x_off_and = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch + self.x_off_and = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m3_pitch # x offset to output inverters self.width = self.x_off_and + self.and_mod.width @@ -68,9 +68,9 @@ class hierarchical_predecode(design.design): def route_rails(self): """ Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """ input_names = ["in_{}".format(x) for x in range(self.number_of_inputs)] - offset = vector(0.5 * self.m2_width, self.m1_pitch) - self.input_rails = self.create_vertical_pin_bus(layer="m2", - pitch=self.m2_pitch, + offset = vector(0.5 * self.m3_width, self.m1_pitch) + self.input_rails = self.create_vertical_pin_bus(layer="m3", + pitch=self.m3_pitch, offset=offset, names=input_names, length=self.height - 2 * self.m1_pitch) @@ -78,9 +78,9 @@ class hierarchical_predecode(design.design): invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)] non_invert_names = ["A_{}".format(x) for x in range(self.number_of_inputs)] decode_names = invert_names + non_invert_names - offset = vector(self.x_off_inv_1 + self.inv.width + 2 * self.m2_pitch, self.m1_pitch) - self.decode_rails = self.create_vertical_bus(layer="m2", - pitch=self.m2_pitch, + offset = vector(self.x_off_inv_1 + self.inv.width + 2 * self.m3_pitch, self.m1_pitch) + self.decode_rails = self.create_vertical_bus(layer="m3", + pitch=self.m3_pitch, offset=offset, names=decode_names, length=self.height - 2 * self.m1_pitch) @@ -146,15 +146,15 @@ class hierarchical_predecode(design.design): # route one signal next to each vdd/gnd rail since this is # typically where the p/n devices are and there are no # pins in the and gates. - y_offset = (num + self.number_of_inputs) * self.inv.height + contact.m1_via.width + self.m1_space + y_offset = (num + self.number_of_inputs) * self.inv.height + contact.m2_via.width + self.m2_space in_pin = "in_{}".format(num) a_pin = "A_{}".format(num) in_pos = vector(self.input_rails[in_pin].x, y_offset) a_pos = vector(self.decode_rails[a_pin].x, y_offset) - self.add_path("m1", [in_pos, a_pos]) - self.add_via_center(layers=self.m1_stack, + self.add_path("m2", [in_pos, a_pos]) + self.add_via_center(layers=self.m2_stack, offset=[self.input_rails[in_pin].x, y_offset]) - self.add_via_center(layers=self.m1_stack, + self.add_via_center(layers=self.m2_stack, offset=[self.decode_rails[a_pin].x, y_offset]) def route_output_and(self): @@ -165,36 +165,43 @@ class hierarchical_predecode(design.design): z_pin = self.and_inst[num].get_pin("Z") self.add_layout_pin(text="out_{}".format(num), - layer="m1", + layer=z_pin.layer, offset=z_pin.ll(), height=z_pin.height(), width=z_pin.width()) def route_input_inverters(self): """ - Route all conections of the inputs inverters [Inputs, outputs, vdd, gnd] + Route all conections of the inputs inverters [Inputs, outputs, vdd, gnd] """ for inv_num in range(self.number_of_inputs): out_pin = "Abar_{}".format(inv_num) in_pin = "in_{}".format(inv_num) - #add output so that it is just below the vdd or gnd rail + # add output so that it is just below the vdd or gnd rail # since this is where the p/n devices are and there are no # pins in the and gates. - y_offset = (inv_num+1) * self.inv.height - 3*self.m1_space - inv_out_pos = self.in_inst[inv_num].get_pin("Z").rc() - right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(),0) - rail_pos = vector(self.decode_rails[out_pin].x,y_offset) - self.add_path("m1", [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) - self.add_via_center(layers = self.m1_stack, - offset=rail_pos) - + y_offset = (inv_num + 1) * self.inv.height - 3 * self.m1_space + inv_out_pin = self.in_inst[inv_num].get_pin("Z") + inv_out_pos = inv_out_pin.rc() + right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(), 0) + rail_pos = vector(self.decode_rails[out_pin].x, y_offset) + self.add_path(inv_out_pin.layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) + self.add_via_stack_center(from_layer=inv_out_pin.layer, + to_layer="m3", + offset=rail_pos, + directions="nonpref") - #route input - inv_in_pos = self.in_inst[inv_num].get_pin("A").lc() - in_pos = vector(self.input_rails[in_pin].x,inv_in_pos.y) - self.add_path("m1", [in_pos, inv_in_pos]) - self.add_via_center(layers=self.m1_stack, + # route input + pin = self.in_inst[inv_num].get_pin("A") + inv_in_pos = pin.lc() + in_pos = vector(self.input_rails[in_pin].x, inv_in_pos.y) + self.add_path("m2", [in_pos, inv_in_pos]) + self.add_via_stack_center(from_layer=pin.layer, + to_layer="m2", + offset=inv_in_pos, + directions="nonpref") + self.add_via_center(layers=self.m2_stack, offset=in_pos) def route_and_to_rails(self): @@ -205,17 +212,23 @@ class hierarchical_predecode(design.design): index_lst= and_input_line_combination[k] if self.number_of_inputs == 2: - gate_lst = ["A","B"] + gate_lst = ["A", "B"] else: - gate_lst = ["A","B","C"] + gate_lst = ["A", "B", "C"] # this will connect pins A,B or A,B,C - for rail_pin,gate_pin in zip(index_lst,gate_lst): - pin_pos = self.and_inst[k].get_pin(gate_pin).lc() + for rail_pin, gate_pin in zip(index_lst, gate_lst): + pin = self.and_inst[k].get_pin(gate_pin) + pin_pos = pin.center() rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y) - self.add_path("m1", [rail_pos, pin_pos]) - self.add_via_center(layers=self.m1_stack, - offset=rail_pos) + self.add_path("m2", [rail_pos, pin_pos]) + self.add_via_center(layers=self.m2_stack, + offset=rail_pos, + directions="nonpref") + self.add_via_stack_center(from_layer=pin.layer, + to_layer="m2", + offset=pin_pos, + directions=("H", "H")) def route_vdd_gnd(self): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 76a31074..3afe1c3c 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -26,8 +26,8 @@ class wordline_driver(design.design): debug.info(1, "Creating {0}".format(self.name)) self.add_comment("rows: {0} cols: {1}".format(rows, cols)) - self.rows = rows - self.cols = cols + self.bitcell_rows = rows + self.bitcell_cols = cols b = factory.create(module_type="bitcell") try: @@ -36,6 +36,11 @@ class wordline_driver(design.design): self.cell_multiple = 1 self.cell_height = self.cell_multiple * b.height + # We may have more than one bitcell per decoder row + self.num_rows = math.ceil(self.bitcell_rows / self.cell_multiple) + # We will place this many final decoders per row + self.decoders_per_row = math.ceil(self.bitcell_rows / self.num_rows) + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -56,10 +61,10 @@ class wordline_driver(design.design): def add_pins(self): # inputs to wordline_driver. - for i in range(self.rows): + for i in range(self.bitcell_rows): self.add_pin("in_{0}".format(i), "INPUT") # Outputs from wordline_driver. - for i in range(self.rows): + for i in range(self.bitcell_rows): self.add_pin("wl_{0}".format(i), "OUTPUT") self.add_pin("en", "INPUT") self.add_pin("vdd", "POWER") @@ -68,7 +73,7 @@ class wordline_driver(design.design): def add_modules(self): self.and2 = factory.create(module_type="pand2", height=self.cell_height, - size=self.cols) + size=self.bitcell_cols) self.add_mod(self.and2) def route_vdd_gnd(self): @@ -79,7 +84,7 @@ class wordline_driver(design.design): # Find the x offsets for where the vias/pins should be placed xoffset_list = [self.and_inst[0].lx()] - for num in range(self.rows): + for num in range(self.bitcell_rows): # this will result in duplicate polygons for rails, but who cares # use the inverter offset even though it will be the and's too @@ -97,32 +102,32 @@ class wordline_driver(design.design): def create_drivers(self): self.and_inst = [] - for row in range(self.rows): + for row in range(self.bitcell_rows): name_and = "wl_driver_and{}".format(row) # add and2 self.and_inst.append(self.add_inst(name=name_and, mod=self.and2)) - self.connect_inst(["en", - "in_{0}".format(row), + self.connect_inst(["in_{0}".format(row), + "en", "wl_{0}".format(row), "vdd", "gnd"]) def setup_layout_constants(self): # We may have more than one bitcell per decoder row - self.num_rows = math.ceil(self.rows / self.cell_multiple) + self.driver_rows = math.ceil(self.bitcell_rows / self.cell_multiple) # We will place this many final decoders per row - self.decoders_per_row = math.ceil(self.rows / self.num_rows) + self.decoders_per_row = math.ceil(self.bitcell_rows / self.driver_rows) def place_drivers(self): and2_xoffset = 2 * self.m1_width + 5 * self.m1_space - self.width = and2_xoffset + self.and2.width - self.height = self.and2.height * self.num_rows + self.width = and2_xoffset + self.decoders_per_row * self.and2.width + self.height = self.and2.height * self.driver_rows - for row in range(self.rows): - #row = math.floor(inst_index / self.decoders_per_row) - #dec = inst_index % self.decoders_per_row + for inst_index in range(self.bitcell_rows): + row = math.floor(inst_index / self.decoders_per_row) + dec = inst_index % self.decoders_per_row if (row % 2): y_offset = self.and2.height * (row + 1) @@ -131,12 +136,12 @@ class wordline_driver(design.design): y_offset = self.and2.height * row inst_mirror = "R0" - # x_off = self.internal_routing_width + dec * and_mod.width - and2_offset = [and2_xoffset, y_offset] + x_offset = and2_xoffset + dec * self.and2.width + and2_offset = [x_offset, y_offset] # add and2 - self.and_inst[row].place(offset=and2_offset, - mirror=inst_mirror) + self.and_inst[inst_index].place(offset=and2_offset, + mirror=inst_mirror) def route_layout(self): """ Route all of the signals """ @@ -149,45 +154,30 @@ class wordline_driver(design.design): width=self.m2_width, height=self.height) - for row in range(self.rows): - and_inst = self.and_inst[row] + for inst_index in range(self.bitcell_rows): + and_inst = self.and_inst[inst_index] + row = math.floor(inst_index / self.decoders_per_row) + dec = inst_index % self.decoders_per_row # en connection - a_pin = and_inst.get_pin("A") - a_pos = a_pin.lc() - clk_offset = vector(en_pin.bc().x, a_pos.y) - self.add_segment_center(layer="m1", - start=clk_offset, - end=a_pos) - self.add_via_center(layers=self.m1_stack, - offset=clk_offset) - - # connect the decoder input pin to and2 B b_pin = and_inst.get_pin("B") - b_pos = b_pin.lc() - # needs to move down since B and input is - # nearly aligned with A inv input - up_or_down = self.m2_space if row % 2 else -self.m2_space - input_offset = vector(0, b_pos.y + up_or_down) - base_offset = vector(clk_offset.x, input_offset.y) - contact_offset = vector(0.5 * self.m2_width + self.m2_space + 0.5 * contact.m1_via.width, 0) - mid_via_offset = base_offset + contact_offset + b_pos = b_pin.center() + clk_offset = vector(en_pin.bc().x, b_pos.y) + self.add_segment_center(layer="m2", + start=clk_offset, + end=b_pos) + self.add_via_center(layers=self.m1_stack, + offset=b_pos) + # connect the decoder input pin to and2 A + a_pin = and_inst.get_pin("A") + a_pos = a_pin.center() + a_offset = vector(clk_offset.x, a_pos.y) # must under the clk line in M1 self.add_layout_pin_segment_center(text="in_{0}".format(row), layer="m1", - start=input_offset, - end=mid_via_offset) - self.add_via_center(layers=self.m1_stack, - offset=mid_via_offset, - directions=("V", "V")) - - # now connect to the and2 B - self.add_path("m2", [mid_via_offset, b_pos]) - contact_offset = b_pos - vector(0.5 * contact.m1_via.height, 0) - self.add_via_center(layers=self.m1_stack, - offset=contact_offset, - directions=("H", "H")) + start=vector(0, a_pos.y), + end=a_pos) # output each WL on the right wl_offset = and_inst.get_pin("Z").rc() diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 4c044f1c..c042947f 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -76,7 +76,7 @@ class pand2(pgate.pgate): a2_pin = self.inv_inst.get_pin("A") mid1_point = vector(0.5 * (z1_pin.cx() + a2_pin.cx()), z1_pin.cy()) mid2_point = vector(mid1_point, a2_pin.cy()) - self.add_path("m1", + self.add_path(self.route_layer, [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()]) def add_layout_pins(self): diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index f8cc2ac3..ec0a5a31 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -77,7 +77,7 @@ class pand3(pgate.pgate): a2_pin = self.inv_inst.get_pin("A") mid1_point = vector(0.5 * (z1_pin.cx()+a2_pin.cx()), z1_pin.cy()) mid2_point = vector(mid1_point, a2_pin.cy()) - self.add_path("m1", + self.add_path(z1_pin.layer, [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()]) def add_layout_pins(self): diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 4bf654a4..6e79ae14 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -141,7 +141,7 @@ class pdriver(pgate.pgate): z_inst_list.append(self.inv_inst_list[x].get_pin("Z")) a_inst_list.append(self.inv_inst_list[x + 1].get_pin("A")) mid_point = vector(z_inst_list[x].cx(), a_inst_list[x].cy()) - self.add_path("m1", + self.add_path(self.route_layer, [z_inst_list[x].center(), mid_point, a_inst_list[x].center()]) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 918cd17b..7c294e0a 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -33,6 +33,14 @@ class pgate(design.design): # By default, we make it 10 M1 pitch tall self.height = 10*self.m1_pitch + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" + self.route_layer_width = getattr(self, "{}_width".format(self.route_layer)) + self.route_layer_space = getattr(self, "{}_space".format(self.route_layer)) + self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer)) + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -47,22 +55,21 @@ class pgate(design.design): """ Pure virtual function """ debug.error("Must over-ride create_layout.", -1) - def connect_pin_to_rail(self, inst, pin, supply): + def connect_pin_to_rail(self, inst, pin_name, supply_name): """ Connects a ptx pin to a supply rail. """ - source_pin = inst.get_pin(pin) - supply_pin = self.get_pin(supply) - if supply_pin.overlaps(source_pin): - return - - if supply == "gnd": - height = supply_pin.by() - source_pin.by() - elif supply == "vdd": - height = supply_pin.uy() - source_pin.by() - else: - debug.error("Invalid supply name.", -1) + supply_pin = self.get_pin(supply_name) - if abs(height) > 0: - self.add_rect(layer="m1", + source_pins = inst.get_pins(pin_name) + for source_pin in source_pins: + + if supply_name == "gnd": + height = supply_pin.by() - source_pin.by() + elif supply_name == "vdd": + height = supply_pin.uy() - source_pin.by() + else: + debug.error("Invalid supply name.", -1) + + self.add_rect(layer=source_pin.layer, offset=source_pin.ll(), height=height, width=source_pin.width()) @@ -346,4 +353,4 @@ class pgate(design.design): return(scaled_bins) def bin_accuracy(self, ideal_width, width): - return abs(1-(ideal_width - width)/ideal_width) \ No newline at end of file + return abs(1-(ideal_width - width)/ideal_width) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 0a26a2fd..b522227b 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -22,17 +22,17 @@ from errors import drc_error if(OPTS.tech_name == "s8"): from tech import nmos_bins, pmos_bins, accuracy_requirement + class pinv(pgate.pgate): """ Pinv generates gds of a parametrically sized inverter. The size is specified as the drive size (relative to minimum NMOS) and a beta value for choosing the pmos size. The inverter's cell height is usually the same as the 6t library cell and is measured - from center of rail to rail.. The route_output will route the - output to the right side of the cell for easier access. + from center of rail to rail. """ - def __init__(self, name, size=1, beta=parameter["beta"], height=None, route_output=True): + def __init__(self, name, size=1, beta=parameter["beta"], height=None): debug.info(2, "creating pinv structure {0} with size of {1}".format(name, @@ -43,7 +43,6 @@ class pinv(pgate.pgate): self.nmos_size = size self.pmos_size = beta * size self.beta = beta - self.route_output = False pgate.pgate.__init__(self, name, height) @@ -202,16 +201,20 @@ class pinv(pgate.pgate): width=self.nmos_width, mults=self.tx_mults, tx_type="nmos", + add_source_contact="m1", + add_drain_contact=self.route_layer, connect_poly=True, - connect_active=True) + connect_drain_active=True) self.add_mod(self.nmos) self.pmos = factory.create(module_type="ptx", width=self.pmos_width, mults=self.tx_mults, tx_type="pmos", + add_source_contact="m1", + add_drain_contact=self.route_layer, connect_poly=True, - connect_active=True) + connect_drain_active=True) self.add_mod(self.pmos) def route_supply_rails(self): @@ -220,7 +223,7 @@ class pinv(pgate.pgate): layer="m1", offset=vector(0.5 * self.width, 0), width=self.width) - + self.add_layout_pin_rect_center(text="vdd", layer="m1", offset=vector(0.5 * self.width, self.height), @@ -266,7 +269,7 @@ class pinv(pgate.pgate): Route the output (drains) together. Optionally, routes output to edge. """ - + # Get the drain pins nmos_drain_pin = self.nmos_inst.get_pin("D") pmos_drain_pin = self.pmos_inst.get_pin("D") @@ -274,24 +277,16 @@ class pinv(pgate.pgate): # Pick point at right most of NMOS and connect down to PMOS nmos_drain_pos = nmos_drain_pin.bc() pmos_drain_pos = vector(nmos_drain_pos.x, pmos_drain_pin.uc().y) - self.add_path("m1", [nmos_drain_pos, pmos_drain_pos]) + self.add_path(self.route_layer, [nmos_drain_pos, pmos_drain_pos]) # Remember the mid for the output mid_drain_offset = vector(nmos_drain_pos.x, self.output_pos.y) - if self.route_output: - # This extends the output to the edge of the cell - output_offset = mid_drain_offset.scale(0, 1) + vector(self.width, 0) - self.add_layout_pin_segment_center(text="Z", - layer="m1", - start=mid_drain_offset, - end=output_offset) - else: - # This leaves the output as an internal pin (min sized) - self.add_layout_pin_rect_center(text="Z", - layer="m1", - offset=mid_drain_offset \ - + vector(0.5 * self.m1_width, 0)) + # This leaves the output as an internal pin (min sized) + output_offset = mid_drain_offset + vector(0.5 * self.route_layer_width, 0) + self.add_layout_pin_rect_center(text="Z", + layer=self.route_layer, + offset=output_offset) def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 08024cea..713f779d 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -72,32 +72,38 @@ class pnand2(pgate.pgate): def add_ptx(self): """ Create the PMOS and NMOS transistors. """ - self.nmos_nd = factory.create(module_type="ptx", - width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - add_drain_contact=False, - connect_poly=True, - connect_active=True) - self.add_mod(self.nmos_nd) + self.nmos_left = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact="m1", + add_drain_contact="active") + self.add_mod(self.nmos_left) - self.nmos_ns = factory.create(module_type="ptx", - width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - add_source_contact=False, - connect_poly=True, - connect_active=True) - self.add_mod(self.nmos_ns) + self.nmos_right = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact="active", + add_drain_contact=self.route_layer) + self.add_mod(self.nmos_right) - self.pmos = factory.create(module_type="ptx", - width=self.pmos_width, - mults=self.tx_mults, - tx_type="pmos", - connect_poly=True, - connect_active=True) - self.add_mod(self.pmos) + self.pmos_left = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact="m1", + add_drain_contact=self.route_layer) + self.add_mod(self.pmos_left) + self.pmos_right = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact=self.route_layer, + add_drain_contact="m1") + self.add_mod(self.pmos_right) + def setup_layout_constants(self): """ Pre-compute some handy layout parameters. """ @@ -111,11 +117,11 @@ class pnand2(pgate.pgate): # Compute the other pmos2 location, # but determining offset to overlap the # source and drain pins - self.overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll() + self.overlap_offset = self.pmos_left.get_pin("D").center() - self.pmos_left.get_pin("S").center() # This is the extra space needed to ensure DRC rules # to the active contacts - extra_contact_space = max(-self.nmos_nd.get_pin("D").by(), 0) + extra_contact_space = max(-self.nmos_left.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, self.poly_extend_active + self.poly_space) @@ -138,19 +144,19 @@ class pnand2(pgate.pgate): """ self.pmos1_inst = self.add_inst(name="pnand2_pmos1", - mod=self.pmos) + mod=self.pmos_left) self.connect_inst(["vdd", "A", "Z", "vdd"]) self.pmos2_inst = self.add_inst(name="pnand2_pmos2", - mod=self.pmos) + mod=self.pmos_right) self.connect_inst(["Z", "B", "vdd", "vdd"]) self.nmos1_inst = self.add_inst(name="pnand2_nmos1", - mod=self.nmos_nd) + mod=self.nmos_left) self.connect_inst(["Z", "B", "net1", "gnd"]) self.nmos2_inst = self.add_inst(name="pnand2_nmos2", - mod=self.nmos_ns) + mod=self.nmos_right) self.connect_inst(["net1", "A", "gnd", "gnd"]) def place_ptx(self): @@ -159,35 +165,29 @@ class pnand2(pgate.pgate): to provide maximum routing in channel """ - pmos1_pos = vector(self.pmos.active_offset.x, - self.height - self.pmos.active_height \ + pmos1_pos = vector(self.pmos_left.active_offset.x, + self.height - self.pmos_left.active_height \ - self.top_bottom_space) self.pmos1_inst.place(pmos1_pos) self.pmos2_pos = pmos1_pos + self.overlap_offset self.pmos2_inst.place(self.pmos2_pos) - nmos1_pos = vector(self.pmos.active_offset.x, + nmos1_pos = vector(self.pmos_left.active_offset.x, self.top_bottom_space) self.nmos1_inst.place(nmos1_pos) self.nmos2_pos = nmos1_pos + self.overlap_offset self.nmos2_inst.place(self.nmos2_pos) - # Output position will be in between the PMOS and NMOS - self.output_pos = vector(0, - 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos_nd.active_height)) - def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies AFTER the wells are created """ - self.add_nwell_contact(self.pmos, - self.pmos2_pos + vector(self.m1_pitch, 0)) - self.add_pwell_contact(self.nmos_nd, - self.nmos2_pos + vector(self.m1_pitch, 0)) + self.add_nwell_contact(self.pmos_right, self.pmos2_pos) + self.add_pwell_contact(self.nmos_left, self.nmos2_pos) def connect_rails(self): """ Connect the nmos and pmos to its respective power rails """ @@ -200,16 +200,17 @@ class pnand2(pgate.pgate): def route_inputs(self): """ Route the A and B inputs """ - inputB_yoffset = self.nmos2_inst.uy() + 0.5 * contact.poly_contact.height + # This will help with the wells and the input/output placement + inputB_yoffset = self.pmos2_inst.by() - max(self.poly_extend_active + contact.poly_contact.height, + self.m1_space + 0.5 * contact.m1_via.height) self.route_input_gate(self.pmos2_inst, self.nmos2_inst, inputB_yoffset, "B", - position="center") + position="right") - # This will help with the wells and the input/output placement - self.inputA_yoffset = self.pmos2_inst.by() - self.poly_extend_active \ - - contact.poly_contact.height + self.inputA_yoffset = self.nmos2_inst.uy() + max(self.poly_extend_active + contact.poly_contact.height, + self.m1_space + 0.5 * contact.m1_via.height) self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, @@ -226,8 +227,7 @@ class pnand2(pgate.pgate): bottom_pin_offset = nmos_pin.center() # Output pin - c_pin = self.get_pin("B") - out_offset = vector(c_pin.cx() + self.m1_pitch, + out_offset = vector(nmos_pin.cx(), self.inputA_yoffset) # This routes on M2 @@ -251,27 +251,17 @@ class pnand2(pgate.pgate): # [top_pin_offset, mid1_offset, out_offset, # mid2_offset, bottom_pin_offset]) - # This routes on M1 + # This routes on route_layer # Midpoints of the L routes goes vertical first then horizontal mid1_offset = vector(top_pin_offset.x, out_offset.y) - # Midpoints of the L routes goes horizontal first then vertical - mid2_offset = vector(out_offset.x, bottom_pin_offset.y) - self.add_path("m1", - [top_pin_offset, mid1_offset, out_offset]) - # Route in two segments to have the width rule - self.add_path("m1", - [bottom_pin_offset, mid2_offset + vector(0.5 * self.m1_width, 0)], - width=nmos_pin.height()) - self.add_path("m1", - [mid2_offset, out_offset]) + self.add_path(self.route_layer, + [top_pin_offset, mid1_offset, out_offset, bottom_pin_offset]) # This extends the output to the edge of the cell self.add_layout_pin_rect_center(text="Z", - layer="m1", - offset=out_offset, - width=contact.m1_via.first_layer_width, - height=contact.m1_via.first_layer_height) + layer=self.route_layer, + offset=out_offset) def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 5f047fc4..20337095 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -74,48 +74,59 @@ class pnand3(pgate.pgate): def add_ptx(self): """ Create the PMOS and NMOS transistors. """ - self.nmos_nsnd = factory.create(module_type="ptx", + self.nmos_center = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact="active", + add_drain_contact="active") + self.add_mod(self.nmos_center) + + self.nmos_right = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact="active", + add_drain_contact=self.route_layer) + self.add_mod(self.nmos_right) + + self.nmos_left = factory.create(module_type="ptx", width=self.nmos_width, mults=self.tx_mults, tx_type="nmos", - add_source_contact=False, - add_drain_contact=False, - connect_poly=True, - connect_active=True) - self.add_mod(self.nmos_nsnd) - - self.nmos_ns = factory.create(module_type="ptx", - width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - add_source_contact=False, - connect_poly=True, - connect_active=True) - self.add_mod(self.nmos_ns) - - self.nmos_nd = factory.create(module_type="ptx", - width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - add_drain_contact=False, - connect_poly=True, - connect_active=True) - self.add_mod(self.nmos_nd) + add_source_contact="m1", + add_drain_contact="active") + self.add_mod(self.nmos_left) - self.pmos = factory.create(module_type="ptx", - width=self.pmos_width, - mults=self.tx_mults, - tx_type="pmos", - connect_poly=True, - connect_active=True) - self.add_mod(self.pmos) + self.pmos_left = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact="m1", + add_drain_contact=self.route_layer) + self.add_mod(self.pmos_left) + self.pmos_center = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact=self.route_layer, + add_drain_contact="m1") + self.add_mod(self.pmos_center) + + self.pmos_right = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact="m1", + add_drain_contact=self.route_layer) + self.add_mod(self.pmos_right) + def setup_layout_constants(self): """ Pre-compute some handy layout parameters. """ # Compute the overlap of the source and drain pins - overlap_xoffset = self.pmos.get_pin("D").ll().x - self.pmos.get_pin("S").ll().x - self.ptx_offset = vector(overlap_xoffset, 0) + self.ptx_offset = self.pmos_left.get_pin("D").center() - self.pmos_left.get_pin("S").center() # This is the extra space needed to ensure DRC rules # to the active contacts @@ -143,27 +154,27 @@ class pnand3(pgate.pgate): """ self.pmos1_inst = self.add_inst(name="pnand3_pmos1", - mod=self.pmos) + mod=self.pmos_left) self.connect_inst(["vdd", "A", "Z", "vdd"]) self.pmos2_inst = self.add_inst(name="pnand3_pmos2", - mod=self.pmos) + mod=self.pmos_center) self.connect_inst(["Z", "B", "vdd", "vdd"]) self.pmos3_inst = self.add_inst(name="pnand3_pmos3", - mod=self.pmos) + mod=self.pmos_right) self.connect_inst(["Z", "C", "vdd", "vdd"]) self.nmos1_inst = self.add_inst(name="pnand3_nmos1", - mod=self.nmos_nd) + mod=self.nmos_left) self.connect_inst(["Z", "C", "net1", "gnd"]) self.nmos2_inst = self.add_inst(name="pnand3_nmos2", - mod=self.nmos_nsnd) + mod=self.nmos_center) self.connect_inst(["net1", "B", "net2", "gnd"]) self.nmos3_inst = self.add_inst(name="pnand3_nmos3", - mod=self.nmos_ns) + mod=self.nmos_right) self.connect_inst(["net2", "A", "gnd", "gnd"]) def place_ptx(self): @@ -172,8 +183,8 @@ class pnand3(pgate.pgate): and lowest position to provide maximum routing in channel """ - pmos1_pos = vector(self.pmos.active_offset.x, - self.height - self.pmos.active_height - self.top_bottom_space) + pmos1_pos = vector(self.pmos_left.active_offset.x, + self.height - self.pmos_left.active_height - self.top_bottom_space) self.pmos1_inst.place(pmos1_pos) pmos2_pos = pmos1_pos + self.ptx_offset @@ -182,7 +193,7 @@ class pnand3(pgate.pgate): self.pmos3_pos = pmos2_pos + self.ptx_offset self.pmos3_inst.place(self.pmos3_pos) - nmos1_pos = vector(self.pmos.active_offset.x, + nmos1_pos = vector(self.pmos_left.active_offset.x, self.top_bottom_space) self.nmos1_inst.place(nmos1_pos) @@ -195,9 +206,9 @@ class pnand3(pgate.pgate): def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ - self.add_nwell_contact(self.pmos, + self.add_nwell_contact(self.pmos_right, self.pmos3_pos + vector(self.m1_pitch, 0)) - self.add_pwell_contact(self.nmos_ns, + self.add_pwell_contact(self.nmos_right, self.nmos3_pos + vector(self.m1_pitch, 0)) def connect_rails(self): @@ -250,14 +261,9 @@ class pnand3(pgate.pgate): # NMOS3 drain nmos3_pin = self.nmos3_inst.get_pin("D") - # midpoint for routing - mid_offset = vector(nmos3_pin.cx() + self.m1_pitch, + out_offset = vector(nmos3_pin.cx() + self.route_layer_pitch, self.inputA_yoffset) - # Aligned with the well taps - out_offset = vector(self.nwell_contact.cx(), - self.inputA_yoffset) - # Go up to metal2 for ease on all output pins # self.add_via_center(layers=self.m1_stack, # offset=pmos1_pin.center(), @@ -282,26 +288,24 @@ class pnand3(pgate.pgate): bottom_pin_offset = nmos3_pin.center() # PMOS1 to output - self.add_path("m1", [top_left_pin_offset, - vector(top_left_pin_offset.x, out_offset.y), - out_offset]) + self.add_path(self.route_layer, [top_left_pin_offset, + vector(top_left_pin_offset.x, out_offset.y), + out_offset]) # PMOS3 to output - self.add_path("m1", [top_right_pin_offset, - vector(top_right_pin_offset.x, mid_offset.y), - mid_offset]) + self.add_path(self.route_layer, [top_right_pin_offset, + vector(top_right_pin_offset.x, out_offset.y), + out_offset]) # NMOS3 to output - mid2_offset = vector(mid_offset.x, bottom_pin_offset.y) - self.add_path("m1", + mid2_offset = vector(out_offset.x, bottom_pin_offset.y) + self.add_path(self.route_layer, [bottom_pin_offset, mid2_offset], width=nmos3_pin.height()) - mid3_offset = vector(mid_offset.x, nmos3_pin.by()) - self.add_path("m1", [mid3_offset, mid_offset]) + mid3_offset = vector(out_offset.x, nmos3_pin.by()) + self.add_path(self.route_layer, [mid3_offset, out_offset]) self.add_layout_pin_rect_center(text="Z", - layer="m1", - offset=out_offset, - width=contact.m1_via.first_layer_width, - height=contact.m1_via.first_layer_height) + layer=self.route_layer, + offset=out_offset) def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 225a795c..3ba7d9fd 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -71,31 +71,37 @@ class pnor2(pgate.pgate): def add_ptx(self): """ Create the PMOS and NMOS transistors. """ - self.nmos = factory.create(module_type="ptx", - width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - connect_poly=True, - connect_active=True) - self.add_mod(self.nmos) + self.nmos_left = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact="m1", + add_drain_contact=self.route_layer) + self.add_mod(self.nmos_left) - self.pmos_nd = factory.create(module_type="ptx", - width=self.pmos_width, - mults=self.tx_mults, - tx_type="pmos", - add_drain_contact=False, - connect_poly=True, - connect_active=True) - self.add_mod(self.pmos_nd) + self.nmos_right = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact=self.route_layer, + add_drain_contact="m1") + self.add_mod(self.nmos_right) + + self.pmos_left = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact="m1", + add_drain_contact="active") + self.add_mod(self.pmos_left) - self.pmos_ns = factory.create(module_type="ptx", - width=self.pmos_width, - mults=self.tx_mults, - tx_type="pmos", - add_source_contact=False, - connect_poly=True, - connect_active=True) - self.add_mod(self.pmos_ns) + self.pmos_right = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact="active", + add_drain_contact=self.route_layer) + self.add_mod(self.pmos_right) def setup_layout_constants(self): """ Pre-compute some handy layout parameters. """ @@ -108,12 +114,12 @@ class pnor2(pgate.pgate): # Compute the other pmos2 location, but determining # offset to overlap the source and drain pins - self.overlap_offset = self.pmos_ns.get_pin("D").ll() - self.pmos_nd.get_pin("S").ll() + self.overlap_offset = self.pmos_right.get_pin("D").center() - self.pmos_left.get_pin("S").center() # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.width = 2 * self.pmos_ns.active_width \ - + self.pmos_ns.active_contact.width \ + self.width = 2 * self.pmos_right.active_width \ + + self.pmos_right.active_contact.width \ + 2 * self.active_space \ + 0.5 * self.nwell_enclose_active self.well_width = self.width + 2 * self.nwell_enclose_active @@ -121,7 +127,7 @@ class pnor2(pgate.pgate): # This is the extra space needed to ensure DRC rules # to the active contacts - extra_contact_space = max(-self.nmos.get_pin("D").by(), 0) + extra_contact_space = max(-self.nmos_right.get_pin("D").by(), 0) # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, self.poly_extend_active, @@ -146,19 +152,19 @@ class pnor2(pgate.pgate): """ self.pmos1_inst = self.add_inst(name="pnor2_pmos1", - mod=self.pmos_nd) + mod=self.pmos_left) self.connect_inst(["vdd", "A", "net1", "vdd"]) self.pmos2_inst = self.add_inst(name="pnor2_pmos2", - mod=self.pmos_ns) + mod=self.pmos_right) self.connect_inst(["net1", "B", "Z", "vdd"]) self.nmos1_inst = self.add_inst(name="pnor2_nmos1", - mod=self.nmos) + mod=self.nmos_left) self.connect_inst(["Z", "A", "gnd", "gnd"]) self.nmos2_inst = self.add_inst(name="pnor2_nmos2", - mod=self.nmos) + mod=self.nmos_right) self.connect_inst(["Z", "B", "gnd", "gnd"]) def place_ptx(self): @@ -167,29 +173,26 @@ class pnor2(pgate.pgate): to provide maximum routing in channel """ - pmos1_pos = vector(self.pmos_ns.active_offset.x, - self.height - self.pmos_ns.active_height \ + pmos1_pos = vector(self.pmos_right.active_offset.x, + self.height - self.pmos_right.active_height \ - self.top_bottom_space) self.pmos1_inst.place(pmos1_pos) self.pmos2_pos = pmos1_pos + self.overlap_offset self.pmos2_inst.place(self.pmos2_pos) - nmos1_pos = vector(self.pmos_ns.active_offset.x, self.top_bottom_space) + nmos1_pos = vector(self.pmos_right.active_offset.x, self.top_bottom_space) self.nmos1_inst.place(nmos1_pos) self.nmos2_pos = nmos1_pos + self.overlap_offset self.nmos2_inst.place(self.nmos2_pos) - # Output position will be in between the PMOS and NMOS - self.output_pos = vector(0, - 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height)) def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ - self.add_nwell_contact(self.pmos_ns, self.pmos2_pos) - self.add_pwell_contact(self.nmos, self.nmos2_pos) + self.add_nwell_contact(self.pmos_right, self.pmos2_pos) + self.add_pwell_contact(self.nmos_right, self.nmos2_pos) def connect_rails(self): """ Connect the nmos and pmos to its respective power rails """ @@ -208,7 +211,7 @@ class pnor2(pgate.pgate): self.nmos2_inst, inputB_yoffset, "B", - position="center") + position="right") # This will help with the wells and the input/output placement self.inputA_yoffset = inputB_yoffset + self.input_spacing @@ -217,38 +220,32 @@ class pnor2(pgate.pgate): self.inputA_yoffset, "A") + self.output_yoffset = self.inputA_yoffset + self.input_spacing + def route_output(self): """ Route the Z output """ - # PMOS2 drain + # PMOS2 (right) drain pmos_pin = self.pmos2_inst.get_pin("D") - # NMOS1 drain + # NMOS1 (left) drain nmos_pin = self.nmos1_inst.get_pin("D") - # NMOS2 drain (for output via placement) + # NMOS2 (right) drain (for output via placement) nmos2_pin = self.nmos2_inst.get_pin("D") # Go up to metal2 for ease on all output pins - self.add_via_center(layers=self.m1_stack, - offset=pmos_pin.center()) - m1m2_contact = self.add_via_center(layers=self.m1_stack, - offset=nmos_pin.center()) - - mid1_offset = vector(pmos_pin.center().x, nmos2_pin.center().y) - mid2_offset = vector(pmos_pin.center().x, self.inputA_yoffset) - mid3_offset = mid2_offset + vector(self.m2_width, 0) + # self.add_via_center(layers=self.m1_stack, + # offset=pmos_pin.center()) + # m1m2_contact = self.add_via_center(layers=self.m1_stack, + # offset=nmos_pin.center()) + mid1_offset = vector(nmos_pin.center().x, self.output_yoffset) + mid2_offset = vector(pmos_pin.center().x, self.output_yoffset) + # PMOS1 to mid-drain to NMOS2 drain - self.add_path("m2", - [pmos_pin.center(), mid2_offset, mid3_offset]) - self.add_path("m2", - [nmos_pin.rc(), mid1_offset, mid2_offset]) - # This extends the output to the edge of the cell - self.add_via_center(layers=self.m1_stack, - offset=mid3_offset) + self.add_path(self.route_layer, + [nmos_pin.center(), mid1_offset, mid2_offset, pmos_pin.center()]) self.add_layout_pin_rect_center(text="Z", - layer="m1", - offset=mid3_offset, - width=contact.m1_via.first_layer_height, - height=contact.m1_via.first_layer_width) + layer=self.route_layer, + offset=mid2_offset) def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 19aab991..b8ecb3e1 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -114,7 +114,7 @@ class precharge(design.design): self.add_power_pin("vdd", self.well_contact_pos, - vertical=True) + directions=("V", "V")) # Hack for li layers if hasattr(self, "li_stack"): diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index a5d9c3b5..6fcb722d 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -23,32 +23,44 @@ class ptx(design.design): the transistor width. Mults is the number of transistors of the given width. Total width is therefore mults*width. Options allow you to connect the fingered gates and active for parallel devices. - + The add_*_contact option tells which layer to bring source/drain up to. """ def __init__(self, name="", width=drc("minwidth_tx"), mults=1, tx_type="nmos", - add_source_contact=True, - add_drain_contact=True, + add_source_contact=None, + add_drain_contact=None, series_devices=False, - connect_active=False, + connect_drain_active=False, + connect_source_active=False, connect_poly=False, num_contacts=None): + + if not add_source_contact and "li" in layer: + add_source_contact = "li" + elif not add_source_contact: + add_source_contact = "m1" + + if not add_drain_contact and "li" in layer: + add_drain_contact = "li" + elif not add_drain_contact: + add_drain_contact = "m1" + # We need to keep unique names because outputting to GDSII # will use the last record with a given name. I.e., you will # over-write a design in GDS if one has and the other doesn't # have poly connected, for example. name = "{0}_m{1}_w{2:.3f}".format(tx_type, mults, width) - if not add_source_contact: - name += "_ns" - if not add_drain_contact: - name += "_nd" + name += "_s{}".format(add_source_contact) + name += "_d{}".format(add_drain_contact) if series_devices: name += "_sd" - if connect_active: - name += "_a" + if connect_drain_active: + name += "_da" + if connect_source_active: + name += "_sa" if connect_poly: name += "_p" if num_contacts: @@ -61,13 +73,21 @@ class ptx(design.design): self.tx_type = tx_type self.mults = mults self.tx_width = width - self.connect_active = connect_active + self.connect_drain_active = connect_drain_active + self.connect_source_active = connect_source_active self.connect_poly = connect_poly self.add_source_contact = add_source_contact self.add_drain_contact = add_drain_contact self.series_devices = series_devices self.num_contacts = num_contacts + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" + self.route_layer_width = drc("minwidth_{}".format(self.route_layer)) + self.route_layer_space = drc("{0}_to_{0}".format(self.route_layer)) + # Since it has variable height, it is not a pgate. self.create_netlist() # We must always create ptx layout for pbitcell @@ -266,55 +286,44 @@ class ptx(design.design): width=poly_width, height=self.poly_width) - def connect_fingered_active(self, drain_positions, source_positions): + def connect_fingered_active(self, positions, pin_name, layer, top): """ Connect each contact up/down to a source or drain pin """ + + if top: + dir = 1 + else: + dir = -1 + + if len(positions) <= 1: + return + + debug.check(layer != "active", "Must specify a metal for source connections.") + layer_space = getattr(self, "{}_space".format(layer)) + layer_width = getattr(self, "{}_width".format(layer)) + # This is the distance that we must route up or down from the center # of the contacts to avoid DRC violations to the other contacts pin_offset = vector(0, - 0.5 * self.active_contact.second_layer_height + self.m1_space + 0.5 * self.m1_width) + 0.5 * self.active_contact.second_layer_height + layer_space + 0.5 * layer_width) # This is the width of a m1 extend the ends of the pin - end_offset = vector(self.m1_width / 2.0, 0) + end_offset = vector(layer_width / 2.0, 0) - # drains always go to the MIDDLE of the cell, - # so top of NMOS, bottom of PMOS - # so reverse the directions for NMOS compared to PMOS. - if self.tx_type == "pmos": - drain_dir = -1 - source_dir = 1 - else: - drain_dir = 1 - source_dir = -1 - - if len(source_positions) > 1: - source_offset = pin_offset.scale(source_dir, source_dir) - # remove the individual connections - self.remove_layout_pin("S") - # Add each vertical segment - for a in source_positions: - self.add_path(("m1"), - [a, a + pin_offset.scale(source_dir, - source_dir)]) - # Add a single horizontal pin - self.add_layout_pin_segment_center(text="S", - layer="m1", - start=source_positions[0] + source_offset - end_offset, - end=source_positions[-1] + source_offset + end_offset) + offset = pin_offset.scale(dir, dir) + # remove the individual connections + self.remove_layout_pin(pin_name) + # Add each vertical segment + for a in positions: + self.add_path(self.add_source_contact, + [a, a + pin_offset.scale(dir, dir)]) + # Add a single horizontal pin + self.add_layout_pin_segment_center(text=pin_name, + layer=layer, + start=positions[0] + offset - end_offset, + end=positions[-1] + offset + end_offset) - if len(drain_positions)>1: - drain_offset = pin_offset.scale(drain_dir,drain_dir) - self.remove_layout_pin("D") # remove the individual connections - # Add each vertical segment - for a in drain_positions: - self.add_path(("m1"), [a,a+drain_offset]) - # Add a single horizontal pin - self.add_layout_pin_segment_center(text="D", - layer="m1", - start=drain_positions[0] + drain_offset - end_offset, - end=drain_positions[-1] + drain_offset + end_offset) - def add_poly(self): """ Add the poly gates(s) and (optionally) connect them. @@ -433,12 +442,12 @@ class ptx(design.design): label = "S" source_positions.append(pos) - if (label=="S" and self.add_source_contact) or (label=="D" and self.add_drain_contact): + if (label=="S" and self.add_source_contact): contact = self.add_diff_contact(label, pos) - if label == "S": - self.source_contacts.append(contact) - else: - self.drain_contacts.append(contact) + self.source_contacts.append(contact) + elif (label=="D" and self.add_drain_contact): + contact = self.add_diff_contact(label, pos) + self.drain_contacts.append(contact) else: self.add_layout_pin_rect_center(text=label, layer="active", @@ -454,19 +463,22 @@ class ptx(design.design): label = "S" source_positions.append(pos) - if (label=="S" and self.add_source_contact) or (label=="D" and self.add_drain_contact): + if (label=="S" and self.add_source_contact): contact = self.add_diff_contact(label, pos) - if label == "S": - self.source_contacts.append(contact) - else: - self.drain_contacts.append(contact) + self.source_contacts.append(contact) + elif (label=="D" and self.add_drain_contact): + contact = self.add_diff_contact(label, pos) + self.drain_contacts.append(contact) else: self.add_layout_pin_rect_center(text=label, layer="active", offset=pos) - if self.connect_active: - self.connect_fingered_active(drain_positions, source_positions) + if self.connect_source_active: + self.connect_fingered_active(source_positions, "S", self.add_source_contact, top=(self.tx_type=="pmos")) + + if self.connect_drain_active: + self.connect_fingered_active(drain_positions, "D", self.add_drain_contact, top=(self.tx_type=="nmos")) def get_stage_effort(self, cout): """Returns an object representing the parameters for delay in tau units.""" @@ -489,34 +501,36 @@ class ptx(design.design): return self.mults * self.tx_width / drc("minwidth_tx") def add_diff_contact(self, label, pos): - contact=self.add_via_center(layers=self.active_stack, - offset=pos, - size=(1, self.num_contacts), - directions=("V", "V"), - implant_type=self.implant_type, - well_type=self.well_type) - - if hasattr(self, "li_stack"): - contact=self.add_via_center(layers=self.li_stack, - offset=pos, - directions=("V", "V")) - # contact_area = contact.mod.second_layer_width * contact.mod.second_layer_height - # min_area = drc("minarea_m1") - # width = contact.mod.second_layer_width - # if contact_area < min_area: - # height = min_area / width - # else: - # height = contact.mod.second_layer_height - width = contact.mod.second_layer_width - height = contact.mod.second_layer_height + if label == "S": + layer = self.add_source_contact + elif label == "D": + layer = self.add_drain_contact + else: + debug.error("Invalid source drain name.") + + via=self.add_via_stack_center(offset=pos, + from_layer="active", + to_layer=layer, + size=(1, self.num_contacts), + directions=("V", "V"), + implant_type=self.implant_type, + well_type=self.well_type) + + if layer == "active": + source_via = getattr(contact, "{}_contact".format(layer)) + else: + source_via = getattr(contact, "{}_via".format(layer)) + # Source drain vias are all vertical + pin_height = source_via.first_layer_width + pin_width = source_via.first_layer_height self.add_layout_pin_rect_center(text=label, - layer="m1", + layer=layer, offset=pos, - width=width, - height=height) + width=pin_width, + height=pin_height) - return(contact) + return(via) def get_cin(self): """Returns the relative gate cin of the tx""" diff --git a/compiler/router/supply_grid_router.py b/compiler/router/supply_grid_router.py index b28f875e..cd7b6b7b 100644 --- a/compiler/router/supply_grid_router.py +++ b/compiler/router/supply_grid_router.py @@ -5,21 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import gdsMill -import tech -import math import debug -from globals import OPTS,print_time -from contact import contact -from pin_group import pin_group -from pin_layout import pin_layout -from vector3d import vector3d +from globals import print_time +from vector3d import vector3d from router import router from direction import direction from datetime import datetime -import grid import grid_utils + class supply_grid_router(router): """ A router class to read an obstruction map from a gds and @@ -44,14 +38,13 @@ class supply_grid_router(router): self.supply_rail_tracks = {} print_time("Init supply router", datetime.now(), start_time, 3) - def create_routing_grid(self): """ Create a sprase routing grid with A* expansion functions. """ size = self.ur - self.ll - debug.info(1,"Size: {0} x {1}".format(size.x,size.y)) + debug.info(1, "Size: {0} x {1}".format(size.x, size.y)) import supply_grid self.rg = supply_grid.supply_grid(self.ll, self.ur, self.track_width) @@ -60,12 +53,12 @@ class supply_grid_router(router): """ Add power supply rails and connect all pins to these rails. """ - debug.info(1,"Running supply router on {0} and {1}...".format(vdd_name, gnd_name)) + debug.info(1, "Running supply router on {0} and {1}...".format(vdd_name, gnd_name)) self.vdd_name = vdd_name self.gnd_name = gnd_name # Clear the pins if we have previously routed - if (hasattr(self,'rg')): + if (hasattr(self, 'rg')): self.clear_pins() else: # Creat a routing grid over the entire area @@ -76,32 +69,32 @@ class supply_grid_router(router): # Get the pin shapes start_time = datetime.now() self.find_pins_and_blockages([self.vdd_name, self.gnd_name]) - print_time("Finding pins and blockages",datetime.now(), start_time, 3) + print_time("Finding pins and blockages", datetime.now(), start_time, 3) # Add the supply rails in a mesh network and connect H/V with vias start_time = datetime.now() # Block everything self.prepare_blockages(self.gnd_name) # Determine the rail locations - self.route_supply_rails(self.gnd_name,0) + self.route_supply_rails(self.gnd_name, 0) # Block everything self.prepare_blockages(self.vdd_name) # Determine the rail locations - self.route_supply_rails(self.vdd_name,1) - print_time("Routing supply rails",datetime.now(), start_time, 3) + self.route_supply_rails(self.vdd_name, 1) + print_time("Routing supply rails", datetime.now(), start_time, 3) start_time = datetime.now() self.route_simple_overlaps(vdd_name) self.route_simple_overlaps(gnd_name) - print_time("Simple overlap routing",datetime.now(), start_time, 3) + print_time("Simple overlap routing", datetime.now(), start_time, 3) # Route the supply pins to the supply rails # Route vdd first since we want it to be shorter start_time = datetime.now() self.route_pins_to_rails(vdd_name) self.route_pins_to_rails(gnd_name) - print_time("Maze routing supplies",datetime.now(), start_time, 3) - #self.write_debug_gds("final.gds",False) + print_time("Maze routing supplies", datetime.now(), start_time, 3) + # self.write_debug_gds("final.gds", False) # Did we route everything?? if not self.check_all_routed(vdd_name): @@ -111,9 +104,8 @@ class supply_grid_router(router): return True - def check_all_routed(self, pin_name): - """ + """ Check that all pin groups are routed. """ for pg in self.pin_groups[pin_name]: @@ -125,7 +117,7 @@ class supply_grid_router(router): This checks for simple cases where a pin component already overlaps a supply rail. It will add an enclosure to ensure the overlap in wide DRC rule cases. """ - debug.info(1,"Routing simple overlap pins for {0}".format(pin_name)) + debug.info(1, "Routing simple overlap pins for {0}".format(pin_name)) # These are the wire tracks wire_tracks = self.supply_rail_tracks[pin_name] @@ -142,10 +134,10 @@ class supply_grid_router(router): continue # Else, if we overlap some of the space track, we can patch it with an enclosure - #pg.create_simple_overlap_enclosure(pg.grids) - #pg.add_enclosure(self.cell) + # pg.create_simple_overlap_enclosure(pg.grids) + # pg.add_enclosure(self.cell) - debug.info(1,"Routed {} simple overlap pins".format(routed_count)) + debug.info(1, "Routed {} simple overlap pins".format(routed_count)) def finalize_supply_rails(self, name): """ @@ -158,7 +150,7 @@ class supply_grid_router(router): connections = set() via_areas = [] - for i1,r1 in enumerate(all_rails): + for i1, r1 in enumerate(all_rails): # Only consider r1 horizontal rails e = next(iter(r1)) if e.z==1: @@ -166,9 +158,9 @@ class supply_grid_router(router): # We need to move this rail to the other layer for the z indices to match # during the intersection. This also makes a copy. - new_r1 = {vector3d(i.x,i.y,1) for i in r1} + new_r1 = {vector3d(i.x, i.y, 1) for i in r1} - for i2,r2 in enumerate(all_rails): + for i2, r2 in enumerate(all_rails): # Never compare to yourself if i1==i2: continue @@ -184,16 +176,16 @@ class supply_grid_router(router): # the overlap area for placement of a via overlap = new_r1 & r2 if len(overlap) >= 1: - debug.info(3,"Via overlap {0} {1}".format(len(overlap),overlap)) - connections.update([i1,i2]) + debug.info(3, "Via overlap {0} {1}".format(len(overlap),overlap)) + connections.update([i1, i2]) via_areas.append(overlap) # Go through and add the vias at the center of the intersection for area in via_areas: ll = grid_utils.get_lower_left(area) ur = grid_utils.get_upper_right(area) - center = (ll + ur).scale(0.5,0.5,0) - self.add_via(center,1) + center = (ll + ur).scale(0.5, 0.5, 0) + self.add_via(center, 1) # Determien which indices were not connected to anything above missing_indices = set([x for x in range(len(self.supply_rails[name]))]) @@ -204,13 +196,12 @@ class supply_grid_router(router): for rail_index in sorted(missing_indices, reverse=True): ll = grid_utils.get_lower_left(all_rails[rail_index]) ur = grid_utils.get_upper_right(all_rails[rail_index]) - debug.info(1,"Removing disconnected supply rail {0} .. {1}".format(ll,ur)) + debug.info(1, "Removing disconnected supply rail {0} .. {1}".format(ll, ur)) self.supply_rails[name].pop(rail_index) # Make the supply rails into a big giant set of grids for easy blockages. # Must be done after we determine which ones are connected. self.create_supply_track_set(name) - def add_supply_rails(self, name): """ @@ -223,7 +214,7 @@ class supply_grid_router(router): ur = grid_utils.get_upper_right(rail) z = ll.z pin = self.compute_pin_enclosure(ll, ur, z, name) - debug.info(3,"Adding supply rail {0} {1}->{2} {3}".format(name,ll,ur,pin)) + debug.info(3, "Adding supply rail {0} {1}->{2} {3}".format(name, ll, ur, pin)) self.cell.add_layout_pin(text=name, layer=pin.layer, offset=pin.ll(), @@ -243,19 +234,18 @@ class supply_grid_router(router): max_xoffset = self.rg.ur.x min_yoffset = self.rg.ll.y min_xoffset = self.rg.ll.x - # Horizontal supply rails start_offset = min_yoffset + supply_number for offset in range(start_offset, max_yoffset, 2): # Seed the function at the location with the given width - wave = [vector3d(min_xoffset,offset,0)] + wave = [vector3d(min_xoffset, offset, 0)] # While we can keep expanding east in this horizontal track while wave and wave[0].x < max_xoffset: added_rail = self.find_supply_rail(name, wave, direction.EAST) if not added_rail: # Just seed with the next one - wave = [x+vector3d(1,0,0) for x in wave] + wave = [x+vector3d(1, 0, 0) for x in wave] else: # Seed with the neighbor of the end of the last rail wave = added_rail.neighbor(direction.EAST) @@ -264,15 +254,15 @@ class supply_grid_router(router): start_offset = min_xoffset + supply_number for offset in range(start_offset, max_xoffset, 2): # Seed the function at the location with the given width - wave = [vector3d(offset,min_yoffset,1)] + wave = [vector3d(offset, min_yoffset, 1)] # While we can keep expanding north in this vertical track while wave and wave[0].y < max_yoffset: added_rail = self.find_supply_rail(name, wave, direction.NORTH) if not added_rail: # Just seed with the next one - wave = [x+vector3d(0,1,0) for x in wave] + wave = [x + vector3d(0, 1, 0) for x in wave] else: - # Seed with the neighbor of the end of the last rail + # Seed with the neighbor of the end of the last rail wave = added_rail.neighbor(direction.NORTH) def find_supply_rail(self, name, seed_wave, direct): @@ -294,7 +284,6 @@ class supply_grid_router(router): # Return the rail whether we approved it or not, # as it will be used to find the next start location return wave_path - def probe_supply_rail(self, name, start_wave, direct): """ @@ -328,23 +317,19 @@ class supply_grid_router(router): data structure. Return whether it was added or not. """ # We must have at least 2 tracks to drop plus 2 tracks for a via - if len(wave_path)>=4*self.rail_track_width: + if len(wave_path) >= 4 * self.rail_track_width: grid_set = wave_path.get_grids() self.supply_rails[name].append(grid_set) return True return False - - - - def route_supply_rails(self, name, supply_number): """ Route the horizontal and vertical supply rails across the entire design. Must be done with lower left at 0,0 """ - debug.info(1,"Routing supply rail {0}.".format(name)) + debug.info(1, "Routing supply rail {0}.".format(name)) # Compute the grid locations of the supply rails self.compute_supply_rails(name, supply_number) @@ -355,7 +340,6 @@ class supply_grid_router(router): # Add the rails themselves self.add_supply_rails(name) - def create_supply_track_set(self, pin_name): """ Make a single set of all the tracks for the rail and wire itself. @@ -364,24 +348,22 @@ class supply_grid_router(router): for rail in self.supply_rails[pin_name]: rail_set.update(rail) self.supply_rail_tracks[pin_name] = rail_set - - def route_pins_to_rails(self, pin_name): """ - This will route each of the remaining pin components to the supply rails. + This will route each of the remaining pin components to the supply rails. After it is done, the cells are added to the pin blockage list. """ remaining_components = sum(not x.is_routed() for x in self.pin_groups[pin_name]) - debug.info(1,"Maze routing {0} with {1} pin components to connect.".format(pin_name, - remaining_components)) + debug.info(1, "Maze routing {0} with {1} pin components to connect.".format(pin_name, + remaining_components)) - for index,pg in enumerate(self.pin_groups[pin_name]): + for index, pg in enumerate(self.pin_groups[pin_name]): if pg.is_routed(): continue - debug.info(3,"Routing component {0} {1}".format(pin_name, index)) + debug.info(3, "Routing component {0} {1}".format(pin_name, index)) # Clear everything in the routing grid. self.rg.reinit() @@ -400,28 +382,26 @@ class supply_grid_router(router): # Actually run the A* router if not self.run_router(detour_scale=5): - self.write_debug_gds("debug_route.gds",False) + self.write_debug_gds("debug_route.gds", False) - #if index==3 and pin_name=="vdd": - # self.write_debug_gds("route.gds",False) + # if index==3 and pin_name=="vdd": + # self.write_debug_gds("route.gds",False) - def add_supply_rail_target(self, pin_name): """ Add the supply rails of given name as a routing target. """ - debug.info(4,"Add supply rail target {}".format(pin_name)) + debug.info(4, "Add supply rail target {}".format(pin_name)) # Add the wire itself as the target self.rg.set_target(self.supply_rail_tracks[pin_name]) # But unblock all the rail tracks including the space - self.rg.set_blocked(self.supply_rail_tracks[pin_name],False) - + self.rg.set_blocked(self.supply_rail_tracks[pin_name], False) def set_supply_rail_blocked(self, value=True): """ Add the supply rails of given name as a routing target. """ - debug.info(4,"Blocking supply rail") + debug.info(4, "Blocking supply rail") for rail_name in self.supply_rail_tracks: self.rg.set_blocked(self.supply_rail_tracks[rail_name]) diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index 95700e8f..0b24ffd5 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -27,7 +27,8 @@ class ptx_3finger_nmos_test(openram_test): width=tech.drc["minwidth_tx"], mults=3, tx_type="nmos", - connect_active=True, + connect_source_active=True, + connect_drain_active=True, connect_poly=True) self.local_drc_check(fet) diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 8c09cf9b..ccb8b586 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -27,7 +27,8 @@ class ptx_3finger_pmos_test(openram_test): width=tech.drc["minwidth_tx"], mults=3, tx_type="pmos", - connect_active=True, + connect_source_active=True, + connect_drain_active=True, connect_poly=True) self.local_drc_check(fet) diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index da9e438d..f7f3db78 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -23,11 +23,12 @@ class ptx_4finger_nmos_test(openram_test): import tech debug.info(2, "Checking three fingers NMOS") - fet = factory.create(module_type="ptx", + fet = factory.create(module_type="ptx", width= tech.drc["minwidth_tx"], mults=4, tx_type="nmos", - connect_active=True, + connect_source_active=True, + connect_drain_active=True, connect_poly=True) self.local_drc_check(fet) diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index 4fc60d5c..0bcdf909 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -23,11 +23,12 @@ class ptx_test(openram_test): import tech debug.info(2, "Checking three fingers PMOS") - fet = factory.create(module_type="ptx", + fet = factory.create(module_type="ptx", width=tech.drc["minwidth_tx"], mults=4, tx_type="pmos", - connect_active=True, + connect_source_active=True, + connect_drain_active=True, connect_poly=True) self.local_drc_check(fet) diff --git a/compiler/tests/03_ptx_no_contacts_test.py b/compiler/tests/03_ptx_no_contacts_test.py new file mode 100755 index 00000000..ff39da79 --- /dev/null +++ b/compiler/tests/03_ptx_no_contacts_test.py @@ -0,0 +1,60 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class ptx_no_contacts_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + import tech + + debug.info(2, "Checking single finger no source/drain") + fet = factory.create(module_type="ptx", + width=tech.drc["minwidth_tx"], + mults=1, + add_source_contact=False, + add_drain_contact=False, + tx_type="nmos") + self.local_drc_check(fet) + + debug.info(2, "Checking multifinger no source/drain") + fet = factory.create(module_type="ptx", + width=tech.drc["minwidth_tx"], + mults=4, + add_source_contact=False, + add_drain_contact=False, + tx_type="nmos") + self.local_drc_check(fet) + + debug.info(2, "Checking series ptx") + fet = factory.create(module_type="ptx", + width=tech.drc["minwidth_tx"], + mults=4, + series_devices=True, + tx_type="nmos") + self.local_drc_check(fet) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pinv_100x_test.py b/compiler/tests/04_pinv_100x_test.py new file mode 100755 index 00000000..91b55d5d --- /dev/null +++ b/compiler/tests/04_pinv_100x_test.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class pinv_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + debug.info(2, "Checking 100x inverter") + tx = factory.create(module_type="pinv", size=100) + self.local_check(tx) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/16_control_logic_r_test.py b/compiler/tests/16_control_logic_r_test.py new file mode 100755 index 00000000..b695f9c9 --- /dev/null +++ b/compiler/tests/16_control_logic_r_test.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class control_logic_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + debug.info(1, "Testing sample for control_logic_r") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="r") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_rw_test.py similarity index 100% rename from compiler/tests/16_control_logic_test.py rename to compiler/tests/16_control_logic_rw_test.py diff --git a/compiler/tests/16_control_logic_w_test.py b/compiler/tests/16_control_logic_w_test.py new file mode 100755 index 00000000..8407d1e8 --- /dev/null +++ b/compiler/tests/16_control_logic_w_test.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class control_logic_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + debug.info(1, "Testing sample for control_logic_w") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="w") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From b7c66d7e073566d775ef8b9b902e8931a547e56d Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 7 May 2020 12:35:21 -0700 Subject: [PATCH 308/521] Changes to simplify metal preferred directions and pitches. Changes to allow decoder height to be a 2x multiple of bitcell height. Split of control logic tests. Fixed track spacing in SRAM and channel router PEP8 cleanup. --- compiler/base/contact.py | 10 +- compiler/base/design.py | 105 +++++-- compiler/base/hierarchy_layout.py | 297 ++++++++++-------- compiler/base/wire.py | 9 +- compiler/base/wire_path.py | 17 +- compiler/bitcells/bitcell.py | 2 +- compiler/bitcells/pbitcell.py | 53 ++-- compiler/modules/bank.py | 61 ++-- compiler/modules/bank_select.py | 31 +- compiler/modules/control_logic.py | 98 +++--- compiler/modules/dff_buf.py | 2 +- compiler/modules/hierarchical_decoder.py | 184 ++++++----- compiler/modules/hierarchical_predecode.py | 77 +++-- compiler/modules/port_address.py | 37 +-- compiler/modules/port_data.py | 2 +- compiler/modules/replica_bitcell_array.py | 22 +- compiler/modules/sense_amp_array.py | 4 +- compiler/modules/wordline_driver.py | 34 +- compiler/modules/write_driver_array.py | 2 +- compiler/modules/write_mask_and_array.py | 65 ++-- compiler/pgates/pand2.py | 17 +- compiler/pgates/pand3.py | 17 +- compiler/pgates/pbuf.py | 20 +- compiler/pgates/pdriver.py | 16 +- compiler/pgates/pgate.py | 69 ++-- compiler/pgates/pinv.py | 23 +- compiler/pgates/pnand2.py | 76 ++--- compiler/pgates/pnand3.py | 68 ++-- compiler/pgates/pnor2.py | 66 ++-- compiler/pgates/precharge.py | 2 +- compiler/pgates/ptristate_inv.py | 3 - compiler/pgates/ptx.py | 80 ++--- compiler/router/router_tech.py | 24 +- compiler/sram/sram_1bank.py | 120 +++---- compiler/sram/sram_base.py | 67 +--- compiler/tests/04_pinv_1x_test.py | 2 +- .../tests/06_hierarchical_decoder_test.py | 25 +- compiler/tests/16_control_logic_rw_test.py | 15 +- compiler/tests/19_single_bank_test.py | 40 +-- compiler/tests/21_ngspice_delay_test.py | 28 +- technology/freepdk45/tech/tech.py | 9 +- technology/scn4m_subm/tech/tech.py | 7 + 42 files changed, 953 insertions(+), 953 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 1ffdc7bf..f4fda552 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -47,8 +47,16 @@ class contact(hierarchy_design.hierarchy_design): self.layer_stack = layer_stack self.dimensions = dimensions - if directions: + + # Non-preferred directions + if directions == "nonpref": + first_dir = "H" if self.get_preferred_direction(layer_stack[0])=="V" else "V" + second_dir = "H" if self.get_preferred_direction(layer_stack[2])=="V" else "V" + self.directions = (first_dir, second_dir) + # User directions + elif directions: self.directions = directions + # Preferred directions else: self.directions = (tech.preferred_directions[layer_stack[0]], tech.preferred_directions[layer_stack[2]]) diff --git a/compiler/base/design.py b/compiler/base/design.py index 73ace38e..7a570b28 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -6,6 +6,7 @@ # All rights reserved. # from hierarchy_design import hierarchy_design +from utils import round_to_grid import contact from globals import OPTS import re @@ -31,48 +32,98 @@ class design(hierarchy_design): in many places in the compiler. """ + from tech import layer_indices import tech - for key in dir(tech): - # Single layer width rules - match = re.match(r".*_stack$", key) - if match: + for layer in layer_indices: + key = "{}_stack".format(layer) + + # Set the stack as a local helper + try: layer_stack = getattr(tech, key) - - # Set the stack as a local helper setattr(self, key, layer_stack) + except AttributeError: + pass - # Add the pitch - setattr(self, - "{}_pitch".format(layer_stack[0]), - self.compute_pitch(layer_stack)) - + # Skip computing the pitch for active + if layer == "active": + continue + + # Add the pitch + setattr(self, + "{}_pitch".format(layer), + self.compute_pitch(layer, True)) + + # Add the non-preferrd pitch (which has vias in the "wrong" way) + setattr(self, + "{}_nonpref_pitch".format(layer), + self.compute_pitch(layer, False)) + if False: - print("m1_pitch", self.m1_pitch) - print("m2_pitch", self.m2_pitch) - print("m3_pitch", self.m3_pitch) + from tech import preferred_directions + print(preferred_directions) + from tech import layer, layer_indices + for name in layer_indices: + if name == "active": + continue + try: + print("{0} width {1} space {2}".format(name, + getattr(self, "{}_width".format(name)), + getattr(self, "{}_space".format(name)))) + + print("pitch {0} nonpref {1}".format(getattr(self, "{}_pitch".format(name)), + getattr(self, "{}_nonpref_pitch".format(name)))) + except AttributeError: + pass import sys sys.exit(1) - def compute_pitch(self, layer_stack): + def compute_pitch(self, layer, preferred=True): """ - This is contact direction independent pitch, - i.e. we take the maximum contact dimension + This is the preferred direction pitch + i.e. we take the minimum or maximum contact dimension """ + # Find the layer stacks this is used in + from tech import layer_stacks + pitches = [] + for stack in layer_stacks: + # Compute the pitch with both vias above and below (if they exist) + if stack[0] == layer: + pitches.append(self.compute_layer_pitch(stack, preferred)) + if stack[2] == layer: + pitches.append(self.compute_layer_pitch(stack[::-1], True)) + + return max(pitches) + + def compute_layer_pitch(self, layer_stack, preferred): + (layer1, via, layer2) = layer_stack + try: + if layer1 == "poly" or layer1 == "active": + contact1 = getattr(contact, layer1 + "_contact") + else: + contact1 = getattr(contact, layer1 + "_via") + except AttributeError: + contact1 = getattr(contact, layer2 + "_via") - if layer1 == "poly" or layer1 == "active": - contact1 = getattr(contact, layer1 + "_contact") + if preferred: + if self.get_preferred_direction(layer1) == "V": + contact_width = contact1.first_layer_width + else: + contact_width = contact1.first_layer_height else: - contact1 = getattr(contact, layer1 + "_via") - max_contact = max(contact1.width, contact1.height) - - layer1_space = getattr(self, layer1 + "_space") - layer2_space = getattr(self, layer2 + "_space") - pitch = max_contact + max(layer1_space, layer2_space) + if self.get_preferred_direction(layer1) == "V": + contact_width = contact1.first_layer_height + else: + contact_width = contact1.first_layer_width + layer_space = getattr(self, layer1 + "_space") - return pitch - + #print(layer_stack) + #print(contact1) + pitch = contact_width + layer_space + + return round_to_grid(pitch) + def setup_drc_constants(self): """ These are some DRC constants used in many places diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index a2761084..df7095df 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -12,6 +12,7 @@ import debug from math import sqrt from tech import drc, GDS from tech import layer as techlayer +from tech import layer_indices from tech import layer_stacks import os from globals import OPTS @@ -47,11 +48,7 @@ class layout(): self.pwr_grid_layer = power_grid[0] except ImportError: self.pwr_grid_layer = "m3" - - if "li" in techlayer: - self.layer_indices = ["active", "li", "m1", "m2", "m3", "m4"] - else: - self.layer_indices = ["active", "m1", "m2", "m3", "m4"] + ############################################################ @@ -451,7 +448,40 @@ class layout(): path=coordinates, layer_widths=layer_widths) - def add_wire(self, layers, coordinates): + def add_zjog(self, layer, start, end, first_direction="H"): + """ + Add a simple jog at the halfway point. + If layer is a single value, it is a path. + If layer is a tuple, it is a wire with preferred directions. + """ + + # vertical first + if first_direction == "V": + mid1 = vector(start.x, 0.5 * start.y + 0.5 * end.y) + mid2 = vector(end.x, mid1.y) + # horizontal first + elif first_direction == "H": + mid1 = vector(0.5 * start.x + 0.5 * end.x, start.y) + mid2 = vector(mid1, end.y) + else: + debug.error("Invalid direction for jog -- must be H or V.") + + if layer in layer_stacks: + self.add_wire(layer, [start, mid1, mid2, end]) + elif layer in techlayer: + self.add_path(layer, [start, mid1, mid2, end]) + else: + debug.error("Could not find layer {}".format(layer)) + + def add_horizontal_zjog_path(self, layer, start, end): + """ Add a simple jog at the halfway point """ + + # horizontal first + mid1 = vector(0.5 * start.x + 0.5 * end.x, start.y) + mid2 = vector(mid1, end.y) + self.add_path(layer, [start, mid1, mid2, end]) + + def add_wire(self, layers, coordinates, widen_short_wires=True): """Connects a routing path on given layer,coordinates,width. The layers are the (horizontal, via, vertical). """ import wire @@ -459,7 +489,8 @@ class layout(): # into rectangles and contacts wire.wire(obj=self, layer_stack=layers, - position_list=coordinates) + position_list=coordinates, + widen_short_wires=widen_short_wires) def get_preferred_direction(self, layer): """ Return the preferred routing directions """ @@ -468,16 +499,6 @@ class layout(): def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None): """ Add a three layer via structure. """ - - # Non-preferred directions - if directions == "nonpref": - directions = (self.get_preferred_direction(layers[2]), - self.get_preferred_direction(layers[0])) - # Preferred if not specified - elif not directions or directions == "pref": - directions = (self.get_preferred_direction(layers[0]), - self.get_preferred_direction(layers[2])) - from sram_factory import factory via = factory.create(module_type="contact", layer_stack=layers, @@ -498,16 +519,6 @@ class layout(): Add a three layer via structure by the center coordinate accounting for mirroring and rotation. """ - - # Non-preferred directions - if directions == "nonpref": - directions = (self.get_preferred_direction(layers[2]), - self.get_preferred_direction(layers[0])) - # Preferred if not specified - elif not directions or directions == "pref": - directions = (self.get_preferred_direction(layers[0]), - self.get_preferred_direction(layers[2])) - from sram_factory import factory via = factory.create(module_type="contact", layer_stack=layers, @@ -547,13 +558,6 @@ class layout(): implant_type=implant_type, well_type=well_type) - def get_layer_index(self, layer_name): - """ - Return a layer index from bottom up in this tech. - """ - - return self.layer_indices.index(layer_name) - def add_via_stack_center(self, offset, from_layer, @@ -586,8 +590,8 @@ class layout(): if from_layer == to_layer: return last_via - from_id = self.get_layer_index(from_layer) - to_id = self.get_layer_index(to_layer) + from_id = layer_indices[from_layer] + to_id = layer_indices[to_layer] if from_id < to_id: # grow the stack up search_id = 0 @@ -608,24 +612,13 @@ class layout(): implant_type=implant_type, well_type=well_type) - if from_layer == "active": - via = self.__add_via_stack_internal(offset=offset, - directions=directions, - from_layer=curr_stack[next_id], - to_layer=to_layer, - via_func=via_func, - last_via=via, - size=size, - implant_type=implant_type, - well_type=well_type) - else: - via = self.__add_via_stack_internal(offset=offset, - directions=directions, - from_layer=curr_stack[next_id], - to_layer=to_layer, - via_func=via_func, - last_via=via, - size=size) + via = self.__add_via_stack_internal(offset=offset, + directions=directions, + from_layer=curr_stack[next_id], + to_layer=to_layer, + via_func=via_func, + last_via=via, + size=size) return via def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"): @@ -781,47 +774,47 @@ class layout(): return blockages - def create_horizontal_pin_bus(self, layer, pitch, offset, names, length): + def create_horizontal_pin_bus(self, layer, offset, names, length, pitch=None): """ Create a horizontal bus of pins. """ return self.create_bus(layer, - pitch, offset, names, length, vertical=False, - make_pins=True) + make_pins=True, + pitch=pitch) - def create_vertical_pin_bus(self, layer, pitch, offset, names, length): + def create_vertical_pin_bus(self, layer, offset, names, length, pitch=None): """ Create a horizontal bus of pins. """ return self.create_bus(layer, - pitch, offset, names, length, vertical=True, - make_pins=True) + make_pins=True, + pitch=pitch) - def create_vertical_bus(self, layer, pitch, offset, names, length): + def create_vertical_bus(self, layer, offset, names, length, pitch=None): """ Create a horizontal bus. """ return self.create_bus(layer, - pitch, offset, names, length, vertical=True, - make_pins=False) + make_pins=False, + pitch=pitch) - def create_horizontal_bus(self, layer, pitch, offset, names, length): + def create_horizontal_bus(self, layer, offset, names, length, pitch=None): """ Create a horizontal bus. """ return self.create_bus(layer, - pitch, offset, names, length, vertical=False, - make_pins=False) + make_pins=False, + pitch=pitch) - def create_bus(self, layer, pitch, offset, names, length, vertical, make_pins): + def create_bus(self, layer, offset, names, length, vertical, make_pins, pitch=None): """ Create a horizontal or vertical bus. It can be either just rectangles, or actual layout pins. It returns an map of line center line positions indexed by name. @@ -831,11 +824,14 @@ class layout(): # half minwidth so we can return the center line offsets half_minwidth = 0.5 * drc["minwidth_{}".format(layer)] + if not pitch: + pitch = getattr(self, "{}_pitch".format(layer)) line_positions = {} if vertical: for i in range(len(names)): - line_offset = offset + vector(i * pitch, 0) + line_offset = offset + vector(i * pitch, + 0) if make_pins: self.add_layout_pin(text=names[i], layer=layer, @@ -900,8 +896,10 @@ class layout(): # left/right then up/down mid_pos = vector(bus_pos.x, pin_pos.y) + # Don't widen short wires because pin_pos and mid_pos could be really close self.add_wire(layer_stack, - [bus_pos, mid_pos, pin_pos]) + [bus_pos, mid_pos, pin_pos], + widen_short_wires=False) # Connect to the pin on the instances with a via if it is # not on the right layer @@ -918,33 +916,76 @@ class layout(): offset=bus_pos, rotate=90) + def connect_vbus(self, src_pin, dest_pin, hlayer="m3", vlayer="m2"): + """ + Helper routine to connect an instance to a vertical bus. + Routes horizontal then vertical L shape. + """ + + if src_pin.cx() self.horiz_layer_contact_width: + if self.widen_short_wires and abs(line_length) < self.pitch and abs(line_length) > self.horiz_layer_contact_width: width = self.horiz_layer_contact_width else: width = self.horiz_layer_width @@ -134,7 +137,7 @@ class wire(wire_path): line_length = pl[index + 1][1] - pl[index][1] # Make the wire wider to avoid via-to-via spacing problems # But don't make it wider if it is shorter than one via - if abs(line_length) < self.pitch and abs(line_length) > self.vert_layer_contact_width: + if self.widen_short_wires and abs(line_length) < self.pitch and abs(line_length) > self.vert_layer_contact_width: width = self.vert_layer_contact_width else: width = self.vert_layer_width diff --git a/compiler/base/wire_path.py b/compiler/base/wire_path.py index ebfb8a0a..31d0ae78 100644 --- a/compiler/base/wire_path.py +++ b/compiler/base/wire_path.py @@ -24,11 +24,12 @@ def create_rectilinear_route(my_list): my_list.append(vector(pl[index][0], pl[index + 1][1])) my_list.append(vector(pl[-1])) return my_list - + + class wire_path(): """ Object metal wire_path; given the layer type - Add a wire_path of minimium metal width between a set of points. + Add a wire_path of minimium metal width between a set of points. The points should be rectilinear to control the bend points. If not, it will always go down first. The points are the center of the wire_path. If width is not given, it uses minimum layer width. @@ -37,7 +38,7 @@ class wire_path(): self.obj = obj self.layer_name = layer self.layer_id = techlayer[layer] - if width==None: + if width == None: self.layer_width = drc["minwidth_{0}".format(layer)] else: self.layer_width = width @@ -46,7 +47,6 @@ class wire_path(): self.switch_pos_list = [] self.create_layout() - def create_layout(self): self.create_rectilinear() self.connect_corner() @@ -60,9 +60,9 @@ class wire_path(): def connect_corner(self): """ Add a corner square at every corner of the wire_path.""" - from itertools import tee,islice - nwise = lambda g,n=2: zip(*(islice(g,i,None) for i,g in enumerate(tee(g,n)))) - threewise=nwise(self.position_list,3) + from itertools import tee, islice + nwise = lambda g, n=2: zip(*(islice(g, i, None) for i, g in enumerate(tee(g, n)))) + threewise=nwise(self.position_list, 3) for (a, offset, c) in list(threewise): # add a exceptions to prevent a corner when we retrace back in the same direction @@ -74,7 +74,6 @@ class wire_path(): offset[1] - 0.5 * self.layer_width] self.draw_corner_wire(corner_offset) - def draw_corner_wire(self, offset): """ This function adds the corner squares since the center line convention only draws to the center of the corner.""" @@ -117,7 +116,7 @@ class wire_path(): def add_line(self, layer_name, length, offset, orientation, layer_width): """ - straight line object with layer_minwidth + straight line object with layer_minwidth (orientation: "vertical" or "horizontal") default is vertical """ diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index 68e70e7e..b0e79208 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -50,7 +50,7 @@ class bitcell(bitcell_base.bitcell_base): self.pin_map = bitcell.pin_map self.add_pin_types(self.type_list) self.nets_match = self.do_nets_exist(self.storage_nets) - + def get_all_wl_names(self): """ Creates a list of all wordline pin names """ if props.bitcell.split_wl: diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index be96a129..aea7a6dc 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -264,7 +264,7 @@ class pbitcell(bitcell_base.bitcell_base): + 2 * self.implant_enclose_active \ + 0.5*(self.inverter_pmos.active_contact.height - self.m1_width) metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space - self.vdd_offset = max(implant_constraint, metal1_constraint) + 0.5*self.m1_width + self.vdd_offset = max(implant_constraint, metal1_constraint) + self.m1_width # read port dimensions width_reduction = self.read_nmos.active_width - self.read_nmos.get_pin("D").cx() @@ -275,7 +275,7 @@ class pbitcell(bitcell_base.bitcell_base): Calculate positions that describe the edges and dimensions of the cell """ - self.botmost_ypos = self.m1_offset - self.total_ports * self.m1_pitch + self.botmost_ypos = self.m1_offset - self.total_ports * self.m1_nonpref_pitch self.topmost_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ + self.inverter_gap \ @@ -378,14 +378,15 @@ class pbitcell(bitcell_base.bitcell_base): + 0.5 * contact.poly_contact.height, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, - offset=contact_offset_left) - + offset=contact_offset_left, + directions=("H", "H")) contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x \ - 0.5*contact.poly_contact.height, self.cross_couple_lower_ypos) self.add_via_center(layers=self.poly_stack, - offset=contact_offset_right) + offset=contact_offset_right, + directions=("H", "H")) # connect contacts to gate poly (cross couple connections) gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").lc().x, @@ -399,12 +400,12 @@ class pbitcell(bitcell_base.bitcell_base): def route_rails(self): """ Adds gnd and vdd rails and connects them to the inverters """ # Add rails for vdd and gnd - gnd_ypos = self.m1_offset - self.total_ports * self.m1_pitch + gnd_ypos = self.m1_offset - self.total_ports * self.m1_nonpref_pitch self.gnd_position = vector(0, gnd_ypos) self.add_rect_center(layer="m1", offset=self.gnd_position, width=self.width) - self.add_power_pin("gnd", vector(0, gnd_ypos)) + self.add_power_pin("gnd", vector(0, gnd_ypos), directions=("H", "H")) vdd_ypos = self.inverter_nmos_ypos \ @@ -416,7 +417,7 @@ class pbitcell(bitcell_base.bitcell_base): self.add_rect_center(layer="m1", offset=self.vdd_position, width=self.width) - self.add_power_pin("vdd", vector(0, vdd_ypos)) + self.add_power_pin("vdd", vector(0, vdd_ypos), directions=("H", "H")) def create_readwrite_ports(self): """ @@ -483,7 +484,7 @@ class pbitcell(bitcell_base.bitcell_base): self.port_ypos]) # add pin for RWWL - rwwl_ypos = self.m1_offset - k * self.m1_pitch + rwwl_ypos = self.m1_offset - k * self.m1_nonpref_pitch self.rwwl_positions[k] = vector(0, rwwl_ypos) self.add_layout_pin_rect_center(text=self.rw_wl_names[k], layer="m1", @@ -579,8 +580,8 @@ class pbitcell(bitcell_base.bitcell_base): # add pin for WWL wwl_ypos = rwwl_ypos = self.m1_offset \ - - self.num_rw_ports * self.m1_pitch \ - - k * self.m1_pitch + - self.num_rw_ports * self.m1_nonpref_pitch \ + - k * self.m1_nonpref_pitch self.wwl_positions[k] = vector(0, wwl_ypos) self.add_layout_pin_rect_center(text=self.w_wl_names[k], layer="m1", @@ -705,9 +706,9 @@ class pbitcell(bitcell_base.bitcell_base): # add pin for RWL rwl_ypos = rwwl_ypos = self.m1_offset \ - - self.num_rw_ports * self.m1_pitch \ - - self.num_w_ports * self.m1_pitch \ - - k * self.m1_pitch + - self.num_rw_ports * self.m1_nonpref_pitch \ + - self.num_w_ports * self.m1_nonpref_pitch \ + - k * self.m1_nonpref_pitch self.rwl_positions[k] = vector(0, rwl_ypos) self.add_layout_pin_rect_center(text=self.r_wl_names[k], layer="m1", @@ -771,6 +772,7 @@ class pbitcell(bitcell_base.bitcell_base): self.add_via_center(layers=self.poly_stack, offset=port_contact_offset) + self.add_path("poly", [gate_offset, port_contact_offset]) self.add_path("m1", [port_contact_offset, wl_contact_offset]) @@ -821,7 +823,8 @@ class pbitcell(bitcell_base.bitcell_base): # Leave bitline disconnected if a dummy cell if not self.dummy_bitcell: self.add_via_center(layers=self.m1_stack, - offset=port_contact_offest) + offset=port_contact_offest, + directions="nonpref") self.add_path("m2", [port_contact_offest, bl_offset], width=contact.m1_via.height) @@ -833,7 +836,8 @@ class pbitcell(bitcell_base.bitcell_base): # Leave bitline disconnected if a dummy cell if not self.dummy_bitcell: self.add_via_center(layers=self.m1_stack, - offset=port_contact_offest) + offset=port_contact_offest, + directions="nonpref") self.add_path("m2", [port_contact_offest, br_offset], width=contact.m1_via.height) @@ -850,7 +854,9 @@ class pbitcell(bitcell_base.bitcell_base): for position in nmos_contact_positions: self.add_via_center(layers=self.m1_stack, - offset=position) + offset=position, + directions=("V", "V")) + if position.x > 0: contact_correct = 0.5 * contact.m1_via.height @@ -859,7 +865,8 @@ class pbitcell(bitcell_base.bitcell_base): supply_offset = vector(position.x + contact_correct, self.gnd_position.y) self.add_via_center(layers=self.m1_stack, - offset=supply_offset) + offset=supply_offset, + directions=("H", "H")) self.add_path("m2", [position, supply_offset]) @@ -924,13 +931,16 @@ class pbitcell(bitcell_base.bitcell_base): - self.poly_to_contact - 0.5*contact.poly_contact.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, - offset=left_storage_contact) + offset=left_storage_contact, + directions=("H", "H")) + right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \ + self.poly_to_contact + 0.5*contact.poly_contact.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, - offset=right_storage_contact) + offset=right_storage_contact, + directions=("H", "H")) inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_upper_ypos) self.add_path("poly", [left_storage_contact, inverter_gate_offset_left]) @@ -1007,8 +1017,7 @@ class pbitcell(bitcell_base.bitcell_base): well_height = self.vdd_position.y - inverter_well_ypos \ + self.nwell_enclose_active + drc["minwidth_tx"] - # FIXME fudge factor xpos - offset = [inverter_well_xpos + 2*self.nwell_enclose_active, inverter_well_ypos] + offset = [inverter_well_xpos, inverter_well_ypos] self.add_rect(layer="nwell", offset=offset, width=well_width, diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 5e6ce004..393631e5 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -83,10 +83,10 @@ class bank(design.design): self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]), "OUTPUT") for port in self.write_ports: for bit in range(self.word_size): - self.add_pin("din{0}_{1}".format(port,bit), "INPUT") + self.add_pin("din{0}_{1}".format(port, bit), "INPUT") for port in self.all_ports: for bit in range(self.addr_size): - self.add_pin("addr{0}_{1}".format(port,bit), "INPUT") + self.add_pin("addr{0}_{1}".format(port, bit), "INPUT") # For more than one bank, we have a bank select and name # the signals gated_*. @@ -128,16 +128,14 @@ class bank(design.design): bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name) # This will ensure the pin is only on the top or bottom edge if port % 2: - via_offset = bl_pin.uc() + vector(0, self.m2_pitch) + via_offset = bl_pin.uc() + vector(0, 1.5 * self.m2_pitch) left_right_offset = vector(self.max_x_offset, via_offset.y) else: - via_offset = bl_pin.bc() - vector(0, self.m2_pitch) + via_offset = bl_pin.bc() - vector(0, 1.5 * self.m2_pitch) left_right_offset = vector(self.min_x_offset, via_offset.y) - if bl_pin == "m1": - self.add_via_center(layers=self.m1_stack, - offset=via_offset) - self.add_via_center(layers=self.m2_stack, - offset=via_offset) + self.add_via_stack_center(from_layer=bl_pin.layer, + to_layer="m3", + offset=via_offset) self.add_layout_pin_segment_center(text="rbl_bl{0}".format(port), layer="m3", start=left_right_offset, @@ -635,11 +633,10 @@ class bank(design.design): # Port 0 # The bank is at (0,0), so this is to the left of the y-axis. # 2 pitches on the right for vias/jogs to access the inputs - control_bus_offset = vector(-self.m2_pitch * self.num_control_lines[0] - self.m2_pitch, self.min_y_offset) + control_bus_offset = vector(-self.m3_pitch * self.num_control_lines[0] - self.m3_pitch, self.min_y_offset) # The control bus is routed up to two pitches below the bitcell array control_bus_length = self.main_bitcell_array_bottom - self.min_y_offset - 2 * self.m1_pitch self.bus_xoffset[0] = self.create_bus(layer="m2", - pitch=self.m2_pitch, offset=control_bus_offset, names=self.control_signals[0], length=control_bus_length, @@ -650,11 +647,10 @@ class bank(design.design): if len(self.all_ports)==2: # The other control bus is routed up to two pitches above the bitcell array control_bus_length = self.max_y_offset - self.main_bitcell_array_top - 2 * self.m1_pitch - control_bus_offset = vector(self.bitcell_array_right + self.m2_pitch, + control_bus_offset = vector(self.bitcell_array_right + self.m3_pitch, self.max_y_offset - control_bus_length) # The bus for the right port is reversed so that the rbl_wl is closest to the array self.bus_xoffset[1] = self.create_bus(layer="m2", - pitch=self.m2_pitch, offset=control_bus_offset, names=list(reversed(self.control_signals[1])), length=control_bus_length, @@ -844,9 +840,9 @@ class bank(design.design): self.copy_layout_pin(self.column_decoder_inst[port], decoder_name, addr_name) if port % 2: - offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines * self.m2_pitch, 0) + offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines * self.m2_nonpref_pitch, 0) else: - offset = self.column_decoder_inst[port].lr() + vector(self.m2_pitch, 0) + offset = self.column_decoder_inst[port].lr() + vector(self.m2_nonpref_pitch, 0) decode_pins = [self.column_decoder_inst[port].get_pin(x) for x in decode_names] @@ -854,7 +850,9 @@ class bank(design.design): column_mux_pins = [self.port_data_inst[port].get_pin(x) for x in sel_names] route_map = list(zip(decode_pins, column_mux_pins)) - self.create_vertical_channel_route(route_map, offset, self.m1_stack) + self.create_vertical_channel_route(route_map, + offset, + self.m1_stack) def add_lvs_correspondence_points(self): """ @@ -910,30 +908,39 @@ class bank(design.design): # pre-decoder and this connection is in metal3 connection = [] connection.append((self.prefix + "p_en_bar{}".format(port), - self.port_data_inst[port].get_pin("p_en_bar").lc())) + self.port_data_inst[port].get_pin("p_en_bar").lc(), + self.port_data_inst[port].get_pin("p_en_bar").layer)) rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]) connection.append((self.prefix + "wl_en{}".format(port), - self.bitcell_array_inst.get_pin(rbl_wl_name).lc())) + self.bitcell_array_inst.get_pin(rbl_wl_name).lc(), + self.bitcell_array_inst.get_pin(rbl_wl_name).layer)) if port in self.write_ports: if port % 2: connection.append((self.prefix + "w_en{}".format(port), - self.port_data_inst[port].get_pin("w_en").rc())) + self.port_data_inst[port].get_pin("w_en").rc(), + self.port_data_inst[port].get_pin("w_en").layer)) else: connection.append((self.prefix + "w_en{}".format(port), - self.port_data_inst[port].get_pin("w_en").lc())) + self.port_data_inst[port].get_pin("w_en").lc(), + self.port_data_inst[port].get_pin("w_en").layer)) if port in self.read_ports: connection.append((self.prefix + "s_en{}".format(port), - self.port_data_inst[port].get_pin("s_en").lc())) + self.port_data_inst[port].get_pin("s_en").lc(), + self.port_data_inst[port].get_pin("s_en").layer)) - for (control_signal, pin_pos) in connection: - control_mid_pos = self.bus_xoffset[port][control_signal] - control_pos = vector(self.bus_xoffset[port][control_signal].x, pin_pos.y) - self.add_wire(self.m1_stack, [control_mid_pos, control_pos, pin_pos]) - self.add_via_center(layers=self.m1_stack, - offset=control_pos) + for (control_signal, pin_pos, pin_layer) in connection: + if port==0: + y_offset = self.min_y_offset + else: + y_offset = self.max_y_offset + control_pos = vector(self.bus_xoffset[port][control_signal].x, y_offset) + if pin_layer == "m1": + self.add_wire(self.m1_stack, [control_pos, pin_pos]) + elif pin_layer == "m3": + self.add_wire(self.m2_stack[::-1], [control_pos, pin_pos]) # clk to wordline_driver control_signal = self.prefix + "wl_en{}".format(port) diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index 3be10d3e..b6246268 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -205,7 +205,7 @@ class bank_select(design.design): bank_sel_line_end = vector(xoffset_bank_sel, self.yoffset_maxpoint) self.add_path("m2", [bank_sel_line_pos, bank_sel_line_end]) self.add_via_center(layers=self.m1_stack, - offset=bank_sel_inv_pin.lc()) + offset=bank_sel_inv_pin.center()) # Route the pin to the left edge as well bank_sel_pin_pos=vector(0, 0) @@ -242,30 +242,31 @@ class bank_select(design.design): # Connect the logic output to inverter input out_pin = logic_inst.get_pin("Z") - out_pos = out_pin.rc() + out_pos = out_pin.center() in_pin = inv_inst.get_pin("A") - in_pos = in_pin.lc() + in_pos = in_pin.center() mid1_pos = vector(0.5 * (out_pos.x + in_pos.x), out_pos.y) mid2_pos = vector(0.5 * (out_pos.x + in_pos.x), in_pos.y) self.add_path("m1", [out_pos, mid1_pos, mid2_pos, in_pos]) # Connect the logic B input to bank_sel / bank_sel_bar - logic_pos = logic_inst.get_pin("B").lc() - vector(0.5 * contact.m1_via.height, 0) + logic_pin = logic_inst.get_pin("B") + logic_pos = logic_pin.center() input_pos = vector(xoffset_bank_signal, logic_pos.y) - self.add_path("m2", [logic_pos, input_pos]) - self.add_via_center(layers=self.m1_stack, - offset=logic_pos, - directions=("H", "H")) + self.add_path("m3", [logic_pos, input_pos]) + self.add_via_center(self.m2_stack, + input_pos) + self.add_via_stack_center(from_layer=logic_pin.layer, + to_layer="m3", + offset=logic_pos) # Connect the logic A input to the input pin - logic_pos = logic_inst.get_pin("A").lc() + logic_pin = logic_inst.get_pin("A") + logic_pos = logic_pin.center() input_pos = vector(0, logic_pos.y) - self.add_via_center(layers=self.m1_stack, - offset=logic_pos, - directions=("H", "H")) - self.add_via_center(layers=self.m2_stack, - offset=logic_pos, - directions=("H", "H")) + self.add_via_stack_center(from_layer=logic_pin.layer, + to_layer="m3", + offset=logic_pos) self.add_layout_pin_segment_center(text=input_name, layer="m3", start=input_pos, diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 5dd8182e..078dc3ae 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -384,7 +384,10 @@ class control_logic(design.design): height = self.control_logic_center.y - self.m2_pitch offset = vector(self.ctrl_dff_array.width, 0) - self.rail_offsets = self.create_vertical_bus("m2", self.m2_pitch, offset, self.internal_bus_list, height) + self.rail_offsets = self.create_vertical_bus("m2", + offset, + self.internal_bus_list, + height) def create_instances(self): """ Create all the instances """ @@ -432,7 +435,7 @@ class control_logic(design.design): row += 1 if (self.port_type == "rw") or (self.port_type == "w"): self.place_rbl_delay_row(row) - row += 1 + row += 1 if (self.port_type == "rw") or (self.port_type == "r"): self.place_sen_row(row) row += 1 @@ -522,16 +525,8 @@ class control_logic(design.design): self.add_via_center(layers=self.m1_stack, offset=clk_pos) - # Connect this at the bottom of the buffer - out_pos = self.clk_buf_inst.get_pin("Z").center() - mid1 = vector(out_pos.x, 2 * self.m2_pitch) - mid2 = vector(self.rail_offsets["clk_buf"].x, mid1.y) - bus_pos = self.rail_offsets["clk_buf"] - self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) - # The pin is on M1, so we need another via as well - self.add_via_center(layers=self.m1_stack, - offset=self.clk_buf_inst.get_pin("Z").center()) - + self.route_output_to_bus_jogged(self.clk_buf_inst, + "clk_buf") self.connect_output(self.clk_buf_inst, "Z", "clk_buf") def create_gated_clk_bar_row(self): @@ -541,7 +536,7 @@ class control_logic(design.design): self.gated_clk_bar_inst = self.add_inst(name="and2_gated_clk_bar", mod=self.and2) - self.connect_inst(["cs", "clk_bar", "gated_clk_bar", "vdd", "gnd"]) + self.connect_inst(["clk_bar", "cs", "gated_clk_bar", "vdd", "gnd"]) def place_gated_clk_bar_row(self, row): x_offset = self.control_x_offset @@ -554,31 +549,26 @@ class control_logic(design.design): def route_gated_clk_bar(self): clkbuf_map = zip(["A"], ["clk_buf"]) self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets) - + out_pos = self.clk_bar_inst.get_pin("Z").center() - in_pos = self.gated_clk_bar_inst.get_pin("B").center() - mid1 = vector(in_pos.x, out_pos.y) - self.add_path("m1", [out_pos, mid1, in_pos]) + in_pos = self.gated_clk_bar_inst.get_pin("A").center() + self.add_zjog("m1", out_pos, in_pos) # This is the second gate over, so it needs to be on M3 - clkbuf_map = zip(["A"], ["cs"]) + clkbuf_map = zip(["B"], ["cs"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, self.m2_stack[::-1]) # The pin is on M1, so we need another via as well - self.add_via_center(layers=self.m1_stack, - offset=self.gated_clk_bar_inst.get_pin("A").center()) + b_pin = self.gated_clk_bar_inst.get_pin("B") + self.add_via_stack_center(from_layer=b_pin.layer, + to_layer="m3", + offset=b_pin.center()) # This is the second gate over, so it needs to be on M3 - clkbuf_map = zip(["Z"], ["gated_clk_bar"]) - self.connect_vertical_bus(clkbuf_map, - self.gated_clk_bar_inst, - self.rail_offsets, - self.m2_stack[::-1]) - # The pin is on M1, so we need another via as well - self.add_via_center(layers=self.m1_stack, - offset=self.gated_clk_bar_inst.get_pin("Z").center()) + self.route_output_to_bus_jogged(self.gated_clk_bar_inst, + "gated_clk_bar") def create_gated_clk_buf_row(self): self.gated_clk_buf_inst = self.add_inst(name="and2_gated_clk_buf", @@ -594,7 +584,9 @@ class control_logic(design.design): def route_gated_clk_buf(self): clkbuf_map = zip(["A", "B"], ["clk_buf", "cs"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets) + self.connect_vertical_bus(clkbuf_map, + self.gated_clk_buf_inst, + self.rail_offsets) clkbuf_map = zip(["Z"], ["gated_clk_buf"]) self.connect_vertical_bus(clkbuf_map, @@ -602,8 +594,10 @@ class control_logic(design.design): self.rail_offsets, self.m2_stack[::-1]) # The pin is on M1, so we need another via as well - self.add_via_center(layers=self.m1_stack, - offset=self.gated_clk_buf_inst.get_pin("Z").center()) + z_pin = self.gated_clk_buf_inst.get_pin("Z") + self.add_via_stack_center(from_layer=z_pin.layer, + to_layer="m2", + offset=z_pin.center()) def create_wlen_row(self): # input pre_p_en, output: wl_en @@ -647,11 +641,16 @@ class control_logic(design.design): in_map = zip(["A", "B"], ["gated_clk_buf", "rbl_bl_delay"]) self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.rail_offsets) - out_pos = self.p_en_bar_nand_inst.get_pin("Z").rc() - in_pos = self.p_en_bar_driver_inst.get_pin("A").lc() - mid1 = vector(out_pos.x, in_pos.y) - self.add_wire(self.m1_stack, [out_pos, mid1, in_pos]) - + out_pin = self.p_en_bar_nand_inst.get_pin("Z") + out_pos = out_pin.center() + in_pin = self.p_en_bar_driver_inst.get_pin("A") + in_pos = in_pin.center() + mid1 = vector(in_pos.x, out_pos.y) + self.add_path(out_pin.layer, [out_pos, mid1, in_pos]) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer=in_pin.layer, + offset=in_pin.center()) + self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar") def create_sen_row(self): @@ -704,11 +703,7 @@ class control_logic(design.design): # Connect from delay line # Connect to rail - rbl_map = zip(["Z"], ["rbl_bl_delay_bar"]) - self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets, ("m3", "via2", "m2")) - # The pin is on M1, so we need another via as well - self.add_via_center(layers=self.m1_stack, - offset=self.rbl_bl_delay_inv_inst.get_pin("Z").center()) + self.route_output_to_bus_jogged(self.rbl_bl_delay_inv_inst, "rbl_bl_delay_bar") rbl_map = zip(["A"], ["rbl_bl_delay"]) self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets) @@ -766,11 +761,12 @@ class control_logic(design.design): dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) else: dff_out_map = zip(["dout_bar_0"], ["cs"]) - self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets, ("m3", "via2", "m2")) + self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets, self.m2_stack[::-1]) # Connect the clock rail to the other clock rail + # by routing in the supply rail track to avoid channel conflicts in_pos = self.ctrl_dff_inst.get_pin("clk").uc() - mid_pos = in_pos + vector(0, 2 * self.m2_pitch) + mid_pos = in_pos + vector(0, self.and2.height) rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y) self.add_wire(self.m1_stack, [in_pos, mid_pos, rail_pos]) self.add_via_center(layers=self.m1_stack, @@ -823,10 +819,10 @@ class control_logic(design.design): self.add_path("m1", [row_loc, pin_loc]) self.copy_layout_pin(self.delay_inst, "gnd") - self.copy_layout_pin(self.delay_inst, "vdd") + self.copy_layout_pin(self.delay_inst, "vdd") self.copy_layout_pin(self.ctrl_dff_inst, "gnd") - self.copy_layout_pin(self.ctrl_dff_inst, "vdd") + self.copy_layout_pin(self.ctrl_dff_inst, "vdd") def add_lvs_correspondence_points(self): """ This adds some points for easier debugging if LVS goes wrong. @@ -1000,3 +996,15 @@ class control_logic(design.design): offset = vector(x_offset, y_offset) inst.place(offset, mirror) return x_offset + inst.width + + def route_output_to_bus_jogged(self, inst, name): + # Connect this at the bottom of the buffer + out_pos = inst.get_pin("Z").center() + mid1 = vector(out_pos.x, out_pos.y - 0.25 * inst.mod.height) + mid2 = vector(self.rail_offsets[name].x, mid1.y) + bus_pos = self.rail_offsets[name] + self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) + # The pin is on M1, so we need another via as well + self.add_via_center(layers=self.m1_stack, + offset=out_pos) + diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 500767d8..0366b10b 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -180,7 +180,7 @@ class dff_buf(design.design): height=din_pin.height()) dout_pin = self.inv2_inst.get_pin("Z") - mid_pos = dout_pin.center() + vector(self.m1_pitch, 0) + mid_pos = dout_pin.center() + vector(self.m1_nonpref_pitch, 0) q_pos = mid_pos - vector(0, self.m2_pitch) self.add_layout_pin_rect_center(text="Q", layer="m2", diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index be3ba9c1..c1593932 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -12,7 +12,7 @@ from sram_factory import factory from vector import vector from globals import OPTS from errors import drc_error -from tech import cell_properties +from tech import cell_properties, layer class hierarchical_decoder(design.design): @@ -89,6 +89,7 @@ class hierarchical_decoder(design.design): self.place_pre_decoder() self.place_row_decoder() self.route_inputs() + self.route_outputs() self.route_decoder_bus() self.route_vdd_gnd() self.offset_all_coordinates() @@ -103,7 +104,7 @@ class hierarchical_decoder(design.design): height=self.cell_height) self.add_mod(self.and2) self.and3 = factory.create(module_type="pand3", - height=self.cell_height) + height=self.cell_height) self.add_mod(self.and3) self.add_decoders() @@ -186,6 +187,13 @@ class hierarchical_decoder(design.design): self.num_rows = math.ceil(self.num_outputs / self.cell_multiple) # We will place this many final decoders per row self.decoders_per_row = math.ceil(self.num_outputs / self.num_rows) + # We will need to use M2 and M3 in the vertical bus if we have multiple decoders per row + if self.decoders_per_row == 1: + self.decoder_bus_pitch = self.m2_pitch + elif self.decoders_per_row == 2: + self.decoder_bus_pitch = self.m3_pitch + else: + debug.error("Insufficient layers for multi-bit height decoder.", -1) # Calculates height and width of row-decoder if (self.num_inputs == 4 or self.num_inputs == 5): @@ -194,20 +202,21 @@ class hierarchical_decoder(design.design): else: nand_width = self.and3.width nand_inputs = 3 - self.internal_routing_width = self.m3_pitch * (self.total_number_of_predecoder_outputs + 1) + self.internal_routing_width = self.decoder_bus_pitch * (self.total_number_of_predecoder_outputs + 1) self.row_decoder_height = self.inv.height * self.num_rows - decoder_input_wire_height = self.decoders_per_row * nand_inputs * self.m3_pitch - #print(self.decoders_per_row, nand_inputs) - #print(decoder_input_wire_height, self.cell_height) + decoder_input_wire_height = self.decoders_per_row * nand_inputs * self.m2_pitch + # print(self.decoders_per_row, nand_inputs) + # print(decoder_input_wire_height, self.cell_height) if decoder_input_wire_height > self.cell_height: debug.warning("Cannot fit multi-bit decoder routes per row.") - #debug.check(decoder_input_wire_height < self.cell_height, "Cannot fit multi-bit decoder routes per row.") + # debug.check(decoder_input_wire_height < self.cell_height, "Cannot fit multi-bit decoder routes per row.") + + self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch - self.input_routing_width = (self.num_inputs + 1) * self.m3_pitch # Calculates height and width of hierarchical decoder # Add extra pitch for good measure - self.height = max(self.predecoder_height, self.row_decoder_height) + self.m3_pitch + self.height = max(self.predecoder_height, self.row_decoder_height) + self.m2_pitch self.width = self.input_routing_width + self.predecoder_width \ + self.internal_routing_width \ + self.decoders_per_row * nand_width + self.inv.width @@ -226,8 +235,7 @@ class hierarchical_decoder(design.design): input_offset=vector(min_x - self.input_routing_width, 0) input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)] - self.input_bus = self.create_vertical_pin_bus(layer="m3", - pitch=self.m3_pitch, + self.input_bus = self.create_vertical_pin_bus(layer="m2", offset=input_offset, names=input_bus_names, length=input_height) @@ -276,13 +284,11 @@ class hierarchical_decoder(design.design): self.add_via_stack_center(from_layer="m2", to_layer="m3", - offset=input_offset, - directions="nonpref") + offset=input_offset) self.add_via_stack_center(from_layer="m2", to_layer="m3", - offset=output_offset, - directions="nonpref") - self.add_path(("m2"), [input_offset, output_offset]) + offset=output_offset) + self.add_path("m3", [input_offset, output_offset]) def add_pins(self): """ Add the module pins """ @@ -424,7 +430,7 @@ class hierarchical_decoder(design.design): """ if (self.num_inputs >= 4): self.place_decoder_and_array() - self.route_decoder() + def place_decoder_and_array(self): """ @@ -460,16 +466,28 @@ class hierarchical_decoder(design.design): self.and_inst[inst_index].place(offset=vector(x_off, y_off), mirror=mirror) - def route_decoder(self): + def route_outputs(self): """ Add the pins. """ - for output in range(self.num_outputs): - z_pin = self.and_inst[output].get_pin("Z") - self.add_layout_pin(text="decode_{0}".format(output), - layer="m1", - offset=z_pin.ll(), - width=z_pin.width(), - height=z_pin.height()) + max_xoffset = max(x.rx() for x in self.and_inst) + + for output_index in range(self.num_outputs): + row_remainder = (output_index % self.decoders_per_row) + + and_inst = self.and_inst[output_index] + z_pin = and_inst.get_pin("Z") + if row_remainder == 0 and self.decoders_per_row > 1: + layer = "m3" + self.add_via_stack_center(from_layer=z_pin.layer, + to_layer="m3", + offset=z_pin.center()) + else: + layer = z_pin.layer + + self.add_layout_pin_segment_center(text="decode_{0}".format(output_index), + layer=layer, + start=z_pin.center(), + end=vector(max_xoffset, z_pin.cy())) def route_decoder_bus(self): """ @@ -480,8 +498,8 @@ class hierarchical_decoder(design.design): if (self.num_inputs >= 4): # This leaves an offset for the predecoder output jogs input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)] - self.predecode_bus = self.create_vertical_pin_bus(layer="m3", - pitch=self.m3_pitch, + self.predecode_bus = self.create_vertical_pin_bus(layer="m2", + pitch=self.decoder_bus_pitch, offset=vector(0, 0), names=input_bus_names, length=self.height) @@ -525,22 +543,27 @@ class hierarchical_decoder(design.design): """ output_index = 0 + if "li" in layer: + self.decoder_layers = [self.m1_stack, self.m2_stack[::-1]] + else: + self.decoder_layers = [self.m2_stack[::-1]] + debug.check(self.decoders_per_row <= len(self.decoder_layers), "Must have more layers for multi-height decoder.") + if (self.num_inputs == 4 or self.num_inputs == 5): for index_B in self.predec_groups[1]: for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? if (output_index < self.num_outputs): - row_index = math.floor(output_index / self.decoders_per_row) - row_remainder = (output_index % self.decoders_per_row) - row_offset = row_index * self.and_inst[0].height + (2 * row_remainder + 1) * self.m3_pitch predecode_name = "predecode_{}".format(index_A) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("A"), - row_offset) + output_index, + 0) predecode_name = "predecode_{}".format(index_B) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("B"), - row_offset + self.m3_pitch) + output_index, + 1) output_index = output_index + 1 elif (self.num_inputs > 5): @@ -549,21 +572,21 @@ class hierarchical_decoder(design.design): for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? if (output_index < self.num_outputs): - row_index = math.floor(output_index / self.decoders_per_row) - row_remainder = (output_index % self.decoders_per_row) - row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 1) * self.m2_pitch predecode_name = "predecode_{}".format(index_A) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("A"), - row_offset) + output_index, + 0) predecode_name = "predecode_{}".format(index_B) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("B"), - row_offset + self.m2_pitch) + output_index, + 1) predecode_name = "predecode_{}".format(index_C) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("C"), - row_offset + 2 * self.m2_pitch) + output_index, + 2) output_index = output_index + 1 def route_vdd_gnd(self): @@ -583,47 +606,56 @@ class hierarchical_decoder(design.design): # The nand and inv are the same height rows... supply_pin = self.and_inst[num].get_pin(pin_name) pin_pos = vector(xoffset, supply_pin.cy()) - self.add_path("m1", + self.add_path(supply_pin.layer, [supply_pin.lc(), vector(xoffset, supply_pin.cy())]) self.add_power_pin(name=pin_name, - loc=pin_pos) + loc=pin_pos, + start_layer=supply_pin.layer) # Copy the pins from the predecoders for pre in self.pre2x4_inst + self.pre3x8_inst: self.copy_layout_pin(pre, "vdd") self.copy_layout_pin(pre, "gnd") - def route_predecode_bus_outputs(self, rail_name, pin, y_offset): + def route_predecode_bus_outputs(self, rail_name, pin, output_index, pin_index): """ Connect the routing rail to the given metal1 pin using a routing track at the given y_offset - """ - pin_pos = pin.center() - # If we have a single decoder per row, we can route on M1 - if self.decoders_per_row == 1: - rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y) - self.add_path("m2", [rail_pos, pin_pos]) - self.add_via_stack_center(from_layer=pin.layer, - to_layer="m2", - offset=pin_pos, - directions=("H", "H")) - self.add_via_stack_center(from_layer="m2", - to_layer="m3", - offset=rail_pos, - directions="nonpref") - # If not, we must route over the decoder cells on M3 - else: - rail_pos = vector(self.predecode_bus[rail_name].x, y_offset) - mid_pos = vector(pin_pos.x, rail_pos.y) - self.add_wire(self.m2_stack, [rail_pos, mid_pos, pin_pos]) - self.add_via_center(layers=self.m2_stack, - offset=rail_pos) - self.add_via_stack_center(from_layer=pin_pos.layer, - to_layer="m3", - offset=pin_pos, - directions="nonpref") + row_index = math.floor(output_index / self.decoders_per_row) + row_remainder = (output_index % self.decoders_per_row) + row_offset = row_index * self.and_inst[0].height + + pin_pos = pin.center() + + # y_offset is the same for both the M2 and M4 routes so that the rail + # contacts align and don't cause problems + if pin_index == 0: + # Bottom pitch + y_offset = row_offset + elif pin_index == 1: + # One pitch from top + y_offset = row_offset + self.and_inst[0].height - self.m3_pitch + elif pin_index == 2: + # One pitch from bottom + y_offset = row_offset + self.m3_pitch + else: + debug.error("Invalid decoder pitch.") + + rail_pos = vector(self.predecode_bus[rail_name].x, y_offset) + mid_pos = vector(pin_pos.x, rail_pos.y) + self.add_wire(self.decoder_layers[row_remainder], [rail_pos, mid_pos, pin_pos]) + + self.add_via_stack_center(from_layer="m2", + to_layer=self.decoder_layers[row_remainder][0], + offset=rail_pos) + + self.add_via_stack_center(from_layer=pin.layer, + to_layer=self.decoder_layers[row_remainder][2], + offset=pin_pos, + directions=("H", "H")) + def route_predecode_bus_inputs(self, rail_name, pin, x_offset): """ Connect the routing rail to the given metal1 pin using a jog @@ -631,15 +663,21 @@ class hierarchical_decoder(design.design): """ # This routes the pin up to the rail, basically, to avoid conflicts. # It would be fixed with a channel router. + # pin_pos = pin.center() + # mid_point1 = vector(x_offset, pin_pos.y) + # mid_point2 = vector(x_offset, pin_pos.y + self.inv.height / 2) + # rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y) + # self.add_path("m1", [pin_pos, mid_point1, mid_point2, rail_pos]) + pin_pos = pin.center() - mid_point1 = vector(x_offset, pin_pos.y) - mid_point2 = vector(x_offset, pin_pos.y + self.inv.height / 2) - rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y) - self.add_path("m1", [pin_pos, mid_point1, mid_point2, rail_pos]) + rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y) + self.add_path("m1", [pin_pos, rail_pos]) + self.add_via_stack_center(from_layer=pin.layer, + to_layer="m1", + offset=pin_pos) self.add_via_stack_center(from_layer="m1", - to_layer="m3", - offset=rail_pos, - directions="nonpref") + to_layer="m2", + offset=rail_pos) def input_load(self): if self.determine_predecodes(self.num_inputs)[1]==0: diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index c5fd1777..9a658546 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -11,6 +11,7 @@ import math import contact from vector import vector from sram_factory import factory +from tech import cell_properties class hierarchical_predecode(design.design): @@ -19,7 +20,17 @@ class hierarchical_predecode(design.design): """ def __init__(self, name, input_number, height=None): self.number_of_inputs = input_number - self.cell_height = height + + if not height: + b = factory.create(module_type="bitcell") + try: + self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple + except AttributeError: + self.cell_multiple = 1 + self.cell_height = self.cell_multiple * b.height + else: + self.cell_height = height + self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) design.design.__init__(self, name) @@ -57,10 +68,10 @@ class hierarchical_predecode(design.design): self.height = self.number_of_outputs * self.and_mod.height # x offset for input inverters - self.x_off_inv_1 = self.number_of_inputs*self.m3_pitch + self.x_off_inv_1 = self.number_of_inputs * self.m2_pitch + self.m2_space # x offset to AND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches - self.x_off_and = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m3_pitch + self.x_off_and = self.x_off_inv_1 + self.inv.width + (2 * self.number_of_inputs + 2) * self.m2_pitch # x offset to output inverters self.width = self.x_off_and + self.and_mod.width @@ -68,9 +79,8 @@ class hierarchical_predecode(design.design): def route_rails(self): """ Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """ input_names = ["in_{}".format(x) for x in range(self.number_of_inputs)] - offset = vector(0.5 * self.m3_width, self.m1_pitch) - self.input_rails = self.create_vertical_pin_bus(layer="m3", - pitch=self.m3_pitch, + offset = vector(0.5 * self.m2_width, self.m3_pitch) + self.input_rails = self.create_vertical_pin_bus(layer="m2", offset=offset, names=input_names, length=self.height - 2 * self.m1_pitch) @@ -78,9 +88,8 @@ class hierarchical_predecode(design.design): invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)] non_invert_names = ["A_{}".format(x) for x in range(self.number_of_inputs)] decode_names = invert_names + non_invert_names - offset = vector(self.x_off_inv_1 + self.inv.width + 2 * self.m3_pitch, self.m1_pitch) - self.decode_rails = self.create_vertical_bus(layer="m3", - pitch=self.m3_pitch, + offset = vector(self.x_off_inv_1 + self.inv.width + 2 * self.m2_pitch, self.m3_pitch) + self.decode_rails = self.create_vertical_bus(layer="m2", offset=offset, names=decode_names, length=self.height - 2 * self.m1_pitch) @@ -151,11 +160,13 @@ class hierarchical_predecode(design.design): a_pin = "A_{}".format(num) in_pos = vector(self.input_rails[in_pin].x, y_offset) a_pos = vector(self.decode_rails[a_pin].x, y_offset) - self.add_path("m2", [in_pos, a_pos]) - self.add_via_center(layers=self.m2_stack, - offset=[self.input_rails[in_pin].x, y_offset]) - self.add_via_center(layers=self.m2_stack, - offset=[self.decode_rails[a_pin].x, y_offset]) + self.add_path("m1", [in_pos, a_pos]) + self.add_via_stack_center(from_layer="m1", + to_layer="m2", + offset=[self.input_rails[in_pin].x, y_offset]) + self.add_via_stack_center(from_layer="m1", + to_layer="m2", + offset=[self.decode_rails[a_pin].x, y_offset]) def route_output_and(self): """ @@ -188,21 +199,20 @@ class hierarchical_predecode(design.design): rail_pos = vector(self.decode_rails[out_pin].x, y_offset) self.add_path(inv_out_pin.layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) self.add_via_stack_center(from_layer=inv_out_pin.layer, - to_layer="m3", - offset=rail_pos, - directions="nonpref") + to_layer="m2", + offset=rail_pos) # route input pin = self.in_inst[inv_num].get_pin("A") inv_in_pos = pin.lc() in_pos = vector(self.input_rails[in_pin].x, inv_in_pos.y) - self.add_path("m2", [in_pos, inv_in_pos]) + self.add_path("m1", [in_pos, inv_in_pos]) self.add_via_stack_center(from_layer=pin.layer, + to_layer="m1", + offset=inv_in_pos) + self.add_via_stack_center(from_layer="m1", to_layer="m2", - offset=inv_in_pos, - directions="nonpref") - self.add_via_center(layers=self.m2_stack, - offset=in_pos) + offset=in_pos) def route_and_to_rails(self): # This 2D array defines the connection mapping @@ -221,14 +231,19 @@ class hierarchical_predecode(design.design): pin = self.and_inst[k].get_pin(gate_pin) pin_pos = pin.center() rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y) - self.add_path("m2", [rail_pos, pin_pos]) - self.add_via_center(layers=self.m2_stack, - offset=rail_pos, - directions="nonpref") - self.add_via_stack_center(from_layer=pin.layer, + self.add_path("m1", [rail_pos, pin_pos]) + self.add_via_stack_center(from_layer="m1", to_layer="m2", + offset=rail_pos) + if gate_pin == "A": + direction = None + else: + direction = ("H", "H") + + self.add_via_stack_center(from_layer=pin.layer, + to_layer="m1", offset=pin_pos, - directions=("H", "H")) + directions=direction) def route_vdd_gnd(self): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ @@ -243,14 +258,16 @@ class hierarchical_predecode(design.design): for n in ["vdd", "gnd"]: and_pin = self.and_inst[num].get_pin(n) supply_offset = and_pin.ll().scale(0, 1) - self.add_rect(layer="m1", + self.add_rect(layer=and_pin.layer, offset=supply_offset, width=self.and_inst[num].rx()) # Add pins in two locations for xoffset in [in_xoffset]: pin_pos = vector(xoffset, and_pin.cy()) - self.add_power_pin(n, pin_pos) + self.add_power_pin(name=n, + loc=pin_pos, + start_layer=and_pin.layer) diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 6938219a..a27894ae 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -3,8 +3,6 @@ # Copyright (c) 2016-2019 Regents of the University of California # All rights reserved. # -import sys -from tech import drc, parameter from math import log import debug import design @@ -13,6 +11,7 @@ from vector import vector from globals import OPTS + class port_address(design.design): """ Create the address port (row decoder and wordline driver).. @@ -25,17 +24,16 @@ class port_address(design.design): self.addr_size = int(log(self.num_rows, 2)) if name == "": - name = "port_address_{0}_{1}".format(cols,rows) + name = "port_address_{0}_{1}".format(cols, rows) design.design.__init__(self, name) - debug.info(2, "create data port of cols {0} rows {1}".format(cols,rows)) + debug.info(2, "create data port of cols {0} rows {1}".format(cols, rows)) self.create_netlist() if not OPTS.netlist_only: - debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.") + debug.check(len(self.all_ports) <= 2, "Bank layout cannot handle more than two ports.") self.create_layout() self.add_boundary() - def create_netlist(self): self.add_pins() self.add_modules() @@ -51,16 +49,15 @@ class port_address(design.design): """ Adding pins for port address module""" for bit in range(self.addr_size): - self.add_pin("addr_{0}".format(bit),"INPUT") + self.add_pin("addr_{0}".format(bit), "INPUT") self.add_pin("wl_en", "INPUT") for bit in range(self.num_rows): - self.add_pin("wl_{0}".format(bit),"OUTPUT") + self.add_pin("wl_{0}".format(bit), "OUTPUT") - self.add_pin("vdd","POWER") - self.add_pin("gnd","GROUND") - + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def route_layout(self): """ Create routing amoung the modules """ @@ -71,8 +68,8 @@ class port_address(design.design): def route_supplies(self): """ Propagate all vdd/gnd pins up to this level for all modules """ for inst in self.insts: - self.copy_power_pins(inst,"vdd") - self.copy_power_pins(inst,"gnd") + self.copy_power_pins(inst, "vdd") + self.copy_power_pins(inst, "gnd") def route_pins(self): for row in range(self.addr_size): @@ -119,12 +116,10 @@ class port_address(design.design): temp.extend(["vdd", "gnd"]) self.connect_inst(temp) - - def create_wordline_driver(self): """ Create the Wordline Driver """ - self.wordline_driver_inst = self.add_inst(name="wordline_driver", + self.wordline_driver_inst = self.add_inst(name="wordline_driver", mod=self.wordline_driver) temp = [] @@ -137,19 +132,13 @@ class port_address(design.design): temp.append("gnd") self.connect_inst(temp) - - def place_instances(self): """ Compute the offsets and place the instances. """ - # A space for wells or jogging m2 - self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"), - 3*self.m2_pitch) - - row_decoder_offset = vector(0,0) - wordline_driver_offset = vector(self.row_decoder.width + self.m2_gap,0) + row_decoder_offset = vector(0, 0) + wordline_driver_offset = vector(self.row_decoder.width, 0) self.wordline_driver_inst.place(wordline_driver_offset) self.row_decoder_inst.place(row_decoder_offset) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index bdf10f39..91e20a45 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -694,7 +694,7 @@ class port_data(design.design): # Channel route each mux separately since we don't minimize the number # of tracks in teh channel router yet. If we did, we could route all the bits at once! - offset = bot_inst_group.inst.ul() + vector(0, self.m1_pitch) + offset = bot_inst_group.inst.ul() + vector(0, self.m1_nonpref_pitch) for bit in range(num_bits): bottom_names = self._get_bitline_pins(bot_inst_group, bit) top_names = self._get_bitline_pins(top_inst_group, bit) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index d5865658..c88dbe6d 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -354,32 +354,30 @@ class replica_bitcell_array(design.design): width=self.width, height=pin.height()) - # Replica bitlines - for port in range(self.left_rbl+self.right_rbl): + for port in range(self.left_rbl + self.right_rbl): inst = self.replica_col_inst[port] - for (pin_name, bl_name) in zip(self.cell.get_all_bitline_names(),self.replica_bl_names[port]): + for (pin_name, bl_name) in zip(self.cell.get_all_bitline_names(), self.replica_bl_names[port]): pin = inst.get_pin(pin_name) if bl_name in self.rbl_bl_names or bl_name in self.rbl_br_names: name = bl_name else: - name = "rbl_{0}_{1}".format(pin_name,port) + name = "rbl_{0}_{1}".format(pin_name, port) self.add_layout_pin(text=name, layer=pin.layer, - offset=pin.ll().scale(1,0), + offset=pin.ll().scale(1, 0), width=pin.width(), height=self.height) - - for pin_name in ["vdd","gnd"]: + for pin_name in ["vdd", "gnd"]: for inst in self.insts: pin_list = inst.get_pins(pin_name) for pin in pin_list: - self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer) + self.add_power_pin(name=pin_name, + loc=pin.center(), + directions=("V", "V"), + start_layer=pin.layer) - - - def get_rbl_wl_name(self, port): """ Return the WL for the given RBL port """ return self.rbl_wl_names[port] @@ -398,7 +396,7 @@ class replica_bitcell_array(design.design): # Dynamic Power from Bitline bl_wire = self.gen_bl_wire() - cell_load = 2 * bl_wire.return_input_cap() + cell_load = 2 * bl_wire.return_input_cap() bl_swing = OPTS.rbl_delay_percentage freq = spice["default_event_frequency"] bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index c2f68f9b..cb413c45 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -130,13 +130,13 @@ class sense_amp_array(design.design): self.add_power_pin(name="gnd", loc=gnd_pin.center(), start_layer=gnd_pin.layer, - vertical=True) + directions=("V", "V")) vdd_pin = inst.get_pin("vdd") self.add_power_pin(name="vdd", loc=vdd_pin.center(), start_layer=vdd_pin.layer, - vertical=True) + directions=("V", "V")) bl_pin = inst.get_pin(inst.mod.get_bl_names()) br_pin = inst.get_pin(inst.mod.get_br_names()) diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 3afe1c3c..55f5e707 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -8,7 +8,7 @@ import debug import design import math -import contact +from tech import drc from vector import vector from sram_factory import factory from globals import OPTS @@ -120,9 +120,11 @@ class wordline_driver(design.design): self.decoders_per_row = math.ceil(self.bitcell_rows / self.driver_rows) def place_drivers(self): - and2_xoffset = 2 * self.m1_width + 5 * self.m1_space + + # Leave a well gap to separate the bitcell array well from this well + well_gap = 2 * drc("pwell_to_nwell") + drc("nwell_enclose_active") - self.width = and2_xoffset + self.decoders_per_row * self.and2.width + self.width = self.decoders_per_row * self.and2.width + well_gap self.height = self.and2.height * self.driver_rows for inst_index in range(self.bitcell_rows): @@ -136,7 +138,7 @@ class wordline_driver(design.design): y_offset = self.and2.height * row inst_mirror = "R0" - x_offset = and2_xoffset + dec * self.and2.width + x_offset = dec * self.and2.width and2_offset = [x_offset, y_offset] # add and2 @@ -147,32 +149,26 @@ class wordline_driver(design.design): """ Route all of the signals """ # Wordline enable connection - en_offset = [self.m1_width + 2 * self.m1_space, 0] + en_pin = self.and_inst[0].get_pin("B") + en_bottom_pos = vector(en_pin.lx(), 0) en_pin = self.add_layout_pin(text="en", layer="m2", - offset=en_offset, - width=self.m2_width, + offset=en_bottom_pos, height=self.height) for inst_index in range(self.bitcell_rows): and_inst = self.and_inst[inst_index] row = math.floor(inst_index / self.decoders_per_row) - dec = inst_index % self.decoders_per_row - - # en connection - b_pin = and_inst.get_pin("B") - b_pos = b_pin.center() - clk_offset = vector(en_pin.bc().x, b_pos.y) - self.add_segment_center(layer="m2", - start=clk_offset, - end=b_pos) - self.add_via_center(layers=self.m1_stack, - offset=b_pos) + # Drop a via + b_pin = and_inst.get_pin("B") + self.add_via_stack_center(from_layer=b_pin.layer, + to_layer="m2", + offset=b_pin.center()) + # connect the decoder input pin to and2 A a_pin = and_inst.get_pin("A") a_pos = a_pin.center() - a_offset = vector(clk_offset.x, a_pos.y) # must under the clk line in M1 self.add_layout_pin_segment_center(text="in_{0}".format(row), layer="m1", diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index ab369dda..49e830e2 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -165,7 +165,7 @@ class write_driver_array(design.design): for pin in pin_list: self.add_power_pin(name=n, loc=pin.center(), - vertical=True, + directions=("V", "V"), start_layer=pin.layer) if self.write_size: for bit in range(self.num_wmasks): diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 25acb324..4d4e0c50 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -5,9 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from math import log import design -from tech import drc import debug from sram_factory import factory from vector import vector @@ -43,33 +41,28 @@ class write_mask_and_array(design.design): self.add_pins() self.create_and2_array() - def create_layout(self): self.place_and2_array() - spacing = self.wmask_en_len - self.and2.width - self.width = (self.num_wmasks*self.and2.width) + ((self.num_wmasks-1)*spacing) - self.height = self.and2.height self.add_layout_pins() self.add_boundary() self.DRC_LVS() def add_pins(self): for bit in range(self.num_wmasks): - self.add_pin("wmask_in_{}".format(bit),"INPUT") + self.add_pin("wmask_in_{}".format(bit), "INPUT") self.add_pin("en", "INPUT") for bit in range(self.num_wmasks): - self.add_pin("wmask_out_{}".format(bit),"OUTPUT") - self.add_pin("vdd","POWER") - self.add_pin("gnd","GROUND") + self.add_pin("wmask_out_{}".format(bit), "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): # Size the AND gate for the number of write drivers it drives, which is equal to the write size. # Assume stage effort of 3 to compute the size self.and2 = factory.create(module_type="pand2", - size=self.write_size/4.0) + size=self.write_size / 4.0) self.add_mod(self.and2) - def create_and2_array(self): self.and2_insts = {} for bit in range(self.num_wmasks): @@ -81,7 +74,6 @@ class write_mask_and_array(design.design): "wmask_out_{}".format(bit), "vdd", "gnd"]) - def place_and2_array(self): # Place the write mask AND array at the start of each write driver enable length. # This ensures the write mask AND array will be directly under the corresponding write driver enable wire. @@ -96,56 +88,45 @@ class write_mask_and_array(design.design): self.wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing) debug.check(self.wmask_en_len >= self.and2.width, - "Write mask AND is wider than the corresponding write drivers {0} vs {1}.".format(self.and2.width,self.wmask_en_len)) + "Write mask AND is wider than the corresponding write drivers {0} vs {1}.".format(self.and2.width, + self.wmask_en_len)) + self.width = self.bitcell.width * self.columns + self.height = self.and2.height + for i in range(self.num_wmasks): base = vector(i * self.wmask_en_len, 0) self.and2_insts[i].place(base) - def add_layout_pins(self): # Create the enable pin that connects all write mask AND array's B pins - beg_en_pin = self.and2_insts[0].get_pin("B") - end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B") - if self.port % 2: - # Extend metal3 to edge of AND array in multiport - en_to_edge = self.and2.width - beg_en_pin.cx() - self.add_layout_pin(text="en", - layer="m3", - offset=beg_en_pin.bc(), - width=end_en_pin.cx() - beg_en_pin.cx() + en_to_edge) - self.add_via_center(layers=self.m1_stack, - offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy())) - self.add_via_center(layers=self.m2_stack, - offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy())) - else: - self.add_layout_pin(text="en", - layer="m3", - offset=beg_en_pin.bc(), - width=end_en_pin.cx() - beg_en_pin.cx()) + en_pin = self.and2_insts[0].get_pin("B") + self.add_layout_pin_segment_center(text="en", + layer="m3", + start=vector(0, en_pin.cy()), + end=vector(self.width, en_pin.cy())) for i in range(self.num_wmasks): # Copy remaining layout pins - self.copy_layout_pin(self.and2_insts[i],"A","wmask_in_{0}".format(i)) - self.copy_layout_pin(self.and2_insts[i],"Z","wmask_out_{0}".format(i)) + self.copy_layout_pin(self.and2_insts[i], "A", "wmask_in_{0}".format(i)) + self.copy_layout_pin(self.and2_insts[i], "Z", "wmask_out_{0}".format(i)) # Add via connections to metal3 for AND array's B pin en_pin = self.and2_insts[i].get_pin("B") - self.add_via_center(layers=self.m1_stack, - offset=en_pin.center()) - self.add_via_center(layers=self.m2_stack, - offset=en_pin.center()) + en_pos = en_pin.center() + self.add_via_stack_center(from_layer=en_pin.layer, + to_layer="m3", + offset=en_pos) for supply in ["gnd", "vdd"]: supply_pin=self.and2_insts[i].get_pin(supply) self.add_power_pin(supply, supply_pin.center()) - for supply in ["gnd", "vdd"]: supply_pin_left = self.and2_insts[0].get_pin(supply) - supply_pin_right = self.and2_insts[self.num_wmasks-1].get_pin(supply) - self.add_path("m1",[supply_pin_left.lc(), supply_pin_right.rc()]) + supply_pin_right = self.and2_insts[self.num_wmasks - 1].get_pin(supply) + self.add_path("m1", [supply_pin_left.lc(), supply_pin_right.rc()]) def get_cin(self): """Get the relative capacitance of all the input connections in the bank""" diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index c042947f..69af1e62 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -44,6 +44,7 @@ class pand2(pgate.pgate): self.place_insts() self.add_wires() self.add_layout_pins() + self.route_supply_rails() self.add_boundary() self.DRC_LVS() @@ -80,22 +81,6 @@ class pand2(pgate.pgate): [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()]) def add_layout_pins(self): - # Continous vdd rail along with label. - vdd_pin = self.inv_inst.get_pin("vdd") - self.add_layout_pin(text="vdd", - layer="m1", - offset=vdd_pin.ll().scale(0, 1), - width=self.width, - height=vdd_pin.height()) - - # Continous gnd rail along with label. - gnd_pin = self.inv_inst.get_pin("gnd") - self.add_layout_pin(text="gnd", - layer="m1", - offset=gnd_pin.ll().scale(0, 1), - width=self.width, - height=vdd_pin.height()) - pin = self.inv_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", layer=pin.layer, diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index ec0a5a31..841ac69d 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -44,6 +44,7 @@ class pand3(pgate.pgate): self.place_insts() self.add_wires() self.add_layout_pins() + self.route_supply_rails() self.add_boundary() self.DRC_LVS() @@ -81,22 +82,6 @@ class pand3(pgate.pgate): [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()]) def add_layout_pins(self): - # Continous vdd rail along with label. - vdd_pin = self.inv_inst.get_pin("vdd") - self.add_layout_pin(text="vdd", - layer="m1", - offset=vdd_pin.ll().scale(0, 1), - width=self.width, - height=vdd_pin.height()) - - # Continous gnd rail along with label. - gnd_pin = self.inv_inst.get_pin("gnd") - self.add_layout_pin(text="gnd", - layer="m1", - offset=gnd_pin.ll().scale(0, 1), - width=self.width, - height=vdd_pin.height()) - pin = self.inv_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", layer=pin.layer, diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 6f9719eb..4d90286d 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -37,6 +37,7 @@ class pbuf(pgate.pgate): self.place_insts() self.add_wires() self.add_layout_pins() + self.route_supply_rails() self.add_boundary() def add_pins(self): @@ -78,26 +79,9 @@ class pbuf(pgate.pgate): # inv1 Z to inv2 A z1_pin = self.inv1_inst.get_pin("Z") a2_pin = self.inv2_inst.get_pin("A") - mid_point = vector(z1_pin.cx(), a2_pin.cy()) - self.add_path("m1", [z1_pin.center(), mid_point, a2_pin.center()]) + self.add_zjog(self.route_layer, z1_pin.center(), a2_pin.center()) def add_layout_pins(self): - # Continous vdd rail along with label. - vdd_pin = self.inv1_inst.get_pin("vdd") - self.add_layout_pin(text="vdd", - layer="m1", - offset=vdd_pin.ll().scale(0, 1), - width=self.width, - height=vdd_pin.height()) - - # Continous gnd rail along with label. - gnd_pin = self.inv1_inst.get_pin("gnd") - self.add_layout_pin(text="gnd", - layer="m1", - offset=gnd_pin.ll().scale(0, 1), - width=self.width, - height=vdd_pin.height()) - z_pin = self.inv2_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", layer=z_pin.layer, diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 6e79ae14..9bba7aee 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -76,6 +76,7 @@ class pdriver(pgate.pgate): self.width = self.inv_inst_list[-1].rx() self.height = self.inv_inst_list[0].height + self.route_supply_rails() self.add_boundary() def add_pins(self): @@ -146,21 +147,6 @@ class pdriver(pgate.pgate): a_inst_list[x].center()]) def add_layout_pins(self): - # Continous vdd rail along with label. - vdd_pin = self.inv_inst_list[0].get_pin("vdd") - self.add_layout_pin(text="vdd", - layer="m1", - offset=vdd_pin.ll().scale(0, 1), - width=self.width, - height=vdd_pin.height()) - - # Continous gnd rail along with label. - gnd_pin = self.inv_inst_list[0].get_pin("gnd") - self.add_layout_pin(text="gnd", - layer="m1", - offset=gnd_pin.ll().scale(0, 1), - width=self.width, - height=vdd_pin.height()) z_pin = self.inv_inst_list[len(self.inv_inst_list) - 1].get_pin("Z") self.add_layout_pin_rect_center(text="Z", diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 7c294e0a..5351be07 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -17,6 +17,7 @@ from globals import OPTS if(OPTS.tech_name == "s8"): from tech import nmos_bins, pmos_bins, accuracy_requirement + class pgate(design.design): """ This is a module that implements some shared @@ -30,8 +31,8 @@ class pgate(design.design): if height: self.height = height elif not height: - # By default, we make it 10 M1 pitch tall - self.height = 10*self.m1_pitch + # By default, something simple + self.height = 14 * self.m1_pitch if "li" in layer: self.route_layer = "li" @@ -40,7 +41,15 @@ class pgate(design.design): self.route_layer_width = getattr(self, "{}_width".format(self.route_layer)) self.route_layer_space = getattr(self, "{}_space".format(self.route_layer)) self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer)) - + + # This is the space from a S/D contact to the supply rail + # Assume the contact starts at the active edge + contact_to_vdd_rail_space = 0.5 * self.m1_width + self.m1_space + # This is a poly-to-poly of a flipped cell + poly_to_poly_gate_space = self.poly_extend_active + self.poly_space + self.top_bottom_space = max(contact_to_vdd_rail_space, + poly_to_poly_gate_space) + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -68,13 +77,14 @@ class pgate(design.design): height = supply_pin.uy() - source_pin.by() else: debug.error("Invalid supply name.", -1) - + + debug.check(supply_pin.layer == source_pin.layer, "Supply pin is not on correct layer.") self.add_rect(layer=source_pin.layer, offset=source_pin.ll(), height=height, width=source_pin.width()) - def route_input_gate(self, pmos_inst, nmos_inst, ypos, name, position="left"): + def route_input_gate(self, pmos_inst, nmos_inst, ypos, name, position="left", directions=None): """ Route the input gate to the left side of the cell for access. Position specifies to place the contact the left, center, or @@ -100,8 +110,6 @@ class pgate(design.design): # Center is completely symmetric. contact_width = contact.poly_contact.width - contact_m1_width = contact.poly_contact.second_layer_width - contact_m1_height = contact.poly_contact.second_layer_height if position == "center": contact_offset = left_gate_offset \ @@ -118,18 +126,16 @@ class pgate(design.design): else: debug.error("Invalid contact placement option.", -1) - if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=contact_offset) - - self.add_via_center(layers=self.poly_stack, - offset=contact_offset) + via = self.add_via_stack_center(from_layer="poly", + to_layer=self.route_layer, + offset=contact_offset, + directions=directions) self.add_layout_pin_rect_center(text=name, - layer="m1", + layer=self.route_layer, offset=contact_offset, - width=contact_m1_width, - height=contact_m1_height) + width=via.mod.second_layer_width, + height=via.mod.second_layer_height) # This is to ensure that the contact is # connected to the gate mid_point = contact_offset.scale(0.5, 1) \ @@ -201,12 +207,10 @@ class pgate(design.design): self.nwell_contact = self.add_via_center(layers=layer_stack, offset=contact_offset, implant_type="n", - well_type="n") - if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=contact_offset) + well_type="n", + directions=("V", "V")) - self.add_rect_center(layer="m1", + self.add_rect_center(layer=self.route_layer, offset=contact_offset + vector(0, 0.5 * (self.height - contact_offset.y)), width=self.nwell_contact.mod.second_layer_width, height=self.height - contact_offset.y) @@ -256,13 +260,10 @@ class pgate(design.design): self.pwell_contact= self.add_via_center(layers=layer_stack, offset=contact_offset, implant_type="p", - well_type="p") - - if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=contact_offset) - - self.add_rect_center(layer="m1", + well_type="p", + directions=("V", "V")) + + self.add_rect_center(layer=self.route_layer, offset=contact_offset.scale(1, 0.5), width=self.pwell_contact.mod.second_layer_width, height=contact_offset.y) @@ -286,6 +287,18 @@ class pgate(design.design): # offset=implant_offset, # width=implant_width, # height=implant_height) + + def route_supply_rails(self): + """ Add vdd/gnd rails to the top and bottom. """ + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, 0), + width=self.width) + + self.add_layout_pin_rect_center(text="vdd", + layer=self.route_layer, + offset=vector(0.5 * self.width, self.height), + width=self.width) def determine_width(self): """ Determine the width based on the well contacts (assumed to be on the right side) """ diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index b522227b..e0e1ce81 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -107,13 +107,6 @@ class pinv(pgate.pgate): min_channel = max(contact.poly_contact.width + self.m1_space, contact.poly_contact.width + 2 * self.poly_to_active) - # This is the extra space needed to ensure DRC rules - # to the active contacts - extra_contact_space = max(-nmos.get_pin("D").by(), 0) - # This is a poly-to-poly of a flipped cell - self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space, - self.poly_extend_active + self.poly_space) - total_height = tx_height + min_channel + 2 * self.top_bottom_space # debug.check(self.height > total_height, # "Cell height {0} too small for simple min height {1}.".format(self.height, @@ -201,7 +194,7 @@ class pinv(pgate.pgate): width=self.nmos_width, mults=self.tx_mults, tx_type="nmos", - add_source_contact="m1", + add_source_contact=self.route_layer, add_drain_contact=self.route_layer, connect_poly=True, connect_drain_active=True) @@ -211,24 +204,12 @@ class pinv(pgate.pgate): width=self.pmos_width, mults=self.tx_mults, tx_type="pmos", - add_source_contact="m1", + add_source_contact=self.route_layer, add_drain_contact=self.route_layer, connect_poly=True, connect_drain_active=True) self.add_mod(self.pmos) - def route_supply_rails(self): - """ Add vdd/gnd rails to the top and bottom. """ - self.add_layout_pin_rect_center(text="gnd", - layer="m1", - offset=vector(0.5 * self.width, 0), - width=self.width) - - self.add_layout_pin_rect_center(text="vdd", - layer="m1", - offset=vector(0.5 * self.width, self.height), - width=self.width) - def create_ptx(self): """ Create the PMOS and NMOS netlist. diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 713f779d..5d20201e 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -76,7 +76,7 @@ class pnand2(pgate.pgate): width=self.nmos_width, mults=self.tx_mults, tx_type="nmos", - add_source_contact="m1", + add_source_contact=self.route_layer, add_drain_contact="active") self.add_mod(self.nmos_left) @@ -92,7 +92,7 @@ class pnand2(pgate.pgate): width=self.pmos_width, mults=self.tx_mults, tx_type="pmos", - add_source_contact="m1", + add_source_contact=self.route_layer, add_drain_contact=self.route_layer) self.add_mod(self.pmos_left) @@ -101,43 +101,17 @@ class pnand2(pgate.pgate): mults=self.tx_mults, tx_type="pmos", add_source_contact=self.route_layer, - add_drain_contact="m1") + add_drain_contact=self.route_layer) self.add_mod(self.pmos_right) def setup_layout_constants(self): """ Pre-compute some handy layout parameters. """ - # metal spacing to allow contacts on any layer - self.input_spacing = max(self.poly_space + contact.poly_contact.first_layer_width, - self.m1_space + contact.m1_via.first_layer_width, - self.m2_space + contact.m2_via.first_layer_width, - self.m3_space + contact.m2_via.second_layer_width) - - # Compute the other pmos2 location, # but determining offset to overlap the # source and drain pins self.overlap_offset = self.pmos_left.get_pin("D").center() - self.pmos_left.get_pin("S").center() - # This is the extra space needed to ensure DRC rules - # to the active contacts - extra_contact_space = max(-self.nmos_left.get_pin("D").by(), 0) - # This is a poly-to-poly of a flipped cell - self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, - self.poly_extend_active + self.poly_space) - - def route_supply_rails(self): - """ Add vdd/gnd rails to the top and bottom. """ - self.add_layout_pin_rect_center(text="gnd", - layer="m1", - offset=vector(0.5*self.width, 0), - width=self.width) - - self.add_layout_pin_rect_center(text="vdd", - layer="m1", - offset=vector(0.5 * self.width, self.height), - width=self.width) - def create_ptx(self): """ Add PMOS and NMOS to the netlist. @@ -200,35 +174,46 @@ class pnand2(pgate.pgate): def route_inputs(self): """ Route the A and B inputs """ + + + # Top of NMOS drain + nmos_pin = self.nmos2_inst.get_pin("D") + bottom_pin_offset = nmos_pin.uy() + self.inputA_yoffset = bottom_pin_offset + self.m1_pitch + + self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch + # This will help with the wells and the input/output placement - inputB_yoffset = self.pmos2_inst.by() - max(self.poly_extend_active + contact.poly_contact.height, - self.m1_space + 0.5 * contact.m1_via.height) self.route_input_gate(self.pmos2_inst, self.nmos2_inst, - inputB_yoffset, + self.inputB_yoffset, "B", - position="right") + position="center") - self.inputA_yoffset = self.nmos2_inst.uy() + max(self.poly_extend_active + contact.poly_contact.height, - self.m1_space + 0.5 * contact.m1_via.height) self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, - "A") + "A", + position="center") def route_output(self): """ Route the Z output """ + + # One routing track layer below the PMOS contacts + route_layer_offset = 0.5 * self.route_layer_width + self.route_layer_space + output_yoffset = self.pmos1_inst.get_pin("D").by() - route_layer_offset + # PMOS1 drain pmos_pin = self.pmos1_inst.get_pin("D") - top_pin_offset = pmos_pin.center() + top_pin_offset = pmos_pin.bc() # NMOS2 drain nmos_pin = self.nmos2_inst.get_pin("D") - bottom_pin_offset = nmos_pin.center() + bottom_pin_offset = nmos_pin.uc() # Output pin - out_offset = vector(nmos_pin.cx(), - self.inputA_yoffset) + out_offset = vector(nmos_pin.cx() + self.route_layer_pitch, + output_yoffset) # This routes on M2 # # Midpoints of the L routes go horizontal first then vertical @@ -253,10 +238,15 @@ class pnand2(pgate.pgate): # This routes on route_layer # Midpoints of the L routes goes vertical first then horizontal - mid1_offset = vector(top_pin_offset.x, out_offset.y) - + top_mid_offset = vector(top_pin_offset.x, out_offset.y) + # Top transistors self.add_path(self.route_layer, - [top_pin_offset, mid1_offset, out_offset, bottom_pin_offset]) + [top_pin_offset, top_mid_offset, out_offset]) + + bottom_mid_offset = bottom_pin_offset + vector(0, self.route_layer_pitch) + # Bottom transistors + self.add_path(self.route_layer, + [out_offset, bottom_mid_offset, bottom_pin_offset]) # This extends the output to the edge of the cell self.add_layout_pin_rect_center(text="Z", diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 20337095..454b75dd 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -5,7 +5,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import contact import pgate import debug from tech import drc, parameter, spice @@ -14,6 +13,7 @@ import logical_effort from sram_factory import factory from globals import OPTS + class pnand3(pgate.pgate): """ This module generates gds of a parametrically sized 2-input nand. @@ -94,7 +94,7 @@ class pnand3(pgate.pgate): width=self.nmos_width, mults=self.tx_mults, tx_type="nmos", - add_source_contact="m1", + add_source_contact=self.route_layer, add_drain_contact="active") self.add_mod(self.nmos_left) @@ -102,7 +102,7 @@ class pnand3(pgate.pgate): width=self.pmos_width, mults=self.tx_mults, tx_type="pmos", - add_source_contact="m1", + add_source_contact=self.route_layer, add_drain_contact=self.route_layer) self.add_mod(self.pmos_left) @@ -111,14 +111,14 @@ class pnand3(pgate.pgate): mults=self.tx_mults, tx_type="pmos", add_source_contact=self.route_layer, - add_drain_contact="m1") + add_drain_contact=self.route_layer) self.add_mod(self.pmos_center) self.pmos_right = factory.create(module_type="ptx", width=self.pmos_width, mults=self.tx_mults, tx_type="pmos", - add_source_contact="m1", + add_source_contact=self.route_layer, add_drain_contact=self.route_layer) self.add_mod(self.pmos_right) @@ -132,21 +132,6 @@ class pnand3(pgate.pgate): # to the active contacts nmos = factory.create(module_type="ptx", tx_type="nmos") extra_contact_space = max(-nmos.get_pin("D").by(), 0) - # This is a poly-to-poly of a flipped cell - self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, - self.poly_extend_active + self.poly_space) - - def route_supply_rails(self): - """ Add vdd/gnd rails to the top and bottom. """ - self.add_layout_pin_rect_center(text="gnd", - layer="m1", - offset=vector(0.5 * self.width, 0), - width=self.width) - - self.add_layout_pin_rect_center(text="vdd", - layer="m1", - offset=vector(0.5 * self.width, self.height), - width=self.width) def create_ptx(self): """ @@ -223,37 +208,34 @@ class pnand3(pgate.pgate): def route_inputs(self): """ Route the A and B and C inputs """ - m1_pitch = self.m1_space + contact.m1_via.first_layer_height - # Put B right on the well line - self.inputB_yoffset = self.nwell_y_offset - self.route_input_gate(self.pmos2_inst, - self.nmos2_inst, - self.inputB_yoffset, - "B", - position="center") - - # FIXME: constant hack - self.inputC_yoffset = self.inputB_yoffset - 1.15 * m1_pitch - self.route_input_gate(self.pmos3_inst, - self.nmos3_inst, - self.inputC_yoffset, - "C", - position="right") + pmos_drain_bottom = self.pmos1_inst.get_pin("D").by() + self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space - # FIXME: constant hack - if OPTS.tech_name == "s8": - self.inputA_yoffset = self.inputB_yoffset + 1.15 * m1_pitch - else: - self.inputA_yoffset = self.inputB_yoffset + 1.12 * m1_pitch + self.inputA_yoffset = self.output_yoffset - 0.5 * self.route_layer_width - self.route_layer_space self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, "A", position="left") + + # Put B right on the well line + self.inputB_yoffset = self.inputA_yoffset - self.m1_pitch + self.route_input_gate(self.pmos2_inst, + self.nmos2_inst, + self.inputB_yoffset, + "B", + position="center") + + self.inputC_yoffset = self.inputB_yoffset - self.m1_pitch + self.route_input_gate(self.pmos3_inst, + self.nmos3_inst, + self.inputC_yoffset, + "C", + position="right") def route_output(self): """ Route the Z output """ - + # PMOS1 drain pmos1_pin = self.pmos1_inst.get_pin("D") # PMOS3 drain @@ -262,7 +244,7 @@ class pnand3(pgate.pgate): nmos3_pin = self.nmos3_inst.get_pin("D") out_offset = vector(nmos3_pin.cx() + self.route_layer_pitch, - self.inputA_yoffset) + self.output_yoffset) # Go up to metal2 for ease on all output pins # self.add_via_center(layers=self.m1_stack, diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 3ba7d9fd..f522578e 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -75,7 +75,7 @@ class pnor2(pgate.pgate): width=self.nmos_width, mults=self.tx_mults, tx_type="nmos", - add_source_contact="m1", + add_source_contact=self.route_layer, add_drain_contact=self.route_layer) self.add_mod(self.nmos_left) @@ -84,14 +84,14 @@ class pnor2(pgate.pgate): mults=self.tx_mults, tx_type="nmos", add_source_contact=self.route_layer, - add_drain_contact="m1") + add_drain_contact=self.route_layer) self.add_mod(self.nmos_right) self.pmos_left = factory.create(module_type="ptx", width=self.pmos_width, mults=self.tx_mults, tx_type="pmos", - add_source_contact="m1", + add_source_contact=self.route_layer, add_drain_contact="active") self.add_mod(self.pmos_left) @@ -106,12 +106,6 @@ class pnor2(pgate.pgate): def setup_layout_constants(self): """ Pre-compute some handy layout parameters. """ - # metal spacing to allow contacts on any layer - self.input_spacing = max(self.poly_space + contact.poly_contact.first_layer_width, - self.m1_space + contact.m1_via.first_layer_width, - self.m2_space + contact.m2_via.first_layer_width, - self.m3_space + contact.m2_via.second_layer_width) - # Compute the other pmos2 location, but determining # offset to overlap the source and drain pins self.overlap_offset = self.pmos_right.get_pin("D").center() - self.pmos_left.get_pin("S").center() @@ -124,27 +118,7 @@ class pnor2(pgate.pgate): + 0.5 * self.nwell_enclose_active self.well_width = self.width + 2 * self.nwell_enclose_active # Height is an input parameter, so it is not recomputed. - - # This is the extra space needed to ensure DRC rules - # to the active contacts - extra_contact_space = max(-self.nmos_right.get_pin("D").by(), 0) - # This is a poly-to-poly of a flipped cell - self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, - self.poly_extend_active, - self.poly_space) - def route_supply_rails(self): - """ Add vdd/gnd rails to the top and bottom. """ - self.add_layout_pin_rect_center(text="gnd", - layer="m1", - offset=vector(0.5 * self.width, 0), - width=self.width) - - self.add_layout_pin_rect_center(text="vdd", - layer="m1", - offset=vector(0.5 * self.width, self.height), - width=self.width) - def create_ptx(self): """ Add PMOS and NMOS to the layout at the upper-most and lowest position @@ -172,10 +146,19 @@ class pnor2(pgate.pgate): Add PMOS and NMOS to the layout at the upper-most and lowest position to provide maximum routing in channel """ + # Some of the S/D contacts may extend beyond the active, + # but this needs to be done in the gate itself + contact_extend_active_space = max(-self.nmos_right.get_pin("D").by(), 0) + # Assume the contact starts at the active edge + contact_to_vdd_rail_space = 0.5 * self.m1_width + self.m1_space + contact_extend_active_space + # This is a poly-to-poly of a flipped cell + poly_to_poly_gate_space = self.poly_extend_active + self.poly_space + # Recompute this since it has a small txwith the added contact extend active spacing + self.top_bottom_space = max(contact_to_vdd_rail_space, + poly_to_poly_gate_space) pmos1_pos = vector(self.pmos_right.active_offset.x, - self.height - self.pmos_right.active_height \ - - self.top_bottom_space) + self.height - self.pmos_right.active_height - self.top_bottom_space) self.pmos1_inst.place(pmos1_pos) self.pmos2_pos = pmos1_pos + self.overlap_offset @@ -186,7 +169,6 @@ class pnor2(pgate.pgate): self.nmos2_pos = nmos1_pos + self.overlap_offset self.nmos2_inst.place(self.nmos2_pos) - def add_well_contacts(self): """ Add n/p well taps to the layout and connect to supplies """ @@ -205,22 +187,28 @@ class pnor2(pgate.pgate): def route_inputs(self): """ Route the A and B inputs """ - # Use M2 spaces so we can drop vias on the pins later! - inputB_yoffset = self.nmos2_inst.uy() + contact.poly_contact.height + + # Top of NMOS drain + nmos_pin = self.nmos2_inst.get_pin("D") + bottom_pin_offset = nmos_pin.uy() + self.inputB_yoffset = bottom_pin_offset + self.m1_nonpref_pitch + self.inputA_yoffset = self.inputB_yoffset + self.m1_nonpref_pitch + self.route_input_gate(self.pmos2_inst, self.nmos2_inst, - inputB_yoffset, + self.inputB_yoffset, "B", - position="right") + position="right", + directions=("V", "V")) # This will help with the wells and the input/output placement - self.inputA_yoffset = inputB_yoffset + self.input_spacing self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, - "A") + "A", + directions=("V", "V")) - self.output_yoffset = self.inputA_yoffset + self.input_spacing + self.output_yoffset = self.inputA_yoffset + self.m1_nonpref_pitch def route_output(self): """ Route the Z output """ diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index b8ecb3e1..d47e445f 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -159,7 +159,7 @@ class precharge(design.design): self.lower_pmos_inst.place(self.lower_pmos_position) # adds the upper pmos(s) to layout with 2 M2 tracks - ydiff = self.pmos.height + self.m2_pitch + ydiff = self.pmos.height + 2 * self.m2_pitch self.upper_pmos1_pos = self.lower_pmos_position + vector(0, ydiff) self.upper_pmos1_inst.place(self.upper_pmos1_pos) diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index 22f6b164..9fd5f8b6 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -79,9 +79,6 @@ class ptristate_inv(pgate.pgate): self.width = self.well_width + 0.5 * self.m1_space # Height is an input parameter, so it is not recomputed. - # Make sure we can put a well above and below - self.top_bottom_space = max(contact.active_contact.width, contact.active_contact.height) - def add_ptx(self): """ Create the PMOS and NMOS transistors. """ self.nmos = factory.create(module_type="ptx", diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 6fcb722d..c584e70b 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -38,15 +38,18 @@ class ptx(design.design): connect_poly=False, num_contacts=None): - if not add_source_contact and "li" in layer: - add_source_contact = "li" - elif not add_source_contact: - add_source_contact = "m1" + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" - if not add_drain_contact and "li" in layer: - add_drain_contact = "li" - elif not add_drain_contact: - add_drain_contact = "m1" + # Default contacts are the lowest layer + if not add_source_contact: + add_source_contact = self.route_layer + + # Default contacts are the lowest layer + if not add_drain_contact: + add_drain_contact = self.route_layer # We need to keep unique names because outputting to GDSII # will use the last record with a given name. I.e., you will @@ -81,10 +84,6 @@ class ptx(design.design): self.series_devices = series_devices self.num_contacts = num_contacts - if "li" in layer: - self.route_layer = "li" - else: - self.route_layer = "m1" self.route_layer_width = drc("minwidth_{}".format(self.route_layer)) self.route_layer_space = drc("{0}_to_{0}".format(self.route_layer)) @@ -286,23 +285,16 @@ class ptx(design.design): width=poly_width, height=self.poly_width) - def connect_fingered_active(self, positions, pin_name, layer, top): + def connect_fingered_active(self, positions, pin_name, top): """ Connect each contact up/down to a source or drain pin """ - - if top: - dir = 1 - else: - dir = -1 if len(positions) <= 1: return - debug.check(layer != "active", "Must specify a metal for source connections.") - - layer_space = getattr(self, "{}_space".format(layer)) - layer_width = getattr(self, "{}_width".format(layer)) + layer_space = getattr(self, "{}_space".format(self.route_layer)) + layer_width = getattr(self, "{}_width".format(self.route_layer)) # This is the distance that we must route up or down from the center # of the contacts to avoid DRC violations to the other contacts @@ -311,16 +303,21 @@ class ptx(design.design): # This is the width of a m1 extend the ends of the pin end_offset = vector(layer_width / 2.0, 0) - offset = pin_offset.scale(dir, dir) + # We move the opposite direction from the bottom + if not top: + offset = pin_offset.scale(-1, -1) + else: + offset = pin_offset + # remove the individual connections self.remove_layout_pin(pin_name) # Add each vertical segment for a in positions: - self.add_path(self.add_source_contact, - [a, a + pin_offset.scale(dir, dir)]) + self.add_path(self.route_layer, + [a, a + offset]) # Add a single horizontal pin self.add_layout_pin_segment_center(text=pin_name, - layer=layer, + layer=self.route_layer, start=positions[0] + offset - end_offset, end=positions[-1] + offset + end_offset) @@ -475,10 +472,10 @@ class ptx(design.design): offset=pos) if self.connect_source_active: - self.connect_fingered_active(source_positions, "S", self.add_source_contact, top=(self.tx_type=="pmos")) + self.connect_fingered_active(source_positions, "S", top=(self.tx_type=="pmos")) if self.connect_drain_active: - self.connect_fingered_active(drain_positions, "D", self.add_drain_contact, top=(self.tx_type=="nmos")) + self.connect_fingered_active(drain_positions, "D", top=(self.tx_type=="nmos")) def get_stage_effort(self, cout): """Returns an object representing the parameters for delay in tau units.""" @@ -509,21 +506,24 @@ class ptx(design.design): else: debug.error("Invalid source drain name.") - via=self.add_via_stack_center(offset=pos, - from_layer="active", - to_layer=layer, - size=(1, self.num_contacts), - directions=("V", "V"), - implant_type=self.implant_type, - well_type=self.well_type) + if layer != "active": + via=self.add_via_stack_center(offset=pos, + from_layer="active", + to_layer=layer, + size=(1, self.num_contacts), + directions=("V", "V"), + implant_type=self.implant_type, + well_type=self.well_type) - if layer == "active": - source_via = getattr(contact, "{}_contact".format(layer)) + pin_height = via.mod.second_layer_height + pin_width = via.mod.second_layer_width else: - source_via = getattr(contact, "{}_via".format(layer)) + via = None + + pin_height = None + pin_width = None + # Source drain vias are all vertical - pin_height = source_via.first_layer_width - pin_width = source_via.first_layer_height self.add_layout_pin_rect_center(text=label, layer=layer, offset=pos, diff --git a/compiler/router/router_tech.py b/compiler/router/router_tech.py index e0f277e9..27156eeb 100644 --- a/compiler/router/router_tech.py +++ b/compiler/router/router_tech.py @@ -18,17 +18,13 @@ class router_tech: """ def __init__(self, layers, rail_track_width): """ - Allows us to change the layers that we are routing on. First layer - is always horizontal, middle is via, and last is always - vertical. + Allows us to change the layers that we are routing on. + This uses the preferreed directions. """ self.layers = layers self.rail_track_width = rail_track_width if len(self.layers) == 1: - if preferred_directions[self.layers[0]] != "H": - debug.warning("Using '{}' for horizontal routing, but it " \ - "prefers vertical routing".format(self.layers[0])) self.horiz_layer_name = self.vert_layer_name = self.layers[0] self.horiz_lpp = self.vert_lpp = layer[self.layers[0]] @@ -42,13 +38,21 @@ class router_tech: # figure out wich of the two layers prefers horizontal/vertical # routing - if preferred_directions[try_horiz_layer] == "H" and preferred_directions[try_vert_layer] == "V": + self.horiz_layer_name = None + self.vert_layer_name = None + + if preferred_directions[try_horiz_layer] == "H": self.horiz_layer_name = try_horiz_layer + else: + self.horiz_layer_name = try_vert_layer + if preferred_directions[try_vert_layer] == "V": self.vert_layer_name = try_vert_layer else: - raise ValueError("Layer '{}' and '{}' are using the wrong " \ - "preferred_directions '{}' and '{}'. Only "\ - "('H', 'V') are supported") + self.vert_layer_name = try_horiz_layer + + if not self.horiz_layer_name or not self.vert_layer_name: + raise ValueError("Layer '{}' and '{}' are using the wrong " + "preferred_directions '{}' and '{}'.") via_connect = contact(self.layers, (1, 1)) max_via_size = max(via_connect.width,via_connect.height) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 76e9f805..8dbcfaf4 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -59,14 +59,23 @@ class sram_1bank(sram_base): wmask_pos = [None] * len(self.all_ports) data_pos = [None] * len(self.all_ports) + # These positions utilize the channel route sizes. + # FIXME: Auto-compute these rather than manual computation. + # If a horizontal channel, they rely on the vertical channel non-preferred (contacted) pitch. + # If a vertical channel, they rely on the horizontal channel non-preferred (contacted) pitch. + # So, m3 non-pref pitch means that this is routed on the m2 layer. if self.write_size: - max_gap_size = self.m3_pitch * self.word_size + 2 * self.m1_pitch - max_gap_size_wmask = self.m2_pitch * max(self.num_wmasks + 1, self.col_addr_size + 1) + 2 * self.m1_pitch + self.data_bus_gap = self.m4_nonpref_pitch * 2 + self.data_bus_size = self.m4_nonpref_pitch * (self.word_size) + self.data_bus_gap + self.wmask_bus_gap = self.m2_nonpref_pitch * 2 + self.wmask_bus_size = self.m2_nonpref_pitch * (max(self.num_wmasks + 1, self.col_addr_size + 1)) + self.wmask_bus_gap else: - # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk - # The M1 pitch is for supply rail spacings - max_gap_size = self.m2_pitch * max(self.word_size + 1,self.col_addr_size + 1) + 2 * self.m1_pitch + self.data_bus_gap = self.m3_nonpref_pitch * 2 + self.data_bus_size = self.m3_nonpref_pitch * (max(self.word_size + 1, self.col_addr_size + 1)) + self.data_bus_gap + self.col_addr_bus_gap = self.m2_nonpref_pitch * 2 + self.col_addr_bus_size = self.m2_nonpref_pitch * (self.col_addr_size) + self.col_addr_bus_gap + # Port 0 port = 0 @@ -74,12 +83,12 @@ class sram_1bank(sram_base): if self.write_size: # Add the write mask flops below the write mask AND array. wmask_pos[port] = vector(self.bank.bank_array_ll.x, - -max_gap_size_wmask - self.dff.height) + - self.wmask_bus_size - self.dff.height) self.wmask_dff_insts[port].place(wmask_pos[port]) # Add the data flops below the write mask flops. data_pos[port] = vector(self.bank.bank_array_ll.x, - -max_gap_size - max_gap_size_wmask - 2 * self.dff.height) + - self.data_bus_size - self.wmask_bus_size - 2 * self.dff.height) self.data_dff_insts[port].place(data_pos[port]) else: # Add the data flops below the bank to the right of the lower-left of bank array @@ -89,7 +98,7 @@ class sram_1bank(sram_base): # sense amps. if port in self.write_ports: data_pos[port] = vector(self.bank.bank_array_ll.x, - -max_gap_size - self.dff.height) + -self.data_bus_size - self.dff.height) self.data_dff_insts[port].place(data_pos[port]) else: wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0) @@ -99,10 +108,10 @@ class sram_1bank(sram_base): if self.col_addr_dff: if self.write_size: col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, - -max_gap_size_wmask - self.col_addr_dff_insts[port].height) + -self.wmask_bus_size - self.col_addr_dff_insts[port].height) else: col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, - -max_gap_size - self.col_addr_dff_insts[port].height) + -self.data_bus_size - self.col_addr_dff_insts[port].height) self.col_addr_dff_insts[port].place(col_addr_pos[port]) else: col_addr_pos[port] = vector(self.bank.bank_array_ll.x, 0) @@ -127,12 +136,12 @@ class sram_1bank(sram_base): if self.write_size: # Add the write mask flops below the write mask AND array. wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.wmask_dff_insts[port].width, - self.bank.height + max_gap_size_wmask + self.dff.height) + self.bank.height + self.wmask_bus_size + self.dff.height) self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") # Add the data flops below the write mask flops data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.height + max_gap_size_wmask + max_gap_size + 2 * self.dff.height) + self.bank.height + self.wmask_bus_size + self.data_bus_size + 2 * self.dff.height) self.data_dff_insts[port].place(data_pos[port], mirror="MX") else: # Add the data flops above the bank to the left of the upper-right of bank array @@ -141,17 +150,17 @@ class sram_1bank(sram_base): # These flops go below the sensing and leave a gap to channel route to the # sense amps. data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.height + max_gap_size + self.dff.height) + self.bank.height + self.data_bus_size + self.dff.height) self.data_dff_insts[port].place(data_pos[port], mirror="MX") # Add the col address flops above the bank to the right of the upper-right of bank array if self.col_addr_dff: if self.write_size: col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, - self.bank.height + max_gap_size_wmask + self.dff.height) + self.bank.height + self.wmask_bus_size + self.dff.height) else: col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, - self.bank.height + max_gap_size + self.dff.height) + self.bank.height + self.data_bus_size + self.dff.height) self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX") else: col_addr_pos[port] = self.bank_inst.ur() @@ -245,7 +254,7 @@ class sram_1bank(sram_base): # This uses a metal2 track to the right (for port0) of the control/row addr DFF # to route vertically. For port1, it is to the left. row_addr_clk_pin = self.row_addr_dff_insts[port].get_pin("clk") - if port%2: + if port % 2: control_clk_buf_pos = control_clk_buf_pin.lc() row_addr_clk_pos = row_addr_clk_pin.lc() mid1_pos = vector(self.row_addr_dff_insts[port].lx() - self.m2_pitch, @@ -258,19 +267,20 @@ class sram_1bank(sram_base): # This is the steiner point where the net branches out clk_steiner_pos = vector(mid1_pos.x, control_clk_buf_pos.y) - self.add_path("m1", [control_clk_buf_pos, clk_steiner_pos]) - self.add_via_center(layers=self.m1_stack, - offset=clk_steiner_pos) + self.add_path(control_clk_buf_pin.layer, [control_clk_buf_pos, clk_steiner_pos]) + self.add_via_stack_center(from_layer=control_clk_buf_pin.layer, + to_layer="m2", + offset=clk_steiner_pos) # Note, the via to the control logic is taken care of above - self.add_wire(("m3", "via2", "m2"), + self.add_wire(self.m2_stack[::-1], [row_addr_clk_pos, mid1_pos, clk_steiner_pos]) if self.col_addr_dff: dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk") dff_clk_pos = dff_clk_pin.center() mid_pos = vector(clk_steiner_pos.x, dff_clk_pos.y) - self.add_wire(("m3", "via2", "m2"), + self.add_wire(self.m2_stack[::-1], [dff_clk_pos, mid_pos, clk_steiner_pos]) if port in self.write_ports: @@ -282,7 +292,7 @@ class sram_1bank(sram_base): self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height)) - self.add_wire(("m3", "via2", "m2"), + self.add_wire(self.m2_stack[::-1], [data_dff_clk_pos, mid_pos, clk_steiner_pos]) if self.write_size: @@ -292,7 +302,7 @@ class sram_1bank(sram_base): # In some designs, the steiner via will be too close to the mid_pos via # so make the wire as wide as the contacts self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height)) - self.add_wire(("m3", "via2", "m2"), [wmask_dff_clk_pos, mid_pos, clk_steiner_pos]) + self.add_wire(self.m2_stack[::-1], [wmask_dff_clk_pos, mid_pos, clk_steiner_pos]) def route_control_logic(self): """ Route the control logic pins that are not inputs """ @@ -304,14 +314,13 @@ class sram_1bank(sram_base): continue src_pin = self.control_logic_insts[port].get_pin(signal) dest_pin = self.bank_inst.get_pin(signal + "{}".format(port)) - self.connect_vbus_m2m3(src_pin, dest_pin) + self.connect_vbus(src_pin, dest_pin) for port in self.all_ports: # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) - - self.connect_hbus_m2m3(src_pin, dest_pin) + self.connect_hbus(src_pin, dest_pin) def route_row_addr_dff(self): """ Connect the output of the row flops to the bank pins """ @@ -324,33 +333,37 @@ class sram_1bank(sram_base): flop_pos = flop_pin.center() bank_pos = bank_pin.center() mid_pos = vector(bank_pos.x, flop_pos.y) - self.add_wire(("m3", "via2", "m2"), + self.add_wire(self.m2_stack[::-1], [flop_pos, mid_pos, bank_pos]) - self.add_via_center(layers=self.m2_stack, - offset=flop_pos) + self.add_via_stack_center(from_layer=flop_pin.layer, + to_layer="m3", + offset=flop_pos) def route_col_addr_dff(self): """ Connect the output of the col flops to the bank pins """ for port in self.all_ports: - if port%2: - offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.col_addr_size + 2) * self.m1_pitch) + if port % 2: + offset = self.col_addr_dff_insts[port].ll() - vector(0, self.col_addr_bus_size) else: - offset = self.col_addr_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch) + offset = self.col_addr_dff_insts[port].ul() + vector(0, self.col_addr_bus_gap) bus_names = ["addr_{}".format(x) for x in range(self.col_addr_size)] col_addr_bus_offsets = self.create_horizontal_bus(layer="m1", - pitch=self.m1_pitch, offset=offset, names=bus_names, length=self.col_addr_dff_insts[port].width) dff_names = ["dout_{}".format(x) for x in range(self.col_addr_size)] data_dff_map = zip(dff_names, bus_names) - self.connect_horizontal_bus(data_dff_map, self.col_addr_dff_insts[port], col_addr_bus_offsets) + self.connect_horizontal_bus(data_dff_map, + self.col_addr_dff_insts[port], + col_addr_bus_offsets) bank_names = ["addr{0}_{1}".format(port, x) for x in range(self.col_addr_size)] data_bank_map = zip(bank_names, bus_names) - self.connect_horizontal_bus(data_bank_map, self.bank_inst, col_addr_bus_offsets) + self.connect_horizontal_bus(data_bank_map, + self.bank_inst, + col_addr_bus_offsets) def route_data_dff(self): """ Connect the output of the data flops to the write driver """ @@ -358,48 +371,47 @@ class sram_1bank(sram_base): for port in self.write_ports: if self.write_size: if port % 2: - offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size + 2) * self.m3_pitch) + offset = self.data_dff_insts[port].ll() - vector(0, self.data_bus_size) else: - offset = self.data_dff_insts[port].ul() + vector(0, 2 * self.m3_pitch) + offset = self.data_dff_insts[port].ul() + vector(0, self.data_bus_gap) else: if port % 2: - offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size + 2) * self.m1_pitch) + offset = self.data_dff_insts[port].ll() - vector(0, self.data_bus_size) else: - offset = self.data_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch) + offset = self.data_dff_insts[port].ul() + vector(0, self.data_bus_gap) dff_names = ["dout_{}".format(x) for x in range(self.word_size)] dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] if self.write_size: for x in dff_names: - pin_offset = self.data_dff_insts[port].get_pin(x).center() + pin = self.data_dff_insts[port].get_pin(x) + pin_offset = pin.center() self.add_via_center(layers=self.m1_stack, offset=pin_offset, directions=("V", "V")) - self.add_via_center(layers=self.m2_stack, - offset=pin_offset) - self.add_via_center(layers=self.m3_stack, - offset=pin_offset) + self.add_via_stack_center(from_layer="m2", + to_layer="m4", + offset=pin_offset) bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size)] bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] if self.write_size: for x in bank_names: + pin = self.bank_inst.get_pin(x) if port % 2: - pin_offset = self.bank_inst.get_pin(x).uc() + pin_offset = pin.uc() else: - pin_offset = self.bank_inst.get_pin(x).bc() - self.add_via_center(layers=self.m1_stack, - offset=pin_offset) - self.add_via_center(layers=self.m2_stack, - offset=pin_offset) - self.add_via_center(layers=self.m3_stack, - offset=pin_offset) + pin_offset = pin.bc() + self.add_via_stack_center(from_layer=pin.layer, + to_layer="m4", + offset=pin_offset) route_map = list(zip(bank_pins, dff_pins)) if self.write_size: layer_stack = self.m3_stack else: layer_stack = self.m1_stack + self.create_horizontal_channel_route(netlist=route_map, offset=offset, layer_stack=layer_stack) @@ -409,9 +421,9 @@ class sram_1bank(sram_base): # This is where the channel will start (y-dimension at least) for port in self.write_ports: if port % 2: - offset = self.wmask_dff_insts[port].ll() - vector(0, (self.num_wmasks + 2) * self.m1_pitch) + offset = self.wmask_dff_insts[port].ll() - vector(0, self.wmask_bus_size) else: - offset = self.wmask_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch) + offset = self.wmask_dff_insts[port].ul() + vector(0, self.wmask_bus_gap) dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)] dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names] diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index b9c4c909..bcb85308 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -7,6 +7,7 @@ # import datetime import debug +from math import log from importlib import reload from vector import vector from globals import OPTS, print_time @@ -137,7 +138,6 @@ class sram_base(design, verilog, lef): self.copy_power_pins(inst, "vdd") self.copy_power_pins(inst, "gnd") - import tech if not OPTS.route_supplies: # Do not route the power supply (leave as must-connect pins) return @@ -148,6 +148,7 @@ class sram_base(design, verilog, lef): grid_stack = power_grid except ImportError: # if no power_grid is specified by tech we use sensible defaults + import tech if "m4" in tech.layer: # Route a M3/M4 grid grid_stack = self.m3_stack @@ -496,70 +497,6 @@ class sram_base(design, verilog, lef): self.connect_inst(temp) return insts - - def connect_vbus_m2m3(self, src_pin, dest_pin): - """ - Helper routine to connect an instance to a vertical bus. - Routes horizontal then vertical L shape. - Dest pin is assumed to be on M2. - Src pin can be on M1/M2/M3. - """ - - if src_pin.cx() Date: Mon, 11 May 2020 16:22:08 -0700 Subject: [PATCH 309/521] Add no well option. Add stack gates vertical option. --- compiler/pgates/pand2.py | 80 +++++++++++++++++++++++++------- compiler/pgates/pand3.py | 76 ++++++++++++++++++++++++------ compiler/pgates/pbuf.py | 3 +- compiler/pgates/pdriver.py | 5 +- compiler/pgates/pgate.py | 18 +++++-- compiler/pgates/pinv.py | 7 +-- compiler/pgates/pnand2.py | 9 ++-- compiler/pgates/pnand3.py | 7 +-- compiler/pgates/pnor2.py | 11 +++-- compiler/tests/04_pand2_test.py | 4 ++ compiler/tests/04_pand3_test.py | 4 ++ compiler/tests/04_pnand2_test.py | 5 ++ compiler/tests/04_pnand3_test.py | 5 ++ compiler/tests/04_pnor2_test.py | 4 ++ 14 files changed, 187 insertions(+), 51 deletions(-) diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 69af1e62..6df877fd 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -15,14 +15,14 @@ class pand2(pgate.pgate): """ This is a simple buffer used for driving loads. """ - def __init__(self, name, size=1, height=None): - debug.info(1, "Creating pnand2 {}".format(name)) + def __init__(self, name, size=1, height=None, vertical=False): + debug.info(1, "Creating pand2 {}".format(name)) self.add_comment("size: {}".format(size)) - + + self.vertical = vertical self.size = size - - # Creates the netlist and layout - pgate.pgate.__init__(self, name, height) + + pgate.pgate.__init__(self, name) def create_netlist(self): self.add_pins() @@ -30,17 +30,22 @@ class pand2(pgate.pgate): self.create_insts() def create_modules(self): - self.nand = factory.create(module_type="pnand2", height=self.height) + self.nand = factory.create(module_type="pnand2", + height=self.height) self.add_mod(self.nand) self.inv = factory.create(module_type="pdriver", - neg_polarity=True, - fanout=self.size, + size_list=[self.size], height=self.height) self.add_mod(self.inv) def create_layout(self): - self.width = self.nand.width + self.inv.width + if self.vertical: + self.height = 2 * self.nand.height + self.width = max(self.nand.width, self.inv.width) + else: + self.width = self.nand.width + self.inv.width + self.place_insts() self.add_wires() self.add_layout_pins() @@ -68,17 +73,60 @@ class pand2(pgate.pgate): # Add NAND to the right self.nand_inst.place(offset=vector(0, 0)) - # Add INV to the right - self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0)) + if self.vertical: + # Add INV above + self.inv_inst.place(offset=vector(self.inv.width, + 2 * self.nand.height), + mirror="XY") + else: + # Add INV to the right + self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0)) + + def route_supply_rails(self): + """ Add vdd/gnd rails to the top, (middle), and bottom. """ + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, 0), + width=self.width) + + # Second gnd of the inverter gate + if self.vertical: + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, self.height), + width=self.width) + if self.vertical: + # Shared between two gates + y_offset = 0.5 * self.height + else: + y_offset = self.height + self.add_layout_pin_rect_center(text="vdd", + layer=self.route_layer, + offset=vector(0.5 * self.width, y_offset), + width=self.width) + def add_wires(self): # nand Z to inv A z1_pin = self.nand_inst.get_pin("Z") a2_pin = self.inv_inst.get_pin("A") - mid1_point = vector(0.5 * (z1_pin.cx() + a2_pin.cx()), z1_pin.cy()) - mid2_point = vector(mid1_point, a2_pin.cy()) - self.add_path(self.route_layer, - [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()]) + if self.vertical: + route_layer = "m2" + self.add_via_stack_center(offset=z1_pin.center(), + from_layer=z1_pin.layer, + to_layer=route_layer) + self.add_zjog(route_layer, + z1_pin.uc(), + a2_pin.bc(), + "V") + self.add_via_stack_center(offset=a2_pin.center(), + from_layer=a2_pin.layer, + to_layer=route_layer) + else: + route_layer = self.route_layer + mid1_point = vector(z1_pin.cx(), a2_pin.cy()) + self.add_path(route_layer, + [z1_pin.center(), mid1_point, a2_pin.center()]) def add_layout_pins(self): pin = self.inv_inst.get_pin("Z") diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index 841ac69d..5e2e83f8 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -15,10 +15,11 @@ class pand3(pgate.pgate): """ This is a simple buffer used for driving loads. """ - def __init__(self, name, size=1, height=None): + def __init__(self, name, size=1, height=None, vertical=False): debug.info(1, "Creating pand3 {}".format(name)) self.add_comment("size: {}".format(size)) - + + self.vertical = vertical self.size = size # Creates the netlist and layout @@ -31,16 +32,22 @@ class pand3(pgate.pgate): def create_modules(self): # Shield the cap, but have at least a stage effort of 4 - self.nand = factory.create(module_type="pnand3", height=self.height) + self.nand = factory.create(module_type="pnand3", + height=self.height) self.add_mod(self.nand) - self.inv = factory.create(module_type="pinv", - size=self.size, + self.inv = factory.create(module_type="pdriver", + size_list=[self.size], height=self.height) self.add_mod(self.inv) def create_layout(self): - self.width = self.nand.width + self.inv.width + if self.vertical: + self.height = 2 * self.nand.height + self.width = max(self.nand.width, self.inv.width) + else: + self.width = self.nand.width + self.inv.width + self.place_insts() self.add_wires() self.add_layout_pins() @@ -69,18 +76,61 @@ class pand3(pgate.pgate): # Add NAND to the right self.nand_inst.place(offset=vector(0, 0)) - # Add INV to the right - self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0)) + if self.vertical: + # Add INV above + self.inv_inst.place(offset=vector(self.inv.width, + 2 * self.nand.height), + mirror="XY") + else: + # Add INV to the right + self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0)) + + def route_supply_rails(self): + """ Add vdd/gnd rails to the top, (middle), and bottom. """ + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, 0), + width=self.width) + + # Second gnd of the inverter gate + if self.vertical: + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, self.height), + width=self.width) + if self.vertical: + # Shared between two gates + y_offset = 0.5 * self.height + else: + y_offset = self.height + self.add_layout_pin_rect_center(text="vdd", + layer=self.route_layer, + offset=vector(0.5 * self.width, y_offset), + width=self.width) + def add_wires(self): # nand Z to inv A z1_pin = self.nand_inst.get_pin("Z") a2_pin = self.inv_inst.get_pin("A") - mid1_point = vector(0.5 * (z1_pin.cx()+a2_pin.cx()), z1_pin.cy()) - mid2_point = vector(mid1_point, a2_pin.cy()) - self.add_path(z1_pin.layer, - [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()]) - + if self.vertical: + route_layer = "m2" + self.add_via_stack_center(offset=z1_pin.center(), + from_layer=z1_pin.layer, + to_layer=route_layer) + self.add_zjog(route_layer, + z1_pin.uc(), + a2_pin.bc(), + "V") + self.add_via_stack_center(offset=a2_pin.center(), + from_layer=a2_pin.layer, + to_layer=route_layer) + else: + route_layer = self.route_layer + mid1_point = vector(z1_pin.cx(), a2_pin.cy()) + self.add_path(route_layer, + [z1_pin.center(), mid1_point, a2_pin.center()]) + def add_layout_pins(self): pin = self.inv_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 4d90286d..8b9c4eab 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -56,7 +56,8 @@ class pbuf(pgate.pgate): self.inv2 = factory.create(module_type="pinv", size=self.size, - height=self.height) + height=self.height, + add_wells=False) self.add_mod(self.inv2) def create_insts(self): diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 9bba7aee..b36d3e95 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -87,10 +87,13 @@ class pdriver(pgate.pgate): def add_modules(self): self.inv_list = [] + add_well = True for size in self.size_list: temp_inv = factory.create(module_type="pinv", size=size, - height=self.height) + height=self.height, + add_wells=add_well) + add_well=False self.inv_list.append(temp_inv) self.add_mod(temp_inv) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 5351be07..be317f48 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -24,7 +24,7 @@ class pgate(design.design): functions for parameterized gates. """ - def __init__(self, name, height=None): + def __init__(self, name, height=None, add_wells=True): """ Creates a generic cell """ design.design.__init__(self, name) @@ -33,7 +33,8 @@ class pgate(design.design): elif not height: # By default, something simple self.height = 14 * self.m1_pitch - + self.add_wells = add_wells + if "li" in layer: self.route_layer = "li" else: @@ -150,7 +151,7 @@ class pgate(design.design): # This should match the cells in the cell library self.nwell_y_offset = 0.48 * self.height - full_height = self.height + 0.5* self.m1_width + full_height = self.height + 0.5 * self.m1_width # FIXME: float rounding problem if "nwell" in layer: @@ -302,10 +303,17 @@ class pgate(design.design): def determine_width(self): """ Determine the width based on the well contacts (assumed to be on the right side) """ + # Width is determined by well contact and spacing and allowing a supply via between each cell - self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width + if self.add_wells: + self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width + # Height is an input parameter, so it is not recomputed. + else: + max_active_xoffset = self.find_highest_layer_coords("active").x + max_route_xoffset = self.find_highest_layer_coords(self.route_layer).x + 0.5 * self.m1_space + self.width = max(max_active_xoffset, max_route_xoffset) + self.well_width = self.width + 2 * self.nwell_enclose_active - # Height is an input parameter, so it is not recomputed. @staticmethod def bin_width(tx_type, target_width): diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index e0e1ce81..214e66dc 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -32,7 +32,7 @@ class pinv(pgate.pgate): from center of rail to rail. """ - def __init__(self, name, size=1, beta=parameter["beta"], height=None): + def __init__(self, name, size=1, beta=parameter["beta"], height=None, add_wells=True): debug.info(2, "creating pinv structure {0} with size of {1}".format(name, @@ -44,7 +44,7 @@ class pinv(pgate.pgate): self.pmos_size = beta * size self.beta = beta - pgate.pgate.__init__(self, name, height) + pgate.pgate.__init__(self, name, height, add_wells) def create_netlist(self): """ Calls all functions related to the generation of the netlist """ @@ -56,7 +56,8 @@ class pinv(pgate.pgate): def create_layout(self): """ Calls all functions related to the generation of the layout """ self.place_ptx() - self.add_well_contacts() + if self.add_wells: + self.add_well_contacts() self.determine_width() self.extend_wells() self.route_supply_rails() diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 5d20201e..59995133 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -20,7 +20,7 @@ class pnand2(pgate.pgate): This module generates gds of a parametrically sized 2-input nand. This model use ptx to generate a 2-input nand within a cetrain height. """ - def __init__(self, name, size=1, height=None): + def __init__(self, name, size=1, height=None, add_wells=True): """ Creates a cell for a simple 2 input nand """ debug.info(2, @@ -43,7 +43,7 @@ class pnand2(pgate.pgate): (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) # Creates the netlist and layout - pgate.pgate.__init__(self, name, height) + pgate.pgate.__init__(self, name, height, add_wells) def create_netlist(self): self.add_pins() @@ -55,13 +55,14 @@ class pnand2(pgate.pgate): self.setup_layout_constants() self.place_ptx() - self.add_well_contacts() + if self.add_wells: + self.add_well_contacts() + self.route_output() self.determine_width() self.route_supply_rails() self.connect_rails() self.extend_wells() self.route_inputs() - self.route_output() self.add_boundary() def add_pins(self): diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 454b75dd..446b8212 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -19,7 +19,7 @@ class pnand3(pgate.pgate): This module generates gds of a parametrically sized 2-input nand. This model use ptx to generate a 2-input nand within a cetrain height. """ - def __init__(self, name, size=1, height=None): + def __init__(self, name, size=1, height=None, add_wells=True): """ Creates a cell for a simple 3 input nand """ debug.info(2, @@ -45,7 +45,7 @@ class pnand3(pgate.pgate): (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) # Creates the netlist and layout - pgate.pgate.__init__(self, name, height) + pgate.pgate.__init__(self, name, height, add_wells) def add_pins(self): """ Adds pins for spice netlist """ @@ -63,7 +63,8 @@ class pnand3(pgate.pgate): self.setup_layout_constants() self.place_ptx() - self.add_well_contacts() + if self.add_wells: + self.add_well_contacts() self.determine_width() self.route_supply_rails() self.connect_rails() diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index f522578e..2126e86c 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -19,7 +19,7 @@ class pnor2(pgate.pgate): This module generates gds of a parametrically sized 2-input nor. This model use ptx to generate a 2-input nor within a cetrain height. """ - def __init__(self, name, size=1, height=None): + def __init__(self, name, size=1, height=None, add_wells=True): """ Creates a cell for a simple 2 input nor """ debug.info(2, @@ -42,7 +42,7 @@ class pnor2(pgate.pgate): (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) # Creates the netlist and layout - pgate.pgate.__init__(self, name, height) + pgate.pgate.__init__(self, name, height, add_wells) def create_netlist(self): self.add_pins() @@ -54,13 +54,14 @@ class pnor2(pgate.pgate): self.setup_layout_constants() self.place_ptx() - self.add_well_contacts() + if self.add_wells: + self.add_well_contacts() + self.route_inputs() + self.route_output() self.determine_width() self.route_supply_rails() self.connect_rails() self.extend_wells() - self.route_inputs() - self.route_output() self.add_boundary() def add_pins(self): diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index f7e5f304..21a0a38e 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -29,6 +29,10 @@ class pand2_test(openram_test): a = pand2.pand2(name="pand2x4", size=4) self.local_check(a) + debug.info(2, "Testing vertical pand2 gate 4x") + a = pand2.pand2(name="pand2x4", size=4, vertical=True) + self.local_check(a) + globals.end_openram() # instantiate a copdsay of the class to actually run the test diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index e58f1ee9..f851077b 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -29,6 +29,10 @@ class pand3_test(openram_test): a = pand3.pand3(name="pand3x4", size=4) self.local_check(a) + debug.info(2, "Testing vertical pand3 gate 4x") + a = pand3.pand3(name="pand3x4", size=4, vertical=True) + self.local_check(a) + globals.end_openram() # instantiate a copdsay of the class to actually run the test diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index f939738a..77a6932c 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -25,6 +25,11 @@ class pnand2_test(openram_test): tx = factory.create(module_type="pnand2", size=1) self.local_check(tx) + debug.info(2, "Checking 2-input nand gate") + tx = factory.create(module_type="pnand2", size=1, add_wells=False) + # Only DRC because well contacts will fail LVS + self.local_drc_check(tx) + globals.end_openram() diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index f1af19ac..82bf1846 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -25,6 +25,11 @@ class pnand3_test(openram_test): tx = factory.create(module_type="pnand3", size=1) self.local_check(tx) + debug.info(2, "Checking 3-input nand gate") + tx = factory.create(module_type="pnand3", size=1, add_wells=False) + # Only DRC because well contacts will fail LVS + self.local_drc_check(tx) + globals.end_openram() diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index ea0d6dbc..1e8abaa4 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -25,6 +25,10 @@ class pnor2_test(openram_test): tx = factory.create(module_type="pnor2", size=1) self.local_check(tx) + debug.info(2, "Checking 2-input nor gate") + tx = factory.create(module_type="pnor2", size=1, add_wells=False) + self.local_drc_check(tx) + globals.end_openram() # run the test from the command line From 848241a3ad501ef78df9ac05a99e3ba4ef411d67 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 11 May 2020 16:22:17 -0700 Subject: [PATCH 310/521] PEP8 cleanup --- compiler/base/geometry.py | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index cfcfa73a..96da3d99 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -66,14 +66,17 @@ class geometry: self.compute_boundary(self.offset, self.mirror, self.rotate) def compute_boundary(self, offset=vector(0, 0), mirror="", rotate=0): - """ Transform with offset, mirror and rotation to get the absolute pin location. - We must then re-find the ll and ur. The master is the cell instance. """ + """ + Transform with offset, mirror and rotation to get the absolute pin location. + We must then re-find the ll and ur. The master is the cell instance. + """ if OPTS.netlist_only: - self.boundary = [vector(0,0), vector(0,0)] + self.boundary = [vector(0, 0), vector(0, 0)] return (ll, ur) = [vector(0, 0), vector(self.width, self.height)] + # Mirroring is performed before rotation if mirror == "MX": ll = ll.scale(1, -1) ur = ur.scale(1, -1) @@ -195,14 +198,13 @@ class instance(geometry): blockages = [] blockages = self.mod.gds.getBlockages(lpp) for b in blockages: - new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) + new_blockages.append(self.transform_coords(b, self.offset, mirr, angle)) else: blockages = self.mod.get_blockages(lpp) for b in blockages: - new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) + new_blockages.append(self.transform_coords(b, self.offset, mirr, angle)) return new_blockages - def gds_write_file(self, new_layout): """Recursively writes all the sub-modules in this instance""" debug.info(4, "writing instance: " + self.name) @@ -225,26 +227,25 @@ class instance(geometry): self.update_boundary() debug.info(3, "placing instance {}".format(self)) - - def get_pin(self,name,index=-1): + def get_pin(self, name, index=-1): """ Return an absolute pin that is offset and transformed based on this instance location. Index will return one of several pins.""" import copy if index == -1: pin = copy.deepcopy(self.mod.get_pin(name)) - pin.transform(self.offset,self.mirror,self.rotate) + pin.transform(self.offset, self.mirror, self.rotate) return pin else: pins = copy.deepcopy(self.mod.get_pin(name)) - pin.transform(self.offset,self.mirror,self.rotate) + pins.transform(self.offset, self.mirror, self.rotate) return pin[index] def get_num_pins(self, name): """ Return the number of pins of a given name """ return len(self.mod.get_pins(name)) - def get_pins(self,name): + def get_pins(self, name): """ Return an absolute pin that is offset and transformed based on this instance location. """ @@ -253,7 +254,7 @@ class instance(geometry): new_pins = [] for p in pin: - p.transform(self.offset,self.mirror,self.rotate) + p.transform(self.offset, self.mirror, self.rotate) new_pins.append(p) return new_pins @@ -265,6 +266,7 @@ class instance(geometry): """ override print function output """ return "( inst: " + self.name + " @" + str(self.offset) + " mod=" + self.mod.name + " " + self.mirror + " R=" + str(self.rotate) + ")" + class path(geometry): """Represents a Path""" @@ -322,7 +324,7 @@ class label(geometry): self.size = 0 - debug.info(4,"creating label " + self.text + " " + str(self.layerNumber) + " " + str(self.offset)) + debug.info(4, "creating label " + self.text + " " + str(self.layerNumber) + " " + str(self.offset)) def gds_write_file(self, new_layout): """Writes the text label to GDS""" @@ -340,7 +342,7 @@ class label(geometry): def __str__(self): """ override print function output """ - return "label: " + self.text + " layer=" + str(self.layerNumber) + " purpose=" + str(self.layerPurpose) + return "label: " + self.text + " layer=" + str(self.layerNumber) + " purpose=" + str(self.layerPurpose) def __repr__(self): """ override print function output """ From 617bf302d18f1863da212073d8e80d71097d7dae Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 13 May 2020 14:46:42 -0700 Subject: [PATCH 311/521] Add option to remove wells. Save area in pgates with redundant wells. --- compiler/pgates/pand2.py | 13 ++++++++----- compiler/pgates/pand3.py | 15 ++++++++++----- compiler/pgates/pdriver.py | 8 ++++---- compiler/pgates/pgate.py | 17 +++++++++-------- compiler/pgates/pinv.py | 4 ++-- compiler/pgates/pnand2.py | 1 - compiler/pgates/single_level_column_mux.py | 4 ++-- compiler/tests/04_pnor2_test.py | 4 ---- .../04_single_level_column_mux_pbitcell_test.py | 0 compiler/tests/05_replica_bitcell_array_test.py | 0 ...ngle_level_column_mux_array_pbitcell_test.py | 0 .../tests/08_wordline_driver_pbitcell_test.py | 0 .../tests/09_sense_amp_array_test_pbitcell.py | 0 .../10_write_driver_array_pbitcell_test.py | 0 ...10_write_driver_array_wmask_pbitcell_test.py | 0 .../10_write_mask_and_array_pbitcell_test.py | 0 compiler/tests/19_bank_select_pbitcell_test.py | 0 17 files changed, 35 insertions(+), 31 deletions(-) mode change 100644 => 100755 compiler/tests/04_single_level_column_mux_pbitcell_test.py mode change 100644 => 100755 compiler/tests/05_replica_bitcell_array_test.py mode change 100644 => 100755 compiler/tests/07_single_level_column_mux_array_pbitcell_test.py mode change 100644 => 100755 compiler/tests/08_wordline_driver_pbitcell_test.py mode change 100644 => 100755 compiler/tests/09_sense_amp_array_test_pbitcell.py mode change 100644 => 100755 compiler/tests/10_write_driver_array_pbitcell_test.py mode change 100644 => 100755 compiler/tests/10_write_driver_array_wmask_pbitcell_test.py mode change 100644 => 100755 compiler/tests/10_write_mask_and_array_pbitcell_test.py mode change 100644 => 100755 compiler/tests/19_bank_select_pbitcell_test.py diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 6df877fd..dfbdc3e7 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -15,14 +15,14 @@ class pand2(pgate.pgate): """ This is a simple buffer used for driving loads. """ - def __init__(self, name, size=1, height=None, vertical=False): + def __init__(self, name, size=1, height=None, vertical=False, add_wells=True): debug.info(1, "Creating pand2 {}".format(name)) self.add_comment("size: {}".format(size)) self.vertical = vertical self.size = size - pgate.pgate.__init__(self, name) + pgate.pgate.__init__(self, name, height, add_wells) def create_netlist(self): self.add_pins() @@ -31,12 +31,15 @@ class pand2(pgate.pgate): def create_modules(self): self.nand = factory.create(module_type="pnand2", - height=self.height) - self.add_mod(self.nand) + height=self.height, + add_wells=False) self.inv = factory.create(module_type="pdriver", size_list=[self.size], - height=self.height) + height=self.height, + add_wells=self.add_wells) + + self.add_mod(self.nand) self.add_mod(self.inv) def create_layout(self): diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index 5e2e83f8..d7f0b00e 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -15,7 +15,7 @@ class pand3(pgate.pgate): """ This is a simple buffer used for driving loads. """ - def __init__(self, name, size=1, height=None, vertical=False): + def __init__(self, name, size=1, height=None, vertical=False, add_wells=True): debug.info(1, "Creating pand3 {}".format(name)) self.add_comment("size: {}".format(size)) @@ -23,7 +23,7 @@ class pand3(pgate.pgate): self.size = size # Creates the netlist and layout - pgate.pgate.__init__(self, name, height) + pgate.pgate.__init__(self, name, height, add_wells) def create_netlist(self): self.add_pins() @@ -33,12 +33,17 @@ class pand3(pgate.pgate): def create_modules(self): # Shield the cap, but have at least a stage effort of 4 self.nand = factory.create(module_type="pnand3", - height=self.height) - self.add_mod(self.nand) + height=self.height, + add_wells=False) + # Add the well tap to the inverter because when stacked + # vertically it is sometimes narrower self.inv = factory.create(module_type="pdriver", size_list=[self.size], - height=self.height) + height=self.height, + add_wells=self.add_wells) + + self.add_mod(self.nand) self.add_mod(self.inv) def create_layout(self): diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index b36d3e95..266400c9 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -17,7 +17,7 @@ class pdriver(pgate.pgate): sized for driving a load. """ - def __init__(self, name, neg_polarity=False, fanout=0, size_list=None, height=None): + def __init__(self, name, neg_polarity=False, fanout=0, size_list=None, height=None, add_wells=True): debug.info(1, "creating pdriver {}".format(name)) @@ -35,7 +35,7 @@ class pdriver(pgate.pgate): debug.error("Cannot specify both size_list and neg_polarity.", -1) # Creates the netlist and layout - pgate.pgate.__init__(self, name, height) + pgate.pgate.__init__(self, name, height, add_wells) def compute_sizes(self): # size_list specified @@ -73,9 +73,9 @@ class pdriver(pgate.pgate): self.place_modules() self.route_wires() self.add_layout_pins() - self.width = self.inv_inst_list[-1].rx() self.height = self.inv_inst_list[0].height + self.extend_wells() self.route_supply_rails() self.add_boundary() @@ -87,7 +87,7 @@ class pdriver(pgate.pgate): def add_modules(self): self.inv_list = [] - add_well = True + add_well = self.add_wells for size in self.size_list: temp_inv = factory.create(module_type="pinv", size=size, diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index be317f48..cdb89fcb 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -162,12 +162,12 @@ class pgate(design.design): nwell_height = nwell_max_offset - self.nwell_y_offset self.add_rect(layer="nwell", offset=nwell_position, - width=self.well_width, + width=self.width + 2 * self.well_extend_active, height=nwell_height) if "vtg" in layer: self.add_rect(layer="vtg", offset=nwell_position, - width=self.well_width, + width=self.width + 2 * self.well_extend_active, height=nwell_height) # Start this half a rail width below the cell @@ -178,12 +178,12 @@ class pgate(design.design): pwell_height = self.nwell_y_offset - pwell_position.y self.add_rect(layer="pwell", offset=pwell_position, - width=self.well_width, + width=self.width + 2 * self.well_extend_active, height=pwell_height) if "vtg" in layer: self.add_rect(layer="vtg", offset=pwell_position, - width=self.well_width, + width=self.width + 2 * self.well_extend_active, height=pwell_height) def add_nwell_contact(self, pmos, pmos_pos): @@ -304,16 +304,17 @@ class pgate(design.design): def determine_width(self): """ Determine the width based on the well contacts (assumed to be on the right side) """ + # It was already set or is left as default (minimum) # Width is determined by well contact and spacing and allowing a supply via between each cell if self.add_wells: - self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width + width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width # Height is an input parameter, so it is not recomputed. else: max_active_xoffset = self.find_highest_layer_coords("active").x max_route_xoffset = self.find_highest_layer_coords(self.route_layer).x + 0.5 * self.m1_space - self.width = max(max_active_xoffset, max_route_xoffset) - - self.well_width = self.width + 2 * self.nwell_enclose_active + width = max(max_active_xoffset, max_route_xoffset) + + self.width = width @staticmethod def bin_width(tx_type, target_width): diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 214e66dc..465f7a58 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -60,14 +60,14 @@ class pinv(pgate.pgate): self.add_well_contacts() self.determine_width() self.extend_wells() - self.route_supply_rails() - self.connect_rails() self.route_input_gate(self.pmos_inst, self.nmos_inst, self.output_pos.y, "A", position="farleft") self.route_outputs() + self.route_supply_rails() + self.connect_rails() self.add_boundary() def add_pins(self): diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 59995133..51581e61 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -5,7 +5,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import contact import pgate import debug from tech import drc, parameter, spice diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 9e38287f..e1d19534 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -50,7 +50,7 @@ class single_level_column_mux(pgate.pgate): self.connect_poly() self.add_bitline_pins() self.connect_bitlines() - self.add_wells() + self.add_pn_wells() def add_modules(self): self.bitcell = factory.create(module_type="bitcell") @@ -218,7 +218,7 @@ class single_level_column_mux(pgate.pgate): self.add_path(self.col_mux_stack[2], [br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()]) - def add_wells(self): + def add_pn_wells(self): """ Add a well and implant over the whole cell. Also, add the pwell contact (if it exists) diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index 1e8abaa4..ea0d6dbc 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -25,10 +25,6 @@ class pnor2_test(openram_test): tx = factory.create(module_type="pnor2", size=1) self.local_check(tx) - debug.info(2, "Checking 2-input nor gate") - tx = factory.create(module_type="pnor2", size=1, add_wells=False) - self.local_drc_check(tx) - globals.end_openram() # run the test from the command line diff --git a/compiler/tests/04_single_level_column_mux_pbitcell_test.py b/compiler/tests/04_single_level_column_mux_pbitcell_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/05_replica_bitcell_array_test.py b/compiler/tests/05_replica_bitcell_array_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py b/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/08_wordline_driver_pbitcell_test.py b/compiler/tests/08_wordline_driver_pbitcell_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/09_sense_amp_array_test_pbitcell.py b/compiler/tests/09_sense_amp_array_test_pbitcell.py old mode 100644 new mode 100755 diff --git a/compiler/tests/10_write_driver_array_pbitcell_test.py b/compiler/tests/10_write_driver_array_pbitcell_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/10_write_mask_and_array_pbitcell_test.py b/compiler/tests/10_write_mask_and_array_pbitcell_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/19_bank_select_pbitcell_test.py b/compiler/tests/19_bank_select_pbitcell_test.py old mode 100644 new mode 100755 From f8bcc543385ff8da82cf2d04c477714bcb8fc85e Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 13 May 2020 16:04:38 -0700 Subject: [PATCH 312/521] Determine width after routing with no well contacts. --- compiler/pgates/pnand3.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 446b8212..85b3f0b6 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -65,12 +65,12 @@ class pnand3(pgate.pgate): self.place_ptx() if self.add_wells: self.add_well_contacts() + self.route_inputs() + self.route_output() self.determine_width() self.route_supply_rails() self.connect_rails() self.extend_wells() - self.route_inputs() - self.route_output() self.add_boundary() def add_ptx(self): From 4b526f0d5fd970a87628aadf85183045ab06cbe0 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 13 May 2020 16:54:26 -0700 Subject: [PATCH 313/521] Check min size inverter. --- compiler/modules/write_mask_and_array.py | 2 +- compiler/pgates/pinv.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 4d4e0c50..e660d519 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -60,7 +60,7 @@ class write_mask_and_array(design.design): # Size the AND gate for the number of write drivers it drives, which is equal to the write size. # Assume stage effort of 3 to compute the size self.and2 = factory.create(module_type="pand2", - size=self.write_size / 4.0) + size=max(self.write_size / 4.0, 1)) self.add_mod(self.and2) def create_and2_array(self): diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 465f7a58..5e1aab7b 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -40,6 +40,7 @@ class pinv(pgate.pgate): self.add_comment("size: {}".format(size)) self.size = size + debug.check(self.size >= 1, "Must have a size greater than or equal to 1.") self.nmos_size = size self.pmos_size = beta * size self.beta = beta From a305d788d7635b4536ea43e0b2486660a59e5682 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 13 May 2020 16:54:35 -0700 Subject: [PATCH 314/521] Vertical gates need both well contacts. --- compiler/pgates/pand2.py | 2 +- compiler/pgates/pand3.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index dfbdc3e7..41189876 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -32,7 +32,7 @@ class pand2(pgate.pgate): def create_modules(self): self.nand = factory.create(module_type="pnand2", height=self.height, - add_wells=False) + add_wells=self.vertical) self.inv = factory.create(module_type="pdriver", size_list=[self.size], diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index d7f0b00e..92429921 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -34,7 +34,7 @@ class pand3(pgate.pgate): # Shield the cap, but have at least a stage effort of 4 self.nand = factory.create(module_type="pnand3", height=self.height, - add_wells=False) + add_wells=self.vertical) # Add the well tap to the inverter because when stacked # vertically it is sometimes narrower From 8bd1052fc2777fdcb228e55bd47b87ace6912b56 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Thu, 14 May 2020 10:30:29 +0000 Subject: [PATCH 315/521] Spare columns in full sram layout --- compiler/modules/control_logic.py | 9 ++- compiler/sram/sram_1bank.py | 14 +++-- compiler/sram/sram_base.py | 22 +++++-- ..._sram_1bank_2mux_1rw_1r_spare_cols_test.py | 58 ++++++++++++++++++ ...0_sram_1bank_2mux_1w_1r_spare_cols_test.py | 59 +++++++++++++++++++ ...sram_1bank_nomux_1rw_1r_spare_cols_test.py | 59 +++++++++++++++++++ 6 files changed, 208 insertions(+), 13 deletions(-) create mode 100755 compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py create mode 100755 compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py create mode 100755 compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 078dc3ae..c8805049 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -20,7 +20,7 @@ class control_logic(design.design): Dynamically generated Control logic for the total SRAM circuit. """ - def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""): + def __init__(self, num_rows, words_per_row, word_size, spare_columns=None, sram=None, port_type="rw", name=""): """ Constructor """ name = "control_logic_" + port_type design.design.__init__(self, name) @@ -35,7 +35,12 @@ class control_logic(design.design): self.word_size = word_size self.port_type = port_type - self.num_cols = word_size * words_per_row + if not spare_columns: + self.num_spare_cols = spare_columns + else: + self.num_spare_cols = 0 + + self.num_cols = word_size * words_per_row + self.num_spare_cols self.num_words = num_rows * words_per_row self.enable_delay_chain_resizing = False diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 8dbcfaf4..ac4b7e33 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -71,7 +71,7 @@ class sram_1bank(sram_base): self.wmask_bus_size = self.m2_nonpref_pitch * (max(self.num_wmasks + 1, self.col_addr_size + 1)) + self.wmask_bus_gap else: self.data_bus_gap = self.m3_nonpref_pitch * 2 - self.data_bus_size = self.m3_nonpref_pitch * (max(self.word_size + 1, self.col_addr_size + 1)) + self.data_bus_gap + self.data_bus_size = self.m3_nonpref_pitch * (max(self.word_size + self.num_spare_cols + 1, self.col_addr_size + 1)) + self.data_bus_gap self.col_addr_bus_gap = self.m2_nonpref_pitch * 2 self.col_addr_bus_size = self.m2_nonpref_pitch * (self.col_addr_size) + self.col_addr_bus_gap @@ -191,7 +191,7 @@ class sram_1bank(sram_base): signal + "{}".format(port)) if port in self.read_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): self.copy_layout_pin(self.bank_inst, "dout{0}_{1}".format(port, bit), "dout{0}[{1}]".format(port, bit)) @@ -208,7 +208,7 @@ class sram_1bank(sram_base): "addr{0}[{1}]".format(port, bit + self.col_addr_size)) if port in self.write_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): self.copy_layout_pin(self.data_dff_insts[port], "din_{}".format(bit), "din{0}[{1}]".format(port, bit)) @@ -218,6 +218,10 @@ class sram_1bank(sram_base): self.copy_layout_pin(self.wmask_dff_insts[port], "din_{}".format(bit), "wmask{0}[{1}]".format(port, bit)) + for bit in range(self.num_spare_cols): + self.copy_layout_pin(self.bank_inst, + "spare_wen{0}_{1}".format(port, bit), + "spare_wen{0}[{1}]".format(port, bit)) def route_layout(self): """ Route a single bank SRAM """ @@ -380,7 +384,7 @@ class sram_1bank(sram_base): else: offset = self.data_dff_insts[port].ul() + vector(0, self.data_bus_gap) - dff_names = ["dout_{}".format(x) for x in range(self.word_size)] + dff_names = ["dout_{}".format(x) for x in range(self.word_size + self.num_spare_cols)] dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] if self.write_size: for x in dff_names: @@ -393,7 +397,7 @@ class sram_1bank(sram_base): to_layer="m4", offset=pin_offset) - bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size)] + bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)] bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] if self.write_size: for x in bank_names: diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index bcb85308..0ca569af 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -37,6 +37,9 @@ class sram_base(design, verilog, lef): else: self.num_wmasks = 0 + if not self.num_spare_cols: + self.num_spare_cols = 0 + # For logical effort delay calculations. self.all_mods_except_control_done = False @@ -44,7 +47,7 @@ class sram_base(design, verilog, lef): """ Add pins for entire SRAM. """ for port in self.write_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): self.add_pin("din{0}[{1}]".format(port, bit), "INPUT") for port in self.all_ports: @@ -75,8 +78,10 @@ class sram_base(design, verilog, lef): for port in self.write_ports: for bit in range(self.num_wmasks): self.add_pin("wmask{0}[{1}]".format(port, bit), "INPUT") + for bit in range(self.num_spare_cols): + self.add_pin("spare_wen{0}[{1}]".format(port, bit), "INPUT") for port in self.read_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT") self.add_pin("vdd", "POWER") @@ -274,7 +279,7 @@ class sram_base(design, verilog, lef): else: self.col_addr_dff = None - self.data_dff = factory.create("dff_array", module_name="data_dff", rows=1, columns=self.word_size) + self.data_dff = factory.create("dff_array", module_name="data_dff", rows=1, columns=self.word_size + self.num_spare_cols) self.add_mod(self.data_dff) if self.write_size: @@ -303,6 +308,7 @@ class sram_base(design, verilog, lef): self.control_logic_rw = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, + spare_columns=self.num_spare_cols, sram=self, port_type="rw") self.add_mod(self.control_logic_rw) @@ -310,6 +316,7 @@ class sram_base(design, verilog, lef): self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, + spare_columns=self.num_spare_cols, sram=self, port_type="w") self.add_mod(self.control_logic_w) @@ -317,6 +324,7 @@ class sram_base(design, verilog, lef): self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, + spare_columns=self.num_spare_cols, sram=self, port_type="r") self.add_mod(self.control_logic_r) @@ -328,12 +336,12 @@ class sram_base(design, verilog, lef): temp = [] for port in self.read_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): temp.append("dout{0}[{1}]".format(port, bit)) for port in self.all_ports: temp.append("rbl_bl{0}".format(port)) for port in self.write_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): temp.append("bank_din{0}[{1}]".format(port, bit)) for port in self.all_ports: for bit in range(self.bank_addr_size): @@ -349,6 +357,8 @@ class sram_base(design, verilog, lef): temp.append("w_en{0}".format(port)) for bit in range(self.num_wmasks): temp.append("bank_wmask{}[{}]".format(port, bit)) + for bit in range(self.num_spare_cols): + temp.append("spare_wen{0}[{1}]".format(port, bit)) for port in self.all_ports: temp.append("wl_en{0}".format(port)) temp.extend(["vdd", "gnd"]) @@ -436,7 +446,7 @@ class sram_base(design, verilog, lef): # inputs, outputs/output/bar inputs = [] outputs = [] - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): inputs.append("din{}[{}]".format(port, bit)) outputs.append("bank_din{}[{}]".format(port, bit)) diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py new file mode 100755 index 00000000..d087a47b --- /dev/null +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class sram_1bank_2mux_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + c = sram_config(word_size=4, + num_words=32, + num_spare_cols=3, + num_banks=1) + + c.words_per_row=2 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py new file mode 100755 index 00000000..349f5374 --- /dev/null +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") +class psram_1bank_2mux_1w_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + OPTS.bitcell = "bitcell_1w_1r" + OPTS.replica_bitcell="replica_bitcell_1w_1r" + OPTS.dummy_bitcell="dummy_bitcell_1w_1r" + OPTS.num_rw_ports = 0 + OPTS.num_w_ports = 1 + OPTS.num_r_ports = 1 + + c = sram_config(word_size=4, + num_words=32, + num_spare_cols=3, + num_banks=1) + c.num_words=32 + c.words_per_row=2 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py new file mode 100755 index 00000000..d2df2aef --- /dev/null +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class sram_1bank_nomux_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + c = sram_config(word_size=4, + num_words=16, + num_spare_cols=4, + num_banks=1) + + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From c14190c5aa20b9bf6f4a743a385949e41d149396 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Thu, 14 May 2020 10:41:54 +0000 Subject: [PATCH 316/521] Changes in control logic for spare columns --- compiler/modules/control_logic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index c8805049..e09a6615 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -36,9 +36,9 @@ class control_logic(design.design): self.port_type = port_type if not spare_columns: - self.num_spare_cols = spare_columns - else: self.num_spare_cols = 0 + else: + self.num_spare_cols = spare_columns self.num_cols = word_size * words_per_row + self.num_spare_cols self.num_words = num_rows * words_per_row From c7d86b21ae12eea5038618dca5e4e67b2385230a Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Sat, 16 May 2020 10:09:03 +0000 Subject: [PATCH 317/521] Spare cols with wmask enabled --- compiler/modules/port_data.py | 11 +++- compiler/modules/write_driver_array.py | 22 ++++++-- compiler/sram/sram_1bank.py | 2 +- ...rite_driver_array_wmask_spare_cols_test.py | 47 ++++++++++++++++ ...0_sram_1bank_2mux_wmask_spare_cols_test.py | 56 +++++++++++++++++++ ..._sram_1bank_nomux_wmask_spare_cols_test.py | 56 +++++++++++++++++++ 6 files changed, 185 insertions(+), 9 deletions(-) create mode 100755 compiler/tests/10_write_driver_array_wmask_spare_cols_test.py create mode 100755 compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py create mode 100755 compiler/tests/20_sram_1bank_nomux_wmask_spare_cols_test.py diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 9ff99bdd..968b4605 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -386,8 +386,10 @@ class port_data(design.design): if self.write_size is not None: for i in range(self.num_wmasks): temp.append("wdriver_sel_{}".format(i)) + for i in range(self.num_spare_cols): + temp.append("spare_wen{}".format(i)) - elif self.num_spare_cols: + elif self.num_spare_cols and not self.write_size: temp.append("w_en") for i in range(self.num_spare_cols): temp.append("spare_wen{}".format(i)) @@ -690,7 +692,7 @@ class port_data(design.design): else: debug.error("Didn't find precharge array.") - # Copy layout pins of spare columns + # Copy bitlines of spare columns for bit in range(self.num_spare_cols): if self.precharge_array_inst: self.copy_layout_pin(self.precharge_array_inst, @@ -718,7 +720,10 @@ class port_data(design.design): for bit in range(self.num_wmasks): # Add write driver's en_{} pins self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit), "wdriver_sel_{}".format(bit)) - elif self.num_spare_cols: + for bit in range(self.num_spare_cols): + # Add spare columns' en_{} pins + self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + self.num_wmasks), "spare_wen{}".format(bit)) + elif self.num_spare_cols and not self.write_mask_and_array_inst: self.copy_layout_pin(self.write_driver_array_inst, "en_0", "w_en") for bit in range(self.num_spare_cols): self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + 1), "spare_wen{}".format(bit)) diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 640db97e..48564e86 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -85,9 +85,9 @@ class write_driver_array(design.design): self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT") self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT") if self.write_size: - for i in range(self.num_wmasks): + for i in range(self.num_wmasks + self.num_spare_cols): self.add_pin(self.en_name + "_{0}".format(i), "INPUT") - elif self.num_spare_cols: + elif self.num_spare_cols and not self.write_size: for i in range(self.num_spare_cols + 1): self.add_pin(self.en_name + "_{0}".format(i), "INPUT") else: @@ -124,7 +124,7 @@ class write_driver_array(design.design): w = 0 windex+=1 - elif self.num_spare_cols: + elif self.num_spare_cols and not self.write_size: self.connect_inst([self.data_name + "_{0}".format(index), self.get_bl_name() + "_{0}".format(index), self.get_br_name() + "_{0}".format(index), @@ -138,6 +138,10 @@ class write_driver_array(design.design): for i in range(self.num_spare_cols): index = self.word_size + i + if self.write_size: + offset = self.num_wmasks + else: + offset = 1 name = "write_driver{}".format(index) self.driver_insts[index]=self.add_inst(name=name, mod=self.driver) @@ -145,7 +149,7 @@ class write_driver_array(design.design): self.connect_inst([self.data_name + "_{0}".format(index), self.get_bl_name() + "_{0}".format(index), self.get_br_name() + "_{0}".format(index), - self.en_name + "_{0}".format(i + 1), "vdd", "gnd"]) + self.en_name + "_{0}".format(i + offset), "vdd", "gnd"]) def place_write_array(self): @@ -227,8 +231,16 @@ class write_driver_array(design.design): offset=en_pin.ll(), width=wmask_en_len - en_gap, height=en_pin.height()) + + for i in range(self.num_spare_cols): + inst = self.driver_insts[self.word_size + i] + self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks), + layer="m1", + offset=inst.get_pin(inst.mod.en_name).ll(), + width=self.single_col_width - inst.get_pin(inst.mod.en_name).width()) + - elif self.num_spare_cols: + elif self.num_spare_cols and not self.write_size: # shorten enable rail to accomodate those for spare write drivers inst = self.driver_insts[0] self.add_layout_pin(text=self.en_name + "_{0}".format(0), diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index ac4b7e33..4af19f98 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -66,7 +66,7 @@ class sram_1bank(sram_base): # So, m3 non-pref pitch means that this is routed on the m2 layer. if self.write_size: self.data_bus_gap = self.m4_nonpref_pitch * 2 - self.data_bus_size = self.m4_nonpref_pitch * (self.word_size) + self.data_bus_gap + self.data_bus_size = self.m4_nonpref_pitch * (self.word_size + self.num_spare_cols) + self.data_bus_gap self.wmask_bus_gap = self.m2_nonpref_pitch * 2 self.wmask_bus_size = self.m2_nonpref_pitch * (max(self.num_wmasks + 1, self.col_addr_size + 1)) + self.wmask_bus_gap else: diff --git a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py new file mode 100755 index 00000000..be85665e --- /dev/null +++ b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os + +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class write_driver_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check write driver array for single port + debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4") + a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4, num_spare_cols=3) + self.local_check(a) + + debug.info(2, "Testing write_driver_array for columns=16, word_size=16, write_size=2") + a = factory.create(module_type="write_driver_array", columns=16, word_size=16, write_size=2, num_spare_cols=2) + self.local_check(a) + + debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4") + a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4) + self.local_check(a) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py new file mode 100755 index 00000000..0e9c74c3 --- /dev/null +++ b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os + +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_test") +class sram_1bank_2mux_wmask_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + c = sram_config(word_size=8, + write_size=4, + num_spare_cols=3, + num_words=64, + num_banks=1) + + c.words_per_row = 2 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} bit writes, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.write_size, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_spare_cols_test.py new file mode 100755 index 00000000..dba96ca2 --- /dev/null +++ b/compiler/tests/20_sram_1bank_nomux_wmask_spare_cols_test.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os + +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +# @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_test") +class sram_1bank_nomux_wmask_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + c = sram_config(word_size=8, + write_size=4, + num_spare_cols=3, + num_words=16, + num_banks=1) + + c.words_per_row = 1 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} bit writes, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.write_size, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 7505fa5aef116220975e3670091e927cdd93ca37 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Wed, 27 May 2020 20:03:11 -0700 Subject: [PATCH 318/521] update for end caps --- compiler/bitcells/col_cap_bitcell_1rw_1r.py | 43 ++++++ compiler/bitcells/row_cap_bitcell_1rw_1r.py | 43 ++++++ compiler/modules/bitcell_base_array.py | 15 +- compiler/modules/col_cap_array.py | 103 +++++++++++++ compiler/modules/replica_bitcell_array.py | 138 ++++++++++-------- compiler/modules/replica_column.py | 84 ++++++++--- compiler/modules/row_cap_array.py | 128 ++++++++++++++++ compiler/options.py | 21 +-- .../14_replica_bitcell_1rw_1r_array_test.py | 12 +- 9 files changed, 486 insertions(+), 101 deletions(-) create mode 100644 compiler/bitcells/col_cap_bitcell_1rw_1r.py create mode 100644 compiler/bitcells/row_cap_bitcell_1rw_1r.py create mode 100644 compiler/modules/col_cap_array.py create mode 100644 compiler/modules/row_cap_array.py diff --git a/compiler/bitcells/col_cap_bitcell_1rw_1r.py b/compiler/bitcells/col_cap_bitcell_1rw_1r.py new file mode 100644 index 00000000..315ad23f --- /dev/null +++ b/compiler/bitcells/col_cap_bitcell_1rw_1r.py @@ -0,0 +1,43 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +import utils +from tech import GDS, layer +from tech import cell_properties as props +import bitcell_base + + +class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base): + """ + todo""" + + pin_names = [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.bl1, + props.bitcell.cell_1rw1r.pin.br1, + props.bitcell.cell_1rw1r.pin.vdd] + + type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", + "POWER", "GROUND"] + + (width, height) = utils.get_libcell_size("col_cap_cell_1rw_1r", + GDS["unit"], + layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, + "col_cap_cell_1rw_1r", + GDS["unit"]) + + def __init__(self, name=""): + # Ignore the name argument + bitcell_base.bitcell_base.__init__(self, "col_cap_cell_1rw_1r") + debug.info(2, "Create col_cap bitcell 1rw+1r object") + + self.width = col_cap_bitcell_1rw_1r.width + self.height = col_cap_bitcell_1rw_1r.height + self.pin_map = col_cap_bitcell_1rw_1r.pin_map + self.add_pin_types(self.type_list) diff --git a/compiler/bitcells/row_cap_bitcell_1rw_1r.py b/compiler/bitcells/row_cap_bitcell_1rw_1r.py new file mode 100644 index 00000000..b50629f0 --- /dev/null +++ b/compiler/bitcells/row_cap_bitcell_1rw_1r.py @@ -0,0 +1,43 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +import utils +from tech import GDS, layer +from tech import cell_properties as props +import bitcell_base + + +class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base): + """ + A single bit cell which is forced to store a 0. + This module implements the single memory cell used in the design. It + is a hand-made cell, so the layout and netlist should be available in + the technology library. """ + + pin_names = [props.bitcell.cell_1rw1r.pin.wl0, + props.bitcell.cell_1rw1r.pin.wl1, + props.bitcell.cell_1rw1r.pin.gnd] + + type_list = ["INPUT", "INPUT", "GROUND"] + + (width, height) = utils.get_libcell_size("row_cap_cell_1rw_1r", + GDS["unit"], + layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, + "row_cap_cell_1rw_1r", + GDS["unit"]) + + def __init__(self, name=""): + # Ignore the name argument + bitcell_base.bitcell_base.__init__(self, "row_cap_cell_1rw_1r") + debug.info(2, "Create row_cap bitcell 1rw+1r object") + + self.width = row_cap_bitcell_1rw_1r.width + self.height = row_cap_bitcell_1rw_1r.height + self.pin_map = row_cap_bitcell_1rw_1r.pin_map + self.add_pin_types(self.type_list) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index a8829fc3..9b46a192 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -108,16 +108,23 @@ class bitcell_base_array(design.design): except AttributeError: bitcell_power_pin_directions = None + # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. + try: + bitcell_no_vdd_pin = cell_properties.bitcell.no_vdd_via + except AttributeError: + bitcell_no_vdd_pin = False + # Add vdd/gnd via stacks for row in range(self.row_size): for col in range(self.column_size): inst = self.cell_inst[row,col] for pin_name in ["vdd", "gnd"]: for pin in inst.get_pins(pin_name): - self.add_power_pin(name=pin_name, - loc=pin.center(), - directions=bitcell_power_pin_directions, - start_layer=pin.layer) + if not (pin_name == "vdd" and bitcell_no_vdd_pin): + self.add_power_pin(name=pin_name, + loc=pin.center(), + directions=bitcell_power_pin_directions, + start_layer=pin.layer) def _adjust_x_offset(self, xoffset, col, col_offset): tempx = xoffset diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py new file mode 100644 index 00000000..3119f4e5 --- /dev/null +++ b/compiler/modules/col_cap_array.py @@ -0,0 +1,103 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +from bitcell_base_array import bitcell_base_array +from sram_factory import factory +from globals import OPTS +from tech import cell_properties + +class col_cap_array(bitcell_base_array): + """ + Generate a dummy row/column for the replica array. + """ + def __init__(self, cols, rows, column_offset=0, mirror=0, name=""): + super().__init__(cols, rows, name, column_offset) + self.mirror = mirror + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + def create_netlist(self): + """ Create and connect the netlist """ + self.add_modules() + self.add_pins() + self.create_instances() + + def create_layout(self): + + self.place_array("dummy_r{0}_c{1}", self.mirror) + self.add_layout_pins() + self.add_boundary() + self.DRC_LVS() + + def add_modules(self): + """ Add the modules used in this design """ + # self.dummy_cell = factory.create(module_type="col_cap_bitcell_1rw_1r") # TODO: make module_type generic + self.dummy_cell = factory.create(module_type="col_cap_bitcell") + self.add_mod(self.dummy_cell) + + self.cell = factory.create(module_type="bitcell") + + def create_instances(self): + """ Create the module instances used in this design """ + self.cell_inst = {} + for col in range(self.column_size): + for row in range(self.row_size): + name = "bit_r{0}_c{1}".format(row, col) + self.cell_inst[row,col]=self.add_inst(name=name, + mod=self.dummy_cell) + self.connect_inst(self.get_bitcell_pins(col, row)) + + def get_bitcell_pins(self, col, row): + """ + Creates a list of connections in the bitcell, + indexed by column and row, for instance use in bitcell_array + """ + + pin_name = cell_properties.bitcell.cell_1rw1r.pin + bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col), + "{0}_{1}".format(pin_name.br0, col), + "{0}_{1}".format(pin_name.bl1, col), + "{0}_{1}".format(pin_name.br1, col), + "vdd"] + + return bitcell_pins + + def add_layout_pins(self): + """ Add the layout pins """ + + column_list = self.cell.get_all_bitline_names() + + for col in range(self.column_size): + for cell_column in column_list: + bl_pin = self.cell_inst[0,col].get_pin(cell_column) + self.add_layout_pin(text=cell_column+"_{0}".format(col), + layer=bl_pin.layer, + offset=bl_pin.ll().scale(1,0), + width=bl_pin.width(), + height=self.height) + + # Add vdd/gnd via stacks + for row in range(self.row_size): + for col in range(self.column_size): + inst = self.cell_inst[row,col] + for pin_name in ["vdd", "gnd"]: + for pin in inst.get_pins(pin_name): + self.add_power_pin(name=pin.name, + loc=pin.center(), + start_layer=pin.layer) + + + # def input_load(self): + # wl_wire = self.gen_wl_wire() + # return wl_wire.return_input_cap() + # + # def get_wordline_cin(self): + # """Get the relative input capacitance from the wordline connections in all the bitcell""" + # #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns + # bitcell_wl_cin = self.cell.get_wl_cin() + # total_cin = bitcell_wl_cin * self.column_size + # return total_cin diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index c88dbe6d..ff91f7fd 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California +# Copyright (c) 2016-2019 Regents of the University of California # All rights reserved. # import debug import design -from tech import drc, spice +from tech import drc, spice, cell_properties from vector import vector from globals import OPTS from sram_factory import factory @@ -34,11 +34,11 @@ class replica_bitcell_array(design.design): debug.check(left_rbl+right_rbl==len(self.all_ports),"Invalid number of RBLs for port configuration.") debug.check(left_rbl+right_rbl==len(self.bitcell_ports),"Bitcell ports must match total RBLs.") - + # Two dummy rows/cols plus replica for each port self.extra_rows = 2 + left_rbl + right_rbl self.extra_cols = 2 + left_rbl + right_rbl - + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -46,8 +46,8 @@ class replica_bitcell_array(design.design): # We don't offset this because we need to align # the replica bitcell in the control logic #self.offset_all_coordinates() - - + + def create_netlist(self): """ Create and connect the netlist """ self.add_modules() @@ -55,15 +55,15 @@ class replica_bitcell_array(design.design): self.create_instances() def add_modules(self): - """ Array and dummy/replica columns + """ Array and dummy/replica columns d or D = dummy cell (caps to distinguish grouping) r or R = replica cell (caps to distinguish grouping) - b or B = bitcell - replica columns 1 + b or B = bitcell + replica columns 1 v v - bdDDDDDDDDDDDDDDdb <- Dummy row - bdDDDDDDDDDDDDDDrb <- Dummy row + bdDDDDDDDDDDDDDDdb <- Dummy row + bdDDDDDDDDDDDDDDrb <- Dummy row br--------------rb br| Array |rb br| row x col |rb @@ -106,7 +106,7 @@ class replica_bitcell_array(design.design): column_offset=column_offset, replica_bit=replica_bit) self.add_mod(self.replica_columns[bit]) - + # Dummy row self.dummy_row = factory.create(module_type="dummy_array", cols=self.column_size, @@ -116,15 +116,35 @@ class replica_bitcell_array(design.design): mirror=0) self.add_mod(self.dummy_row) - # Dummy col (mirror starting at first if odd replica+dummy rows) - self.dummy_col_left = factory.create(module_type="dummy_array", + + # If there are bitcell end caps, replace the dummy cells on the edge of the bitcell array with end caps. + try: + end_caps_enabled = cell_properties.bitcell.end_caps + except AttributeError: + end_caps_enabled = False + + # Dummy Row or Col Cap, depending on bitcell array properties + edge_row_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array") + + self.edge_row = factory.create(module_type=edge_row_module_type, + cols=self.column_size, + rows=1, + # dummy column + left replica column + column_offset=1 + self.left_rbl, + mirror=0) + self.add_mod(self.edge_row) + + # Dummy Col or Row Cap, depending on bitcell array properties + edge_col_module_type = ("row_cap_array" if end_caps_enabled else "dummy_array") + + self.edge_col_left = factory.create(module_type=edge_col_module_type, cols=1, column_offset=0, rows=self.row_size + self.extra_rows, mirror=(self.left_rbl+1)%2) - self.add_mod(self.dummy_col_left) + self.add_mod(self.edge_col_left) - self.dummy_col_right = factory.create(module_type="dummy_array", + self.edge_col_right = factory.create(module_type=edge_col_module_type, cols=1, # dummy column # + left replica column @@ -133,9 +153,7 @@ class replica_bitcell_array(design.design): column_offset=1 + self.left_rbl + self.column_size + self.right_rbl, rows=self.row_size + self.extra_rows, mirror=(self.left_rbl+1)%2) - self.add_mod(self.dummy_col_right) - - + self.add_mod(self.edge_col_right) def add_pins(self): self.bitcell_array_wl_names = self.bitcell_array.get_all_wordline_names() @@ -150,7 +168,7 @@ class replica_bitcell_array(design.design): self.rbl_bl_names = {} self.rbl_br_names = {} self.rbl_wl_names = {} - + # Create the full WL names include dummy, replica, and regular bit cells self.replica_col_wl_names = [] self.replica_col_wl_names.extend(["{0}_bot".format(x) for x in self.dummy_cell_wl_names]) @@ -193,7 +211,7 @@ class replica_bitcell_array(design.design): wl_names = ["rbl_{0}_{1}".format(x,port) for x in self.cell.get_all_wl_names()] #wl_names[port] = "rbl_wl{}".format(port) self.replica_wl_names[port] = wl_names - + # External pins self.add_pin_list(self.bitcell_array_bl_names, "INOUT") @@ -204,22 +222,22 @@ class replica_bitcell_array(design.design): self.add_pin(bl_name,"OUTPUT") self.add_pin(br_name,"OUTPUT") self.add_pin_list(self.bitcell_array_wl_names, "INPUT") - # Need to sort by port order since dictionary values may not be in order + # Need to sort by port order since dictionary values may not be in order wl_names = [self.rbl_wl_names[x] for x in sorted(self.rbl_wl_names.keys())] for pin_name in wl_names: self.add_pin(pin_name,"INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - + def create_instances(self): """ Create the module instances used in this design """ supplies = ["vdd", "gnd"] - + # Used for names/dimensions only self.cell = factory.create(module_type="bitcell") - + # Main array self.bitcell_array_inst=self.add_inst(name="bitcell_array", mod=self.bitcell_array) @@ -231,35 +249,33 @@ class replica_bitcell_array(design.design): self.replica_col_inst[port]=self.add_inst(name="replica_col_{}".format(port), mod=self.replica_columns[port]) self.connect_inst(self.replica_bl_names[port] + self.replica_col_wl_names + supplies) - - + + # Dummy rows under the bitcell array (connected with with the replica cell wl) self.dummy_row_replica_inst = {} for port in range(self.left_rbl+self.right_rbl): self.dummy_row_replica_inst[port]=self.add_inst(name="dummy_row_{}".format(port), mod=self.dummy_row) self.connect_inst(self.dummy_row_bl_names + self.replica_wl_names[port] + supplies) - - - # Top/bottom dummy rows + + + # Top/bottom dummy rows or col caps self.dummy_row_bot_inst=self.add_inst(name="dummy_row_bot", - mod=self.dummy_row) + mod=self.edge_row) self.connect_inst(self.dummy_row_bl_names + [x+"_bot" for x in self.dummy_cell_wl_names] + supplies) self.dummy_row_top_inst=self.add_inst(name="dummy_row_top", - mod=self.dummy_row) + mod=self.edge_row) self.connect_inst(self.dummy_row_bl_names + [x+"_top" for x in self.dummy_cell_wl_names] + supplies) # Left/right Dummy columns self.dummy_col_left_inst=self.add_inst(name="dummy_col_left", - mod=self.dummy_col_left) + mod=self.edge_col_left) self.connect_inst([x+"_left" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies) self.dummy_col_right_inst=self.add_inst(name="dummy_col_right", - mod=self.dummy_col_right) + mod=self.edge_col_right) self.connect_inst([x+"_right" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies) - - def create_layout(self): self.height = (self.row_size+self.extra_rows)*self.dummy_row.height @@ -267,7 +283,7 @@ class replica_bitcell_array(design.design): # This is a bitcell x bitcell offset to scale offset = vector(self.cell.width, self.cell.height) - + self.bitcell_array_inst.place(offset=[0,0]) # To the left of the bitcell array @@ -276,7 +292,6 @@ class replica_bitcell_array(design.design): # To the right of the bitcell array for bit in range(self.right_rbl): self.replica_col_inst[self.left_rbl+bit].place(offset=offset.scale(bit,-self.left_rbl-1)+self.bitcell_array_inst.lr()) - # Far top dummy row (first row above array is NOT flipped) flip_dummy = self.right_rbl%2 @@ -298,17 +313,17 @@ class replica_bitcell_array(design.design): for bit in range(self.right_rbl): self.dummy_row_replica_inst[self.left_rbl+bit].place(offset=offset.scale(0,bit+bit%2)+self.bitcell_array_inst.ul(), mirror="MX" if bit%2 else "R0") - + self.translate_all(offset.scale(-1-self.left_rbl,-1-self.left_rbl)) - + self.add_layout_pins() - + self.add_boundary() - + self.DRC_LVS() - + def add_layout_pins(self): """ Add the layout pins """ @@ -341,10 +356,10 @@ class replica_bitcell_array(design.design): for (pin_name,wl_name) in zip(self.cell.get_all_wl_names(),self.replica_wl_names[port]): # +1 for dummy row pin_bit = port+1 - # +row_size if above the array + # +row_size if above the array if port>=self.left_rbl: pin_bit += self.row_size - + pin_name += "_{}".format(pin_bit) pin = inst.get_pin(pin_name) if wl_name in self.rbl_wl_names.values(): @@ -368,20 +383,27 @@ class replica_bitcell_array(design.design): offset=pin.ll().scale(1, 0), width=pin.width(), height=self.height) - + + # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. + try: + bitcell_no_vdd_pin = cell_properties.bitcell.no_vdd_via + except AttributeError: + bitcell_no_vdd_pin = False + for pin_name in ["vdd", "gnd"]: for inst in self.insts: pin_list = inst.get_pins(pin_name) for pin in pin_list: - self.add_power_pin(name=pin_name, - loc=pin.center(), - directions=("V", "V"), - start_layer=pin.layer) + if not (pin_name == "vdd" and bitcell_no_vdd_pin): + self.add_power_pin(name=pin_name, + loc=pin.center(), + directions=("V", "V"), + start_layer=pin.layer) def get_rbl_wl_name(self, port): """ Return the WL for the given RBL port """ return self.rbl_wl_names[port] - + def get_rbl_bl_name(self, port): """ Return the BL for the given RBL port """ return self.rbl_bl_names[port] @@ -393,17 +415,17 @@ class replica_bitcell_array(design.design): def analytical_power(self, corner, load): """Power of Bitcell array and bitline in nW.""" from tech import drc, parameter - + # Dynamic Power from Bitline bl_wire = self.gen_bl_wire() cell_load = 2 * bl_wire.return_input_cap() bl_swing = OPTS.rbl_delay_percentage freq = spice["default_event_frequency"] bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing) - - #Calculate the bitcell power which currently only includes leakage + + #Calculate the bitcell power which currently only includes leakage cell_power = self.cell.analytical_power(corner, load) - + #Leakage power grows with entire array and bitlines. total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size, cell_power.leakage * self.column_size * self.row_size) @@ -429,13 +451,13 @@ class replica_bitcell_array(design.design): def graph_exclude_bits(self, targ_row, targ_col): """Excludes bits in column from being added to graph except target""" self.bitcell_array.graph_exclude_bits(targ_row, targ_col) - + def graph_exclude_replica_col_bits(self): """Exclude all replica/dummy cells in the replica columns except the replica bit.""" - + for port in range(self.left_rbl+self.right_rbl): self.replica_columns[port].exclude_all_but_replica() def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" - return self.bitcell_array.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col) + return self.bitcell_array.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col) diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index d874ba8c..2e3d207e 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -1,11 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California +# Copyright (c) 2016-2019 Regents of the University of California # All rights reserved. # import debug import design -from tech import drc +from tech import drc, cell_properties import contact from sram_factory import factory from vector import vector @@ -16,7 +16,7 @@ class replica_column(design.design): Generate a replica bitline column for the replica array. Rows is the total number of rows i the main array. Left_rbl and right_rbl are the number of left and right replica bitlines. - Replica bit specifies which replica column this is (to determine where to put the + Replica bit specifies which replica column this is (to determine where to put the replica cell. """ @@ -31,15 +31,15 @@ class replica_column(design.design): # left, right, regular rows plus top/bottom dummy cells self.total_size = self.left_rbl+rows+self.right_rbl+2 self.column_offset = column_offset - + debug.check(replica_bit!=0 and replica_bit!=rows,"Replica bit cannot be the dummy row.") debug.check(replica_bit<=left_rbl or replica_bit>=self.total_size-right_rbl-1, - "Replica bit cannot be in the regular array.") + "Replica bit cannot be in the regular array.") self.create_netlist() if not OPTS.netlist_only: self.create_layout() - + def create_netlist(self): self.add_modules() self.add_pins() @@ -47,7 +47,7 @@ class replica_column(design.design): def create_layout(self): self.height = self.total_size*self.cell.height - self.width = self.cell.width + self.width = self.cell.width self.place_instances() self.add_layout_pins() @@ -55,7 +55,7 @@ class replica_column(design.design): self.DRC_LVS() def add_pins(self): - + for bl_name in self.cell.get_all_bitline_names(): # In the replica column, these are only outputs! self.add_pin("{0}_{1}".format(bl_name,0), "OUTPUT") @@ -63,7 +63,7 @@ class replica_column(design.design): for row in range(self.total_size): for wl_name in self.cell.get_all_wl_names(): self.add_pin("{0}_{1}".format(wl_name,row), "INPUT") - + self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -72,27 +72,49 @@ class replica_column(design.design): self.add_mod(self.replica_cell) self.dummy_cell = factory.create(module_type="dummy_bitcell") self.add_mod(self.dummy_cell) + try: + edge_module_type = ("col_cap_bitcell" if cell_properties.bitcell.end_caps else "dummy_bitcell") + except AttributeError: + edge_module_type = "dummy_bitcell" + self.edge_cell = factory.create(module_type=edge_module_type) + self.add_mod(self.edge_cell) # Used for pin names only self.cell = factory.create(module_type="bitcell") - + def create_instances(self): + + try: + end_caps_enabled = cell_properties.bitcell.end_caps + except AttributeError: + end_caps_enabled = False + self.cell_inst = {} for row in range(self.total_size): name="rbc_{0}".format(row) # Top/bottom cell are always dummy cells. # Regular array cells are replica cells (>left_rbl and self.left_rbl and row Date: Thu, 28 May 2020 20:31:21 -0700 Subject: [PATCH 319/521] fix for replica column mirroring over y --- compiler/modules/replica_bitcell_array.py | 6 ++++-- compiler/tests/14_replica_bitcell_1rw_1r_array_test.py | 6 +++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index ff91f7fd..ff2260d3 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -91,14 +91,16 @@ class replica_bitcell_array(design.design): # Replica bitlines self.replica_columns = {} for bit in range(self.left_rbl+self.right_rbl): + # Creating left_rbl if bit Date: Thu, 14 May 2020 11:20:37 -0700 Subject: [PATCH 320/521] Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case --- .gitlab-ci.yml | 11 +- compiler/base/contact.py | 8 +- compiler/base/geometry.py | 14 +- compiler/base/hierarchy_layout.py | 58 +-- compiler/base/hierarchy_spice.py | 1 + compiler/bitcells/bitcell.py | 2 +- compiler/{modules => custom}/dff.py | 4 +- compiler/custom/inv_dec.py | 80 ++++ compiler/custom/nand2_dec.py | 77 ++++ compiler/custom/nand3_dec.py | 77 ++++ compiler/custom/nand4_dec.py | 77 ++++ compiler/custom/pand2_dec.py | 138 +++++++ compiler/custom/pand3_dec.py | 149 +++++++ compiler/custom/pand4_dec.py | 149 +++++++ compiler/{modules => custom}/tri_gate.py | 0 compiler/{modules => custom}/write_driver.py | 0 compiler/modules/hierarchical_decoder.py | 373 ++++++++---------- compiler/modules/hierarchical_predecode.py | 260 ++++++++---- compiler/modules/hierarchical_predecode2x4.py | 20 +- compiler/modules/hierarchical_predecode3x8.py | 21 +- .../modules/hierarchical_predecode4x16.py | 64 +++ compiler/modules/port_address.py | 27 +- compiler/modules/port_data.py | 59 ++- ...ine_driver.py => wordline_driver_array.py} | 153 +++---- compiler/options.py | 4 + compiler/pgates/pand2.py | 2 +- compiler/pgates/pdriver.py | 12 +- compiler/pgates/pgate.py | 1 - compiler/pgates/pinv_dec.py | 217 ++++++++++ compiler/pgates/pnand3.py | 3 + compiler/pgates/ptx.py | 10 +- compiler/pgates/wordline_driver.py | 155 ++++++++ compiler/sram_factory.py | 4 +- compiler/tests/02_library_lvs_test.py | 2 +- compiler/tests/04_pand2_dec_test.py | 39 ++ compiler/tests/04_pand3_dec_test.py | 39 ++ compiler/tests/04_pand4_dec_test.py | 39 ++ compiler/tests/04_pdriver_test.py | 4 +- compiler/tests/04_pinv_dec_1x_test.py | 35 ++ ...ver_test.py => 04_wordline_driver_test.py} | 2 +- .../tests/06_hierarchical_decoder_test.py | 8 +- .../06_hierarchical_predecode2x4_test.py | 7 +- .../06_hierarchical_predecode3x8_test.py | 7 +- .../06_hierarchical_predecode4x16_test.py | 42 ++ ...08_wordline_driver_array_pbitcell_test.py} | 5 +- .../tests/08_wordline_driver_array_test.py | 37 ++ compiler/tests/18_port_data_1rw_1r_test.py | 6 +- compiler/tests/19_single_bank_test.py | 40 +- compiler/tests/testutils.py | 1 + 49 files changed, 1991 insertions(+), 552 deletions(-) rename compiler/{modules => custom}/dff.py (95%) create mode 100644 compiler/custom/inv_dec.py create mode 100644 compiler/custom/nand2_dec.py create mode 100644 compiler/custom/nand3_dec.py create mode 100644 compiler/custom/nand4_dec.py create mode 100644 compiler/custom/pand2_dec.py create mode 100644 compiler/custom/pand3_dec.py create mode 100644 compiler/custom/pand4_dec.py rename compiler/{modules => custom}/tri_gate.py (100%) rename compiler/{modules => custom}/write_driver.py (100%) create mode 100644 compiler/modules/hierarchical_predecode4x16.py rename compiler/modules/{wordline_driver.py => wordline_driver_array.py} (50%) create mode 100644 compiler/pgates/pinv_dec.py create mode 100644 compiler/pgates/wordline_driver.py create mode 100755 compiler/tests/04_pand2_dec_test.py create mode 100755 compiler/tests/04_pand3_dec_test.py create mode 100755 compiler/tests/04_pand4_dec_test.py create mode 100755 compiler/tests/04_pinv_dec_1x_test.py rename compiler/tests/{08_wordline_driver_test.py => 04_wordline_driver_test.py} (93%) create mode 100755 compiler/tests/06_hierarchical_predecode4x16_test.py rename compiler/tests/{08_wordline_driver_pbitcell_test.py => 08_wordline_driver_array_pbitcell_test.py} (87%) create mode 100755 compiler/tests/08_wordline_driver_array_test.py diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 27c341aa..27431cb2 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,7 @@ before_script: - . /home/gitlab-runner/setup-paths.sh - export OPENRAM_HOME="`pwd`/compiler" - - export OPENRAM_TECH="`pwd`/technology" + - export OPENRAM_TECH="`pwd`/technology:/home/PDKs/skywater-tech" stages: - test @@ -25,6 +25,15 @@ scn4m_subm: - .coverage.* expire_in: 1 week +# s8: +# stage: test +# script: +# - coverage run -p $OPENRAM_HOME/tests/regress.py -t s8 +# artifacts: +# paths: +# - .coverage.* +# expire_in: 1 week + coverage: stage: coverage script: diff --git a/compiler/base/contact.py b/compiler/base/contact.py index f4fda552..14dbf76e 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -53,6 +53,10 @@ class contact(hierarchy_design.hierarchy_design): first_dir = "H" if self.get_preferred_direction(layer_stack[0])=="V" else "V" second_dir = "H" if self.get_preferred_direction(layer_stack[2])=="V" else "V" self.directions = (first_dir, second_dir) + # Preferred directions + elif directions == "pref": + self.directions = (tech.preferred_directions[layer_stack[0]], + tech.preferred_directions[layer_stack[2]]) # User directions elif directions: self.directions = directions @@ -149,7 +153,7 @@ class contact(hierarchy_design.hierarchy_design): self.first_layer_vertical_enclosure = max(self.first_layer_enclosure, (self.first_layer_minwidth - self.contact_array_height) / 2) else: - debug.error("Invalid first layer direction.", -1) + debug.error("Invalid first layer direction: ".format(self.directions[0]), -1) # In some technologies, the minimum width may be larger # than the overlap requirement around the via, so @@ -165,7 +169,7 @@ class contact(hierarchy_design.hierarchy_design): self.second_layer_vertical_enclosure = max(self.second_layer_enclosure, (self.second_layer_minwidth - self.contact_array_width) / 2) else: - debug.error("Invalid second layer direction.", -1) + debug.error("Invalid secon layer direction: ".format(self.directions[1]), -1) def create_contact_array(self): """ Create the contact array at the origin""" diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 96da3d99..32af7ee9 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -86,8 +86,14 @@ class geometry: elif mirror == "XY": ll = ll.scale(-1, -1) ur = ur.scale(-1, -1) + elif mirror == "" or mirror == "R0": + pass + else: + debug.error("Invalid mirroring: {}".format(mirror), -1) - if rotate == 90: + if rotate == 0: + pass + elif rotate == 90: ll = ll.rotate_scale(-1, 1) ur = ur.rotate_scale(-1, 1) elif rotate == 180: @@ -96,6 +102,8 @@ class geometry: elif rotate == 270: ll = ll.rotate_scale(1, -1) ur = ur.rotate_scale(1, -1) + else: + debug.error("Invalid rotation: {}".format(rotate), -1) self.boundary = [offset + ll, offset + ur] self.normalize() @@ -139,6 +147,10 @@ class geometry: def cy(self): """ Return the center y """ return 0.5 * (self.boundary[0].y + self.boundary[1].y) + + def center(self): + """ Return the center coordinate """ + return vector(self.cx(), self.cy()) class instance(geometry): diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index df7095df..4d0345a3 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -244,25 +244,27 @@ class layout(): height)) return self.objs[-1] - def add_segment_center(self, layer, start, end): + def add_segment_center(self, layer, start, end, width=None): """ Add a min-width rectanglular segment using center line on the start to end point """ - minwidth_layer = drc["minwidth_{}".format(layer)] + if not width: + width = drc["minwidth_{}".format(layer)] + if start.x != end.x and start.y != end.y: debug.error("Nonrectilinear center rect!", -1) elif start.x != end.x: - offset = vector(0, 0.5 * minwidth_layer) + offset = vector(0, 0.5 * width) return self.add_rect(layer, start - offset, end.x - start.x, - minwidth_layer) + width) else: - offset = vector(0.5 * minwidth_layer, 0) + offset = vector(0.5 * width, 0) return self.add_rect(layer, start - offset, - minwidth_layer, + width, end.y - start.y) def get_pin(self, text): @@ -322,7 +324,7 @@ class layout(): for pin_name in self.pin_map.keys(): self.copy_layout_pin(instance, pin_name, prefix + pin_name) - def add_layout_pin_segment_center(self, text, layer, start, end): + def add_layout_pin_segment_center(self, text, layer, start, end, width=None): """ Creates a path like pin with center-line convention """ @@ -331,27 +333,27 @@ class layout(): self.gds_write(file_name) debug.error("Cannot have a non-manhatten layout pin: {}".format(file_name), -1) - minwidth_layer = drc["minwidth_{}".format(layer)] + if not width: + layer_width = drc["minwidth_{}".format(layer)] + else: + layer_width = width # one of these will be zero - width = max(start.x, end.x) - min(start.x, end.x) - height = max(start.y, end.y) - min(start.y, end.y) + bbox_width = max(start.x, end.x) - min(start.x, end.x) + bbox_height = max(start.y, end.y) - min(start.y, end.y) ll_offset = vector(min(start.x, end.x), min(start.y, end.y)) # Shift it down 1/2 a width in the 0 dimension - if height == 0: - ll_offset -= vector(0, 0.5 * minwidth_layer) - if width == 0: - ll_offset -= vector(0.5 * minwidth_layer, 0) - # This makes sure it is long enough, but also it is not 0 width! - height = max(minwidth_layer, height) - width = max(minwidth_layer, width) + if bbox_height == 0: + ll_offset -= vector(0, 0.5 * layer_width) + if bbox_width == 0: + ll_offset -= vector(0.5 * layer_width, 0) - return self.add_layout_pin(text, - layer, - ll_offset, - width, - height) + return self.add_layout_pin(text=text, + layer=layer, + offset=ll_offset, + width=bbox_width, + height=bbox_height) def add_layout_pin_rect_center(self, text, layer, offset, width=None, height=None): """ Creates a path like pin with center-line convention """ @@ -692,6 +694,8 @@ class layout(): boundary_layer = "stdc" boundary = [self.find_lowest_coords(), self.find_highest_coords()] + debug.check(boundary[0] and boundary[1], "No shapes to make a boundary.") + height = boundary[1][1] - boundary[0][1] width = boundary[1][0] - boundary[0][0] (layer_number, layer_purpose) = techlayer[boundary_layer] @@ -1306,16 +1310,16 @@ class layout(): which vias are needed. """ - via = self.add_via_stack_center(from_layer=start_layer, - to_layer=self.pwr_grid_layer, - size=size, - offset=loc, - directions=directions) if start_layer == self.pwr_grid_layer: self.add_layout_pin_rect_center(text=name, layer=self.pwr_grid_layer, offset=loc) else: + via = self.add_via_stack_center(from_layer=start_layer, + to_layer=self.pwr_grid_layer, + size=size, + offset=loc, + directions=directions) # Hack for min area if OPTS.tech_name == "s8": width = round_to_grid(sqrt(drc["minarea_m3"])) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 8091af63..00d7ad44 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -208,6 +208,7 @@ class spice(): # parses line into ports and remove subckt self.pins = subckt_line.split(" ")[2:] else: + debug.info(4, "no spfile {0}".format(self.sp_file)) self.spice = [] # We don't define self.lvs and will use self.spice if dynamically created diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index b0e79208..4ed2d053 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -7,7 +7,7 @@ # import debug import utils -from tech import GDS, layer, parameter +from tech import GDS, layer from tech import cell_properties as props import bitcell_base diff --git a/compiler/modules/dff.py b/compiler/custom/dff.py similarity index 95% rename from compiler/modules/dff.py rename to compiler/custom/dff.py index e319459e..c8fdb4b0 100644 --- a/compiler/modules/dff.py +++ b/compiler/custom/dff.py @@ -61,7 +61,7 @@ class dff(design.design): #Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width. return parameter["dff_clk_cin"] - def build_graph(self, graph, inst_name, port_nets): + def build_graph(self, graph, inst_name, port_nets): """Adds edges based on inputs/outputs. Overrides base class function.""" - self.add_graph_edges(graph, port_nets) + self.add_graph_edges(graph, port_nets) diff --git a/compiler/custom/inv_dec.py b/compiler/custom/inv_dec.py new file mode 100644 index 00000000..80fdb74e --- /dev/null +++ b/compiler/custom/inv_dec.py @@ -0,0 +1,80 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import design +from tech import GDS, layer, spice, parameter +import logical_effort +import utils +import debug + + +class inv_dec(design.design): + """ + INV for address decoders. + """ + + pin_names = ["A", "Z", "vdd", "gnd"] + type_list = ["INPUT", "OUTPUT", "POWER", "GROUND"] + + (width, height) = utils.get_libcell_size("inv_dec", + GDS["unit"], + layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "inv_dec", GDS["unit"]) + + def __init__(self, name="inv_dec", height=None): + design.design.__init__(self, name) + + self.width = inv_dec.width + self.height = inv_dec.height + self.pin_map = inv_dec.pin_map + self.add_pin_types(self.type_list) + + def analytical_power(self, corner, load): + """Returns dynamic and leakage power. Results in nW""" + c_eff = self.calculate_effective_capacitance(load) + freq = spice["default_event_frequency"] + power_dyn = self.calc_dynamic_power(corner, c_eff, freq) + power_leak = spice["inv_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + c_load = load + # In fF + c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"]) + + return transition_prob * (c_load + c_para) + + def input_load(self): + """ + Return the capacitance of the gate connection in generic capacitive + units relative to the minimum width of a transistor + """ + return self.nmos_size + self.pmos_size + + def get_stage_effort(self, cout, inp_is_rise=True): + """ + Returns an object representing the parameters for delay in tau units. + Optional is_rise refers to the input direction rise/fall. + Input inverted by this stage. + """ + parasitic_delay = 1 + return logical_effort.logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) + + def build_graph(self, graph, inst_name, port_nets): + """ + Adds edges based on inputs/outputs. + Overrides base class function. + """ + self.add_graph_edges(graph, port_nets) diff --git a/compiler/custom/nand2_dec.py b/compiler/custom/nand2_dec.py new file mode 100644 index 00000000..30a018a1 --- /dev/null +++ b/compiler/custom/nand2_dec.py @@ -0,0 +1,77 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import design +from tech import GDS, layer, spice, parameter +import logical_effort +import utils + + +class nand2_dec(design.design): + """ + 2-input NAND decoder for address decoders. + """ + + pin_names = ["A", "B", "Z", "vdd", "gnd"] + type_list = ["INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"] + + (width, height) = utils.get_libcell_size("nand2_dec", + GDS["unit"], + layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "nand2_dec", GDS["unit"]) + + def __init__(self, name="nand2_dec", height=None): + design.design.__init__(self, name) + + self.width = nand2_dec.width + self.height = nand2_dec.height + self.pin_map = nand2_dec.pin_map + self.add_pin_types(self.type_list) + + def analytical_power(self, corner, load): + """Returns dynamic and leakage power. Results in nW""" + c_eff = self.calculate_effective_capacitance(load) + freq = spice["default_event_frequency"] + power_dyn = self.calc_dynamic_power(corner, c_eff, freq) + power_leak = spice["nand2_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + c_load = load + # In fF + c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"]) + transition_prob = 0.1875 + return transition_prob * (c_load + c_para) + + def input_load(self): + """Return the relative input capacitance of a single input""" + return self.nmos_size + self.pmos_size + + def get_stage_effort(self, cout, inp_is_rise=True): + """ + Returns an object representing the parameters for delay in tau units. + Optional is_rise refers to the input direction rise/fall. + Input inverted by this stage. + """ + parasitic_delay = 2 + return logical_effort.logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) + + def build_graph(self, graph, inst_name, port_nets): + """ + Adds edges based on inputs/outputs. + Overrides base class function. + """ + self.add_graph_edges(graph, port_nets) + diff --git a/compiler/custom/nand3_dec.py b/compiler/custom/nand3_dec.py new file mode 100644 index 00000000..d700062c --- /dev/null +++ b/compiler/custom/nand3_dec.py @@ -0,0 +1,77 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import design +from tech import GDS, layer, spice, parameter +import logical_effort +import utils + + +class nand3_dec(design.design): + """ + 3-input NAND decoder for address decoders. + """ + + pin_names = ["A", "B", "C", "Z", "vdd", "gnd"] + type_list = ["INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"] + + (width, height) = utils.get_libcell_size("nand3_dec", + GDS["unit"], + layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "nand3_dec", GDS["unit"]) + + def __init__(self, name="nand3_dec", height=None): + design.design.__init__(self, name) + + self.width = nand3_dec.width + self.height = nand3_dec.height + self.pin_map = nand3_dec.pin_map + self.add_pin_types(self.type_list) + + def analytical_power(self, corner, load): + """Returns dynamic and leakage power. Results in nW""" + c_eff = self.calculate_effective_capacitance(load) + freq = spice["default_event_frequency"] + power_dyn = self.calc_dynamic_power(corner, c_eff, freq) + power_leak = spice["nand3_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + c_load = load + # In fF + c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"]) + transition_prob = 0.1875 + return transition_prob * (c_load + c_para) + + def input_load(self): + """Return the relative input capacitance of a single input""" + return self.nmos_size + self.pmos_size + + def get_stage_effort(self, cout, inp_is_rise=True): + """ + Returns an object representing the parameters for delay in tau units. + Optional is_rise refers to the input direction rise/fall. + Input inverted by this stage. + """ + parasitic_delay = 2 + return logical_effort.logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) + + def build_graph(self, graph, inst_name, port_nets): + """ + Adds edges based on inputs/outputs. + Overrides base class function. + """ + self.add_graph_edges(graph, port_nets) + diff --git a/compiler/custom/nand4_dec.py b/compiler/custom/nand4_dec.py new file mode 100644 index 00000000..5c2bb882 --- /dev/null +++ b/compiler/custom/nand4_dec.py @@ -0,0 +1,77 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import design +from tech import GDS, layer, spice, parameter +import logical_effort +import utils + + +class nand4_dec(design.design): + """ + 2-input NAND decoder for address decoders. + """ + + pin_names = ["A", "B", "C", "D", "Z", "vdd", "gnd"] + type_list = ["INPUT", "INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"] + + (width, height) = utils.get_libcell_size("nand4_dec", + GDS["unit"], + layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "nand4_dec", GDS["unit"]) + + def __init__(self, name="nand4_dec", height=None): + design.design.__init__(self, name) + + self.width = nand4_dec.width + self.height = nand4_dec.height + self.pin_map = nand4_dec.pin_map + self.add_pin_types(self.type_list) + + def analytical_power(self, corner, load): + """Returns dynamic and leakage power. Results in nW""" + c_eff = self.calculate_effective_capacitance(load) + freq = spice["default_event_frequency"] + power_dyn = self.calc_dynamic_power(corner, c_eff, freq) + power_leak = spice["nand4_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + c_load = load + # In fF + c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"]) + transition_prob = 0.1875 + return transition_prob * (c_load + c_para) + + def input_load(self): + """Return the relative input capacitance of a single input""" + return self.nmos_size + self.pmos_size + + def get_stage_effort(self, cout, inp_is_rise=True): + """ + Returns an object representing the parameters for delay in tau units. + Optional is_rise refers to the input direction rise/fall. + Input inverted by this stage. + """ + parasitic_delay = 2 + return logical_effort.logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) + + def build_graph(self, graph, inst_name, port_nets): + """ + Adds edges based on inputs/outputs. + Overrides base class function. + """ + self.add_graph_edges(graph, port_nets) + diff --git a/compiler/custom/pand2_dec.py b/compiler/custom/pand2_dec.py new file mode 100644 index 00000000..0db490ff --- /dev/null +++ b/compiler/custom/pand2_dec.py @@ -0,0 +1,138 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +from vector import vector +import pgate +from sram_factory import factory +from globals import OPTS + + +class pand2_dec(pgate.pgate): + """ + This is an AND with configurable drive strength. + """ + def __init__(self, name, size=1, height=None, add_wells=True): + debug.info(1, "Creating pand2_dec {}".format(name)) + self.add_comment("size: {}".format(size)) + + self.size = size + + pgate.pgate.__init__(self, name, height, add_wells) + + def create_netlist(self): + self.add_pins() + self.create_modules() + self.create_insts() + + def create_modules(self): + if OPTS.tech_name == "s8": + self.nand = factory.create(module_type="nand2_dec") + else: + self.nand = factory.create(module_type="nand2_dec", + height=self.height) + + self.inv = factory.create(module_type="inv_dec", + height=self.height, + size=self.size) + + self.add_mod(self.nand) + self.add_mod(self.inv) + + def create_layout(self): + self.width = self.nand.width + self.inv.width + + self.place_insts() + self.add_wires() + self.add_layout_pins() + self.route_supply_rails() + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + self.add_pin("A", "INPUT") + self.add_pin("B", "INPUT") + self.add_pin("Z", "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def create_insts(self): + self.nand_inst = self.add_inst(name="pand2_dec_nand", + mod=self.nand) + self.connect_inst(["A", "B", "zb_int", "vdd", "gnd"]) + + self.inv_inst = self.add_inst(name="pand2_dec_inv", + mod=self.inv) + self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) + + def place_insts(self): + # Add NAND to the right + self.nand_inst.place(offset=vector(0, 0)) + + # Add INV to the right + self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0)) + + def route_supply_rails(self): + """ Add vdd/gnd rails to the top, (middle), and bottom. """ + if OPTS.tech_name == "s8": + for name in ["vdd", "gnd"]: + for inst in [self.nand_inst, self.inv_inst]: + self.copy_layout_pin(inst, name) + else: + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, 0), + width=self.width) + self.add_layout_pin_rect_center(text="vdd", + layer=self.route_layer, + offset=vector(0.5 * self.width, self.height), + width=self.width) + + def add_wires(self): + # nand Z to inv A + z1_pin = self.nand_inst.get_pin("Z") + a2_pin = self.inv_inst.get_pin("A") + if OPTS.tech_name == "s8": + mid1_point = vector(a2_pin.cx(), z1_pin.cy()) + else: + mid1_point = vector(z1_pin.cx(), a2_pin.cy()) + self.add_path(self.route_layer, + [z1_pin.center(), mid1_point, a2_pin.center()]) + + def add_layout_pins(self): + pin = self.inv_inst.get_pin("Z") + self.add_layout_pin_rect_center(text="Z", + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + for pin_name in ["A", "B"]: + pin = self.nand_inst.get_pin(pin_name) + self.add_layout_pin_rect_center(text=pin_name, + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + def get_stage_efforts(self, external_cout, inp_is_rise=False): + """Get the stage efforts of the A or B -> Z path""" + stage_effort_list = [] + stage1_cout = self.inv.get_cin() + stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) + stage_effort_list.append(stage1) + last_stage_is_rise = stage1.is_rise + + stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise) + stage_effort_list.append(stage2) + + return stage_effort_list + + def get_cin(self): + """Return the relative input capacitance of a single input""" + return self.nand.get_cin() + diff --git a/compiler/custom/pand3_dec.py b/compiler/custom/pand3_dec.py new file mode 100644 index 00000000..3ec1eb45 --- /dev/null +++ b/compiler/custom/pand3_dec.py @@ -0,0 +1,149 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +from vector import vector +import pgate +from sram_factory import factory +from globals import OPTS + + +class pand3_dec(pgate.pgate): + """ + This is an AND with configurable drive strength. + """ + def __init__(self, name, size=1, height=None, add_wells=True): + debug.info(1, "Creating pand3_dec {}".format(name)) + self.add_comment("size: {}".format(size)) + + self.size = size + + pgate.pgate.__init__(self, name, height, add_wells) + + def create_netlist(self): + self.add_pins() + self.create_modules() + self.create_insts() + + def create_modules(self): + if OPTS.tech_name == "s8": + self.nand = factory.create(module_type="nand3_dec") + else: + self.nand = factory.create(module_type="nand3_dec", + height=self.height) + + self.inv = factory.create(module_type="inv_dec", + height=self.height, + size=self.size) + + self.add_mod(self.nand) + self.add_mod(self.inv) + + def create_layout(self): + self.width = self.nand.width + self.inv.width + + self.place_insts() + self.add_wires() + self.add_layout_pins() + self.route_supply_rails() + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + self.add_pin("A", "INPUT") + self.add_pin("B", "INPUT") + self.add_pin("C", "INPUT") + self.add_pin("Z", "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def create_insts(self): + self.nand_inst = self.add_inst(name="pand3_dec_nand", + mod=self.nand) + self.connect_inst(["A", "B", "C", "zb_int", "vdd", "gnd"]) + + self.inv_inst = self.add_inst(name="pand3_dec_inv", + mod=self.inv) + self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) + + def place_insts(self): + # Add NAND to the right + self.nand_inst.place(offset=vector(0, 0)) + + # Add INV to the right + self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0)) + + def route_supply_rails(self): + """ Add vdd/gnd rails to the top, (middle), and bottom. """ + if OPTS.tech_name == "s8": + for name in ["vdd", "gnd"]: + for inst in [self.nand_inst, self.inv_inst]: + self.copy_layout_pin(inst, name) + else: + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, 0), + width=self.width) + self.add_layout_pin_rect_center(text="vdd", + layer=self.route_layer, + offset=vector(0.5 * self.width, self.height), + width=self.width) + + def add_wires(self): + # nand Z to inv A + z1_pin = self.nand_inst.get_pin("Z") + a2_pin = self.inv_inst.get_pin("A") + if OPTS.tech_name == "s8": + mid1_point = vector(a2_pin.cx(), z1_pin.cy()) + else: + mid1_point = vector(z1_pin.cx(), a2_pin.cy()) + self.add_path(self.route_layer, + [z1_pin.center(), mid1_point, a2_pin.center()]) + + def add_layout_pins(self): + pin = self.inv_inst.get_pin("Z") + self.add_layout_pin_rect_center(text="Z", + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + for pin_name in ["A", "B", "C"]: + pin = self.nand_inst.get_pin(pin_name) + self.add_layout_pin_rect_center(text=pin_name, + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + def analytical_delay(self, corner, slew, load=0.0): + """ Calculate the analytical delay of DFF-> INV -> INV """ + nand_delay = self.nand.analytical_delay(corner, + slew=slew, + load=self.inv.input_load()) + inv_delay = self.inv.analytical_delay(corner, + slew=nand_delay.slew, + load=load) + return nand_delay + inv_delay + + def get_stage_efforts(self, external_cout, inp_is_rise=False): + """Get the stage efforts of the A or B -> Z path""" + stage_effort_list = [] + stage1_cout = self.inv.get_cin() + stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) + stage_effort_list.append(stage1) + last_stage_is_rise = stage1.is_rise + + stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise) + stage_effort_list.append(stage2) + + return stage_effort_list + + def get_cin(self): + """Return the relative input capacitance of a single input""" + return self.nand.get_cin() + diff --git a/compiler/custom/pand4_dec.py b/compiler/custom/pand4_dec.py new file mode 100644 index 00000000..ee65a349 --- /dev/null +++ b/compiler/custom/pand4_dec.py @@ -0,0 +1,149 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +from vector import vector +import pgate +from sram_factory import factory +from globals import OPTS + + +class pand4_dec(pgate.pgate): + """ + This is an AND with configurable drive strength. + """ + def __init__(self, name, size=1, height=None, add_wells=True): + debug.info(1, "Creating pand4_dec {}".format(name)) + self.add_comment("size: {}".format(size)) + + self.size = size + + pgate.pgate.__init__(self, name, height, add_wells) + + def create_netlist(self): + self.add_pins() + self.create_modules() + self.create_insts() + + def create_modules(self): + if OPTS.tech_name == "s8": + self.nand = factory.create(module_type="nand4_dec") + else: + self.nand = factory.create(module_type="nand4_dec", + height=self.height) + + self.inv = factory.create(module_type="inv_dec", + size=self.size) + + self.add_mod(self.nand) + self.add_mod(self.inv) + + def create_layout(self): + self.width = self.nand.width + self.inv.width + + self.place_insts() + self.add_wires() + self.add_layout_pins() + self.route_supply_rails() + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + self.add_pin("A", "INPUT") + self.add_pin("B", "INPUT") + self.add_pin("C", "INPUT") + self.add_pin("D", "INPUT") + self.add_pin("Z", "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def create_insts(self): + self.nand_inst = self.add_inst(name="pand4_dec_nand", + mod=self.nand) + self.connect_inst(["A", "B", "C", "D", "zb_int", "vdd", "gnd"]) + + self.inv_inst = self.add_inst(name="pand4_dec_inv", + mod=self.inv) + self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) + + def place_insts(self): + # Add NAND to the right + self.nand_inst.place(offset=vector(0, 0)) + + # Add INV to the right + self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0)) + + def route_supply_rails(self): + """ Add vdd/gnd rails to the top, (middle), and bottom. """ + if OPTS.tech_name == "s8": + for name in ["vdd", "gnd"]: + for inst in [self.nand_inst, self.inv_inst]: + self.copy_layout_pin(inst, name) + else: + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, 0), + width=self.width) + self.add_layout_pin_rect_center(text="vdd", + layer=self.route_layer, + offset=vector(0.5 * self.width, self.height), + width=self.width) + + def add_wires(self): + # nand Z to inv A + z1_pin = self.nand_inst.get_pin("Z") + a2_pin = self.inv_inst.get_pin("A") + if OPTS.tech_name == "s8": + mid1_point = vector(a2_pin.cx(), z1_pin.cy()) + else: + mid1_point = vector(z1_pin.cx(), a2_pin.cy()) + self.add_path(self.route_layer, + [z1_pin.center(), mid1_point, a2_pin.center()]) + + def add_layout_pins(self): + pin = self.inv_inst.get_pin("Z") + self.add_layout_pin_rect_center(text="Z", + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + for pin_name in ["A", "B", "C"]: + pin = self.nand_inst.get_pin(pin_name) + self.add_layout_pin_rect_center(text=pin_name, + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + def analytical_delay(self, corner, slew, load=0.0): + """ Calculate the analytical delay of DFF-> INV -> INV """ + nand_delay = self.nand.analytical_delay(corner, + slew=slew, + load=self.inv.input_load()) + inv_delay = self.inv.analytical_delay(corner, + slew=nand_delay.slew, + load=load) + return nand_delay + inv_delay + + def get_stage_efforts(self, external_cout, inp_is_rise=False): + """Get the stage efforts of the A or B -> Z path""" + stage_effort_list = [] + stage1_cout = self.inv.get_cin() + stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) + stage_effort_list.append(stage1) + last_stage_is_rise = stage1.is_rise + + stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise) + stage_effort_list.append(stage2) + + return stage_effort_list + + def get_cin(self): + """Return the relative input capacitance of a single input""" + return self.nand.get_cin() + diff --git a/compiler/modules/tri_gate.py b/compiler/custom/tri_gate.py similarity index 100% rename from compiler/modules/tri_gate.py rename to compiler/custom/tri_gate.py diff --git a/compiler/modules/write_driver.py b/compiler/custom/write_driver.py similarity index 100% rename from compiler/modules/write_driver.py rename to compiler/custom/write_driver.py diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index c1593932..3cb5d35c 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -12,7 +12,6 @@ from sram_factory import factory from vector import vector from globals import OPTS from errors import drc_error -from tech import cell_properties, layer class hierarchical_decoder(design.design): @@ -28,12 +27,8 @@ class hierarchical_decoder(design.design): self.pre3x8_inst = [] b = factory.create(module_type="bitcell") - try: - self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple - except AttributeError: - self.cell_multiple = 1 - self.cell_height = self.cell_multiple * b.height - + self.cell_height = b.height + self.num_outputs = num_outputs self.num_inputs = math.ceil(math.log(self.num_outputs, 2)) (self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) @@ -41,41 +36,6 @@ class hierarchical_decoder(design.design): self.create_netlist() if not OPTS.netlist_only: self.create_layout() - - def find_decoder_height(self): - """ - Dead code. This would dynamically determine the bitcell multiple, - but I just decided to hard code it in the tech file if it is not 1 - because a DRC tool would be required even to run in front-end mode. - """ - b = factory.create(module_type="bitcell") - - # Old behavior - if OPTS.netlist_only: - return (b.height, 1) - - # Search for the smallest multiple that works - cell_multiple = 1 - while cell_multiple < 5: - cell_height = cell_multiple * b.height - # debug.info(2,"Trying mult = {0} height={1}".format(cell_multiple, cell_height)) - try: - and3 = factory.create(module_type="pand3", - height=cell_height) - except drc_error: - # debug.info(1, "Incrementing decoder height by 1 bitcell height {}".format(b.height)) - pass - else: - (drc_errors, lvs_errors) = and3.DRC_LVS(force_check=True) - total_errors = drc_errors + lvs_errors - if total_errors == 0: - debug.info(1, "Decoder height is multiple of {} bitcells.".format(cell_multiple)) - return (cell_height, cell_multiple) - - cell_multiple += 1 - - else: - debug.error("Couldn't find a valid decoder height multiple.", -1) def create_netlist(self): self.add_modules() @@ -97,15 +57,22 @@ class hierarchical_decoder(design.design): self.DRC_LVS() def add_modules(self): - self.inv = factory.create(module_type="pinv", - height=self.cell_height) - self.add_mod(self.inv) - self.and2 = factory.create(module_type="pand2", - height=self.cell_height) + if OPTS.tech_name == "s8": + self.and2 = factory.create(module_type="pand2_dec") + else: + self.and2 = factory.create(module_type="pand2_dec", + height=self.cell_height) self.add_mod(self.and2) - self.and3 = factory.create(module_type="pand3", - height=self.cell_height) + if OPTS.tech_name == "s8": + self.and3 = factory.create(module_type="pand3_dec") + else: + self.and3 = factory.create(module_type="pand3_dec", + height=self.cell_height) + self.add_mod(self.and3) + # TBD + # self.and4 = factory.create(module_type="pand4_dec") + # self.add_mod(self.and4) self.add_decoders() @@ -176,56 +143,63 @@ class hierarchical_decoder(design.design): -1) # Calculates height and width of pre-decoder, - if self.no_of_pre3x8 > 0: + # FIXME: Update with 4x16 + if self.no_of_pre3x8 > 0 and self.no_of_pre2x4 > 0: + self.predecoder_width = max(self.pre3_8.width, self.pre2_4.width) + elif self.no_of_pre3x8 > 0: self.predecoder_width = self.pre3_8.width else: self.predecoder_width = self.pre2_4.width - - self.predecoder_height = self.pre2_4.height * self.no_of_pre2x4 + self.pre3_8.height * self.no_of_pre3x8 - # We may have more than one bitcell per decoder row - self.num_rows = math.ceil(self.num_outputs / self.cell_multiple) - # We will place this many final decoders per row - self.decoders_per_row = math.ceil(self.num_outputs / self.num_rows) - # We will need to use M2 and M3 in the vertical bus if we have multiple decoders per row - if self.decoders_per_row == 1: - self.decoder_bus_pitch = self.m2_pitch - elif self.decoders_per_row == 2: - self.decoder_bus_pitch = self.m3_pitch + # How much space between each predecoder + self.predecoder_spacing = self.and2.height + self.predecoder_height = self.pre2_4.height * self.no_of_pre2x4 + self.pre3_8.height * self.no_of_pre3x8 \ + + (self.no_of_pre2x4 + self.no_of_pre3x8 - 1) * self.predecoder_spacing + + # Inputs to cells are on input layer + # Outputs from cells are on output layer + if OPTS.tech_name == "s8": + self.bus_layer = "m1" + self.bus_directions = "nonpref" + self.bus_pitch = self.m1_pitch + self.bus_space = self.m2_space + self.input_layer = "m2" + self.output_layer = "li" + self.output_layer_pitch = self.li_pitch else: - debug.error("Insufficient layers for multi-bit height decoder.", -1) + self.bus_layer = "m2" + self.bus_directions = "pref" + self.bus_pitch = self.m2_pitch + self.bus_space = self.m2_space + # These two layers being the same requires a special jog + # to ensure to conflicts with the output layers + self.input_layer = "m1" + self.output_layer = "m3" + self.output_layer_pitch = self.m3_pitch + + # Two extra pitches between modules on left and right + self.internal_routing_width = self.total_number_of_predecoder_outputs * self.bus_pitch + self.bus_pitch + self.row_decoder_height = self.and2.height * self.num_outputs + # Extra bus space for supply contacts + self.input_routing_width = self.num_inputs * self.bus_pitch + self.bus_space # Calculates height and width of row-decoder - if (self.num_inputs == 4 or self.num_inputs == 5): - nand_width = self.and2.width - nand_inputs = 2 - else: - nand_width = self.and3.width - nand_inputs = 3 - self.internal_routing_width = self.decoder_bus_pitch * (self.total_number_of_predecoder_outputs + 1) - self.row_decoder_height = self.inv.height * self.num_rows - - decoder_input_wire_height = self.decoders_per_row * nand_inputs * self.m2_pitch - # print(self.decoders_per_row, nand_inputs) - # print(decoder_input_wire_height, self.cell_height) - if decoder_input_wire_height > self.cell_height: - debug.warning("Cannot fit multi-bit decoder routes per row.") - # debug.check(decoder_input_wire_height < self.cell_height, "Cannot fit multi-bit decoder routes per row.") - - self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch - # Calculates height and width of hierarchical decoder # Add extra pitch for good measure - self.height = max(self.predecoder_height, self.row_decoder_height) + self.m2_pitch - self.width = self.input_routing_width + self.predecoder_width \ + self.height = max(self.predecoder_height, self.row_decoder_height) + self.bus_space + if (self.num_inputs == 4 or self.num_inputs == 5): + self.nand_width = self.and2.width + else: + self.nand_width = self.and3.width + + self.width = self.input_routing_width \ + + self.predecoder_width \ + self.internal_routing_width \ - + self.decoders_per_row * nand_width + self.inv.width - + + self.nand_width \ + + self.m1_space + def route_inputs(self): """ Create input bus for the predecoders """ - # inputs should be as high as the decoders - input_height = self.no_of_pre2x4 * self.pre2_4.height + self.no_of_pre3x8 * self.pre3_8.height - # Find the left-most predecoder min_x = 0 if self.no_of_pre2x4 > 0: @@ -235,10 +209,10 @@ class hierarchical_decoder(design.design): input_offset=vector(min_x - self.input_routing_width, 0) input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)] - self.input_bus = self.create_vertical_pin_bus(layer="m2", + self.input_bus = self.create_vertical_pin_bus(layer=self.bus_layer, offset=input_offset, names=input_bus_names, - length=input_height) + length=self.predecoder_height) self.route_input_to_predecodes() @@ -253,9 +227,7 @@ class hierarchical_decoder(design.design): in_name = "in_{}".format(i) decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name) - # To prevent conflicts, we will offset each input connect so - # that it aligns with the vdd/gnd rails - decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * (self.inv.height + self.m1_pitch)) + decoder_offset = decoder_pin.center() input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1) self.route_input_bus(decoder_offset, input_offset) @@ -269,9 +241,7 @@ class hierarchical_decoder(design.design): in_name = "in_{}".format(i) decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name) - # To prevent conflicts, we will offset each input connect so - # that it aligns with the vdd/gnd rails - decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * (self.inv.height + self.m1_pitch)) + decoder_offset = decoder_pin.center() input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1) self.route_input_bus(decoder_offset, input_offset) @@ -282,13 +252,14 @@ class hierarchical_decoder(design.design): vertical M2 coordinate to the predecode inputs """ - self.add_via_stack_center(from_layer="m2", - to_layer="m3", + self.add_via_stack_center(from_layer=self.bus_layer, + to_layer=self.input_layer, offset=input_offset) - self.add_via_stack_center(from_layer="m2", - to_layer="m3", - offset=output_offset) - self.add_path("m3", [input_offset, output_offset]) + self.add_via_stack_center(from_layer=self.bus_layer, + to_layer=self.input_layer, + offset=output_offset, + directions=self.bus_directions) + self.add_path(self.input_layer, [input_offset, output_offset]) def add_pins(self): """ Add the module pins """ @@ -363,19 +334,19 @@ class hierarchical_decoder(design.design): if (self.num_inputs == 2): base = vector(-self.pre2_4.width, 0) else: - base= vector(-self.pre2_4.width, num * self.pre2_4.height) + base= vector(-self.pre2_4.width, num * (self.pre2_4.height + self.predecoder_spacing)) - self.pre2x4_inst[num].place(base - vector(2 * self.m2_pitch, 0)) + self.pre2x4_inst[num].place(base) def place_pre3x8(self, num): """ Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """ if (self.num_inputs == 3): offset = vector(-self.pre_3_8.width, 0) else: - height = self.no_of_pre2x4 * self.pre2_4.height + num * self.pre3_8.height + height = self.no_of_pre2x4 * (self.pre2_4.height + self.predecoder_spacing) + num * (self.pre3_8.height + self.predecoder_spacing) offset = vector(-self.pre3_8.width, height) - self.pre3x8_inst[num].place(offset - vector(2 * self.m2_pitch, 0)) + self.pre3x8_inst[num].place(offset) def create_row_decoder(self): """ Create the row-decoder by placing AND2/AND3 and Inverters @@ -431,7 +402,6 @@ class hierarchical_decoder(design.design): if (self.num_inputs >= 4): self.place_decoder_and_array() - def place_decoder_and_array(self): """ Add a column of AND gates for final decode. @@ -452,9 +422,7 @@ class hierarchical_decoder(design.design): Add a column of AND gates for the decoder above the predecoders. """ - for inst_index in range(self.num_outputs): - row = math.floor(inst_index / self.decoders_per_row) - dec = inst_index % self.decoders_per_row + for row in range(self.num_outputs): if ((row % 2) == 0): y_off = and_mod.height * row mirror = "R0" @@ -462,32 +430,16 @@ class hierarchical_decoder(design.design): y_off = and_mod.height * (row + 1) mirror = "MX" - x_off = self.internal_routing_width + dec * and_mod.width - self.and_inst[inst_index].place(offset=vector(x_off, y_off), - mirror=mirror) + x_off = self.internal_routing_width + self.and_inst[row].place(offset=vector(x_off, y_off), + mirror=mirror) def route_outputs(self): """ Add the pins. """ - max_xoffset = max(x.rx() for x in self.and_inst) - - for output_index in range(self.num_outputs): - row_remainder = (output_index % self.decoders_per_row) - - and_inst = self.and_inst[output_index] - z_pin = and_inst.get_pin("Z") - if row_remainder == 0 and self.decoders_per_row > 1: - layer = "m3" - self.add_via_stack_center(from_layer=z_pin.layer, - to_layer="m3", - offset=z_pin.center()) - else: - layer = z_pin.layer - - self.add_layout_pin_segment_center(text="decode_{0}".format(output_index), - layer=layer, - start=z_pin.center(), - end=vector(max_xoffset, z_pin.cy())) + for row in range(self.num_outputs): + and_inst = self.and_inst[row] + self.copy_layout_pin(and_inst, "Z", "decode_{0}".format(row)) def route_decoder_bus(self): """ @@ -498,9 +450,9 @@ class hierarchical_decoder(design.design): if (self.num_inputs >= 4): # This leaves an offset for the predecoder output jogs input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)] - self.predecode_bus = self.create_vertical_pin_bus(layer="m2", - pitch=self.decoder_bus_pitch, - offset=vector(0, 0), + self.predecode_bus = self.create_vertical_pin_bus(layer=self.bus_layer, + pitch=self.bus_pitch, + offset=vector(self.bus_pitch, 0), names=input_bus_names, length=self.height) @@ -518,8 +470,9 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(pre_num * 4 + i) out_name = "out_{}".format(i) pin = self.pre2x4_inst[pre_num].get_pin(out_name) - x_offset = self.pre2x4_inst[pre_num].rx() + self.m2_pitch - self.route_predecode_bus_inputs(predecode_name, pin, x_offset) + x_offset = self.pre2x4_inst[pre_num].rx() + self.output_layer_pitch + y_offset = self.pre2x4_inst[pre_num].by() + i * self.cell_height + self.route_predecode_bus_inputs(predecode_name, pin, x_offset, y_offset) # FIXME: convert to connect_bus for pre_num in range(self.no_of_pre3x8): @@ -527,8 +480,9 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(pre_num * 8 + i + self.no_of_pre2x4 * 4) out_name = "out_{}".format(i) pin = self.pre3x8_inst[pre_num].get_pin(out_name) - x_offset = self.pre3x8_inst[pre_num].rx() + self.m2_pitch - self.route_predecode_bus_inputs(predecode_name, pin, x_offset) + x_offset = self.pre3x8_inst[pre_num].rx() + self.output_layer_pitch + y_offset = self.pre3x8_inst[pre_num].by() + i * self.cell_height + self.route_predecode_bus_inputs(predecode_name, pin, x_offset, y_offset) def route_bus_to_decoder(self): """ @@ -542,12 +496,6 @@ class hierarchical_decoder(design.design): and the 128th AND3 is connected to [3,7,15] """ output_index = 0 - - if "li" in layer: - self.decoder_layers = [self.m1_stack, self.m2_stack[::-1]] - else: - self.decoder_layers = [self.m2_stack[::-1]] - debug.check(self.decoders_per_row <= len(self.decoder_layers), "Must have more layers for multi-height decoder.") if (self.num_inputs == 4 or self.num_inputs == 5): for index_B in self.predec_groups[1]: @@ -557,13 +505,11 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(index_A) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("A"), - output_index, - 0) + output_index) predecode_name = "predecode_{}".format(index_B) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("B"), - output_index, - 1) + output_index) output_index = output_index + 1 elif (self.num_inputs > 5): @@ -575,18 +521,15 @@ class hierarchical_decoder(design.design): predecode_name = "predecode_{}".format(index_A) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("A"), - output_index, - 0) + output_index) predecode_name = "predecode_{}".format(index_B) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("B"), - output_index, - 1) + output_index) predecode_name = "predecode_{}".format(index_C) self.route_predecode_bus_outputs(predecode_name, self.and_inst[output_index].get_pin("C"), - output_index, - 2) + output_index) output_index = output_index + 1 def route_vdd_gnd(self): @@ -594,90 +537,90 @@ class hierarchical_decoder(design.design): Add a pin for each row of vdd/gnd which are must-connects next level up. """ + + if OPTS.tech_name == "s8": + for n in ["vdd", "gnd"]: + pins = self.and_inst[0].get_pins(n) + for pin in pins: + self.add_rect(layer=pin.layer, + offset=pin.ll() + vector(0, self.bus_space), + width=pin.width(), + height=self.height - 2 * self.bus_space) - # The vias will be placed at the right of the cells. - xoffset = max(x.rx() for x in self.and_inst) - for num in range(0, self.num_outputs): - # Only add the power pin for the 1st in each row - if num % self.decoders_per_row: - continue - - for pin_name in ["vdd", "gnd"]: - # The nand and inv are the same height rows... - supply_pin = self.and_inst[num].get_pin(pin_name) - pin_pos = vector(xoffset, supply_pin.cy()) - self.add_path(supply_pin.layer, - [supply_pin.lc(), vector(xoffset, supply_pin.cy())]) - self.add_power_pin(name=pin_name, - loc=pin_pos, - start_layer=supply_pin.layer) - - # Copy the pins from the predecoders - for pre in self.pre2x4_inst + self.pre3x8_inst: - self.copy_layout_pin(pre, "vdd") - self.copy_layout_pin(pre, "gnd") + # This adds power vias at the top of each cell + # (except the last to keep them inside the boundary) + for i in self.and_inst[:-1]: + pins = i.get_pins(n) + for pin in pins: + self.add_power_pin(name=n, + loc=pin.uc(), + start_layer=pin.layer) + self.add_power_pin(name=n, + loc=pin.uc(), + start_layer=pin.layer) + + for i in self.pre2x4_inst + self.pre3x8_inst: + self.copy_layout_pin(i, n) + else: + # The vias will be placed at the right of the cells. + xoffset = max(x.rx() for x in self.and_inst) + 0.5 * self.m1_space + for row in range(0, self.num_outputs): + for pin_name in ["vdd", "gnd"]: + # The nand and inv are the same height rows... + supply_pin = self.and_inst[row].get_pin(pin_name) + pin_pos = vector(xoffset, supply_pin.cy()) + self.add_power_pin(name=pin_name, + loc=pin_pos, + start_layer=supply_pin.layer) + + # Copy the pins from the predecoders + for pre in self.pre2x4_inst + self.pre3x8_inst: + for pin_name in ["vdd", "gnd"]: + self.copy_layout_pin(pre, pin_name) - def route_predecode_bus_outputs(self, rail_name, pin, output_index, pin_index): + def route_predecode_bus_outputs(self, rail_name, pin, row): """ Connect the routing rail to the given metal1 pin using a routing track at the given y_offset """ - row_index = math.floor(output_index / self.decoders_per_row) - row_remainder = (output_index % self.decoders_per_row) - row_offset = row_index * self.and_inst[0].height - pin_pos = pin.center() - - # y_offset is the same for both the M2 and M4 routes so that the rail - # contacts align and don't cause problems - if pin_index == 0: - # Bottom pitch - y_offset = row_offset - elif pin_index == 1: - # One pitch from top - y_offset = row_offset + self.and_inst[0].height - self.m3_pitch - elif pin_index == 2: - # One pitch from bottom - y_offset = row_offset + self.m3_pitch - else: - debug.error("Invalid decoder pitch.") - - rail_pos = vector(self.predecode_bus[rail_name].x, y_offset) - mid_pos = vector(pin_pos.x, rail_pos.y) - self.add_wire(self.decoder_layers[row_remainder], [rail_pos, mid_pos, pin_pos]) + rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y) + self.add_path(self.input_layer, [rail_pos, pin_pos]) - self.add_via_stack_center(from_layer="m2", - to_layer=self.decoder_layers[row_remainder][0], - offset=rail_pos) + self.add_via_stack_center(from_layer=self.bus_layer, + to_layer=self.input_layer, + offset=rail_pos, + directions=self.bus_directions) self.add_via_stack_center(from_layer=pin.layer, - to_layer=self.decoder_layers[row_remainder][2], + to_layer=self.input_layer, offset=pin_pos, directions=("H", "H")) - def route_predecode_bus_inputs(self, rail_name, pin, x_offset): + def route_predecode_bus_inputs(self, rail_name, pin, x_offset, y_offset): """ Connect the routing rail to the given metal1 pin using a jog to the right of the cell at the given x_offset. """ # This routes the pin up to the rail, basically, to avoid conflicts. # It would be fixed with a channel router. - # pin_pos = pin.center() - # mid_point1 = vector(x_offset, pin_pos.y) - # mid_point2 = vector(x_offset, pin_pos.y + self.inv.height / 2) - # rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y) - # self.add_path("m1", [pin_pos, mid_point1, mid_point2, rail_pos]) + pin_pos = pin.rc() + mid_point1 = vector(x_offset, pin_pos.y) + mid_point2 = vector(x_offset, y_offset) + rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y) + self.add_path(self.output_layer, [pin_pos, mid_point1, mid_point2, rail_pos]) - pin_pos = pin.center() - rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y) - self.add_path("m1", [pin_pos, rail_pos]) + # pin_pos = pin.center() + # rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y) + # self.add_path(self.output_layer, [pin_pos, rail_pos]) self.add_via_stack_center(from_layer=pin.layer, - to_layer="m1", + to_layer=self.output_layer, offset=pin_pos) - self.add_via_stack_center(from_layer="m1", - to_layer="m2", - offset=rail_pos) + self.add_via_stack_center(from_layer=self.bus_layer, + to_layer=self.output_layer, + offset=rail_pos, + directions=self.bus_directions) def input_load(self): if self.determine_predecodes(self.num_inputs)[1]==0: diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 9a658546..8244028e 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -8,29 +8,24 @@ import debug import design import math -import contact from vector import vector from sram_factory import factory -from tech import cell_properties +from globals import OPTS class hierarchical_predecode(design.design): """ - Pre 2x4 and 3x8 decoder shared code. + Pre 2x4 and 3x8 and TBD 4x16 decoder shared code. """ def __init__(self, name, input_number, height=None): self.number_of_inputs = input_number if not height: b = factory.create(module_type="bitcell") - try: - self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple - except AttributeError: - self.cell_multiple = 1 - self.cell_height = self.cell_multiple * b.height + self.cell_height = b.height else: self.cell_height = height - + self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) design.design.__init__(self, name) @@ -44,34 +39,73 @@ class hierarchical_predecode(design.design): def add_modules(self): """ Add the INV and AND gate modules """ - - self.inv = factory.create(module_type="pinv", - height=self.cell_height) - self.add_mod(self.inv) - - self.add_and(self.number_of_inputs) - self.add_mod(self.and_mod) - def add_and(self, inputs): - """ Create the NAND for the predecode input stage """ - if inputs==2: - self.and_mod = factory.create(module_type="pand2", + # FIXME: Default parms are required for hard cells for now. + if self.number_of_inputs == 2: + self.and_mod = factory.create(module_type="pand2_dec", height=self.cell_height) - elif inputs==3: - self.and_mod = factory.create(module_type="pand3", + elif self.number_of_inputs == 3: + self.and_mod = factory.create(module_type="pand3_dec", + height=self.cell_height) + elif self.number_of_inputs == 4: + self.and_mod = factory.create(module_type="pand4_dec", height=self.cell_height) else: - debug.error("Invalid number of predecode inputs: {}".format(inputs), -1) - + debug.error("Invalid number of predecode inputs: {}".format(self.number_of_inputs), -1) + self.add_mod(self.and_mod) + + # This uses the pinv_dec parameterized cell + self.inv = factory.create(module_type="inv_dec", + height=self.cell_height, + size=1) + self.add_mod(self.inv) + + + def create_layout(self): + """ The general organization is from left to right: + 1) a set of M2 rails for input signals + 2) a set of inverters to invert input signals + 3) a set of M2 rails for the vdd, gnd, inverted inputs, inputs + 4) a set of AND gates for inversion + """ + self.setup_layout_constraints() + self.route_rails() + self.place_input_inverters() + self.place_and_array() + self.route() + self.add_boundary() + self.DRC_LVS() + def setup_layout_constraints(self): + # Inputs to cells are on input layer + # Outputs from cells are on output layer + if OPTS.tech_name == "s8": + self.bus_layer = "m1" + self.bus_directions = None + self.bus_pitch = self.m1_pitch + self.bus_space = 1.5 * self.m1_space + self.input_layer = "li" + self.output_layer = "m2" + self.output_layer_pitch = self.m2_pitch + else: + self.bus_layer = "m2" + self.bus_directions = None + self.bus_pitch = self.m2_pitch + self.bus_space = self.m2_space + # This requires a special jog to ensure to conflicts with the output layers + self.input_layer = "m1" + self.output_layer = "m1" + self.output_layer_pitch = self.m1_pitch + self.height = self.number_of_outputs * self.and_mod.height # x offset for input inverters - self.x_off_inv_1 = self.number_of_inputs * self.m2_pitch + self.m2_space + # +1 input for spacing for supply rail contacts + self.x_off_inv_1 = (self.number_of_inputs + 1) * self.bus_pitch + self.bus_pitch - # x offset to AND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches - self.x_off_and = self.x_off_inv_1 + self.inv.width + (2 * self.number_of_inputs + 2) * self.m2_pitch + # x offset to AND decoder includes the left rails, mid rails and inverters, plus two extra bus pitches + self.x_off_and = self.x_off_inv_1 + self.inv.width + (2 * self.number_of_inputs + 2) * self.bus_pitch # x offset to output inverters self.width = self.x_off_and + self.and_mod.width @@ -79,28 +113,30 @@ class hierarchical_predecode(design.design): def route_rails(self): """ Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """ input_names = ["in_{}".format(x) for x in range(self.number_of_inputs)] - offset = vector(0.5 * self.m2_width, self.m3_pitch) - self.input_rails = self.create_vertical_pin_bus(layer="m2", - offset=offset, - names=input_names, - length=self.height - 2 * self.m1_pitch) + # Offsets for the perimeter spacing to other modules + # This uses m3 pitch to leave space for power routes + offset = vector(self.bus_pitch, self.bus_pitch) + self.input_rails = self.create_vertical_bus(layer=self.bus_layer, + offset=offset, + names=input_names, + length=self.height - 2 * self.bus_pitch) invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)] non_invert_names = ["A_{}".format(x) for x in range(self.number_of_inputs)] decode_names = invert_names + non_invert_names - offset = vector(self.x_off_inv_1 + self.inv.width + 2 * self.m2_pitch, self.m3_pitch) - self.decode_rails = self.create_vertical_bus(layer="m2", + offset = vector(self.x_off_inv_1 + self.inv.width + self.bus_pitch, self.bus_pitch) + self.decode_rails = self.create_vertical_bus(layer=self.bus_layer, offset=offset, names=decode_names, - length=self.height - 2 * self.m1_pitch) + length=self.height - 2 * self.bus_pitch) def create_input_inverters(self): """ Create the input inverters to invert input signals for the decode stage. """ - self.in_inst = [] + self.inv_inst = [] for inv_num in range(self.number_of_inputs): name = "pre_inv_{0}".format(inv_num) - self.in_inst.append(self.add_inst(name=name, - mod=self.inv)) + self.inv_inst.append(self.add_inst(name=name, + mod=self.inv)) self.connect_inst(["in_{0}".format(inv_num), "inbar_{0}".format(inv_num), "vdd", "gnd"]) @@ -108,6 +144,7 @@ class hierarchical_predecode(design.design): def place_input_inverters(self): """ Place the input inverters to invert input signals for the decode stage. """ for inv_num in range(self.number_of_inputs): + if (inv_num % 2 == 0): y_off = inv_num * (self.inv.height) mirror = "R0" @@ -115,8 +152,8 @@ class hierarchical_predecode(design.design): y_off = (inv_num + 1) * (self.inv.height) mirror="MX" offset = vector(self.x_off_inv_1, y_off) - self.in_inst[inv_num].place(offset=offset, - mirror=mirror) + self.inv_inst[inv_num].place(offset=offset, + mirror=mirror) def create_and_array(self, connections): """ Create the AND stage for the decodes """ @@ -151,21 +188,30 @@ class hierarchical_predecode(design.design): def route_inputs_to_rails(self): """ Route the uninverted inputs to the second set of rails """ + + top_and_gate = self.and_inst[-1] for num in range(self.number_of_inputs): - # route one signal next to each vdd/gnd rail since this is - # typically where the p/n devices are and there are no - # pins in the and gates. - y_offset = (num + self.number_of_inputs) * self.inv.height + contact.m2_via.width + self.m2_space + if num == 0: + pin = top_and_gate.get_pin("A") + elif num == 1: + pin = top_and_gate.get_pin("B") + elif num == 2: + pin = top_and_gate.get_pin("C") + elif num == 3: + pin = top_and_gate.get_pin("D") + else: + debug.error("Too many inputs for predecoder.", -1) + y_offset = pin.cy() in_pin = "in_{}".format(num) a_pin = "A_{}".format(num) in_pos = vector(self.input_rails[in_pin].x, y_offset) a_pos = vector(self.decode_rails[a_pin].x, y_offset) - self.add_path("m1", [in_pos, a_pos]) - self.add_via_stack_center(from_layer="m1", - to_layer="m2", + self.add_path(self.input_layer, [in_pos, a_pos]) + self.add_via_stack_center(from_layer=self.input_layer, + to_layer=self.bus_layer, offset=[self.input_rails[in_pin].x, y_offset]) - self.add_via_stack_center(from_layer="m1", - to_layer="m2", + self.add_via_stack_center(from_layer=self.input_layer, + to_layer=self.bus_layer, offset=[self.decode_rails[a_pin].x, y_offset]) def route_output_and(self): @@ -188,31 +234,47 @@ class hierarchical_predecode(design.design): for inv_num in range(self.number_of_inputs): out_pin = "Abar_{}".format(inv_num) in_pin = "in_{}".format(inv_num) + + inv_out_pin = self.inv_inst[inv_num].get_pin("Z") + inv_out_pos = inv_out_pin.rc() # add output so that it is just below the vdd or gnd rail # since this is where the p/n devices are and there are no # pins in the and gates. - y_offset = (inv_num + 1) * self.inv.height - 3 * self.m1_space - inv_out_pin = self.in_inst[inv_num].get_pin("Z") - inv_out_pos = inv_out_pin.rc() - right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(), 0) - rail_pos = vector(self.decode_rails[out_pin].x, y_offset) - self.add_path(inv_out_pin.layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) + if OPTS.tech_name == "s8": + rail_pos = vector(self.decode_rails[out_pin].x, inv_out_pos.y) + self.add_path(self.output_layer, [inv_out_pos, rail_pos]) + else: + y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch + right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0) + rail_pos = vector(self.decode_rails[out_pin].x, y_offset) + self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) + self.add_via_stack_center(from_layer=inv_out_pin.layer, - to_layer="m2", - offset=rail_pos) + to_layer=self.output_layer, + offset=inv_out_pos) + self.add_via_stack_center(from_layer=self.output_layer, + to_layer=self.bus_layer, + offset=rail_pos, + directions=self.bus_directions) # route input - pin = self.in_inst[inv_num].get_pin("A") - inv_in_pos = pin.lc() + pin = self.inv_inst[inv_num].get_pin("A") + inv_in_pos = pin.center() in_pos = vector(self.input_rails[in_pin].x, inv_in_pos.y) - self.add_path("m1", [in_pos, inv_in_pos]) + self.add_path(self.input_layer, [in_pos, inv_in_pos]) self.add_via_stack_center(from_layer=pin.layer, - to_layer="m1", + to_layer=self.input_layer, offset=inv_in_pos) - self.add_via_stack_center(from_layer="m1", - to_layer="m2", - offset=in_pos) + via=self.add_via_stack_center(from_layer=self.input_layer, + to_layer=self.bus_layer, + offset=in_pos) + # Create the input pin at this location on the rail + self.add_layout_pin_rect_center(text=in_pin, + layer=self.bus_layer, + offset=in_pos, + height=via.mod.second_layer_height, + width=via.mod.second_layer_width) def route_and_to_rails(self): # This 2D array defines the connection mapping @@ -231,43 +293,67 @@ class hierarchical_predecode(design.design): pin = self.and_inst[k].get_pin(gate_pin) pin_pos = pin.center() rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y) - self.add_path("m1", [rail_pos, pin_pos]) - self.add_via_stack_center(from_layer="m1", - to_layer="m2", - offset=rail_pos) + self.add_path(self.input_layer, [rail_pos, pin_pos]) + self.add_via_stack_center(from_layer=self.input_layer, + to_layer=self.bus_layer, + offset=rail_pos, + directions=self.bus_directions) if gate_pin == "A": direction = None else: direction = ("H", "H") self.add_via_stack_center(from_layer=pin.layer, - to_layer="m1", + to_layer=self.input_layer, offset=pin_pos, directions=direction) def route_vdd_gnd(self): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ - # Find the x offsets for where the vias/pins should be placed - in_xoffset = self.in_inst[0].rx() + self.m1_space - # out_xoffset = self.and_inst[0].cx() + self.m1_space - for num in range(0, self.number_of_outputs): - # this will result in duplicate polygons for rails, but who cares - - # Route both supplies + # In s8, we use hand-made decoder cells with vertical power + if OPTS.tech_name == "s8": for n in ["vdd", "gnd"]: - and_pin = self.and_inst[num].get_pin(n) - supply_offset = and_pin.ll().scale(0, 1) - self.add_rect(layer=and_pin.layer, - offset=supply_offset, - width=self.and_inst[num].rx()) + # This makes a wire from top to bottom for both inv and and gates + for i in [self.inv_inst, self.and_inst]: + bot_pins = i[0].get_pins(n) + top_pins = i[-1].get_pins(n) + for (bot_pin, top_pin) in zip(bot_pins, top_pins): + self.add_rect(layer=bot_pin.layer, + offset=vector(bot_pin.lx(), self.bus_pitch), + width=bot_pin.width(), + height=top_pin.uy() - self.bus_pitch) + # This adds power vias at the top of each cell + # (except the last to keep them inside the boundary) + for i in self.inv_inst[:-1:2] + self.and_inst[:-1:2]: + pins = i.get_pins(n) + for pin in pins: + self.add_power_pin(name=n, + loc=pin.uc(), + start_layer=pin.layer) + self.add_power_pin(name=n, + loc=pin.uc(), + start_layer=pin.layer) + + # In other techs, we are using standard cell decoder cells with horizontal power + else: + for num in range(0, self.number_of_outputs): - # Add pins in two locations - for xoffset in [in_xoffset]: - pin_pos = vector(xoffset, and_pin.cy()) - self.add_power_pin(name=n, - loc=pin_pos, - start_layer=and_pin.layer) + # Route both supplies + for n in ["vdd", "gnd"]: + and_pins = self.and_inst[num].get_pins(n) + for and_pin in and_pins: + self.add_segment_center(layer=and_pin.layer, + start=vector(0, and_pin.cy()), + end=vector(self.width, and_pin.cy())) + + # Add pins in two locations + for xoffset in [self.inv_inst[0].lx() - self.bus_space, + self.and_inst[0].lx() - self.bus_space]: + pin_pos = vector(xoffset, and_pin.cy()) + self.add_power_pin(name=n, + loc=pin_pos, + start_layer=and_pin.layer) diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index b1aacc5a..9c7ddfa3 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -5,13 +5,10 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from tech import drc -import debug -import design -from vector import vector from hierarchical_predecode import hierarchical_predecode from globals import OPTS + class hierarchical_predecode2x4(hierarchical_predecode): """ Pre 2x4 decoder used in hierarchical_decoder. @@ -33,21 +30,6 @@ class hierarchical_predecode2x4(hierarchical_predecode): ["in_0", "in_1", "out_3", "vdd", "gnd"]] self.create_and_array(connections) - def create_layout(self): - """ The general organization is from left to right: - 1) a set of M2 rails for input signals - 2) a set of inverters to invert input signals - 3) a set of M2 rails for the vdd, gnd, inverted inputs, inputs - 4) a set of AND gates for inversion - """ - self.setup_layout_constraints() - self.route_rails() - self.place_input_inverters() - self.place_and_array() - self.route() - self.add_boundary() - self.DRC_LVS() - def get_and_input_line_combination(self): """ These are the decoder connections of the AND gates to the A,B pins """ combination = [["Abar_0", "Abar_1"], diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index 4f2294f1..e8c44e48 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -5,13 +5,10 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from tech import drc -import debug -import design -from vector import vector from hierarchical_predecode import hierarchical_predecode from globals import OPTS + class hierarchical_predecode3x8(hierarchical_predecode): """ Pre 3x8 decoder used in hierarchical_decoder. @@ -37,22 +34,6 @@ class hierarchical_predecode3x8(hierarchical_predecode): ["in_0", "in_1", "in_2", "out_7", "vdd", "gnd"]] self.create_and_array(connections) - def create_layout(self): - """ - The general organization is from left to right: - 1) a set of M2 rails for input signals - 2) a set of inverters to invert input signals - 3) a set of M2 rails for the vdd, gnd, inverted inputs, inputs - 4) a set of NAND gates for inversion - """ - self.setup_layout_constraints() - self.route_rails() - self.place_input_inverters() - self.place_and_array() - self.route() - self.add_boundary() - self.DRC_LVS() - def get_and_input_line_combination(self): """ These are the decoder connections of the NAND gates to the A,B,C pins """ combination = [["Abar_0", "Abar_1", "Abar_2"], diff --git a/compiler/modules/hierarchical_predecode4x16.py b/compiler/modules/hierarchical_predecode4x16.py new file mode 100644 index 00000000..4a258bfb --- /dev/null +++ b/compiler/modules/hierarchical_predecode4x16.py @@ -0,0 +1,64 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +from hierarchical_predecode import hierarchical_predecode +from globals import OPTS + + +class hierarchical_predecode4x16(hierarchical_predecode): + """ + Pre 4x16 decoder used in hierarchical_decoder. + """ + def __init__(self, name, height=None): + hierarchical_predecode.__init__(self, name, 4, height) + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + def create_netlist(self): + self.add_pins() + self.add_modules() + self.create_input_inverters() + connections=[["inbar_0", "inbar_1", "inbar_2", "inbar_3", "out_0", "vdd", "gnd"], + ["in_0", "inbar_1", "inbar_2", "inbar_3", "out_1", "vdd", "gnd"], + ["inbar_0", "in_1", "inbar_2", "inbar_3", "out_2", "vdd", "gnd"], + ["in_0", "in_1", "inbar_2", "inbar_3", "out_3", "vdd", "gnd"], + ["inbar_0", "inbar_1", "in_2", "inbar_3", "out_4", "vdd", "gnd"], + ["in_0", "inbar_1", "in_2", "inbar_3", "out_5", "vdd", "gnd"], + ["inbar_0", "in_1", "in_2", "inbar_3", "out_6", "vdd", "gnd"], + ["in_0", "in_1", "in_2", "inbar_3", "out_7", "vdd", "gnd"], + ["inbar_0", "inbar_1", "inbar_2", "in_3", "out_0", "vdd", "gnd"], + ["in_0", "inbar_1", "inbar_2", "in_3", "out_1", "vdd", "gnd"], + ["inbar_0", "in_1", "inbar_2", "in_3", "out_2", "vdd", "gnd"], + ["in_0", "in_1", "inbar_2", "in_3", "out_3", "vdd", "gnd"], + ["inbar_0", "inbar_1", "in_2", "in_3", "out_4", "vdd", "gnd"], + ["in_0", "inbar_1", "in_2", "in_3", "out_5", "vdd", "gnd"], + ["inbar_0", "in_1", "in_2", "in_3", "out_6", "vdd", "gnd"], + ["in_0", "in_1", "in_2", "in_3", "out_7", "vdd", "gnd"] ] + + self.create_and_array(connections) + + def get_and_input_line_combination(self): + """ These are the decoder connections of the AND gates to the A,B pins """ + combination = [["Abar_0", "Abar_1", "Abar_2", "Abar_3"], + ["A_0", "Abar_1", "Abar_2", "Abar_3"], + ["Abar_0", "A_1", "Abar_2", "Abar_3"], + ["A_0", "A_1", "Abar_2", "Abar_3"], + ["Abar_0", "Abar_1", "A_2" , "Abar_3"], + ["A_0", "Abar_1", "A_2" , "Abar_3"], + ["Abar_0", "A_1", "A_2" , "Abar_3"], + ["A_0", "A_1", "A_2" , "Abar_3"], + ["Abar_0", "Abar_1", "Abar_2", "A_3"], + ["A_0", "Abar_1", "Abar_2", "A_3"], + ["Abar_0", "A_1", "Abar_2", "A_3"], + ["A_0", "A_1", "Abar_2", "A_3"], + ["Abar_0", "Abar_1", "A_2", "A_3"], + ["A_0", "Abar_1", "A_2", "A_3"], + ["Abar_0", "A_1", "A_2", "A_3"], + ["A_0", "A_1", "A_2", "A_3"]] + return combination diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index a27894ae..6293a79d 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -8,7 +8,7 @@ import debug import design from sram_factory import factory from vector import vector - +from tech import layer from globals import OPTS @@ -41,6 +41,10 @@ class port_address(design.design): self.create_wordline_driver() def create_layout(self): + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" self.place_instances() self.route_layout() self.DRC_LVS() @@ -85,11 +89,19 @@ class port_address(design.design): def route_internal(self): for row in range(self.num_rows): # The pre/post is to access the pin from "outside" the cell to avoid DRCs - decoder_out_pos = self.row_decoder_inst.get_pin("decode_{}".format(row)).rc() - driver_in_pos = self.wordline_driver_inst.get_pin("in_{}".format(row)).lc() - mid1 = decoder_out_pos.scale(0.5, 1) + driver_in_pos.scale(0.5, 0) - mid2 = decoder_out_pos.scale(0.5, 0) + driver_in_pos.scale(0.5, 1) - self.add_path("m1", [decoder_out_pos, mid1, mid2, driver_in_pos]) + decoder_out_pin = self.row_decoder_inst.get_pin("decode_{}".format(row)) + decoder_out_pos = decoder_out_pin.rc() + driver_in_pin = self.wordline_driver_inst.get_pin("in_{}".format(row)) + driver_in_pos = driver_in_pin.lc() + self.add_zjog(self.route_layer, decoder_out_pos, driver_in_pos) + + self.add_via_stack_center(from_layer=decoder_out_pin.layer, + to_layer=self.route_layer, + offset=decoder_out_pos) + + self.add_via_stack_center(from_layer=driver_in_pin.layer, + to_layer=self.route_layer, + offset=driver_in_pos) def add_modules(self): @@ -97,7 +109,7 @@ class port_address(design.design): num_outputs=self.num_rows) self.add_mod(self.row_decoder) - self.wordline_driver = factory.create(module_type="wordline_driver", + self.wordline_driver = factory.create(module_type="wordline_driver_array", rows=self.num_rows, cols=self.num_cols) self.add_mod(self.wordline_driver) @@ -139,7 +151,6 @@ class port_address(design.design): row_decoder_offset = vector(0, 0) wordline_driver_offset = vector(self.row_decoder.width, 0) - self.wordline_driver_inst.place(wordline_driver_offset) self.row_decoder_inst.place(row_decoder_offset) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 91e20a45..8cc4e272 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -469,45 +469,37 @@ class port_data(design.design): bank_wmask_name = "bank_wmask_{}".format(bit) self.copy_layout_pin(self.write_mask_and_array_inst, wmask_in_name, bank_wmask_name) - def route_write_mask_and_array_to_write_driver(self,port): - """ Routing of wdriver_sel_{} between write mask AND array and write driver array. Adds layout pin for write - mask AND array output and via for write driver enable """ + def route_write_mask_and_array_to_write_driver(self, port): + """ + Routing of wdriver_sel_{} between write mask AND array and + write driver array. Adds layout pin for write + mask AND array output and via for write driver enable + """ - inst1 = self.write_mask_and_array_inst - inst2 = self.write_driver_array_inst + wmask_inst = self.write_mask_and_array_inst + wdriver_inst = self.write_driver_array_inst - loc = 0 for bit in range(self.num_wmasks): # Bring write mask AND array output pin to port data level - self.copy_layout_pin(inst1, "wmask_out_{0}".format(bit), "wdriver_sel_{0}".format(bit)) + self.copy_layout_pin(wmask_inst, "wmask_out_{0}".format(bit), "wdriver_sel_{0}".format(bit)) - wmask_out_pin = inst1.get_pin("wmask_out_{0}".format(bit)) - wdriver_en_pin = inst2.get_pin("en_{0}".format(bit)) + wmask_out_pin = wmask_inst.get_pin("wmask_out_{0}".format(bit)) + wdriver_en_pin = wdriver_inst.get_pin("en_{0}".format(bit)) + + wmask_pos = wmask_out_pin.center() + wdriver_pos = wdriver_en_pin.rc() - vector(self.m2_pitch, 0) + mid_pos = vector(wdriver_pos.x, wmask_pos.y) - # The metal2 wdriver_sel_{} wire must hit the en_{} pin after the closest bitline pin that's right of the - # the wdriver_sel_{} pin in the write driver AND array. - if bit == 0: - # When the write mask output pin is right of the bitline, the target is found - while (wmask_out_pin.lx() + self.m2_pitch > inst2.get_pin("data_{0}".format(loc)).rx()): - loc += 1 - length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch - debug.check(loc<=self.num_wmasks, - "Couldn't route the write mask select.") - else: - # Stride by the write size rather than finding the next pin to the right - loc += self.write_size - length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch - - beg_pos = wmask_out_pin.center() - middle_pos = vector(length, wmask_out_pin.cy()) - end_pos = vector(length, wdriver_en_pin.cy()) + # Add driver on mask output + self.add_via_center(layers=self.m1_stack, + offset=wmask_pos) # Add via for the write driver array's enable input self.add_via_center(layers=self.m1_stack, - offset=end_pos) + offset=wdriver_pos) # Route between write mask AND array and write driver array - self.add_wire(self.m1_stack, [beg_pos, middle_pos, end_pos]) + self.add_wire(self.m1_stack, [wmask_pos, mid_pos, wdriver_pos]) def route_column_mux_to_precharge_array(self, port): """ Routing of BL and BR between col mux and precharge array """ @@ -516,15 +508,12 @@ class port_data(design.design): if self.col_addr_size==0: return - inst1 = self.column_mux_array_inst - inst2 = self.precharge_array_inst + start_bit = 1 if self.port == 0 else 0 - insn2_start_bit = 1 if self.port == 0 else 0 - - self.connect_bitlines(inst1=inst1, - inst2=inst2, + self.connect_bitlines(inst1=self.column_mux_array_inst, + inst2=self.precharge_array_inst, num_bits=self.num_cols, - inst2_start_bit=insn2_start_bit) + inst2_start_bit=start_bit) def route_sense_amp_to_column_mux_or_precharge_array(self, port): """ Routing of BL and BR between sense_amp and column mux or precharge array """ diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver_array.py similarity index 50% rename from compiler/modules/wordline_driver.py rename to compiler/modules/wordline_driver_array.py index 55f5e707..e3d7c4f9 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver_array.py @@ -7,15 +7,12 @@ # import debug import design -import math -from tech import drc +from tech import drc, layer from vector import vector from sram_factory import factory from globals import OPTS -from tech import cell_properties - -class wordline_driver(design.design): +class wordline_driver_array(design.design): """ Creates a Wordline Driver Generates the wordline-driver to drive the bitcell @@ -26,21 +23,9 @@ class wordline_driver(design.design): debug.info(1, "Creating {0}".format(self.name)) self.add_comment("rows: {0} cols: {1}".format(rows, cols)) - self.bitcell_rows = rows - self.bitcell_cols = cols + self.rows = rows + self.cols = cols - b = factory.create(module_type="bitcell") - try: - self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple - except AttributeError: - self.cell_multiple = 1 - self.cell_height = self.cell_multiple * b.height - - # We may have more than one bitcell per decoder row - self.num_rows = math.ceil(self.bitcell_rows / self.cell_multiple) - # We will place this many final decoders per row - self.decoders_per_row = math.ceil(self.bitcell_rows / self.num_rows) - self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -51,7 +36,10 @@ class wordline_driver(design.design): self.create_drivers() def create_layout(self): - self.setup_layout_constants() + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" self.place_drivers() self.route_layout() self.route_vdd_gnd() @@ -61,104 +49,99 @@ class wordline_driver(design.design): def add_pins(self): # inputs to wordline_driver. - for i in range(self.bitcell_rows): + for i in range(self.rows): self.add_pin("in_{0}".format(i), "INPUT") # Outputs from wordline_driver. - for i in range(self.bitcell_rows): + for i in range(self.rows): self.add_pin("wl_{0}".format(i), "OUTPUT") self.add_pin("en", "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") def add_modules(self): - self.and2 = factory.create(module_type="pand2", - height=self.cell_height, - size=self.bitcell_cols) - self.add_mod(self.and2) + self.wl_driver = factory.create(module_type="wordline_driver", + size=self.cols) + self.add_mod(self.wl_driver) def route_vdd_gnd(self): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ - - # Find the x offsets for where the vias/pins should be placed - xoffset_list = [self.and_inst[0].lx()] - for num in range(self.bitcell_rows): - # this will result in duplicate polygons for rails, but who cares - - # use the inverter offset even though it will be the and's too - (gate_offset, y_dir) = self.get_gate_offset(0, - self.and2.height, - num) - # Route both supplies + if OPTS.tech_name == "s8": for name in ["vdd", "gnd"]: - supply_pin = self.and_inst[num].get_pin(name) - - # Add pins in two locations - for xoffset in xoffset_list: - pin_pos = vector(xoffset, supply_pin.cy()) - self.add_power_pin(name, pin_pos) + supply_pins = self.wld_inst[0].get_pins(name) + for pin in supply_pins: + self.add_layout_pin_segment_center(text=name, + layer=pin.layer, + start=pin.bc(), + end=vector(pin.cx(), self.height)) + else: + # Find the x offsets for where the vias/pins should be placed + xoffset_list = [self.wld_inst[0].rx()] + for num in range(self.rows): + # this will result in duplicate polygons for rails, but who cares + + # use the inverter offset even though it will be the and's too + (gate_offset, y_dir) = self.get_gate_offset(0, + self.wl_driver.height, + num) + # Route both supplies + for name in ["vdd", "gnd"]: + supply_pin = self.wld_inst[num].get_pin(name) + + # Add pins in two locations + for xoffset in xoffset_list: + pin_pos = vector(xoffset, supply_pin.cy()) + self.add_power_pin(name, pin_pos) def create_drivers(self): - self.and_inst = [] - for row in range(self.bitcell_rows): + self.wld_inst = [] + for row in range(self.rows): name_and = "wl_driver_and{}".format(row) # add and2 - self.and_inst.append(self.add_inst(name=name_and, - mod=self.and2)) + self.wld_inst.append(self.add_inst(name=name_and, + mod=self.wl_driver)) self.connect_inst(["in_{0}".format(row), "en", "wl_{0}".format(row), "vdd", "gnd"]) - def setup_layout_constants(self): - # We may have more than one bitcell per decoder row - self.driver_rows = math.ceil(self.bitcell_rows / self.cell_multiple) - # We will place this many final decoders per row - self.decoders_per_row = math.ceil(self.bitcell_rows / self.driver_rows) - def place_drivers(self): + for row in range(self.rows): + if (row % 2): + y_offset = self.wl_driver.height * (row + 1) + inst_mirror = "MX" + else: + y_offset = self.wl_driver.height * row + inst_mirror = "R0" + + and2_offset = [self.wl_driver.width, y_offset] + + # add and2 + self.wld_inst[row].place(offset=and2_offset, + mirror=inst_mirror) + # Leave a well gap to separate the bitcell array well from this well well_gap = 2 * drc("pwell_to_nwell") + drc("nwell_enclose_active") - - self.width = self.decoders_per_row * self.and2.width + well_gap - self.height = self.and2.height * self.driver_rows - - for inst_index in range(self.bitcell_rows): - row = math.floor(inst_index / self.decoders_per_row) - dec = inst_index % self.decoders_per_row - - if (row % 2): - y_offset = self.and2.height * (row + 1) - inst_mirror = "MX" - else: - y_offset = self.and2.height * row - inst_mirror = "R0" - - x_offset = dec * self.and2.width - and2_offset = [x_offset, y_offset] - - # add and2 - self.and_inst[inst_index].place(offset=and2_offset, - mirror=inst_mirror) + self.width = self.wl_driver.width + well_gap + self.height = self.wl_driver.height * self.rows def route_layout(self): """ Route all of the signals """ # Wordline enable connection - en_pin = self.and_inst[0].get_pin("B") + en_pin = self.wld_inst[0].get_pin("B") en_bottom_pos = vector(en_pin.lx(), 0) en_pin = self.add_layout_pin(text="en", layer="m2", offset=en_bottom_pos, height=self.height) - for inst_index in range(self.bitcell_rows): - and_inst = self.and_inst[inst_index] - row = math.floor(inst_index / self.decoders_per_row) + for row in range(self.rows): + and_inst = self.wld_inst[row] # Drop a via b_pin = and_inst.get_pin("B") @@ -167,18 +150,12 @@ class wordline_driver(design.design): offset=b_pin.center()) # connect the decoder input pin to and2 A - a_pin = and_inst.get_pin("A") - a_pos = a_pin.center() - # must under the clk line in M1 - self.add_layout_pin_segment_center(text="in_{0}".format(row), - layer="m1", - start=vector(0, a_pos.y), - end=a_pos) + self.copy_layout_pin(and_inst, "A", "in_{0}".format(row)) # output each WL on the right wl_offset = and_inst.get_pin("Z").rc() self.add_layout_pin_segment_center(text="wl_{0}".format(row), - layer="m1", + layer=self.route_layer, start=wl_offset, end=wl_offset - vector(self.m1_width, 0)) @@ -189,7 +166,7 @@ class wordline_driver(design.design): """ stage_effort_list = [] - stage1 = self.and2.get_stage_effort(external_cout, inp_is_rise) + stage1 = self.wl_driver.get_stage_effort(external_cout, inp_is_rise) stage_effort_list.append(stage1) return stage_effort_list @@ -200,5 +177,5 @@ class wordline_driver(design.design): the enable connections in the bank """ # The enable is connected to a and2 for every row. - total_cin = self.and2.get_cin() * self.rows + total_cin = self.wl_driver.get_cin() * self.rows return total_cin diff --git a/compiler/options.py b/compiler/options.py index d891ebd9..1c48d63d 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -134,6 +134,10 @@ class options(optparse.Values): dff_array = "dff_array" dff = "dff" dummy_bitcell = "dummy_bitcell" + inv_dec = "pinv" + nand2_dec = "pnand2" + nand3_dec = "pnand3" + nand4_dec = "pnand4" # Not available right now precharge_array = "precharge_array" ptx = "ptx" replica_bitcell = "replica_bitcell" diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 41189876..435ace1f 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -13,7 +13,7 @@ from sram_factory import factory class pand2(pgate.pgate): """ - This is a simple buffer used for driving loads. + This is an AND (or NAND) with configurable drive strength. """ def __init__(self, name, size=1, height=None, vertical=False, add_wells=True): debug.info(1, "Creating pand2 {}".format(name)) diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 266400c9..578a11c4 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -17,13 +17,13 @@ class pdriver(pgate.pgate): sized for driving a load. """ - def __init__(self, name, neg_polarity=False, fanout=0, size_list=None, height=None, add_wells=True): + def __init__(self, name, inverting=False, fanout=0, size_list=None, height=None, add_wells=True): debug.info(1, "creating pdriver {}".format(name)) self.stage_effort = 3 self.height = height - self.neg_polarity = neg_polarity + self.inverting = inverting self.size_list = size_list self.fanout = fanout @@ -31,8 +31,8 @@ class pdriver(pgate.pgate): debug.error("Either fanout or size list must be specified.", -1) if self.size_list and self.fanout != 0: debug.error("Cannot specify both size_list and fanout.", -1) - if self.size_list and self.neg_polarity: - debug.error("Cannot specify both size_list and neg_polarity.", -1) + if self.size_list and self.inverting: + debug.error("Cannot specify both size_list and inverting.", -1) # Creates the netlist and layout pgate.pgate.__init__(self, name, height, add_wells) @@ -47,9 +47,9 @@ class pdriver(pgate.pgate): int(round(self.fanout ** (1 / self.stage_effort)))) # Increase the number of stages if we need to fix polarity - if self.neg_polarity and (self.num_stages % 2 == 0): + if self.inverting and (self.num_stages % 2 == 0): self.num_stages += 1 - elif not self.neg_polarity and (self.num_stages % 2): + elif not self.inverting and (self.num_stages % 2): self.num_stages += 1 self.size_list = [] diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index cdb89fcb..a8c45641 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -44,7 +44,6 @@ class pgate(design.design): self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer)) # This is the space from a S/D contact to the supply rail - # Assume the contact starts at the active edge contact_to_vdd_rail_space = 0.5 * self.m1_width + self.m1_space # This is a poly-to-poly of a flipped cell poly_to_poly_gate_space = self.poly_extend_active + self.poly_space diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py new file mode 100644 index 00000000..efc21074 --- /dev/null +++ b/compiler/pgates/pinv_dec.py @@ -0,0 +1,217 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import contact +import pinv +import debug +from tech import drc, parameter +from vector import vector +from globals import OPTS +from sram_factory import factory + +if(OPTS.tech_name == "s8"): + from tech import nmos_bins, pmos_bins, accuracy_requirement + + +class pinv_dec(pinv.pinv): + """ + This is another version of pinv but with layout for the decoder. + Other stuff is the same (netlist, sizes, etc.) + """ + + def __init__(self, name, size=1, beta=parameter["beta"], height=None, add_wells=True): + + debug.info(2, + "creating pinv_dec structure {0} with size of {1}".format(name, + size)) + if not height: + b = factory.create(module_type="bitcell") + self.cell_height = b.height + else: + self.cell_height = height + + # Inputs to cells are on input layer + # Outputs from cells are on output layer + if OPTS.tech_name == "s8": + self.supply_layer = "m1" + else: + self.supply_layer = "m2" + + pinv.pinv.__init__(self, name, size, beta, self.cell_height, add_wells) + + def determine_tx_mults(self): + """ + Determines the number of fingers needed to achieve the size within + the height constraint. This may fail if the user has a tight height. + """ + + # This is always 1 tx, because we have horizontal transistors. + self.tx_mults = 1 + self.nmos_width = self.nmos_size * drc("minwidth_tx") + self.pmos_width = self.pmos_size * drc("minwidth_tx") + if OPTS.tech_name == "s8": + (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) + (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) + return + + # Over-ride the route input gate to call the horizontal version. + # Other top-level netlist and layout functions are not changed. + def route_input_gate(self, pmos_inst, nmos_inst, ypos, name, position="left", directions=None): + """ + Route the input gate to the left side of the cell for access. + Position is actually ignored and is left to be compatible with the pinv. + """ + + nmos_gate_pin = nmos_inst.get_pin("G") + pmos_gate_pin = pmos_inst.get_pin("G") + + # Check if the gates are aligned and give an error if they aren't! + if nmos_gate_pin.ll().y != pmos_gate_pin.ll().y: + self.gds_write("unaliged_gates.gds") + debug.check(nmos_gate_pin.ll().y == pmos_gate_pin.ll().y, + "Connecting unaligned gates not supported. See unaligned_gates.gds.") + + # Pick point on the left of NMOS and up to PMOS + nmos_gate_pos = nmos_gate_pin.rc() + pmos_gate_pos = pmos_gate_pin.lc() + self.add_path("poly", [nmos_gate_pos, pmos_gate_pos]) + + # Center is completely symmetric. + contact_width = contact.poly_contact.width + contact_offset = nmos_gate_pin.lc() \ + - vector(self.poly_extend_active + 0.5 * contact_width, 0) + via = self.add_via_stack_center(from_layer="poly", + to_layer=self.route_layer, + offset=contact_offset, + directions=directions) + self.add_path("poly", [contact_offset, nmos_gate_pin.lc()]) + + self.add_layout_pin_rect_center(text=name, + layer=self.route_layer, + offset=contact_offset, + width=via.mod.second_layer_width, + height=via.mod.second_layer_height) + + def determine_width(self): + self.width = self.pmos_inst.rx() + self.well_extend_active + + def extend_wells(self): + """ Extend bottom to top for each well. """ + + from tech import layer + if "pwell" in layer: + ll = self.nmos_inst.ll() - self.nmos_inst.mod.active_offset + ur = self.nmos_inst.ur() + self.nmos_inst.mod.active_offset + self.add_rect(layer="pwell", + offset=ll, + width=ur.x - ll.x, + height=self.height - ll.y) + + if "nwell" in layer: + ll = self.pmos_inst.ll() - self.pmos_inst.mod.active_offset + ur = self.pmos_inst.ur() + self.pmos_inst.mod.active_offset + self.add_rect(layer="nwell", + offset=ll - vector(self.nwell_enclose_active, 0), + width=ur.x - ll.x + self.nwell_enclose_active, + height=self.height - ll.y + 2 * self.nwell_enclose_active) + + def place_ptx(self): + """ + """ + + # offset so that the input contact is over from the left edge by poly spacing + x_offset = self.nmos.active_offset.y + contact.poly_contact.width + self.poly_space + # center the transistor in the y-dimension + y_offset = self.nmos.width + self.active_space + self.nmos_pos = vector(x_offset, y_offset) + self.nmos_inst.place(self.nmos_pos) + self.nmos_inst.place(self.nmos_pos, + rotate=270) + # place PMOS so it is half a poly spacing down from the top + xoffset = self.nmos_inst.height + 2 * self.poly_extend_active + 2 * self.well_extend_active + drc("pwell_to_nwell") + self.pmos_pos = self.nmos_pos + vector(xoffset, 0) + self.pmos_inst.place(self.pmos_pos, + rotate=270) + + # Output position will be in between the PMOS and NMOS drains + pmos_drain_pos = self.pmos_inst.get_pin("D").center() + nmos_drain_pos = self.nmos_inst.get_pin("D").center() + self.output_pos = vector(0.5 * (pmos_drain_pos.x + nmos_drain_pos.x), nmos_drain_pos.y) + + def route_outputs(self): + """ + Route the output (drains) together. + Optionally, routes output to edge. + """ + + # Get the drain pin + nmos_drain_pin = self.nmos_inst.get_pin("D") + + # Pick point at right most of NMOS and connect over to PMOS + nmos_drain_pos = nmos_drain_pin.lc() + right_side = vector(self.width, nmos_drain_pos.y) + + self.add_layout_pin_segment_center("Z", + self.route_layer, + nmos_drain_pos, + right_side) + + def add_well_contacts(self): + """ Add n/p well taps to the layout and connect to supplies """ + + source_pos = self.pmos_inst.get_pin("S").center() + contact_pos = vector(source_pos.x, self.height) + self.nwell_contact = self.add_via_center(layers=self.active_stack, + offset=contact_pos, + implant_type="n", + well_type="n") + self.add_via_stack_center(offset=contact_pos, + from_layer=self.active_stack[2], + to_layer=self.supply_layer) + + source_pos = self.nmos_inst.get_pin("S").center() + contact_pos = vector(source_pos.x, self.height) + self.pwell_contact= self.add_via_center(layers=self.active_stack, + offset=contact_pos, + implant_type="p", + well_type="p") + self.add_via_stack_center(offset=contact_pos, + from_layer=self.active_stack[2], + to_layer=self.supply_layer) + + def route_supply_rails(self): + pin = self.nmos_inst.get_pin("S") + source_pos = pin.center() + bottom_pos = source_pos.scale(1, 0) + top_pos = bottom_pos + vector(0, self.height) + self.add_layout_pin_segment_center("gnd", + self.supply_layer, + start=bottom_pos, + end=top_pos) + + pin = self.pmos_inst.get_pin("S") + source_pos = pin.center() + bottom_pos = source_pos.scale(1, 0) + top_pos = bottom_pos + vector(0, self.height) + self.add_layout_pin_segment_center("vdd", + self.supply_layer, + start=bottom_pos, + end=top_pos) + + def connect_rails(self): + """ Connect the nmos and pmos to its respective power rails """ + + source_pos = self.nmos_inst.get_pin("S").center() + self.add_via_stack_center(offset=source_pos, + from_layer=self.route_layer, + to_layer=self.supply_layer) + + source_pos = self.pmos_inst.get_pin("S").center() + self.add_via_stack_center(offset=source_pos, + from_layer=self.route_layer, + to_layer=self.supply_layer) + diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 85b3f0b6..6cbd7cca 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -212,7 +212,10 @@ class pnand3(pgate.pgate): pmos_drain_bottom = self.pmos1_inst.get_pin("D").by() self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space + # This is a more compact offset, but the bottom one works better in the decoders to "center" the pins + # in the height of the gates self.inputA_yoffset = self.output_yoffset - 0.5 * self.route_layer_width - self.route_layer_space + # self.inputA_yoffset = self.output_yoffset - self.m1_pitch self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index c584e70b..f6716a1f 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -386,10 +386,12 @@ class ptx(design.design): well_ll = center_pos - vector(0.5 * self.well_width, 0.5 * self.well_height) if well_name in layer: - self.add_rect(layer=well_name, - offset=well_ll, - width=self.well_width, - height=self.well_height) + well = self.add_rect(layer=well_name, + offset=well_ll, + width=self.well_width, + height=self.well_height) + setattr(self, well_name, well) + if "vtg" in layer: self.add_rect(layer="vtg", offset=well_ll, diff --git a/compiler/pgates/wordline_driver.py b/compiler/pgates/wordline_driver.py new file mode 100644 index 00000000..1b035e20 --- /dev/null +++ b/compiler/pgates/wordline_driver.py @@ -0,0 +1,155 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +from vector import vector +import design +from sram_factory import factory +from globals import OPTS +from tech import layer + + +class wordline_driver(design.design): + """ + This is an AND (or NAND) with configurable drive strength to drive the wordlines. + It is matched to the bitcell height. + """ + def __init__(self, name, size=1, height=None): + debug.info(1, "Creating wordline_driver {}".format(name)) + self.add_comment("size: {}".format(size)) + design.design.__init__(self, name) + + if height is None: + b = factory.create(module_type="bitcell") + self.height = b.height + else: + self.height = height + self.size = size + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + def create_netlist(self): + self.add_pins() + self.create_modules() + self.create_insts() + + def create_modules(self): + if OPTS.tech_name == "s8": + self.nand = factory.create(module_type="nand2_dec") + self.height = self.nand.height + else: + self.nand = factory.create(module_type="nand2_dec", + height=self.height) + + self.driver = factory.create(module_type="inv_dec", + size=self.size, + height=self.nand.height) + + self.add_mod(self.nand) + self.add_mod(self.driver) + + def create_layout(self): + self.width = self.nand.width + self.driver.width + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" + + self.place_insts() + self.route_wires() + self.add_layout_pins() + self.route_supply_rails() + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + self.add_pin("A", "INPUT") + self.add_pin("B", "INPUT") + self.add_pin("Z", "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def create_insts(self): + self.nand_inst = self.add_inst(name="wld_nand", + mod=self.nand) + self.connect_inst(["A", "B", "zb_int", "vdd", "gnd"]) + + self.driver_inst = self.add_inst(name="wl_driver", + mod=self.driver) + self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) + + def place_insts(self): + # Add NAND to the right + self.nand_inst.place(offset=vector(0, 0)) + + # Add INV to the right + self.driver_inst.place(offset=vector(self.nand_inst.rx(), 0)) + + def route_supply_rails(self): + """ Add vdd/gnd rails to the top, (middle), and bottom. """ + if OPTS.tech_name == "s8": + for name in ["vdd", "gnd"]: + for inst in [self.nand_inst, self.driver_inst]: + self.copy_layout_pin(inst, name) + else: + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, 0), + width=self.width) + + y_offset = self.height + self.add_layout_pin_rect_center(text="vdd", + layer=self.route_layer, + offset=vector(0.5 * self.width, y_offset), + width=self.width) + + def route_wires(self): + + # nand Z to inv A + z1_pin = self.nand_inst.get_pin("Z") + a2_pin = self.driver_inst.get_pin("A") + if OPTS.tech_name == "s8": + mid1_point = vector(a2_pin.cx(), z1_pin.cy()) + else: + mid1_point = vector(z1_pin.cx(), a2_pin.cy()) + self.add_path(self.route_layer, + [z1_pin.center(), mid1_point, a2_pin.center()]) + + def add_layout_pins(self): + pin = self.driver_inst.get_pin("Z") + self.add_layout_pin_rect_center(text="Z", + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + for pin_name in ["A", "B"]: + pin = self.nand_inst.get_pin(pin_name) + self.add_layout_pin_rect_center(text=pin_name, + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + def get_stage_efforts(self, external_cout, inp_is_rise=False): + """Get the stage efforts of the A or B -> Z path""" + stage_effort_list = [] + stage1_cout = self.driver.get_cin() + stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) + stage_effort_list.append(stage1) + + stage2 = self.driver.get_stage_effort(external_cout, stage1.is_rise) + stage_effort_list.append(stage2) + + return stage_effort_list + + def get_cin(self): + """Return the relative input capacitance of a single input""" + return self.nand.get_cin() + diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 110dbe15..df6b9d99 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -77,7 +77,9 @@ class sram_factory: """ tech_module_type, tm_overridden = self.get_techmodule_type(module_type) user_module_type, um_overridden = self.get_usermodule_type(module_type) - + #print(module_type, tech_module_type, tm_overridden) + #print(module_type, user_module_type, um_overridden) + # overridden user modules have priority if um_overridden: real_module_type = user_module_type diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 0acc8926..ed15770d 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -35,7 +35,7 @@ class library_lvs_test(openram_test): debug.error("Missing GDS file {}".format(gds_name)) if not os.path.isfile(sp_name): lvs_errors += 1 - debug.error("Missing SPICE file {}".format(gds_name)) + debug.error("Missing SPICE file {}".format(sp_name)) drc_errors += verify.run_drc(name, gds_name) lvs_errors += verify.run_lvs(f, gds_name, sp_name) diff --git a/compiler/tests/04_pand2_dec_test.py b/compiler/tests/04_pand2_dec_test.py new file mode 100755 index 00000000..92b80203 --- /dev/null +++ b/compiler/tests/04_pand2_dec_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class pand2_dec_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + global verify + import verify + + import pand2_dec + + debug.info(2, "Testing pand2 gate 4x") + a = pand2_dec.pand2_dec(name="pand2x4", size=4) + self.local_check(a) + + globals.end_openram() + +# instantiate a copdsay of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pand3_dec_test.py b/compiler/tests/04_pand3_dec_test.py new file mode 100755 index 00000000..78e576ed --- /dev/null +++ b/compiler/tests/04_pand3_dec_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class pand3_dec_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + global verify + import verify + + import pand3_dec + + debug.info(2, "Testing pand3 gate 4x") + a = pand3_dec.pand3_dec(name="pand3x4", size=4) + self.local_check(a) + + globals.end_openram() + +# instantiate a copdsay of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pand4_dec_test.py b/compiler/tests/04_pand4_dec_test.py new file mode 100755 index 00000000..78e576ed --- /dev/null +++ b/compiler/tests/04_pand4_dec_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class pand3_dec_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + global verify + import verify + + import pand3_dec + + debug.info(2, "Testing pand3 gate 4x") + a = pand3_dec.pand3_dec(name="pand3x4", size=4) + self.local_check(a) + + globals.end_openram() + +# instantiate a copdsay of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index e65b6fad..41af86f6 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -32,13 +32,13 @@ class pdriver_test(openram_test): c = factory.create(module_type="pdriver", fanout = 50) self.local_check(c) - d = factory.create(module_type="pdriver", fanout = 50, neg_polarity = True) + d = factory.create(module_type="pdriver", fanout = 50, inverting = True) self.local_check(d) e = factory.create(module_type="pdriver", fanout = 64) self.local_check(e) - f = factory.create(module_type="pdriver", fanout = 64, neg_polarity = True) + f = factory.create(module_type="pdriver", fanout = 64, inverting = True) self.local_check(f) globals.end_openram() diff --git a/compiler/tests/04_pinv_dec_1x_test.py b/compiler/tests/04_pinv_dec_1x_test.py new file mode 100755 index 00000000..8876ab58 --- /dev/null +++ b/compiler/tests/04_pinv_dec_1x_test.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class pinv_dec_1x_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + debug.info(2, "Checking 1x size decoder inverter") + tx = factory.create(module_type="pinv_dec", size=1) + self.local_check(tx) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/04_wordline_driver_test.py similarity index 93% rename from compiler/tests/08_wordline_driver_test.py rename to compiler/tests/04_wordline_driver_test.py index 8a18a59d..ada65db7 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/04_wordline_driver_test.py @@ -25,7 +25,7 @@ class wordline_driver_test(openram_test): # check wordline driver for single port debug.info(2, "Checking driver") - tx = factory.create(module_type="wordline_driver", rows=8, cols=32) + tx = factory.create(module_type="wordline_driver") self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index 07d995f9..7d155b01 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -21,11 +21,17 @@ class hierarchical_decoder_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) + # Use the 2 port cell since it is usually bigger/easier + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + # Checks 2x4 and 2-input NAND decoder debug.info(1, "Testing 16 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=16) self.local_check(a) - + # Checks 2x4 and 2-input NAND decoder with non-power-of-two debug.info(1, "Testing 17 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=17) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index ebb06330..94fd4838 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -21,7 +21,12 @@ class hierarchical_predecode2x4_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - # checking hierarchical precode 2x4 for single port + # Use the 2 port cell since it is usually bigger/easier + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + debug.info(1, "Testing sample for hierarchy_predecode2x4") a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index 63acc416..33f94d9d 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -21,7 +21,12 @@ class hierarchical_predecode3x8_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - # checking hierarchical precode 3x8 for single port + # Use the 2 port cell since it is usually bigger/easier + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + debug.info(1, "Testing sample for hierarchy_predecode3x8") a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) diff --git a/compiler/tests/06_hierarchical_predecode4x16_test.py b/compiler/tests/06_hierarchical_predecode4x16_test.py new file mode 100755 index 00000000..b4ebda38 --- /dev/null +++ b/compiler/tests/06_hierarchical_predecode4x16_test.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +@unittest.skip("SKIPPING hierarchical_predecode4x16_test") +class hierarchical_predecode4x16_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # Use the 2 port cell since it is usually bigger/easier + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + debug.info(1, "Testing sample for hierarchy_predecode4x16") + a = factory.create(module_type="hierarchical_predecode4x16") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_wordline_driver_pbitcell_test.py b/compiler/tests/08_wordline_driver_array_pbitcell_test.py similarity index 87% rename from compiler/tests/08_wordline_driver_pbitcell_test.py rename to compiler/tests/08_wordline_driver_array_pbitcell_test.py index 3dd5933d..267aaddf 100755 --- a/compiler/tests/08_wordline_driver_pbitcell_test.py +++ b/compiler/tests/08_wordline_driver_array_pbitcell_test.py @@ -15,9 +15,8 @@ from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 04_driver_test") -class wordline_driver_pbitcell_test(openram_test): +class wordline_driver_array_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -31,7 +30,7 @@ class wordline_driver_pbitcell_test(openram_test): factory.reset() debug.info(2, "Checking driver (multi-port case)") - tx = factory.create(module_type="wordline_driver", rows=8, cols=64) + tx = factory.create(module_type="wordline_driver_array", rows=8, cols=64) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/08_wordline_driver_array_test.py b/compiler/tests/08_wordline_driver_array_test.py new file mode 100755 index 00000000..3491cc4f --- /dev/null +++ b/compiler/tests/08_wordline_driver_array_test.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class wordline_driver_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check wordline driver for single port + debug.info(2, "Checking driver") + tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32) + self.local_check(tx) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_1rw_1r_test.py b/compiler/tests/18_port_data_1rw_1r_test.py index 6201de6a..e9e282a5 100755 --- a/compiler/tests/18_port_data_1rw_1r_test.py +++ b/compiler/tests/18_port_data_1rw_1r_test.py @@ -20,10 +20,10 @@ class port_data_1rw_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1w_1r" - OPTS.num_rw_ports = 0 + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 + OPTS.num_w_ports = 0 c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index 38a847a9..6cff481b 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -25,28 +25,28 @@ class single_bank_test(openram_test): c = sram_config(word_size=4, num_words=16) - # c.words_per_row=1 - # factory.reset() - # c.recompute_sizes() - # debug.info(1, "No column mux") - # a = factory.create("bank", sram_config=c) - # self.local_check(a) + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) - # c.num_words=32 - # c.words_per_row=2 - # factory.reset() - # c.recompute_sizes() - # debug.info(1, "Two way column mux") - # a = factory.create("bank", sram_config=c) - # self.local_check(a) + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) - # c.num_words=64 - # c.words_per_row=4 - # factory.reset() - # c.recompute_sizes() - # debug.info(1, "Four way column mux") - # a = factory.create("bank", sram_config=c) - # self.local_check(a) + c.num_words=64 + c.words_per_row=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) c.word_size=2 c.num_words=128 diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 99d534d0..4cae1a9c 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -60,6 +60,7 @@ class openram_test(unittest.TestCase): #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) debug.warning("DRC failed but LVS passed: {}".format(a.name)) + #self.fail("DRC failed but LVS passed: {}".format(a.name)) elif drc_result != 0: #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) From b00163e4e1e22883ed910826ed7ed5e880cc9088 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Fri, 29 May 2020 13:50:34 -0700 Subject: [PATCH 321/521] lvs fix for regression tests --- compiler/modules/replica_column.py | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 2e3d207e..4ea1b7df 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -114,7 +114,6 @@ class replica_column(design.design): mod=self.dummy_cell) self.connect_inst(self.get_bitcell_pins(0, row)) - def place_instances(self): from tech import cell_properties # Flip the mirrors if we have an odd number of replica+dummy rows at the bottom @@ -149,20 +148,30 @@ class replica_column(design.design): self.cell_inst[row].place(offset=offset, mirror=dir_key) - - def add_layout_pins(self): """ Add the layout pins """ for bl_name in self.cell.get_all_bitline_names(): - bl_pin = self.cell_inst[1].get_pin(bl_name) + bl_pin = self.cell_inst[0].get_pin(bl_name) self.add_layout_pin(text=bl_name, layer=bl_pin.layer, offset=bl_pin.ll(), width=bl_pin.width(), height=self.height) - for row in range(1, self.total_size - 1): + try: + end_caps_enabled = cell_properties.bitcell.end_caps + except AttributeError: + end_caps_enabled = False + + if end_caps_enabled: + row_range_max = self.total_size - 1 + row_range_min = 1 + else: + row_range_max = self.total_size + row_range_min = 0 + + for row in range(row_range_min, row_range_max): for wl_name in self.cell.get_all_wl_names(): wl_pin = self.cell_inst[row].get_pin(wl_name) self.add_layout_pin(text="{0}_{1}".format(wl_name,row), @@ -172,7 +181,7 @@ class replica_column(design.design): height=wl_pin.height()) # For every second row and column, add a via for gnd and vdd - for row in range(1, self.total_size - 1): + for row in range(row_range_min, row_range_max): inst = self.cell_inst[row] for pin_name in ["vdd", "gnd"]: self.copy_layout_pin(inst, pin_name) From 82dc937768e2e88fae741600d8c604348fd7093a Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 29 May 2020 16:53:47 -0700 Subject: [PATCH 322/521] Add missing vias by using via stack function --- compiler/modules/port_data.py | 74 ++++++++++++++++----------------- compiler/pgates/precharge.py | 77 +++++++++++++---------------------- 2 files changed, 65 insertions(+), 86 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 8cc4e272..44bb8ed8 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -534,11 +534,14 @@ class port_data(design.design): else: start_bit=0 - self.channel_route_bitlines(inst1=inst1, - inst1_bls_template=inst1_bls_templ, - inst2=inst2, - num_bits=self.word_size, - inst1_start_bit=start_bit) + # This could be a channel route, but in some techs the bitlines + # are too close together. + print("SA to precharge") + self.connect_bitlines(inst1=inst1, + inst1_bls_template=inst1_bls_templ, + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) def route_write_driver_to_column_mux_or_precharge_array(self, port): """ Routing of BL and BR between sense_amp and column mux or precharge array """ @@ -558,10 +561,13 @@ class port_data(design.design): else: start_bit=0 - self.channel_route_bitlines(inst1=inst1, inst2=inst2, - num_bits=self.word_size, - inst1_bls_template=inst1_bls_templ, - inst1_start_bit=start_bit) + # This could be a channel route, but in some techs the bitlines + # are too close together. + print("WD to precharge") + self.connect_bitlines(inst1=inst1, inst2=inst2, + num_bits=self.word_size, + inst1_bls_template=inst1_bls_templ, + inst1_start_bit=start_bit) def route_write_driver_to_sense_amp(self, port): """ Routing of BL and BR between write driver and sense amp """ @@ -569,11 +575,12 @@ class port_data(design.design): inst1 = self.write_driver_array_inst inst2 = self.sense_amp_array_inst - # These should be pitch matched in the cell library, - # but just in case, do a channel route. - self.channel_route_bitlines(inst1=inst1, - inst2=inst2, - num_bits=self.word_size) + # This could be a channel route, but in some techs the bitlines + # are too close together. + print("WD to SA") + self.connect_bitlines(inst1=inst1, + inst2=inst2, + num_bits=self.word_size) def route_bitline_pins(self): """ Add the bitline pins for the given port """ @@ -676,10 +683,9 @@ class port_data(design.design): Route the bl and br of two modules using the channel router. """ - bot_inst_group, top_inst_group = self._group_bitline_instances( - inst1, inst2, num_bits, - inst1_bls_template, inst1_start_bit, - inst2_bls_template, inst2_start_bit) + bot_inst_group, top_inst_group = self._group_bitline_instances(inst1, inst2, num_bits, + inst1_bls_template, inst1_start_bit, + inst2_bls_template, inst2_start_bit) # Channel route each mux separately since we don't minimize the number # of tracks in teh channel router yet. If we did, we could route all the bits at once! @@ -688,13 +694,8 @@ class port_data(design.design): bottom_names = self._get_bitline_pins(bot_inst_group, bit) top_names = self._get_bitline_pins(top_inst_group, bit) - if bottom_names[0].layer == "m2": - bitline_dirs = ("H", "V") - elif bottom_names[0].layer == "m1": - bitline_dirs = ("V", "H") - route_map = list(zip(bottom_names, top_names)) - self.create_horizontal_channel_route(route_map, offset, self.m1_stack, bitline_dirs) + self.create_horizontal_channel_route(route_map, offset, self.m1_stack) def connect_bitlines(self, inst1, inst2, num_bits, inst1_bls_template="{inst}_{bit}", @@ -707,26 +708,23 @@ class port_data(design.design): in the middle between the two modules (if needed). """ - bot_inst_group, top_inst_group = self._group_bitline_instances( - inst1, inst2, num_bits, - inst1_bls_template, inst1_start_bit, - inst2_bls_template, inst2_start_bit) + bot_inst_group, top_inst_group = self._group_bitline_instances(inst1, inst2, num_bits, + inst1_bls_template, inst1_start_bit, + inst2_bls_template, inst2_start_bit) for col in range(num_bits): + print(col) bot_bl_pin, bot_br_pin = self._get_bitline_pins(bot_inst_group, col) top_bl_pin, top_br_pin = self._get_bitline_pins(top_inst_group, col) bot_bl, bot_br = bot_bl_pin.uc(), bot_br_pin.uc() top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc() - - yoffset = 0.5 * (top_bl.y + bot_bl.y) - self.add_path("m2", [bot_bl, - vector(bot_bl.x, yoffset), - vector(top_bl.x, yoffset), - top_bl]) - self.add_path("m2", [bot_br, - vector(bot_br.x, yoffset), - vector(top_br.x, yoffset), - top_br]) + + print("BL", bot_bl, top_bl) + print(bot_bl_pin, top_bl_pin) + print("BR", bot_br, top_br) + print(bot_br_pin, top_br_pin) + self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V") + self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V") def graph_exclude_precharge(self): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index d47e445f..ae314452 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -105,21 +105,19 @@ class precharge(design.design): # center of vdd rail pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y) - self.add_path("m1", [pmos_pin.uc(), pmos_vdd_pos]) + self.add_path(self.bitline_layer, [pmos_pin.center(), pmos_vdd_pos]) - # if enable is not on M1, the supply can be - if self.en_layer != "m1": - self.add_via_center(layers=self.m1_stack, - offset=pmos_vdd_pos) - + self.add_via_stack_center(from_layer=self.bitline_layer, + to_layer=self.en_layer, + offset=pmos_vdd_pos) self.add_power_pin("vdd", self.well_contact_pos, directions=("V", "V")) - - # Hack for li layers - if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=self.well_contact_pos) + + self.add_via_stack_center(from_layer=pmos_pin.layer, + to_layer=self.bitline_layer, + offset=pmos_pin.center(), + directions=("V", "V")) def create_ptx(self): """ @@ -199,14 +197,9 @@ class precharge(design.design): # midway in the 4 M2 tracks offset = self.lower_pmos_inst.get_pin("G").ul() \ + vector(0, 0.5 * self.m2_pitch) - self.add_via_center(layers=self.poly_stack, - offset=offset) - if self.en_layer == "m2": - self.add_via_center(layers=self.m1_stack, - offset=offset) - if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=offset) + self.add_via_stack_center(from_layer="poly", + to_layer=self.en_layer, + offset=offset) # adds the en rail on metal1 self.add_layout_pin_segment_center(text="en_bar", @@ -225,13 +218,13 @@ class precharge(design.design): self.nwell_extend_active self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) + \ vector(0, offset_height) - self.add_via_center(layers=self.active_stack, - offset=self.well_contact_pos, - implant_type="n", - well_type="n") - if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=self.well_contact_pos) + self.well_contact = self.add_via_center(layers=self.active_stack, + offset=self.well_contact_pos, + implant_type="n", + well_type="n") + self.add_via_stack_center(from_layer=self.active_stack[2], + to_layer=self.bitline_layer, + offset=self.well_contact_pos) self.height = self.well_contact_pos.y + contact.active_contact.height + self.m1_space @@ -288,31 +281,19 @@ class precharge(design.design): Adds contacts/via from metal1 to metal2 for bit-lines """ - # No contacts needed if M1 - if self.bitline_layer == "m1": - return - # BL - lower_pin = self.lower_pmos_inst.get_pin("S") - self.lower_via = self.add_via_center(layers=self.m1_stack, - offset=lower_pin.center(), - directions=("V", "V")) + for lower_pin in [self.lower_pmos_inst.get_pin("S"), self.lower_pmos_inst.get_pin("D")]: + self.add_via_stack_center(from_layer=lower_pin.layer, + to_layer=self.bitline_layer, + offset=lower_pin.center(), + directions=("V", "V")) - lower_pin = self.lower_pmos_inst.get_pin("D") - self.lower_via = self.add_via_center(layers=self.m1_stack, - offset=lower_pin.center(), - directions=("V", "V")) - # BR - upper_pin = self.upper_pmos1_inst.get_pin("S") - self.upper_via2 = self.add_via_center(layers=self.m1_stack, - offset=upper_pin.center(), - directions=("V", "V")) - - upper_pin = self.upper_pmos2_inst.get_pin("D") - self.upper_via2 = self.add_via_center(layers=self.m1_stack, - offset=upper_pin.center(), - directions=("V", "V")) + for upper_pin in [self.upper_pmos1_inst.get_pin("S"), self.upper_pmos2_inst.get_pin("D")]: + self.add_via_stack_center(from_layer=upper_pin.layer, + to_layer=self.bitline_layer, + offset=upper_pin.center(), + directions=("V", "V")) def connect_pmos(self, pmos_pin, bit_xoffset): """ From 496a24389c4e95f780a71a1f73959366a9744f4d Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 29 May 2020 16:57:47 -0700 Subject: [PATCH 323/521] Remove prints --- compiler/modules/port_data.py | 8 -------- 1 file changed, 8 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 44bb8ed8..d544b6be 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -536,7 +536,6 @@ class port_data(design.design): # This could be a channel route, but in some techs the bitlines # are too close together. - print("SA to precharge") self.connect_bitlines(inst1=inst1, inst1_bls_template=inst1_bls_templ, inst2=inst2, @@ -563,7 +562,6 @@ class port_data(design.design): # This could be a channel route, but in some techs the bitlines # are too close together. - print("WD to precharge") self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size, inst1_bls_template=inst1_bls_templ, @@ -577,7 +575,6 @@ class port_data(design.design): # This could be a channel route, but in some techs the bitlines # are too close together. - print("WD to SA") self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size) @@ -713,16 +710,11 @@ class port_data(design.design): inst2_bls_template, inst2_start_bit) for col in range(num_bits): - print(col) bot_bl_pin, bot_br_pin = self._get_bitline_pins(bot_inst_group, col) top_bl_pin, top_br_pin = self._get_bitline_pins(top_inst_group, col) bot_bl, bot_br = bot_bl_pin.uc(), bot_br_pin.uc() top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc() - print("BL", bot_bl, top_bl) - print(bot_bl_pin, top_bl_pin) - print("BR", bot_br, top_br) - print(bot_br_pin, top_br_pin) self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V") self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V") From b3b03d4d397e82dbeb357ac01f381018226e2b27 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Jun 2020 16:46:00 -0700 Subject: [PATCH 324/521] Hard cells can accept height parameter too. --- compiler/custom/{pand2_dec.py => and2_dec.py} | 33 +++++++++++------- compiler/custom/{pand3_dec.py => and3_dec.py} | 29 ++++++++++------ compiler/custom/{pand4_dec.py => and4_dec.py} | 34 ++++++++++++------- compiler/custom/nand2_dec.py | 10 +++++- compiler/custom/nand3_dec.py | 10 +++++- compiler/custom/nand4_dec.py | 10 +++++- compiler/modules/hierarchical_decoder.py | 19 ++++------- compiler/modules/hierarchical_predecode.py | 6 ++-- compiler/pgates/wordline_driver.py | 8 ++--- ..._pand3_dec_test.py => 04_and2_dec_test.py} | 8 ++--- ..._pand4_dec_test.py => 04_and3_dec_test.py} | 8 ++--- ..._pand2_dec_test.py => 04_and4_dec_test.py} | 8 ++--- 12 files changed, 112 insertions(+), 71 deletions(-) rename compiler/custom/{pand2_dec.py => and2_dec.py} (89%) rename compiler/custom/{pand3_dec.py => and3_dec.py} (90%) rename compiler/custom/{pand4_dec.py => and4_dec.py} (89%) rename compiler/tests/{04_pand3_dec_test.py => 04_and2_dec_test.py} (85%) rename compiler/tests/{04_pand4_dec_test.py => 04_and3_dec_test.py} (85%) rename compiler/tests/{04_pand2_dec_test.py => 04_and4_dec_test.py} (85%) diff --git a/compiler/custom/pand2_dec.py b/compiler/custom/and2_dec.py similarity index 89% rename from compiler/custom/pand2_dec.py rename to compiler/custom/and2_dec.py index 0db490ff..b764bb83 100644 --- a/compiler/custom/pand2_dec.py +++ b/compiler/custom/and2_dec.py @@ -7,34 +7,37 @@ # import debug from vector import vector -import pgate +import design from sram_factory import factory from globals import OPTS +from tech import layer -class pand2_dec(pgate.pgate): +class and2_dec(design.design): """ This is an AND with configurable drive strength. """ def __init__(self, name, size=1, height=None, add_wells=True): - debug.info(1, "Creating pand2_dec {}".format(name)) + + design.design.__init__(self, name) + + debug.info(1, "Creating and2_dec {}".format(name)) self.add_comment("size: {}".format(size)) - self.size = size - - pgate.pgate.__init__(self, name, height, add_wells) - + self.height = height + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + def create_netlist(self): self.add_pins() self.create_modules() self.create_insts() def create_modules(self): - if OPTS.tech_name == "s8": - self.nand = factory.create(module_type="nand2_dec") - else: - self.nand = factory.create(module_type="nand2_dec", - height=self.height) + self.nand = factory.create(module_type="nand2_dec", + height=self.height) self.inv = factory.create(module_type="inv_dec", height=self.height, @@ -44,7 +47,13 @@ class pand2_dec(pgate.pgate): self.add_mod(self.inv) def create_layout(self): + + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" self.width = self.nand.width + self.inv.width + self.height = self.nand.height self.place_insts() self.add_wires() diff --git a/compiler/custom/pand3_dec.py b/compiler/custom/and3_dec.py similarity index 90% rename from compiler/custom/pand3_dec.py rename to compiler/custom/and3_dec.py index 3ec1eb45..89cc84f8 100644 --- a/compiler/custom/pand3_dec.py +++ b/compiler/custom/and3_dec.py @@ -7,22 +7,26 @@ # import debug from vector import vector -import pgate +import design from sram_factory import factory from globals import OPTS +from tech import layer -class pand3_dec(pgate.pgate): +class and3_dec(design.design): """ This is an AND with configurable drive strength. """ def __init__(self, name, size=1, height=None, add_wells=True): - debug.info(1, "Creating pand3_dec {}".format(name)) + design.design.__init__(self, name) + debug.info(1, "Creating and3_dec {}".format(name)) self.add_comment("size: {}".format(size)) - self.size = size + self.height = height - pgate.pgate.__init__(self, name, height, add_wells) + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() def create_netlist(self): self.add_pins() @@ -30,11 +34,8 @@ class pand3_dec(pgate.pgate): self.create_insts() def create_modules(self): - if OPTS.tech_name == "s8": - self.nand = factory.create(module_type="nand3_dec") - else: - self.nand = factory.create(module_type="nand3_dec", - height=self.height) + self.nand = factory.create(module_type="nand3_dec", + height=self.height) self.inv = factory.create(module_type="inv_dec", height=self.height, @@ -44,8 +45,14 @@ class pand3_dec(pgate.pgate): self.add_mod(self.inv) def create_layout(self): - self.width = self.nand.width + self.inv.width + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" + self.width = self.nand.width + self.inv.width + self.height = self.nand.height + self.place_insts() self.add_wires() self.add_layout_pins() diff --git a/compiler/custom/pand4_dec.py b/compiler/custom/and4_dec.py similarity index 89% rename from compiler/custom/pand4_dec.py rename to compiler/custom/and4_dec.py index ee65a349..f99c048f 100644 --- a/compiler/custom/pand4_dec.py +++ b/compiler/custom/and4_dec.py @@ -7,22 +7,28 @@ # import debug from vector import vector -import pgate +import design from sram_factory import factory from globals import OPTS +from tech import layer -class pand4_dec(pgate.pgate): +class and4_dec(design.design): """ This is an AND with configurable drive strength. """ def __init__(self, name, size=1, height=None, add_wells=True): - debug.info(1, "Creating pand4_dec {}".format(name)) - self.add_comment("size: {}".format(size)) - - self.size = size - pgate.pgate.__init__(self, name, height, add_wells) + design.design.__init__(self, name) + + debug.info(1, "Creating and4_dec {}".format(name)) + self.add_comment("size: {}".format(size)) + self.size = size + self.height = height + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() def create_netlist(self): self.add_pins() @@ -30,20 +36,24 @@ class pand4_dec(pgate.pgate): self.create_insts() def create_modules(self): - if OPTS.tech_name == "s8": - self.nand = factory.create(module_type="nand4_dec") - else: - self.nand = factory.create(module_type="nand4_dec", - height=self.height) + self.nand = factory.create(module_type="nand4_dec", + height=self.height) self.inv = factory.create(module_type="inv_dec", + height=self.height, size=self.size) self.add_mod(self.nand) self.add_mod(self.inv) def create_layout(self): + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" + self.width = self.nand.width + self.inv.width + self.height = self.nand.height self.place_insts() self.add_wires() diff --git a/compiler/custom/nand2_dec.py b/compiler/custom/nand2_dec.py index 30a018a1..c806bf5a 100644 --- a/compiler/custom/nand2_dec.py +++ b/compiler/custom/nand2_dec.py @@ -6,7 +6,7 @@ # All rights reserved. # import design -from tech import GDS, layer, spice, parameter +from tech import GDS, layer, spice, parameter, drc import logical_effort import utils @@ -31,6 +31,14 @@ class nand2_dec(design.design): self.height = nand2_dec.height self.pin_map = nand2_dec.pin_map self.add_pin_types(self.type_list) + + # FIXME: For now... + size = 1 + self.size = size + self.nmos_size = 2 * size + self.pmos_size = parameter["beta"] * size + self.nmos_width = self.nmos_size * drc("minwidth_tx") + self.pmos_width = self.pmos_size * drc("minwidth_tx") def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/custom/nand3_dec.py b/compiler/custom/nand3_dec.py index d700062c..5eea68de 100644 --- a/compiler/custom/nand3_dec.py +++ b/compiler/custom/nand3_dec.py @@ -6,7 +6,7 @@ # All rights reserved. # import design -from tech import GDS, layer, spice, parameter +from tech import GDS, layer, spice, parameter, drc import logical_effort import utils @@ -31,6 +31,14 @@ class nand3_dec(design.design): self.height = nand3_dec.height self.pin_map = nand3_dec.pin_map self.add_pin_types(self.type_list) + + # FIXME: For now... + size = 1 + self.size = size + self.nmos_size = 2 * size + self.pmos_size = parameter["beta"] * size + self.nmos_width = self.nmos_size * drc("minwidth_tx") + self.pmos_width = self.pmos_size * drc("minwidth_tx") def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/custom/nand4_dec.py b/compiler/custom/nand4_dec.py index 5c2bb882..df3eee14 100644 --- a/compiler/custom/nand4_dec.py +++ b/compiler/custom/nand4_dec.py @@ -6,7 +6,7 @@ # All rights reserved. # import design -from tech import GDS, layer, spice, parameter +from tech import GDS, layer, spice, parameter, drc import logical_effort import utils @@ -31,6 +31,14 @@ class nand4_dec(design.design): self.height = nand4_dec.height self.pin_map = nand4_dec.pin_map self.add_pin_types(self.type_list) + + # FIXME: For now... + size = 1 + self.size = size + self.nmos_size = 2 * size + self.pmos_size = parameter["beta"] * size + self.nmos_width = self.nmos_size * drc("minwidth_tx") + self.pmos_width = self.pmos_size * drc("minwidth_tx") def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 3cb5d35c..8b711031 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -57,21 +57,15 @@ class hierarchical_decoder(design.design): self.DRC_LVS() def add_modules(self): - if OPTS.tech_name == "s8": - self.and2 = factory.create(module_type="pand2_dec") - else: - self.and2 = factory.create(module_type="pand2_dec", - height=self.cell_height) + self.and2 = factory.create(module_type="and2_dec", + height=self.cell_height) self.add_mod(self.and2) - if OPTS.tech_name == "s8": - self.and3 = factory.create(module_type="pand3_dec") - else: - self.and3 = factory.create(module_type="pand3_dec", - height=self.cell_height) - + + self.and3 = factory.create(module_type="and3_dec", + height=self.cell_height) self.add_mod(self.and3) # TBD - # self.and4 = factory.create(module_type="pand4_dec") + # self.and4 = factory.create(module_type="and4_dec") # self.add_mod(self.and4) self.add_decoders() @@ -180,6 +174,7 @@ class hierarchical_decoder(design.design): # Two extra pitches between modules on left and right self.internal_routing_width = self.total_number_of_predecoder_outputs * self.bus_pitch + self.bus_pitch self.row_decoder_height = self.and2.height * self.num_outputs + # Extra bus space for supply contacts self.input_routing_width = self.num_inputs * self.bus_pitch + self.bus_space diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 8244028e..fa44b080 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -42,13 +42,13 @@ class hierarchical_predecode(design.design): # FIXME: Default parms are required for hard cells for now. if self.number_of_inputs == 2: - self.and_mod = factory.create(module_type="pand2_dec", + self.and_mod = factory.create(module_type="and2_dec", height=self.cell_height) elif self.number_of_inputs == 3: - self.and_mod = factory.create(module_type="pand3_dec", + self.and_mod = factory.create(module_type="and3_dec", height=self.cell_height) elif self.number_of_inputs == 4: - self.and_mod = factory.create(module_type="pand4_dec", + self.and_mod = factory.create(module_type="and4_dec", height=self.cell_height) else: debug.error("Invalid number of predecode inputs: {}".format(self.number_of_inputs), -1) diff --git a/compiler/pgates/wordline_driver.py b/compiler/pgates/wordline_driver.py index 1b035e20..a817941b 100644 --- a/compiler/pgates/wordline_driver.py +++ b/compiler/pgates/wordline_driver.py @@ -40,12 +40,8 @@ class wordline_driver(design.design): self.create_insts() def create_modules(self): - if OPTS.tech_name == "s8": - self.nand = factory.create(module_type="nand2_dec") - self.height = self.nand.height - else: - self.nand = factory.create(module_type="nand2_dec", - height=self.height) + self.nand = factory.create(module_type="nand2_dec", + height=self.height) self.driver = factory.create(module_type="inv_dec", size=self.size, diff --git a/compiler/tests/04_pand3_dec_test.py b/compiler/tests/04_and2_dec_test.py similarity index 85% rename from compiler/tests/04_pand3_dec_test.py rename to compiler/tests/04_and2_dec_test.py index 78e576ed..355d3b15 100755 --- a/compiler/tests/04_pand3_dec_test.py +++ b/compiler/tests/04_and2_dec_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class pand3_dec_test(openram_test): +class and2_dec_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -23,10 +23,10 @@ class pand3_dec_test(openram_test): global verify import verify - import pand3_dec + import and2_dec - debug.info(2, "Testing pand3 gate 4x") - a = pand3_dec.pand3_dec(name="pand3x4", size=4) + debug.info(2, "Testing and2 gate 4x") + a = and2_dec.and2_dec(name="and2x4", size=4) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_pand4_dec_test.py b/compiler/tests/04_and3_dec_test.py similarity index 85% rename from compiler/tests/04_pand4_dec_test.py rename to compiler/tests/04_and3_dec_test.py index 78e576ed..7794f36b 100755 --- a/compiler/tests/04_pand4_dec_test.py +++ b/compiler/tests/04_and3_dec_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class pand3_dec_test(openram_test): +class and3_dec_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -23,10 +23,10 @@ class pand3_dec_test(openram_test): global verify import verify - import pand3_dec + import and3_dec - debug.info(2, "Testing pand3 gate 4x") - a = pand3_dec.pand3_dec(name="pand3x4", size=4) + debug.info(2, "Testing and3 gate 4x") + a = and3_dec.and3_dec(name="and3x4", size=4) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_pand2_dec_test.py b/compiler/tests/04_and4_dec_test.py similarity index 85% rename from compiler/tests/04_pand2_dec_test.py rename to compiler/tests/04_and4_dec_test.py index 92b80203..7794f36b 100755 --- a/compiler/tests/04_pand2_dec_test.py +++ b/compiler/tests/04_and4_dec_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class pand2_dec_test(openram_test): +class and3_dec_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -23,10 +23,10 @@ class pand2_dec_test(openram_test): global verify import verify - import pand2_dec + import and3_dec - debug.info(2, "Testing pand2 gate 4x") - a = pand2_dec.pand2_dec(name="pand2x4", size=4) + debug.info(2, "Testing and3 gate 4x") + a = and3_dec.and3_dec(name="and3x4", size=4) self.local_check(a) globals.end_openram() From 9ecf98a4c32c52bde08010d2abb0e8b26ac38054 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Jun 2020 16:46:22 -0700 Subject: [PATCH 325/521] SRAM factory uses default name for first instance even if it has arguments. --- compiler/sram_factory.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index df6b9d99..46eed3d4 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -111,11 +111,12 @@ class sram_factory: return obj_item # If no prefered module name is provided, we generate one. - if module_name is None: - # Use the default name if there are default arguments + if not module_name: + # Use the default name for the first cell. # This is especially for library cells so that the # spice and gds files can be found. - if len(kwargs) > 0: + # Subsequent objects will get unique names to help with GDS limitation. + if len(self.objects[real_module_type]) > 0: # Create a unique name and increment the index module_name = "{0}_{1}".format(real_module_type, self.module_indices[real_module_type]) From b39579c109848845c753bcef74b87cf30af7ad50 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Mon, 1 Jun 2020 20:55:15 -0700 Subject: [PATCH 326/521] temp drc fix for regression tests --- compiler/base/hierarchy_layout.py | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 0da2c4b0..722ac2f1 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1078,15 +1078,18 @@ class layout(): # Route each pin to the trunk for pin in pins: - # If there is sufficient space, Route from the edge of the pins - # Otherwise, route from the center of the pins - if max_y_bc - min_y_uc > pitch: - if pin.center().y == max_y: - mid = vector(trunk_offset.x, pin.bc().y) - else: - mid = vector(trunk_offset.x, pin.uc().y) - else: - mid = vector(trunk_offset.x, pin.center().y) + # This code block currently causes drc violations for the topmost + # port when using multiport, TODO: fix or remove this block + # # If there is sufficient space, Route from the edge of the pins + # # Otherwise, route from the center of the pins + # if max_y_bc - min_y_uc > pitch: + # if pin.center().y == max_y: + # mid = vector(trunk_offset.x, pin.bc().y) + # else: + # mid = vector(trunk_offset.x, pin.uc().y) + # else: + # mid = vector(trunk_offset.x, pin.center().y) + mid = vector(trunk_offset.x, pin.center().y) self.add_path(self.horizontal_layer, [pin.center(), mid]) self.add_via_center(layers=layer_stack, offset=mid) From b0aa70ffda436e9b22f5f51c249671e2660c0ed6 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jun 2020 09:23:27 -0700 Subject: [PATCH 327/521] Fix precharge vdd route layer --- compiler/pgates/precharge.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index ae314452..8b84a1b8 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -105,17 +105,14 @@ class precharge(design.design): # center of vdd rail pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y) - self.add_path(self.bitline_layer, [pmos_pin.center(), pmos_vdd_pos]) + self.add_path(self.en_layer, [pmos_pin.center(), pmos_vdd_pos]) - self.add_via_stack_center(from_layer=self.bitline_layer, - to_layer=self.en_layer, - offset=pmos_vdd_pos) self.add_power_pin("vdd", self.well_contact_pos, directions=("V", "V")) self.add_via_stack_center(from_layer=pmos_pin.layer, - to_layer=self.bitline_layer, + to_layer=self.en_layer, offset=pmos_pin.center(), directions=("V", "V")) From e69b665689c0b2b29ba0a124b15e6ba505199fca Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jun 2020 09:31:43 -0700 Subject: [PATCH 328/521] Flatten pbitcell_1 too --- technology/scn4m_subm/mag_lib/setup.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/technology/scn4m_subm/mag_lib/setup.tcl b/technology/scn4m_subm/mag_lib/setup.tcl index 95e7dbea..09bbea27 100644 --- a/technology/scn4m_subm/mag_lib/setup.tcl +++ b/technology/scn4m_subm/mag_lib/setup.tcl @@ -6,7 +6,7 @@ equate class {-circuit1 pfet} {-circuit2 p} flatten class {-circuit1 dummy_cell_6t} flatten class {-circuit1 dummy_cell_1rw_1r} flatten class {-circuit1 dummy_cell_1w_1r} -flatten class {-circuit1 bitcell_array_0} +flatten class {-circuit1 pbitcell} flatten class {-circuit1 pbitcell_0} flatten class {-circuit1 pbitcell_1} property {-circuit1 nfet} remove as ad ps pd From 620604603c9949627df77b5f887f04e334d84e40 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jun 2020 10:08:37 -0700 Subject: [PATCH 329/521] Fixed offset jogs --- compiler/base/hierarchy_layout.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 4d0345a3..f659aed4 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -450,7 +450,7 @@ class layout(): path=coordinates, layer_widths=layer_widths) - def add_zjog(self, layer, start, end, first_direction="H"): + def add_zjog(self, layer, start, end, first_direction="H", fixed_offset=None): """ Add a simple jog at the halfway point. If layer is a single value, it is a path. @@ -459,11 +459,17 @@ class layout(): # vertical first if first_direction == "V": - mid1 = vector(start.x, 0.5 * start.y + 0.5 * end.y) + if fixed_offset: + mid1 = vector(start.x, fixed_offset) + else: + mid1 = vector(start.x, 0.5 * start.y + 0.5 * end.y) mid2 = vector(end.x, mid1.y) # horizontal first elif first_direction == "H": - mid1 = vector(0.5 * start.x + 0.5 * end.x, start.y) + if fixed_offset: + mid1 = vector(fixed_offset, start.y) + else: + mid1 = vector(0.5 * start.x + 0.5 * end.x, start.y) mid2 = vector(mid1, end.y) else: debug.error("Invalid direction for jog -- must be H or V.") From a1c7474f80aaa35060f503b7bcb886e14f88b2c7 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jun 2020 10:08:53 -0700 Subject: [PATCH 330/521] Revert to channel route of bitlines --- compiler/modules/port_data.py | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index d544b6be..0ad0dd86 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -536,11 +536,11 @@ class port_data(design.design): # This could be a channel route, but in some techs the bitlines # are too close together. - self.connect_bitlines(inst1=inst1, - inst1_bls_template=inst1_bls_templ, - inst2=inst2, - num_bits=self.word_size, - inst1_start_bit=start_bit) + self.channel_route_bitlines(inst1=inst1, + inst1_bls_template=inst1_bls_templ, + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) def route_write_driver_to_column_mux_or_precharge_array(self, port): """ Routing of BL and BR between sense_amp and column mux or precharge array """ @@ -562,10 +562,10 @@ class port_data(design.design): # This could be a channel route, but in some techs the bitlines # are too close together. - self.connect_bitlines(inst1=inst1, inst2=inst2, - num_bits=self.word_size, - inst1_bls_template=inst1_bls_templ, - inst1_start_bit=start_bit) + self.channel_route_bitlines(inst1=inst1, inst2=inst2, + num_bits=self.word_size, + inst1_bls_template=inst1_bls_templ, + inst1_start_bit=start_bit) def route_write_driver_to_sense_amp(self, port): """ Routing of BL and BR between write driver and sense amp """ @@ -714,9 +714,10 @@ class port_data(design.design): top_bl_pin, top_br_pin = self._get_bitline_pins(top_inst_group, col) bot_bl, bot_br = bot_bl_pin.uc(), bot_br_pin.uc() top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc() - - self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V") - self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V") + + layer_pitch = getattr(self, "{}_pitch".format(top_bl_pin.layer)) + self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V", top_bl_pin.by() - layer_pitch) + self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V", top_bl_pin.by() - 2 * layer_pitch) def graph_exclude_precharge(self): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" From 45b0601e4b0789f84c1d38230d2ee9a890fafe34 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jun 2020 11:43:31 -0700 Subject: [PATCH 331/521] Fix via directions in s8 col mux --- .../modules/single_level_column_mux_array.py | 24 +++++++++++++------ 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 5dc9cbf8..1514d64a 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -7,7 +7,7 @@ # import design import debug -from tech import layer +from tech import layer, preferred_directions from vector import vector from sram_factory import factory from globals import OPTS @@ -33,10 +33,15 @@ class single_level_column_mux_array(design.design): if "li" in layer: self.col_mux_stack = self.li_stack - self.col_mux_stack_pitch = self.li_pitch + self.col_mux_stack_pitch = self.m1_pitch else: self.col_mux_stack = self.m1_stack self.col_mux_stack_pitch = self.m1_pitch + + if preferred_directions[self.col_mux_stack[0]] == "V": + self.via_directions = ("H", "H") + else: + self.via_directions = "pref" self.create_netlist() if not OPTS.netlist_only: @@ -173,7 +178,8 @@ class single_level_column_mux_array(design.design): self.get_pin("sel_{}".format(sel_index)).cy()) # Add the poly contact with a shift to account for the rotation self.add_via_center(layers=self.poly_stack, - offset=offset) + offset=offset, + directions=self.via_directions) self.add_path("poly", [offset, gate_offset]) def route_bitlines(self): @@ -224,11 +230,13 @@ class single_level_column_mux_array(design.design): # This via is on the right of the wire self.add_via_center(layers=self.col_mux_stack, - offset=bl_out_offset) + offset=bl_out_offset, + directions=self.via_directions) # This via is on the left of the wire self.add_via_center(layers=self.col_mux_stack, - offset=br_out_offset) + offset=br_out_offset, + directions=self.via_directions) else: self.add_path(self.col_mux_stack[2], [bl_out_offset, bl_offset]) @@ -236,10 +244,12 @@ class single_level_column_mux_array(design.design): # This via is on the right of the wire self.add_via_center(layers=self.col_mux_stack, - offset=bl_out_offset) + offset=bl_out_offset, + directions=self.via_directions) # This via is on the left of the wire self.add_via_center(layers=self.col_mux_stack, - offset=br_out_offset) + offset=br_out_offset, + directions=self.via_directions) def get_drain_cin(self): """Get the relative capacitance of the drain of the NMOS pass TX""" From f1b7b91b1a4958a90b198fce69cd7f21aa9f7ea7 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jun 2020 11:43:57 -0700 Subject: [PATCH 332/521] Use non-channel route for s8 port_data --- compiler/modules/port_data.py | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 0ad0dd86..904c82eb 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -180,6 +180,7 @@ class port_data(design.design): # Precharge will be shifted left if needed self.precharge_array = factory.create(module_type="precharge_array", columns=self.num_cols + 1, + port=self.port, bitcell_bl=self.bl_names[self.port], bitcell_br=self.br_names[self.port]) self.add_mod(self.precharge_array) @@ -250,6 +251,7 @@ class port_data(design.design): # module, which happens before we create the real precharge_array self.precharge_array = factory.create(module_type="precharge_array", columns=self.num_cols + 1, + port=self.port, bitcell_bl=self.bl_names[self.port], bitcell_br=self.br_names[self.port]) @@ -536,11 +538,18 @@ class port_data(design.design): # This could be a channel route, but in some techs the bitlines # are too close together. - self.channel_route_bitlines(inst1=inst1, - inst1_bls_template=inst1_bls_templ, - inst2=inst2, - num_bits=self.word_size, - inst1_start_bit=start_bit) + if OPTS.tech_name == "s8": + self.connect_bitlines(inst1=inst1, + inst1_bls_template=inst1_bls_templ, + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) + else: + self.channel_route_bitlines(inst1=inst1, + inst1_bls_template=inst1_bls_templ, + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) def route_write_driver_to_column_mux_or_precharge_array(self, port): """ Routing of BL and BR between sense_amp and column mux or precharge array """ @@ -562,11 +571,17 @@ class port_data(design.design): # This could be a channel route, but in some techs the bitlines # are too close together. - self.channel_route_bitlines(inst1=inst1, inst2=inst2, - num_bits=self.word_size, - inst1_bls_template=inst1_bls_templ, - inst1_start_bit=start_bit) - + if OPTS.tech_name == "s8": + self.connect_bitlines(inst1=inst1, inst2=inst2, + num_bits=self.word_size, + inst1_bls_template=inst1_bls_templ, + inst1_start_bit=start_bit) + else: + self.channel_route_bitlines(inst1=inst1, inst2=inst2, + num_bits=self.word_size, + inst1_bls_template=inst1_bls_templ, + inst1_start_bit=start_bit) + def route_write_driver_to_sense_amp(self, port): """ Routing of BL and BR between write driver and sense amp """ From fdf51c5a00ca61f8601ae344ee7997be8bd2a5a6 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jun 2020 11:44:22 -0700 Subject: [PATCH 333/521] Add port option to precharge array --- compiler/modules/precharge_array.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index af612af4..3c64e85f 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -19,13 +19,14 @@ class precharge_array(design.design): of bit line columns, height is the height of the bit-cell array. """ - def __init__(self, name, columns, size=1, bitcell_bl="bl", bitcell_br="br"): + def __init__(self, name, columns, port, size=1, bitcell_bl="bl", bitcell_br="br"): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br)) self.columns = columns self.size = size + self.port = port self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br @@ -106,7 +107,7 @@ class precharge_array(design.design): xoffset = 0 for i in range(self.columns): tempx = xoffset - if cell_properties.bitcell.mirror.y and (i + 1) % 2: + if cell_properties.bitcell.mirror.y and (i + 1 + self.port) % 2: mirror = "MY" tempx = tempx + self.pc_cell.width else: From fce8e878b9ac55d57865ef2e7a4883f901d3daf4 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jun 2020 13:57:41 -0700 Subject: [PATCH 334/521] Add port to col mux and simplify route with computation to fix mirror bug. --- .../modules/single_level_column_mux_array.py | 86 +++++++------------ .../07_single_level_column_mux_array_test.py | 6 +- 2 files changed, 34 insertions(+), 58 deletions(-) diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 1514d64a..3d80525a 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -20,12 +20,13 @@ class single_level_column_mux_array(design.design): Array of column mux to read the bitlines through the 6T. """ - def __init__(self, name, columns, word_size, bitcell_bl="bl", bitcell_br="br"): + def __init__(self, name, columns, port, word_size, bitcell_bl="bl", bitcell_br="br"): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("cols: {0} word_size: {1} bl: {2} br: {3}".format(columns, word_size, bitcell_bl, bitcell_br)) self.columns = columns + self.port = port self.word_size = word_size self.words_per_row = int(self.columns / self.word_size) self.bitcell_bl = bitcell_bl @@ -117,7 +118,7 @@ class single_level_column_mux_array(design.design): # For every column, add a pass gate for col_num in range(self.columns): xoffset = col_num * self.mux.width - if cell_properties.bitcell.mirror.y and col_num % 2: + if cell_properties.bitcell.mirror.y and (col_num + self.port) % 2: mirror = "MY" xoffset = xoffset + self.mux.width else: @@ -184,72 +185,47 @@ class single_level_column_mux_array(design.design): def route_bitlines(self): """ Connect the output bit-lines to form the appropriate width mux """ - from tech import cell_properties for j in range(self.columns): - bl_offset = self.mux_inst[j].get_pin("bl_out").bc() - br_offset = self.mux_inst[j].get_pin("br_out").bc() - bl_out_offset = bl_offset - vector(0, (self.words_per_row + 1) * self.col_mux_stack_pitch) - br_out_offset = br_offset - vector(0, (self.words_per_row + 2) * self.col_mux_stack_pitch) + bl_offset_begin = self.mux_inst[j].get_pin("bl_out").bc() + br_offset_begin = self.mux_inst[j].get_pin("br_out").bc() - bl_out_offset_end = bl_out_offset + vector(0, self.route_height) - br_out_offset_end = br_out_offset + vector(0, self.route_height) + bl_out_offset_begin = bl_offset_begin - vector(0, (self.words_per_row + 1) * self.col_mux_stack_pitch) + br_out_offset_begin = br_offset_begin - vector(0, (self.words_per_row + 2) * self.col_mux_stack_pitch) - if cell_properties.bitcell.mirror.y and j % 2: - tmp_bl_out_end = br_out_offset_end - tmp_br_out_end = bl_out_offset_end - else: - tmp_bl_out_end = bl_out_offset_end - tmp_br_out_end = br_out_offset_end - - if (j % self.words_per_row) == 0: - # Create the metal1 to connect the n-way mux output from the pass gate - # These will be located below the select lines. Yes, these are M2 width - # to ensure vias are enclosed and M1 min width rules. - width = self.m2_width + self.mux.width * (self.words_per_row - 1) - - if cell_properties.bitcell.mirror.y and (j % 2) == 0: - bl = self.mux.get_pin("bl") - br = self.mux.get_pin("br") - dist = abs(bl.ll().x - br.ll().x) - else: - dist = 0 - - self.add_path(self.col_mux_stack[0], [bl_out_offset, bl_out_offset + vector(width + dist, 0)]) - self.add_path(self.col_mux_stack[0], [br_out_offset, br_out_offset + vector(width - dist, 0)]) + # Add the horizontal wires for the first bit + if j % self.words_per_row == 0: + bl_offset_end = self.mux_inst[j + self.words_per_row - 1].get_pin("bl_out").bc() + br_offset_end = self.mux_inst[j + self.words_per_row - 1].get_pin("br_out").bc() + bl_out_offset_end = bl_offset_end - vector(0, (self.words_per_row + 1) * self.col_mux_stack_pitch) + br_out_offset_end = br_offset_end - vector(0, (self.words_per_row + 2) * self.col_mux_stack_pitch) + + self.add_path(self.col_mux_stack[0], [bl_out_offset_begin, bl_out_offset_end]) + self.add_path(self.col_mux_stack[0], [br_out_offset_begin, br_out_offset_end]) # Extend the bitline output rails and gnd downward on the first bit of each n-way mux self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j / self.words_per_row)), layer=self.col_mux_stack[2], - start=bl_out_offset, - end=tmp_bl_out_end) + start=bl_offset_begin, + end=bl_out_offset_begin) self.add_layout_pin_segment_center(text="br_out_{}".format(int(j / self.words_per_row)), layer=self.col_mux_stack[2], - start=br_out_offset, - end=tmp_br_out_end) - - # This via is on the right of the wire - self.add_via_center(layers=self.col_mux_stack, - offset=bl_out_offset, - directions=self.via_directions) - - # This via is on the left of the wire - self.add_via_center(layers=self.col_mux_stack, - offset=br_out_offset, - directions=self.via_directions) + start=br_offset_begin, + end=br_out_offset_begin) else: - self.add_path(self.col_mux_stack[2], [bl_out_offset, bl_offset]) - self.add_path(self.col_mux_stack[2], [br_out_offset, br_offset]) + self.add_path(self.col_mux_stack[2], [bl_out_offset_begin, bl_offset_begin]) + self.add_path(self.col_mux_stack[2], [br_out_offset_begin, br_offset_begin]) - # This via is on the right of the wire - self.add_via_center(layers=self.col_mux_stack, - offset=bl_out_offset, - directions=self.via_directions) - # This via is on the left of the wire - self.add_via_center(layers=self.col_mux_stack, - offset=br_out_offset, - directions=self.via_directions) + # This via is on the right of the wire + self.add_via_center(layers=self.col_mux_stack, + offset=bl_out_offset_begin, + directions=self.via_directions) + + # This via is on the left of the wire + self.add_via_center(layers=self.col_mux_stack, + offset=br_out_offset_begin, + directions=self.via_directions) def get_drain_cin(self): """Get the relative capacitance of the drain of the NMOS pass TX""" diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index c5d48689..fb608f68 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -23,15 +23,15 @@ class single_level_column_mux_test(openram_test): # check single level column mux array in single port debug.info(1, "Testing sample for 2-way column_mux_array") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8) + a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=8) self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4) + a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=4) self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array") - a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4) + a = factory.create(module_type="single_level_column_mux_array", columns=32, port=0, word_size=4) self.local_check(a) globals.end_openram() From 34209dac3d6aa9680e1311ed34cac7cbb44199a3 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jun 2020 16:50:07 -0700 Subject: [PATCH 335/521] A port option for correct mirroring in port_data. --- compiler/modules/hierarchical_predecode.py | 2 -- compiler/modules/port_data.py | 1 + compiler/modules/precharge_array.py | 3 +-- .../07_single_level_column_mux_array_pbitcell_test.py | 8 ++++---- compiler/tests/08_precharge_array_1rw1r_test.py | 2 +- compiler/tests/08_precharge_array_test.py | 2 +- compiler/tests/18_port_data_1rw_1r_test.py | 2 +- 7 files changed, 9 insertions(+), 11 deletions(-) diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index fa44b080..d998d882 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -40,7 +40,6 @@ class hierarchical_predecode(design.design): def add_modules(self): """ Add the INV and AND gate modules """ - # FIXME: Default parms are required for hard cells for now. if self.number_of_inputs == 2: self.and_mod = factory.create(module_type="and2_dec", height=self.cell_height) @@ -60,7 +59,6 @@ class hierarchical_predecode(design.design): size=1) self.add_mod(self.inv) - def create_layout(self): """ The general organization is from left to right: 1) a set of M2 rails for input signals diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 904c82eb..ac6022f7 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -196,6 +196,7 @@ class port_data(design.design): if self.col_addr_size > 0: self.column_mux_array = factory.create(module_type="column_mux_array", columns=self.num_cols, + port=self.port, word_size=self.word_size, bitcell_bl=self.bl_names[self.port], bitcell_br=self.br_names[self.port]) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 3c64e85f..2acb1063 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -7,7 +7,6 @@ # import design import debug -from tech import drc from vector import vector from sram_factory import factory from globals import OPTS @@ -26,7 +25,7 @@ class precharge_array(design.design): self.columns = columns self.size = size - self.port = port + self.port = port self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br diff --git a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py b/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py index 84e62a96..7feb067e 100755 --- a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py +++ b/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py @@ -29,19 +29,19 @@ class single_level_column_mux_pbitcell_test(openram_test): factory.reset() debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array in multi-port") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)") - a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=32, port=0, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)") - a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") + a = factory.create(module_type="single_level_column_mux_array", columns=32, port=3, word_size=4, bitcell_bl="bl2", bitcell_br="br2") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/08_precharge_array_1rw1r_test.py b/compiler/tests/08_precharge_array_1rw1r_test.py index 8f51c2d4..1381b93a 100755 --- a/compiler/tests/08_precharge_array_1rw1r_test.py +++ b/compiler/tests/08_precharge_array_1rw1r_test.py @@ -29,7 +29,7 @@ class precharge_test(openram_test): factory.reset() debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell") - pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0") + pc = factory.create(module_type="precharge_array", columns=3, port=0, bitcell_bl="bl0", bitcell_br="br0") self.local_check(pc) # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index b301a909..c3b823b3 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -23,7 +23,7 @@ class precharge_test(openram_test): # check precharge array in single port debug.info(2, "Checking 3 column precharge") - pc = factory.create(module_type="precharge_array", columns=3) + pc = factory.create(module_type="precharge_array", columns=3, port=0) self.local_check(pc) globals.end_openram() diff --git a/compiler/tests/18_port_data_1rw_1r_test.py b/compiler/tests/18_port_data_1rw_1r_test.py index e9e282a5..8081416e 100755 --- a/compiler/tests/18_port_data_1rw_1r_test.py +++ b/compiler/tests/18_port_data_1rw_1r_test.py @@ -36,7 +36,7 @@ class port_data_1rw_1r_test(openram_test): self.local_check(a) a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) - + c.num_words=32 c.words_per_row=2 factory.reset() From eb0c595dbef69cf8fdf67d27b720f5e0ea716a51 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Wed, 3 Jun 2020 12:31:30 +0000 Subject: [PATCH 336/521] SRAM layout and functional tests with spare cols --- compiler/characterizer/functional.py | 35 +++- compiler/characterizer/simulation.py | 54 ++++-- compiler/modules/bank.py | 10 +- compiler/modules/control_logic.py | 4 +- compiler/modules/port_data.py | 14 +- compiler/modules/write_driver_array.py | 17 +- compiler/sram/sram_1bank.py | 157 +++++++++++++++--- compiler/sram/sram_base.py | 28 +++- ...sram_1bank_nomux_1rw_1r_spare_cols_test.py | 2 +- ...=> 20_sram_1bank_nomux_spare_cols_test.py} | 7 +- .../22_sram_1bank_2mux_sparecols_func_test.py | 62 +++++++ ...22_sram_1bank_nomux_sparecols_func_test.py | 60 +++++++ 12 files changed, 373 insertions(+), 77 deletions(-) rename compiler/tests/{20_sram_1bank_nomux_wmask_spare_cols_test.py => 20_sram_1bank_nomux_spare_cols_test.py} (89%) create mode 100755 compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py create mode 100755 compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index cbd9b8d5..8d07a61a 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -18,7 +18,7 @@ from .charutils import * import utils from globals import OPTS from .simulation import simulation -from .delay import delay +# from .delay import delay import graph_util from sram_factory import factory @@ -40,6 +40,9 @@ class functional(simulation): else: self.num_wmasks = 0 + if not self.num_spare_cols: + self.num_spare_cols = 0 + self.set_corner(corner) self.set_spice_constants() self.set_stimulus_variables() @@ -86,6 +89,7 @@ class functional(simulation): if port in self.write_ports: checks.append((self.data_value[port],"data")) checks.append((self.wmask_value[port],"wmask")) + checks.append((self.spare_wen_value[port],"spare_wen")) for (val, name) in checks: debug.check(len(self.cycle_times)==len(val), @@ -226,7 +230,7 @@ class functional(simulation): # Extract dout values from spice timing.lis for (word, dout_port, eo_period, check) in self.read_check: sp_read_value = "" - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): value = parse_spice_list("timing", "v{0}.{1}ck{2}".format(dout_port.lower(),bit,check)) if value > self.v_high: sp_read_value = "1" + sp_read_value @@ -281,13 +285,18 @@ class functional(simulation): def gen_data(self): """ Generates a random word to write. """ - random_value = random.randint(0,(2**self.word_size)-1) + if not self.num_spare_cols: + random_value = random.randint(0,(2**(self.word_size))-1) + else: + random_value1 = random.randint(0,(2**(self.word_size))-1) + random_value2 = random.randint(0,(2**(self.num_spare_cols))-1) + random_value = random_value1 + random_value2 data_bits = self.convert_to_bin(random_value,False) return data_bits def gen_addr(self): """ Generates a random address value to write to. """ - if (self.num_spare_rows == 0): + if self.num_spare_rows==0: random_value = random.randint(0,(2**self.addr_size)-1) else: random_value = random.randint(0,((2**(self.addr_size-1)-1))+(self.num_spare_rows * self.words_per_row)) @@ -307,8 +316,7 @@ class functional(simulation): if(is_addr): expected_value = self.addr_size else: - - expected_value = self.word_size + expected_value = self.word_size + self.num_spare_cols for i in range (expected_value - len(new_value)): new_value = "0" + new_value @@ -337,7 +345,7 @@ class functional(simulation): # Add load capacitance to each of the read ports self.sf.write("\n* SRAM output loads\n") for port in self.read_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): sig_name="{0}{1}_{2} ".format(self.dout_name, port, bit) self.sf.write("CD{0}{1} {2} 0 {3}f\n".format(port, bit, sig_name, self.load)) @@ -357,7 +365,7 @@ class functional(simulation): # Generate data input bits self.sf.write("\n* Generation of data and address signals\n") for port in self.write_ports: - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): sig_name="{0}{1}_{2} ".format(self.din_name, port, bit) self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period, self.slew, 0.05) @@ -386,6 +394,15 @@ class functional(simulation): self.stim.gen_pwl(sig_name, self.cycle_times, self.wmask_values[port][bit], self.period, self.slew, 0.05) + # Generate spare enable bits (for spare cols) + for port in self.write_ports: + if self.num_spare_cols: + self.sf.write("\n* Generation of spare enable signals\n") + for bit in range(self.num_spare_cols): + sig_name = "SPARE_WEN{0}_{1} ".format(port, bit) + self.stim.gen_pwl(sig_name, self.cycle_times, self.spare_wen_values[port][bit], self.period, + self.slew, 0.05) + # Generate CLK signals for port in self.all_ports: self.stim.gen_pulse(sig_name="{0}{1}".format("clk", port), @@ -401,7 +418,7 @@ class functional(simulation): for (word, dout_port, eo_period, check) in self.read_check: t_intital = eo_period - 0.01*self.period t_final = eo_period + 0.01*self.period - for bit in range(self.word_size): + for bit in range(self.word_size + self.num_spare_cols): self.stim.gen_meas_value(meas_name="V{0}_{1}ck{2}".format(dout_port,bit,check), dout="{0}_{1}".format(dout_port,bit), t_intital=t_intital, diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index e0cc6195..9027fca1 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -26,6 +26,10 @@ class simulation(): self.addr_size = self.sram.addr_size self.write_size = self.sram.write_size self.num_spare_rows = self.sram.num_spare_rows + if not self.sram.num_spare_cols: + self.num_spare_cols = 0 + else: + self.num_spare_cols = self.sram.num_spare_cols self.sp_file = spfile self.all_ports = self.sram.all_ports @@ -38,7 +42,6 @@ class simulation(): else: self.num_wmasks = 0 - def set_corner(self,corner): """ Set the corner values """ self.corner = corner @@ -61,10 +64,10 @@ class simulation(): self.pins = self.gen_pin_names(port_signal_names=(self.addr_name,self.din_name,self.dout_name), port_info=(len(self.all_ports),self.write_ports,self.read_ports), abits=self.addr_size, - dbits=self.word_size) + dbits=self.word_size + self.num_spare_cols) debug.check(len(self.sram.pins) == len(self.pins), "Number of pins generated for characterization \ - do match pins of SRAM\nsram.pins = {0}\npin_names = {1}".format(self.sram.pins, + do not match pins of SRAM\nsram.pins = {0}\npin_names = {1}".format(self.sram.pins, self.pins)) #This is TODO once multiport control has been finalized. #self.control_name = "CSB" @@ -82,11 +85,13 @@ class simulation(): self.addr_value = {port:[] for port in self.all_ports} self.data_value = {port:[] for port in self.write_ports} self.wmask_value = {port:[] for port in self.write_ports} + self.spare_wen_value = {port:[] for port in self.write_ports} # Three dimensional list to handle each addr and data bits for each port over the number of checks self.addr_values = {port:[[] for bit in range(self.addr_size)] for port in self.all_ports} - self.data_values = {port:[[] for bit in range(self.word_size)] for port in self.write_ports} + self.data_values = {port:[[] for bit in range(self.word_size + self.num_spare_cols)] for port in self.write_ports} self.wmask_values = {port:[[] for bit in range(self.num_wmasks)] for port in self.write_ports} + self.spare_wen_values = {port:[[] for bit in range(self.num_spare_cols)] for port in self.write_ports} # For generating comments in SPICE stimulus self.cycle_comments = [] @@ -113,10 +118,10 @@ class simulation(): def add_data(self, data, port): """ Add the array of data values """ - debug.check(len(data)==self.word_size, "Invalid data word size.") + debug.check(len(data)==(self.word_size + self.num_spare_cols), "Invalid data word size.") self.data_value[port].append(data) - bit = self.word_size - 1 + bit = self.word_size + self.num_spare_cols - 1 for c in data: if c=="0": self.data_values[port][bit].append(0) @@ -137,10 +142,7 @@ class simulation(): if c=="0": self.addr_values[port][bit].append(0) elif c=="1": - if((self.num_spare_rows != 0) and (bit == (self.addr_size - 1))): - self.addr_values[port][bit].append(0) - else: - self.addr_values[port][bit].append(1) + self.addr_values[port][bit].append(1) else: debug.error("Non-binary address string",1) bit -= 1 @@ -161,7 +163,21 @@ class simulation(): debug.error("Non-binary wmask string", 1) bit -= 1 - + def add_spare_wen(self, spare_wen, port): + """ Add the array of spare write enable values (for spare cols) """ + debug.check(len(spare_wen) == self.num_spare_cols, "Invalid spare enable size.") + + self.spare_wen_value[port].append(spare_wen) + bit = self.num_spare_cols - 1 + for c in spare_wen: + if c == "0": + self.spare_wen_values[port][bit].append(0) + elif c == "1": + self.spare_wen_values[port][bit].append(1) + else: + debug.error("Non-binary spare enable signal string", 1) + bit -= 1 + def add_write(self, comment, address, data, wmask, port): """ Add the control values for a write cycle. """ debug.check(port in self.write_ports, @@ -178,6 +194,7 @@ class simulation(): self.add_data(data,port) self.add_address(address,port) self.add_wmask(wmask,port) + self.add_spare_wen("1" * self.num_spare_cols, port) #Add noops to all other ports. for unselected_port in self.all_ports: @@ -197,6 +214,7 @@ class simulation(): self.t_current += self.period self.add_control_one_port(port, "read") self.add_address(address, port) + self.add_spare_wen("0" * self.num_spare_cols, port) # If the port is also a readwrite then add # the same value as previous cycle @@ -204,7 +222,7 @@ class simulation(): try: self.add_data(self.data_value[port][-1], port) except: - self.add_data("0"*self.word_size, port) + self.add_data("0"*(self.word_size + self.num_spare_cols), port) try: self.add_wmask(self.wmask_value[port][-1], port) except: @@ -239,6 +257,7 @@ class simulation(): self.add_data(data, port) self.add_address(address, port) self.add_wmask(wmask, port) + self.add_spare_wen("1" * self.num_spare_cols, port) def add_read_one_port(self, comment, address, port): """ Add the control values for a read cycle. Does not increment the period. """ @@ -250,13 +269,14 @@ class simulation(): self.add_control_one_port(port, "read") self.add_address(address, port) + self.add_spare_wen("0" * self.num_spare_cols, port) # If the port is also a readwrite then add # the same value as previous cycle if port in self.write_ports: try: self.add_data(self.data_value[port][-1], port) except: - self.add_data("0"*self.word_size, port) + self.add_data("0"*(self.word_size + self.num_spare_cols), port) try: self.add_wmask(self.wmask_value[port][-1], port) except: @@ -266,6 +286,7 @@ class simulation(): def add_noop_one_port(self, port): """ Add the control values for a noop to a single port. Does not increment the period. """ self.add_control_one_port(port, "noop") + self.add_spare_wen("0" * self.num_spare_cols, port) try: self.add_address(self.addr_value[port][-1], port) @@ -278,7 +299,7 @@ class simulation(): try: self.add_data(self.data_value[port][-1], port) except: - self.add_data("0"*self.word_size, port) + self.add_data("0"*(self.word_size + self.num_spare_cols), port) try: self.add_wmask(self.wmask_value[port][-1], port) except: @@ -374,6 +395,11 @@ class simulation(): for port in write_index: for bit in range(self.num_wmasks): pin_names.append("WMASK{0}_{1}".format(port,bit)) + + if self.num_spare_cols: + for port in write_index: + for bit in range(self.num_spare_cols): + pin_names.append("SPARE_WEN{0}_{1}".format(port,bit)) for read_output in read_index: for i in range(dbits): diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 40eabde6..ad8b34df 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -105,7 +105,7 @@ class bank(design.design): for bit in range(self.num_wmasks): self.add_pin("bank_wmask{0}_{1}".format(port, bit), "INPUT") for bit in range(self.num_spare_cols): - self.add_pin("spare_wen{0}_{1}".format(port, bit), "INPUT") + self.add_pin("bank_spare_wen{0}_{1}".format(port, bit), "INPUT") for port in self.all_ports: self.add_pin("wl_en{0}".format(port), "INPUT") self.add_pin("vdd", "POWER") @@ -442,7 +442,7 @@ class bank(design.design): for bit in range(self.num_wmasks): temp.append("bank_wmask{0}_{1}".format(port, bit)) for bit in range(self.num_spare_cols): - temp.append("spare_wen{0}_{1}".format(port, bit)) + temp.append("bank_spare_wen{0}_{1}".format(port, bit)) temp.extend(["vdd", "gnd"]) self.connect_inst(temp) @@ -725,15 +725,15 @@ class bank(design.design): din_name = "din{0}_{1}".format(port, row) self.copy_layout_pin(self.port_data_inst[port], data_name, din_name) - if self.word_size: + if self.write_size: for row in range(self.num_wmasks): wmask_name = "bank_wmask_{}".format(row) bank_wmask_name = "bank_wmask{0}_{1}".format(port, row) self.copy_layout_pin(self.port_data_inst[port], wmask_name, bank_wmask_name) for col in range(self.num_spare_cols): - sparecol_name = "spare_wen{}".format(col) - bank_sparecol_name = "spare_wen{0}_{1}".format(port, col) + sparecol_name = "bank_spare_wen{}".format(col) + bank_sparecol_name = "bank_spare_wen{0}_{1}".format(port, col) self.copy_layout_pin(self.port_data_inst[port], sparecol_name, bank_sparecol_name) def channel_route_bitlines(self, inst1, inst2, num_bits, diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index e09a6615..41970587 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -107,7 +107,7 @@ class control_logic(design.design): # clk_buf drives a flop for every address addr_flops = math.log(self.num_words, 2) + math.log(self.words_per_row, 2) # plus data flops and control flops - num_flops = addr_flops + self.word_size + self.num_control_signals + num_flops = addr_flops + self.word_size + self.num_spare_cols + self.num_control_signals # each flop internally has a FO 5 approximately # plus about 5 fanouts for the control logic clock_fanout = 5 * num_flops + 5 @@ -135,7 +135,7 @@ class control_logic(design.design): # s_en drives every sense amp self.sen_and3 = factory.create(module_type="pand3", - size=self.word_size, + size=self.word_size + self.num_spare_cols, height=dff_height) self.add_mod(self.sen_and3) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 968b4605..483cea93 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -138,7 +138,7 @@ class port_data(design.design): for bit in range(self.num_wmasks): self.add_pin("bank_wmask_{}".format(bit), "INPUT") for bit in range(self.num_spare_cols): - self.add_pin("spare_wen{}".format(bit), "INPUT") + self.add_pin("bank_spare_wen{}".format(bit), "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -387,12 +387,12 @@ class port_data(design.design): for i in range(self.num_wmasks): temp.append("wdriver_sel_{}".format(i)) for i in range(self.num_spare_cols): - temp.append("spare_wen{}".format(i)) + temp.append("bank_spare_wen{}".format(i)) elif self.num_spare_cols and not self.write_size: temp.append("w_en") for i in range(self.num_spare_cols): - temp.append("spare_wen{}".format(i)) + temp.append("bank_spare_wen{}".format(i)) else: temp.append("w_en") temp.extend(["vdd", "gnd"]) @@ -627,9 +627,9 @@ class port_data(design.design): start_bit=0 if self.port==0: - off=1 + off = 1 else: - off=0 + off = 0 if self.num_spare_cols != 0 and self.col_addr_size>0: @@ -722,11 +722,11 @@ class port_data(design.design): self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit), "wdriver_sel_{}".format(bit)) for bit in range(self.num_spare_cols): # Add spare columns' en_{} pins - self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + self.num_wmasks), "spare_wen{}".format(bit)) + self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + self.num_wmasks), "bank_spare_wen{}".format(bit)) elif self.num_spare_cols and not self.write_mask_and_array_inst: self.copy_layout_pin(self.write_driver_array_inst, "en_0", "w_en") for bit in range(self.num_spare_cols): - self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + 1), "spare_wen{}".format(bit)) + self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + 1), "bank_spare_wen{}".format(bit)) else: self.copy_layout_pin(self.write_driver_array_inst, "en", "w_en") if self.write_mask_and_array_inst: diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 48564e86..b9f6c124 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -142,7 +142,7 @@ class write_driver_array(design.design): offset = self.num_wmasks else: offset = 1 - name = "write_driver{}".format(index) + name = "write_driver{}".format(self.columns + i) self.driver_insts[index]=self.add_inst(name=name, mod=self.driver) @@ -234,27 +234,30 @@ class write_driver_array(design.design): for i in range(self.num_spare_cols): inst = self.driver_insts[self.word_size + i] + en_pin = inst.get_pin(inst.mod.en_name) self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks), layer="m1", - offset=inst.get_pin(inst.mod.en_name).ll(), - width=self.single_col_width - inst.get_pin(inst.mod.en_name).width()) + offset=en_pin.ll(), + width=self.driver.width - en_pin.width()) elif self.num_spare_cols and not self.write_size: # shorten enable rail to accomodate those for spare write drivers inst = self.driver_insts[0] + en_pin = inst.get_pin(inst.mod.en_name) self.add_layout_pin(text=self.en_name + "_{0}".format(0), layer="m1", - offset=inst.get_pin(inst.mod.en_name).ll(), - width=self.width_regular_cols - (self.words_per_row * inst.get_pin(inst.mod.en_name).width())) + offset=en_pin.ll(), + width=self.width_regular_cols - self.words_per_row * en_pin.width()) # individual enables for every spare write driver for i in range(self.num_spare_cols): inst = self.driver_insts[self.word_size + i] + en_pin = inst.get_pin(inst.mod.en_name) self.add_layout_pin(text=self.en_name + "_{0}".format(i + 1), layer="m1", - offset=inst.get_pin(inst.mod.en_name).ll(), - width=self.single_col_width - inst.get_pin(inst.mod.en_name).width()) + offset=en_pin.ll(), + width=self.driver.width - en_pin.width()) else: inst = self.driver_insts[0] diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 4af19f98..11a17129 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -39,6 +39,11 @@ class sram_1bank(sram_base): else: self.data_dff_insts = self.create_data_dff() + if self.num_spare_cols: + self.spare_wen_dff_insts = self.create_spare_wen_dff() + else: + self.num_spare_cols = 0 + def place_instances(self): """ This places the instances for a single bank SRAM with control @@ -57,6 +62,7 @@ class sram_1bank(sram_base): row_addr_pos = [None] * len(self.all_ports) col_addr_pos = [None] * len(self.all_ports) wmask_pos = [None] * len(self.all_ports) + spare_wen_pos = [None] * len(self.all_ports) data_pos = [None] * len(self.all_ports) # These positions utilize the channel route sizes. @@ -69,9 +75,21 @@ class sram_1bank(sram_base): self.data_bus_size = self.m4_nonpref_pitch * (self.word_size + self.num_spare_cols) + self.data_bus_gap self.wmask_bus_gap = self.m2_nonpref_pitch * 2 self.wmask_bus_size = self.m2_nonpref_pitch * (max(self.num_wmasks + 1, self.col_addr_size + 1)) + self.wmask_bus_gap + if self.num_spare_cols: + self.spare_wen_bus_gap = self.m2_nonpref_pitch * 2 + self.spare_wen_bus_size = self.m2_nonpref_pitch * (max(self.num_spare_cols + 1, self.col_addr_size + 1)) + self.spare_wen_bus_gap + else: + self.spare_wen_bus_size = 0 + + elif self.num_spare_cols and not self.write_size: + self.data_bus_gap = self.m4_nonpref_pitch * 2 + self.data_bus_size = self.m4_nonpref_pitch * (self.word_size + self.num_spare_cols) + self.data_bus_gap + self.spare_wen_bus_gap = self.m2_nonpref_pitch * 2 + self.spare_wen_bus_size = self.m2_nonpref_pitch * (max(self.num_spare_cols + 1, self.col_addr_size + 1)) + self.spare_wen_bus_gap + else: self.data_bus_gap = self.m3_nonpref_pitch * 2 - self.data_bus_size = self.m3_nonpref_pitch * (max(self.word_size + self.num_spare_cols + 1, self.col_addr_size + 1)) + self.data_bus_gap + self.data_bus_size = self.m3_nonpref_pitch * (max(self.word_size + 1, self.col_addr_size + 1)) + self.data_bus_gap self.col_addr_bus_gap = self.m2_nonpref_pitch * 2 self.col_addr_bus_size = self.m2_nonpref_pitch * (self.col_addr_size) + self.col_addr_bus_gap @@ -81,34 +99,57 @@ class sram_1bank(sram_base): if port in self.write_ports: if self.write_size: + bus_size = max(self.wmask_bus_size, self.spare_wen_bus_size) # Add the write mask flops below the write mask AND array. wmask_pos[port] = vector(self.bank.bank_array_ll.x, - - self.wmask_bus_size - self.dff.height) + - bus_size - self.dff.height) self.wmask_dff_insts[port].place(wmask_pos[port]) # Add the data flops below the write mask flops. data_pos[port] = vector(self.bank.bank_array_ll.x, - - self.data_bus_size - self.wmask_bus_size - 2 * self.dff.height) + - self.data_bus_size - bus_size - 2 * self.dff.height) self.data_dff_insts[port].place(data_pos[port]) + + #Add spare write enable flops to the right of write mask flops + if self.num_spare_cols: + spare_wen_pos[port] = vector(self.bank.bank_array_ll.x + self.wmask_dff_insts[port].width + self.bank.m2_gap, + - bus_size - self.dff.height) + self.spare_wen_dff_insts[port].place(spare_wen_pos[port]) + + elif self.num_spare_cols and not self.write_size: + # Add spare write enable flops below bank (lower right) + spare_wen_pos[port] = vector(self.bank.bank_array_ll.x, + - self.spare_wen_bus_size - self.dff.height) + self.spare_wen_dff_insts[port].place(spare_wen_pos[port]) + + # Add the data flops below the spare write enable flops. + data_pos[port] = vector(self.bank.bank_array_ll.x, + - self.data_bus_size - self.spare_wen_bus_size - 2 * self.dff.height) + self.data_dff_insts[port].place(data_pos[port]) + else: # Add the data flops below the bank to the right of the lower-left of bank array # This relies on the lower-left of the array of the bank # decoder in upper left, bank in upper right, sensing in lower right. # These flops go below the sensing and leave a gap to channel route to the # sense amps. - if port in self.write_ports: - data_pos[port] = vector(self.bank.bank_array_ll.x, - -self.data_bus_size - self.dff.height) - self.data_dff_insts[port].place(data_pos[port]) + data_pos[port] = vector(self.bank.bank_array_ll.x, + -self.data_bus_size - self.dff.height) + self.data_dff_insts[port].place(data_pos[port]) + else: wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0) data_pos[port] = vector(self.bank.bank_array_ll.x, 0) + spare_wen_pos[port] = vector(self.bank.bank_array_ll.x, 0) # Add the col address flops below the bank to the left of the lower-left of bank array if self.col_addr_dff: if self.write_size: col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, - -self.wmask_bus_size - self.col_addr_dff_insts[port].height) + -bus_size - self.col_addr_dff_insts[port].height) + elif self.num_spare_cols and not self.write_size: + col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, + -self.spare_wen_bus_size - self.col_addr_dff_insts[port].height) else: col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, -self.data_bus_size - self.col_addr_dff_insts[port].height) @@ -134,15 +175,34 @@ class sram_1bank(sram_base): if port in self.write_ports: if self.write_size: - # Add the write mask flops below the write mask AND array. + bus_size = max(self.wmask_bus_size, self.spare_wen_bus_size) + # Add the write mask flops above the write mask AND array. wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.wmask_dff_insts[port].width, - self.bank.height + self.wmask_bus_size + self.dff.height) + self.bank.height + bus_size + self.dff.height) self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") - # Add the data flops below the write mask flops + # Add the data flops above the write mask flops data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.height + self.wmask_bus_size + self.data_bus_size + 2 * self.dff.height) + self.bank.height + bus_size + self.data_bus_size + 2 * self.dff.height) self.data_dff_insts[port].place(data_pos[port], mirror="MX") + + if self.num_spare_cols: + spare_wen_pos[port] = vector(self.bank.bank_array_ur.x - self.wmask_dff_insts[port].width + - self.spare_wen_dff_insts[port].width - self.bank.m2_gap, + self.bank.height + bus_size + self.dff.height)) + self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX") + + # Place dffs when spare cols is enabled + elif self.num_spare_cols and not self.write_size: + # Spare wen flops on the upper right, below data flops + spare_wen_pos[port] = vector(self.bank.bank_array_ur.x - self.spare_wen_dff_insts[port].width, + self.bank.height + self.spare_wen_bus_size + self.dff.height) + self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX") + # Add the data flops above the spare write enable flops + data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, + self.bank.height + self.spare_wen_bus_size + self.data_bus_size + 2 * self.dff.height) + self.data_dff_insts[port].place(data_pos[port], mirror="MX") + else: # Add the data flops above the bank to the left of the upper-right of bank array # This relies on the upper-right of the array of the bank @@ -157,7 +217,10 @@ class sram_1bank(sram_base): if self.col_addr_dff: if self.write_size: col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, - self.bank.height + self.wmask_bus_size + self.dff.height) + self.bank.height + bus_size + self.dff.height) + elif self.num_spare_cols and not self.write_size: + col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, + self.bank.height + self.spare_wen_bus_size + self.dff.height) else: col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, self.bank.height + self.data_bus_size + self.dff.height) @@ -218,9 +281,10 @@ class sram_1bank(sram_base): self.copy_layout_pin(self.wmask_dff_insts[port], "din_{}".format(bit), "wmask{0}[{1}]".format(port, bit)) + for bit in range(self.num_spare_cols): - self.copy_layout_pin(self.bank_inst, - "spare_wen{0}_{1}".format(port, bit), + self.copy_layout_pin(self.spare_wen_dff_insts[port], + "din_{}".format(bit), "spare_wen{0}[{1}]".format(port, bit)) def route_layout(self): @@ -242,6 +306,9 @@ class sram_1bank(sram_base): if self.write_size: self.route_wmask_dff() + if self.num_spare_cols: + self.route_spare_wen_dff() + def route_clk(self): """ Route the clock network """ @@ -308,6 +375,15 @@ class sram_1bank(sram_base): self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height)) self.add_wire(self.m2_stack[::-1], [wmask_dff_clk_pos, mid_pos, clk_steiner_pos]) + if self.num_spare_cols: + spare_wen_dff_clk_pin = self.spare_wen_dff_insts[port].get_pin("clk") + spare_wen_dff_clk_pos = spare_wen_dff_clk_pin.center() + mid_pos = vector(clk_steiner_pos.x, spare_wen_dff_clk_pos.y) + # In some designs, the steiner via will be too close to the mid_pos via + # so make the wire as wide as the contacts + self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height)) + self.add_wire(self.m2_stack[::-1], [spare_wen_dff_clk_pos, mid_pos, clk_steiner_pos]) + def route_control_logic(self): """ Route the control logic pins that are not inputs """ @@ -373,20 +449,14 @@ class sram_1bank(sram_base): """ Connect the output of the data flops to the write driver """ # This is where the channel will start (y-dimension at least) for port in self.write_ports: - if self.write_size: - if port % 2: - offset = self.data_dff_insts[port].ll() - vector(0, self.data_bus_size) - else: - offset = self.data_dff_insts[port].ul() + vector(0, self.data_bus_gap) + if port % 2: + offset = self.data_dff_insts[port].ll() - vector(0, self.data_bus_size) else: - if port % 2: - offset = self.data_dff_insts[port].ll() - vector(0, self.data_bus_size) - else: - offset = self.data_dff_insts[port].ul() + vector(0, self.data_bus_gap) + offset = self.data_dff_insts[port].ul() + vector(0, self.data_bus_gap) dff_names = ["dout_{}".format(x) for x in range(self.word_size + self.num_spare_cols)] dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] - if self.write_size: + if self.write_size or self.num_spare_cols: for x in dff_names: pin = self.data_dff_insts[port].get_pin(x) pin_offset = pin.center() @@ -399,7 +469,7 @@ class sram_1bank(sram_base): bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)] bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] - if self.write_size: + if self.write_size or self.num_spare_cols: for x in bank_names: pin = self.bank_inst.get_pin(x) if port % 2: @@ -411,7 +481,7 @@ class sram_1bank(sram_base): offset=pin_offset) route_map = list(zip(bank_pins, dff_pins)) - if self.write_size: + if self.write_size or self.num_spare_cols: layer_stack = self.m3_stack else: layer_stack = self.m1_stack @@ -448,6 +518,36 @@ class sram_1bank(sram_base): self.create_horizontal_channel_route(netlist=route_map, offset=offset, layer_stack=self.m1_stack) + def route_spare_wen_dff(self): + """ Connect the output of the spare write enable flops to the spare write drivers """ + # This is where the channel will start (y-dimension at least) + for port in self.write_ports: + if port % 2: + # for port 0 + offset = self.spare_wen_dff_insts[port].ll() - vector(0, self.spare_wen_bus_size) + else: + offset = self.spare_wen_dff_insts[port].ul() + vector(0, self.spare_wen_bus_gap) + + dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)] + dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names] + for x in dff_names: + offset_pin = self.spare_wen_dff_insts[port].get_pin(x).center() + self.add_via_center(layers=self.m1_stack, + offset=offset_pin, + directions=("V", "V")) + + bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)] + bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + for x in bank_names: + offset_pin = self.bank_inst.get_pin(x).center() + self.add_via_center(layers=self.m1_stack, + offset=offset_pin) + + route_map = list(zip(bank_pins, dff_pins)) + self.create_horizontal_channel_route(netlist=route_map, + offset=offset, + layer_stack=self.m1_stack) + def add_lvs_correspondence_points(self): """ @@ -470,6 +570,9 @@ class sram_1bank(sram_base): if self.write_size: for inst in self.wmask_dff_insts: self.graph_inst_exclude.add(inst) + if self.num_spare_cols: + for inst in self.spare_wen_dff_insts: + self.graph_inst_exclude.add(inst) def graph_exclude_addr_dff(self): """Removes data dff from search graph. """ diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 0ca569af..8002b2f1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -285,6 +285,10 @@ class sram_base(design, verilog, lef): if self.write_size: self.wmask_dff = factory.create("dff_array", module_name="wmask_dff", rows=1, columns=self.num_wmasks) self.add_mod(self.wmask_dff) + + if self.num_spare_cols: + self.spare_wen_dff = factory.create("dff_array", module_name="spare_wen_dff", rows=1, columns=self.num_spare_cols) + self.add_mod(self.spare_wen_dff) # Create the bank module (up to four are instantiated) self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") @@ -358,7 +362,7 @@ class sram_base(design, verilog, lef): for bit in range(self.num_wmasks): temp.append("bank_wmask{}[{}]".format(port, bit)) for bit in range(self.num_spare_cols): - temp.append("spare_wen{0}[{1}]".format(port, bit)) + temp.append("bank_spare_wen{0}[{1}]".format(port, bit)) for port in self.all_ports: temp.append("wl_en{0}".format(port)) temp.extend(["vdd", "gnd"]) @@ -475,7 +479,29 @@ class sram_base(design, verilog, lef): self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) return insts + + def create_spare_wen_dff(self): + """ Add all spare write enable flops """ + insts = [] + for port in self.all_ports: + if port in self.write_ports: + insts.append(self.add_inst(name="spare_wen_dff{}".format(port), + mod=self.spare_wen_dff)) + else: + insts.append(None) + continue + # inputs, outputs/output/bar + inputs = [] + outputs = [] + for bit in range(self.num_spare_cols): + inputs.append("spare_wen{}[{}]".format(port, bit)) + outputs.append("bank_spare_wen{}[{}]".format(port, bit)) + + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + + return insts + def create_control_logic(self): """ Add control logic instances """ diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py index d2df2aef..575fc51f 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class sram_1bank_nomux_1rw_1r_test(openram_test): +class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py similarity index 89% rename from compiler/tests/20_sram_1bank_nomux_wmask_spare_cols_test.py rename to compiler/tests/20_sram_1bank_nomux_spare_cols_test.py index dba96ca2..14001c19 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py @@ -18,14 +18,13 @@ import debug # @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_test") -class sram_1bank_nomux_wmask_test(openram_test): +class sram_1bank_nomux_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=8, - write_size=4, num_spare_cols=3, num_words=16, num_banks=1) @@ -33,13 +32,13 @@ class sram_1bank_nomux_wmask_test(openram_test): c.words_per_row = 1 c.recompute_sizes() debug.info(1, "Layout test for {}rw,{}r,{}w sram " - "with {} bit words, {} words, {} bit writes, {} words per " + "with {} bit words, {} words, {} spare cols, {} words per " "row, {} banks".format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports, c.word_size, c.num_words, - c.write_size, + c.num_spare_cols, c.words_per_row, c.num_banks)) a = factory.create(module_type="sram", sram_config=c) diff --git a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py new file mode 100755 index 00000000..902cacdd --- /dev/null +++ b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +#@unittest.skip("SKIPPING 22_sram_1bank_2mux_sparecols_func_test") +class sram_1bank_2mux_sparecols_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional, delay + from sram_config import sram_config + c = sram_config(word_size=4, + num_words=32, + num_spare_cols=3, + num_banks=1) + c.words_per_row=2 + c.recompute_sizes() + debug.info(1, "Functional test for sram with " + "{} bit words, {} words, {} words per row, {} spare columns, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + tempspice = OPTS.openram_temp + "sram.sp" + s.sp_write(tempspice) + + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, tempspice, corner) + (fail, error) = f.run() + self.assertTrue(fail,error) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py new file mode 100755 index 00000000..347d15d0 --- /dev/null +++ b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py @@ -0,0 +1,60 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +#@unittest.skip("SKIPPING 22_sram_func_test") +class sram_1bank_nomux_sparecols_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=4, + num_words=16, + num_spare_cols=3, + num_banks=1) + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Functional test for sram with " + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + tempspice = OPTS.openram_temp + "sram.sp" + s.sp_write(tempspice) + + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, tempspice, corner) + (fail, error) = f.run() + self.assertTrue(fail,error) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 38f5e8b865e41577959f9eb243d63a466f6cc4f1 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 10:01:02 -0700 Subject: [PATCH 337/521] Add col mux tests for multiport --- .../04_single_level_column_mux_1rw_1r_test.py | 45 +++++++++++++++++++ .../tests/04_single_level_column_mux_test.py | 1 - ...ngle_level_column_mux_array_1rw_1r_test.py | 44 ++++++++++++++++++ .../07_single_level_column_mux_array_test.py | 2 - 4 files changed, 89 insertions(+), 3 deletions(-) create mode 100755 compiler/tests/04_single_level_column_mux_1rw_1r_test.py create mode 100755 compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py diff --git a/compiler/tests/04_single_level_column_mux_1rw_1r_test.py b/compiler/tests/04_single_level_column_mux_1rw_1r_test.py new file mode 100755 index 00000000..525191d7 --- /dev/null +++ b/compiler/tests/04_single_level_column_mux_1rw_1r_test.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class single_level_column_mux_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + debug.info(2, "Checking column mux port 0") + tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + debug.info(2, "Checking column mux port 1") + tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 2b437987..20dfe968 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -15,7 +15,6 @@ from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 04_driver_test") class single_level_column_mux_test(openram_test): diff --git a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py new file mode 100755 index 00000000..a8d804c9 --- /dev/null +++ b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class single_level_column_mux_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + debug.info(1, "Testing sample for 4-way column_mux_array port 0") + a = factory.create(module_type="single_level_column_mux_array", columns=8, port=0, word_size=2, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 4-way column_mux_array port 1") + a = factory.create(module_type="single_level_column_mux_array", columns=8, port=0, word_size=2, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(a) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index fb608f68..ff7ec1c9 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -19,9 +19,7 @@ class single_level_column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - import single_level_column_mux_array - # check single level column mux array in single port debug.info(1, "Testing sample for 2-way column_mux_array") a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=8) self.local_check(a) From 7a602b75a47280399260235fb8ef0edd6e3d4f4b Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Wed, 3 Jun 2020 12:54:15 -0700 Subject: [PATCH 338/521] keep dev routing changes to hierarchy_layout --- compiler/base/hierarchy_layout.py | 37 ++++--------------------------- 1 file changed, 4 insertions(+), 33 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 36505294..c6f6ff49 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -701,7 +701,7 @@ class layout(): boundary = [self.find_lowest_coords(), self.find_highest_coords()] debug.check(boundary[0] and boundary[1], "No shapes to make a boundary.") - + height = boundary[1][1] - boundary[0][1] width = boundary[1][0] - boundary[0][0] (layer_number, layer_purpose) = techlayer[boundary_layer] @@ -1008,13 +1008,8 @@ class layout(): max_x = max([pin.center().x for pin in pins]) min_x = min([pin.center().x for pin in pins]) - # max_x_lc & min_x_rc are for routing to/from the edge of the pins - # to increase spacing between contacts of different nets - max_x_lc = max([pin.lc().x for pin in pins]) - min_x_rc = min([pin.rc().x for pin in pins]) - # if we are less than a pitch, just create a non-preferred layer jog - if max_x_lc - min_x_rc <= pitch: + if max_x - min_x <= pitch: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)] # Add the horizontal trunk on the vertical layer! @@ -1035,15 +1030,7 @@ class layout(): # Route each pin to the trunk for pin in pins: - # If there is sufficient space, Route from the edge of the pins - # Otherwise, route from the center of the pins - if max_x_lc - min_x_rc > pitch: - if pin.center().x == max_x: - mid = vector(pin.lc().x, trunk_offset.y) - else: - mid = vector(pin.rc().x, trunk_offset.y) - else: - mid = vector(pin.center().x, trunk_offset.y) + mid = vector(pin.center().x, trunk_offset.y) self.add_path(self.vertical_layer, [pin.center(), mid]) self.add_via_center(layers=layer_stack, offset=mid) @@ -1060,13 +1047,8 @@ class layout(): max_y = max([pin.center().y for pin in pins]) min_y = min([pin.center().y for pin in pins]) - # max_y_bc & min_y_uc are for routing to/from the edge of the pins - # to reduce spacing between contacts of different nets - max_y_bc = max([pin.bc().y for pin in pins]) - min_y_uc = min([pin.uc().y for pin in pins]) - # if we are less than a pitch, just create a non-preferred layer jog - if max_y_bc - min_y_uc <= pitch: + if max_y - min_y <= pitch: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)] @@ -1088,17 +1070,6 @@ class layout(): # Route each pin to the trunk for pin in pins: - # This code block currently causes drc violations for the topmost - # port when using multiport, TODO: fix or remove this block - # # If there is sufficient space, Route from the edge of the pins - # # Otherwise, route from the center of the pins - # if max_y_bc - min_y_uc > pitch: - # if pin.center().y == max_y: - # mid = vector(trunk_offset.x, pin.bc().y) - # else: - # mid = vector(trunk_offset.x, pin.uc().y) - # else: - # mid = vector(trunk_offset.x, pin.center().y) mid = vector(trunk_offset.x, pin.center().y) self.add_path(self.horizontal_layer, [pin.center(), mid]) self.add_via_center(layers=layer_stack, From e93f3f1d2efed0b55ff7222846126e7533573e1c Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 14:30:15 -0700 Subject: [PATCH 339/521] Add 1rw_1r tests --- .../06_hierarchical_decoder_1rw_1r_test.py | 68 ++++++++++++++++++ .../tests/06_hierarchical_decoder_test.py | 6 -- ...6_hierarchical_predecode2x4_1rw_1r_test.py | 42 +++++++++++ .../06_hierarchical_predecode2x4_test.py | 6 -- ...6_hierarchical_predecode3x8_1rw_1r_test.py | 42 +++++++++++ .../06_hierarchical_predecode3x8_test.py | 6 -- .../08_wordline_driver_array_1rw_1r_test.py | 43 ++++++++++++ compiler/tests/18_port_address_1rw_1r_test.py | 40 +++++++++++ compiler/tests/18_port_address_test.py | 1 + .../tests/19_single_bank_wmask_1rw_1r_test.py | 69 +++++++++++++++++++ 10 files changed, 305 insertions(+), 18 deletions(-) create mode 100755 compiler/tests/06_hierarchical_decoder_1rw_1r_test.py create mode 100755 compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py create mode 100755 compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py create mode 100755 compiler/tests/08_wordline_driver_array_1rw_1r_test.py create mode 100755 compiler/tests/18_port_address_1rw_1r_test.py create mode 100755 compiler/tests/19_single_bank_wmask_1rw_1r_test.py diff --git a/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py new file mode 100755 index 00000000..5b317e6e --- /dev/null +++ b/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class hierarchical_decoder_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # Use the 2 port cell since it is usually bigger/easier + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + # Checks 2x4 and 2-input NAND decoder + debug.info(1, "Testing 16 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", num_outputs=16) + self.local_check(a) + + # Checks 2x4 and 2-input NAND decoder with non-power-of-two + debug.info(1, "Testing 17 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", num_outputs=17) + self.local_check(a) + + # Checks 2x4 with 3x8 and 2-input NAND decoder + debug.info(1, "Testing 32 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", num_outputs=32) + self.local_check(a) + + # Checks 3 x 2x4 and 3-input NAND decoder + debug.info(1, "Testing 64 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", num_outputs=64) + self.local_check(a) + + # Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two + debug.info(1, "Testing 132 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", num_outputs=132) + self.local_check(a) + + # Checks 3 x 3x8 and 3-input NAND decoder + debug.info(1, "Testing 512 row sample for hierarchical_decoder") + a = factory.create(module_type="hierarchical_decoder", num_outputs=512) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index 7d155b01..e2b34cba 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -21,12 +21,6 @@ class hierarchical_decoder_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - # Use the 2 port cell since it is usually bigger/easier - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 0 - # Checks 2x4 and 2-input NAND decoder debug.info(1, "Testing 16 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=16) diff --git a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py new file mode 100755 index 00000000..6512238f --- /dev/null +++ b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class hierarchical_predecode2x4_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # Use the 2 port cell since it is usually bigger/easier + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + debug.info(1, "Testing sample for hierarchy_predecode2x4") + a = factory.create(module_type="hierarchical_predecode2x4") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 94fd4838..c2b51f10 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -21,12 +21,6 @@ class hierarchical_predecode2x4_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - # Use the 2 port cell since it is usually bigger/easier - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 0 - debug.info(1, "Testing sample for hierarchy_predecode2x4") a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) diff --git a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py new file mode 100755 index 00000000..466a7e40 --- /dev/null +++ b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class hierarchical_predecode3x8_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # Use the 2 port cell since it is usually bigger/easier + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + debug.info(1, "Testing sample for hierarchy_predecode3x8") + a = factory.create(module_type="hierarchical_predecode3x8") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index 33f94d9d..c1471a40 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -21,12 +21,6 @@ class hierarchical_predecode3x8_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - # Use the 2 port cell since it is usually bigger/easier - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 0 - debug.info(1, "Testing sample for hierarchy_predecode3x8") a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) diff --git a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py new file mode 100755 index 00000000..7c97ff75 --- /dev/null +++ b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class wordline_driver_array_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # Use the 2 port cell since it is usually bigger/easier + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + # check wordline driver for single port + debug.info(2, "Checking driver") + tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32) + self.local_check(tx) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_address_1rw_1r_test.py b/compiler/tests/18_port_address_1rw_1r_test.py new file mode 100755 index 00000000..402b30a0 --- /dev/null +++ b/compiler/tests/18_port_address_1rw_1r_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class port_address_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # Use the 2 port cell since it is usually bigger/easier + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + debug.info(1, "Port address 16 rows") + a = factory.create("port_address", cols=16, rows=16) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py index 23f35540..a2a8bf0b 100755 --- a/compiler/tests/18_port_address_test.py +++ b/compiler/tests/18_port_address_test.py @@ -13,6 +13,7 @@ from globals import OPTS from sram_factory import factory import debug + class port_address_test(openram_test): def runTest(self): diff --git a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py new file mode 100755 index 00000000..d08ff8cc --- /dev/null +++ b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py @@ -0,0 +1,69 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class single_bank_wmask_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + + c = sram_config(word_size=8, + write_size=4, + num_words=16, + num_banks=1) + + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) + + c.num_words=128 + c.words_per_row=8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 3b1fe26d252ded614cd61a9efa4ec4e50c8fde62 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 14:33:30 -0700 Subject: [PATCH 340/521] Spacing between decoder and driver for s8 --- compiler/modules/hierarchical_decoder.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 8b711031..2b624ddc 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -191,7 +191,7 @@ class hierarchical_decoder(design.design): + self.predecoder_width \ + self.internal_routing_width \ + self.nand_width \ - + self.m1_space + + 2 * self.m1_pitch def route_inputs(self): """ Create input bus for the predecoders """ From 4bc1e9a026cb412374b90945ac6a22642635ae1e Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 15:47:03 -0700 Subject: [PATCH 341/521] Fix the bitline spacing in the column mux to a constant. --- compiler/pgates/single_level_column_mux.py | 101 ++++++------------ .../04_single_level_column_mux_1rw_1r_test.py | 2 +- 2 files changed, 32 insertions(+), 71 deletions(-) diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index bdd03e55..96935158 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -13,6 +13,7 @@ from sram_factory import factory import logical_effort from utils import round_to_grid + class single_level_column_mux(pgate.pgate): """ This module implements the columnmux bitline cell used in the design. @@ -44,9 +45,18 @@ class single_level_column_mux(pgate.pgate): def create_layout(self): - self.pin_height = 2 * self.m2_width + # If li exists, use li and m1 for the mux, otherwise use m1 and m2 + if "li" in layer: + self.col_mux_stack = self.li_stack + else: + self.col_mux_stack = self.m1_stack + self.pin_layer = self.bitcell.get_pin(self.bitcell_bl).layer + self.pin_pitch = getattr(self, "{}_pitch".format(self.pin_layer)) + self.pin_width = getattr(self, "{}_width".format(self.pin_layer)) + self.pin_height = 2 * self.pin_width self.width = self.bitcell.width self.height = self.nmos_upper.uy() + self.pin_height + self.connect_poly() self.add_bitline_pins() self.connect_bitlines() @@ -58,9 +68,7 @@ class single_level_column_mux(pgate.pgate): # Adds nmos_lower,nmos_upper to the module self.ptx_width = self.tx_size * drc("minwidth_tx") self.nmos = factory.create(module_type="ptx", - width=self.ptx_width, - add_source_contact=False, - add_drain_contact=False) + width=self.ptx_width) self.add_mod(self.nmos) def add_pins(self): @@ -69,40 +77,26 @@ class single_level_column_mux(pgate.pgate): def add_bitline_pins(self): """ Add the top and bottom pins to this cell """ - bl_pin=self.bitcell.get_pin(self.bitcell_bl) - br_pin=self.bitcell.get_pin(self.bitcell_br) - - bl_pos = vector(bl_pin.lx(), 0) - br_pos = vector(br_pin.lx(), 0) - - # The bitline input/output pins must be a least as wide as the metal pitch - # so that there is enough space to route to/from the pins. - # FIXME: bitline_metal_pitch should be greater than the horizontal metal pitch used in port_data - bitline_metal_pitch = self.width / 2 - bitline_width = br_pos.x - bl_pos.x - if bitline_width < bitline_metal_pitch: - bitline_width_increase_bl = round_to_grid((bitline_metal_pitch - bitline_width) / 2) - bitline_width_increase_br = round_to_grid((bitline_metal_pitch - bitline_width) - bitline_width_increase_bl) - bl_pos = bl_pos + vector(-bitline_width_increase_bl, 0) - br_pos = br_pos + vector( bitline_width_increase_br, 0) + bl_pos = vector(self.pin_pitch, 0) + br_pos = vector(self.width - self.pin_pitch, 0) # bl and br self.add_layout_pin(text="bl", - layer=bl_pin.layer, + layer=self.pin_layer, offset=bl_pos + vector(0, self.height - self.pin_height), height=self.pin_height) self.add_layout_pin(text="br", - layer=br_pin.layer, + layer=self.pin_layer, offset=br_pos + vector(0, self.height - self.pin_height), height=self.pin_height) # bl_out and br_out self.add_layout_pin(text="bl_out", - layer=bl_pin.layer, + layer=self.pin_layer, offset=bl_pos, height=self.pin_height) self.add_layout_pin(text="br_out", - layer=br_pin.layer, + layer=self.pin_layer, offset=br_pos, height=self.pin_height) @@ -110,7 +104,7 @@ class single_level_column_mux(pgate.pgate): """ Create the two pass gate NMOS transistors to switch the bitlines""" # Space it in the center - nmos_lower_position = self.nmos.active_offset.scale(0,1) \ + nmos_lower_position = self.nmos.active_offset.scale(0, 1) \ + vector(0.5 * self.bitcell.width- 0.5 * self.nmos.active_width, 0) self.nmos_lower = self.add_inst(name="mux_tx1", mod=self.nmos, @@ -145,62 +139,29 @@ class single_level_column_mux(pgate.pgate): def connect_bitlines(self): """ Connect the bitlines to the mux transistors """ - # If li exists, use li and m1 for the mux, otherwise use m1 and m2 - if "li" in layer: - self.col_mux_stack = self.li_stack - else: - self.col_mux_stack = self.m1_stack - - # These are on metal2 bl_pin = self.get_pin("bl") br_pin = self.get_pin("br") bl_out_pin = self.get_pin("bl_out") br_out_pin = self.get_pin("br_out") - # These are on metal1 nmos_lower_s_pin = self.nmos_lower.get_pin("S") nmos_lower_d_pin = self.nmos_lower.get_pin("D") nmos_upper_s_pin = self.nmos_upper.get_pin("S") nmos_upper_d_pin = self.nmos_upper.get_pin("D") # Add vias to bl, br_out, nmos_upper/S, nmos_lower/D - self.add_via_center(layers=self.col_mux_stack, - offset=bl_pin.bc(), - directions=("V", "V")) - self.add_via_center(layers=self.col_mux_stack, - offset=br_out_pin.uc(), - directions=("V", "V")) - self.add_via_center(layers=self.col_mux_stack, - offset=nmos_upper_s_pin.center(), - directions=("V", "V")) - self.add_via_center(layers=self.col_mux_stack, - offset=nmos_lower_d_pin.center(), - directions=("V", "V")) - - # Add diffusion contacts - # These were previously omitted with the options: add_source_contact=False, add_drain_contact=False - # They are added now and not previously so that they do not include m1 (which is usually included by default) - # This is only a concern when the local interconnect (li) layer is being used - self.add_via_center(layers=self.active_stack, - offset=nmos_upper_d_pin.center(), - directions=("V", "V"), - implant_type="n", - well_type="nwell") - self.add_via_center(layers=self.active_stack, - offset=nmos_lower_s_pin.center(), - directions=("V", "V"), - implant_type="n", - well_type="nwell") - self.add_via_center(layers=self.active_stack, - offset=nmos_upper_s_pin.center(), - directions=("V", "V"), - implant_type="n", - well_type="nwell") - self.add_via_center(layers=self.active_stack, - offset=nmos_lower_d_pin.center(), - directions=("V", "V"), - implant_type="n", - well_type="nwell") + self.add_via_stack_center(from_layer=bl_pin.layer, + to_layer=self.col_mux_stack[0], + offset=bl_pin.bc()) + self.add_via_stack_center(from_layer=br_out_pin.layer, + to_layer=self.col_mux_stack[0], + offset=br_out_pin.uc()) + self.add_via_stack_center(from_layer=nmos_upper_s_pin.layer, + to_layer=self.col_mux_stack[2], + offset=nmos_upper_s_pin.center()) + self.add_via_stack_center(from_layer=nmos_lower_d_pin.layer, + to_layer=self.col_mux_stack[2], + offset=nmos_lower_d_pin.center()) # bl -> nmos_upper/D on metal1 # bl_out -> nmos_upper/S on metal2 diff --git a/compiler/tests/04_single_level_column_mux_1rw_1r_test.py b/compiler/tests/04_single_level_column_mux_1rw_1r_test.py index 525191d7..69b31cc6 100755 --- a/compiler/tests/04_single_level_column_mux_1rw_1r_test.py +++ b/compiler/tests/04_single_level_column_mux_1rw_1r_test.py @@ -32,7 +32,7 @@ class single_level_column_mux_1rw_1r_test(openram_test): self.local_check(tx) debug.info(2, "Checking column mux port 1") - tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) globals.end_openram() From 4183638f0354cb7ac909c1d6752b67a137d1191d Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 16:05:57 -0700 Subject: [PATCH 342/521] Align precharge bitlines with col mux --- compiler/pgates/precharge.py | 12 ++++++------ ...w1r_test.py => 08_precharge_array_1rw_1r_test.py} | 0 2 files changed, 6 insertions(+), 6 deletions(-) rename compiler/tests/{08_precharge_array_1rw1r_test.py => 08_precharge_array_1rw_1r_test.py} (100%) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 8b84a1b8..278fef3d 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -235,11 +235,11 @@ class precharge(design.design): """ Adds both bit-line and bit-line-bar to the module """ - layer_width = drc("minwidth_" + self.bitline_layer) - layer_space = drc("{0}_to_{0}".format(self.bitline_layer)) + layer_pitch = getattr(self, "{}_pitch".format(self.bitline_layer)) + layer_width = getattr(self, "{}_width".format(self.bitline_layer)) - # adds the BL - self.bl_xoffset = layer_space + 0.5 * layer_width + # adds the BL so it aligns with the col mux + self.bl_xoffset = layer_pitch + 0.5 * layer_width top_pos = vector(self.bl_xoffset, self.height) pin_pos = vector(self.bl_xoffset, 0) self.add_path(self.bitline_layer, [top_pos, pin_pos]) @@ -248,8 +248,8 @@ class precharge(design.design): start=pin_pos, end=top_pos) - # adds the BR - self.br_xoffset = self.width - layer_space - 0.5 * layer_width + # adds the BR so it aligns with the col mux + self.br_xoffset = self.width - layer_pitch - 0.5 * layer_width top_pos = vector(self.br_xoffset, self.height) pin_pos = vector(self.br_xoffset, 0) self.add_path(self.bitline_layer, [top_pos, pin_pos]) diff --git a/compiler/tests/08_precharge_array_1rw1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py similarity index 100% rename from compiler/tests/08_precharge_array_1rw1r_test.py rename to compiler/tests/08_precharge_array_1rw_1r_test.py From b2b7e7800bd01ac27e4051a6f78764d549086205 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 16:39:05 -0700 Subject: [PATCH 343/521] Undo same bitline pitch --- compiler/pgates/precharge.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 278fef3d..893736f4 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -236,10 +236,9 @@ class precharge(design.design): Adds both bit-line and bit-line-bar to the module """ layer_pitch = getattr(self, "{}_pitch".format(self.bitline_layer)) - layer_width = getattr(self, "{}_width".format(self.bitline_layer)) - # adds the BL so it aligns with the col mux - self.bl_xoffset = layer_pitch + 0.5 * layer_width + # adds the BL + self.bl_xoffset = layer_pitch top_pos = vector(self.bl_xoffset, self.height) pin_pos = vector(self.bl_xoffset, 0) self.add_path(self.bitline_layer, [top_pos, pin_pos]) @@ -248,8 +247,8 @@ class precharge(design.design): start=pin_pos, end=top_pos) - # adds the BR so it aligns with the col mux - self.br_xoffset = self.width - layer_pitch - 0.5 * layer_width + # adds the BR + self.br_xoffset = self.width - layer_pitch top_pos = vector(self.br_xoffset, self.height) pin_pos = vector(self.br_xoffset, 0) self.add_path(self.bitline_layer, [top_pos, pin_pos]) From 3927c62e3269f9fa4a0860fdf0a259bc3a14477b Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 16:39:33 -0700 Subject: [PATCH 344/521] Undo extra space due to nwell spacing --- compiler/modules/hierarchical_decoder.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 2b624ddc..8b711031 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -191,7 +191,7 @@ class hierarchical_decoder(design.design): + self.predecoder_width \ + self.internal_routing_width \ + self.nand_width \ - + 2 * self.m1_pitch + + self.m1_space def route_inputs(self): """ Create input bus for the predecoders """ From 77c95b28da19b37ae638a50b85d53c7bb06bb206 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 16:39:46 -0700 Subject: [PATCH 345/521] Rename precharge test --- compiler/tests/08_precharge_array_1rw_1r_test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/tests/08_precharge_array_1rw_1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py index 1381b93a..dde36b23 100755 --- a/compiler/tests/08_precharge_array_1rw_1r_test.py +++ b/compiler/tests/08_precharge_array_1rw_1r_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class precharge_test(openram_test): +class precharge_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) From 249b5355ba8ed083e011c000c3f3fb3ed6f8b01f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 17:08:04 -0700 Subject: [PATCH 346/521] Adjust rbl route --- compiler/modules/bank.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 393631e5..2aa4e871 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -128,10 +128,10 @@ class bank(design.design): bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name) # This will ensure the pin is only on the top or bottom edge if port % 2: - via_offset = bl_pin.uc() + vector(0, 1.5 * self.m2_pitch) + via_offset = bl_pin.uc() + vector(0, self.m2_pitch) left_right_offset = vector(self.max_x_offset, via_offset.y) else: - via_offset = bl_pin.bc() - vector(0, 1.5 * self.m2_pitch) + via_offset = bl_pin.bc() - vector(0, self.m2_pitch) left_right_offset = vector(self.min_x_offset, via_offset.y) self.add_via_stack_center(from_layer=bl_pin.layer, to_layer="m3", From 7aafa438978cd4f38afa501d40357ddea0593ce6 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 4 Jun 2020 10:22:52 -0700 Subject: [PATCH 347/521] Connect RBL to bottom of precharge cell --- compiler/modules/bank.py | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 2aa4e871..92e4e8cd 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -123,23 +123,22 @@ class bank(design.design): def route_rbl(self, port): """ Route the rbl_bl and rbl_wl """ - - bl_pin_name = self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) - bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name) - # This will ensure the pin is only on the top or bottom edge + + # Connect the rbl to the port data pin + bl_pin = self.port_data_inst[port].get_pin("rbl_bl") if port % 2: - via_offset = bl_pin.uc() + vector(0, self.m2_pitch) - left_right_offset = vector(self.max_x_offset, via_offset.y) + pin_offset = bl_pin.uc() + left_right_offset = vector(self.max_x_offset, pin_offset.y) else: - via_offset = bl_pin.bc() - vector(0, self.m2_pitch) - left_right_offset = vector(self.min_x_offset, via_offset.y) + pin_offset = bl_pin.bc() + left_right_offset = vector(self.min_x_offset, pin_offset.y) self.add_via_stack_center(from_layer=bl_pin.layer, to_layer="m3", - offset=via_offset) + offset=pin_offset) self.add_layout_pin_segment_center(text="rbl_bl{0}".format(port), layer="m3", start=left_right_offset, - end=via_offset) + end=pin_offset) def route_bitlines(self, port): """ Route the bitlines depending on the port type rw, w, or r. """ From 717188f85c47dc8dccaa822ef5d7b20e5cdec2b5 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 4 Jun 2020 11:03:39 -0700 Subject: [PATCH 348/521] Change L shape of rbl route --- compiler/sram/sram_1bank.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 8dbcfaf4..f9a40545 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -320,7 +320,9 @@ class sram_1bank(sram_base): # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) - self.connect_hbus(src_pin, dest_pin) + self.add_wire(self.m2_stack[::-1], + [src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()]) + # self.connect_hbus(src_pin, dest_pin) def route_row_addr_dff(self): """ Connect the output of the row flops to the bank pins """ From e06dc3810a333819ba1fdb21258c77cfcbf94f41 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 4 Jun 2020 12:12:19 -0700 Subject: [PATCH 349/521] Move precharge pin to bottom --- compiler/pgates/precharge.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 893736f4..cfc2a688 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -191,14 +191,15 @@ class precharge(design.design): """ # adds the en contact to connect the gates to the en rail - # midway in the 4 M2 tracks - offset = self.lower_pmos_inst.get_pin("G").ul() \ - + vector(0, 0.5 * self.m2_pitch) + pin_offset = self.lower_pmos_inst.get_pin("G").lr() + # This is an extra space down for some techs with contact to active spacing + offset = pin_offset - vector(0, self.poly_space) self.add_via_stack_center(from_layer="poly", to_layer=self.en_layer, offset=offset) - - # adds the en rail on metal1 + self.add_path("poly", + [self.lower_pmos_inst.get_pin("G").bc(), offset]) + # adds the en rail self.add_layout_pin_segment_center(text="en_bar", layer=self.en_layer, start=offset.scale(0, 1), From 2fcecb7227e7de15fe78a3c9f3ab292062b9ae0c Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 4 Jun 2020 16:01:32 -0700 Subject: [PATCH 350/521] Variable zjog. 512 port address test. s8 port address working. --- compiler/base/hierarchy_layout.py | 7 +++--- compiler/modules/hierarchical_decoder.py | 22 ++++++------------- compiler/modules/port_address.py | 2 +- compiler/tests/18_port_address_1rw_1r_test.py | 4 ++++ compiler/tests/18_port_address_test.py | 4 ++++ 5 files changed, 20 insertions(+), 19 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index c6f6ff49..12a9826e 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -450,26 +450,27 @@ class layout(): path=coordinates, layer_widths=layer_widths) - def add_zjog(self, layer, start, end, first_direction="H", fixed_offset=None): + def add_zjog(self, layer, start, end, first_direction="H", var_offset=0.5, fixed_offset=None): """ Add a simple jog at the halfway point. If layer is a single value, it is a path. If layer is a tuple, it is a wire with preferred directions. """ + neg_offset = 1.0 - var_offset # vertical first if first_direction == "V": if fixed_offset: mid1 = vector(start.x, fixed_offset) else: - mid1 = vector(start.x, 0.5 * start.y + 0.5 * end.y) + mid1 = vector(start.x, neg_offset * start.y + var_offset * end.y) mid2 = vector(end.x, mid1.y) # horizontal first elif first_direction == "H": if fixed_offset: mid1 = vector(fixed_offset, start.y) else: - mid1 = vector(0.5 * start.x + 0.5 * end.x, start.y) + mid1 = vector(neg_offset * start.x + var_offset * end.x, start.y) mid2 = vector(mid1, end.y) else: debug.error("Invalid direction for jog -- must be H or V.") diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 8b711031..fbf8ef29 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -48,11 +48,18 @@ class hierarchical_decoder(design.design): self.setup_layout_constants() self.place_pre_decoder() self.place_row_decoder() + + self.height = max(self.predecoder_height, self.row_decoder_height) + self.bus_space + self.route_inputs() self.route_outputs() self.route_decoder_bus() self.route_vdd_gnd() + self.offset_all_coordinates() + + self.width = self.and_inst[0].rx() + self.m1_space + self.add_boundary() self.DRC_LVS() @@ -178,21 +185,6 @@ class hierarchical_decoder(design.design): # Extra bus space for supply contacts self.input_routing_width = self.num_inputs * self.bus_pitch + self.bus_space - # Calculates height and width of row-decoder - # Calculates height and width of hierarchical decoder - # Add extra pitch for good measure - self.height = max(self.predecoder_height, self.row_decoder_height) + self.bus_space - if (self.num_inputs == 4 or self.num_inputs == 5): - self.nand_width = self.and2.width - else: - self.nand_width = self.and3.width - - self.width = self.input_routing_width \ - + self.predecoder_width \ - + self.internal_routing_width \ - + self.nand_width \ - + self.m1_space - def route_inputs(self): """ Create input bus for the predecoders """ # Find the left-most predecoder diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 6293a79d..b0c24e1e 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -93,7 +93,7 @@ class port_address(design.design): decoder_out_pos = decoder_out_pin.rc() driver_in_pin = self.wordline_driver_inst.get_pin("in_{}".format(row)) driver_in_pos = driver_in_pin.lc() - self.add_zjog(self.route_layer, decoder_out_pos, driver_in_pos) + self.add_zjog(self.route_layer, decoder_out_pos, driver_in_pos, var_offset=0.3) self.add_via_stack_center(from_layer=decoder_out_pin.layer, to_layer=self.route_layer, diff --git a/compiler/tests/18_port_address_1rw_1r_test.py b/compiler/tests/18_port_address_1rw_1r_test.py index 402b30a0..33bff4ed 100755 --- a/compiler/tests/18_port_address_1rw_1r_test.py +++ b/compiler/tests/18_port_address_1rw_1r_test.py @@ -29,6 +29,10 @@ class port_address_1rw_1r_test(openram_test): debug.info(1, "Port address 16 rows") a = factory.create("port_address", cols=16, rows=16) self.local_check(a) + + debug.info(1, "Port address 512 rows") + a = factory.create("port_address", cols=256, rows=512) + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py index a2a8bf0b..11da333e 100755 --- a/compiler/tests/18_port_address_test.py +++ b/compiler/tests/18_port_address_test.py @@ -24,6 +24,10 @@ class port_address_test(openram_test): a = factory.create("port_address", cols=16, rows=16) self.local_check(a) + debug.info(1, "Port address 512 rows") + a = factory.create("port_address", cols=256, rows=512) + self.local_check(a) + globals.end_openram() # run the test from the command line From e14deff3d144f497126cab50675b0074bb7ae247 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 4 Jun 2020 16:03:39 -0700 Subject: [PATCH 351/521] Fixed offset in port_data --- compiler/modules/port_data.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 34ad4ca9..5e7ed8e5 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -732,8 +732,8 @@ class port_data(design.design): top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc() layer_pitch = getattr(self, "{}_pitch".format(top_bl_pin.layer)) - self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V", top_bl_pin.by() - layer_pitch) - self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V", top_bl_pin.by() - 2 * layer_pitch) + self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V", fixed_offset=top_bl_pin.by() - layer_pitch) + self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V", fixed_offset=top_bl_pin.by() - 2 * layer_pitch) def graph_exclude_precharge(self): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" From 08f6bd8d241bd6aaa591a134002d8c1cf307ae41 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Fri, 5 Jun 2020 02:53:03 -0700 Subject: [PATCH 352/521] optimize tx binning for area --- compiler/pgates/pgate.py | 146 ++++++++++++++++++++++++--------------- 1 file changed, 89 insertions(+), 57 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 918cd17b..8e18d4d2 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -17,22 +17,39 @@ from globals import OPTS if(OPTS.tech_name == "s8"): from tech import nmos_bins, pmos_bins, accuracy_requirement + class pgate(design.design): """ This is a module that implements some shared functions for parameterized gates. """ - def __init__(self, name, height=None): + def __init__(self, name, height=None, add_wells=True): """ Creates a generic cell """ design.design.__init__(self, name) if height: self.height = height elif not height: - # By default, we make it 10 M1 pitch tall - self.height = 10*self.m1_pitch - + # By default, something simple + self.height = 14 * self.m1_pitch + self.add_wells = add_wells + + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" + self.route_layer_width = getattr(self, "{}_width".format(self.route_layer)) + self.route_layer_space = getattr(self, "{}_space".format(self.route_layer)) + self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer)) + + # This is the space from a S/D contact to the supply rail + contact_to_vdd_rail_space = 0.5 * self.m1_width + self.m1_space + # This is a poly-to-poly of a flipped cell + poly_to_poly_gate_space = self.poly_extend_active + self.poly_space + self.top_bottom_space = max(contact_to_vdd_rail_space, + poly_to_poly_gate_space) + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -47,27 +64,27 @@ class pgate(design.design): """ Pure virtual function """ debug.error("Must over-ride create_layout.", -1) - def connect_pin_to_rail(self, inst, pin, supply): + def connect_pin_to_rail(self, inst, pin_name, supply_name): """ Connects a ptx pin to a supply rail. """ - source_pin = inst.get_pin(pin) - supply_pin = self.get_pin(supply) - if supply_pin.overlaps(source_pin): - return - - if supply == "gnd": - height = supply_pin.by() - source_pin.by() - elif supply == "vdd": - height = supply_pin.uy() - source_pin.by() - else: - debug.error("Invalid supply name.", -1) + supply_pin = self.get_pin(supply_name) - if abs(height) > 0: - self.add_rect(layer="m1", + source_pins = inst.get_pins(pin_name) + for source_pin in source_pins: + + if supply_name == "gnd": + height = supply_pin.by() - source_pin.by() + elif supply_name == "vdd": + height = supply_pin.uy() - source_pin.by() + else: + debug.error("Invalid supply name.", -1) + + debug.check(supply_pin.layer == source_pin.layer, "Supply pin is not on correct layer.") + self.add_rect(layer=source_pin.layer, offset=source_pin.ll(), height=height, width=source_pin.width()) - def route_input_gate(self, pmos_inst, nmos_inst, ypos, name, position="left"): + def route_input_gate(self, pmos_inst, nmos_inst, ypos, name, position="left", directions=None): """ Route the input gate to the left side of the cell for access. Position specifies to place the contact the left, center, or @@ -93,8 +110,6 @@ class pgate(design.design): # Center is completely symmetric. contact_width = contact.poly_contact.width - contact_m1_width = contact.poly_contact.second_layer_width - contact_m1_height = contact.poly_contact.second_layer_height if position == "center": contact_offset = left_gate_offset \ @@ -111,18 +126,16 @@ class pgate(design.design): else: debug.error("Invalid contact placement option.", -1) - if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=contact_offset) - - self.add_via_center(layers=self.poly_stack, - offset=contact_offset) + via = self.add_via_stack_center(from_layer="poly", + to_layer=self.route_layer, + offset=contact_offset, + directions=directions) self.add_layout_pin_rect_center(text=name, - layer="m1", + layer=self.route_layer, offset=contact_offset, - width=contact_m1_width, - height=contact_m1_height) + width=via.mod.second_layer_width, + height=via.mod.second_layer_height) # This is to ensure that the contact is # connected to the gate mid_point = contact_offset.scale(0.5, 1) \ @@ -137,7 +150,7 @@ class pgate(design.design): # This should match the cells in the cell library self.nwell_y_offset = 0.48 * self.height - full_height = self.height + 0.5* self.m1_width + full_height = self.height + 0.5 * self.m1_width # FIXME: float rounding problem if "nwell" in layer: @@ -148,12 +161,12 @@ class pgate(design.design): nwell_height = nwell_max_offset - self.nwell_y_offset self.add_rect(layer="nwell", offset=nwell_position, - width=self.well_width, + width=self.width + 2 * self.well_extend_active, height=nwell_height) if "vtg" in layer: self.add_rect(layer="vtg", offset=nwell_position, - width=self.well_width, + width=self.width + 2 * self.well_extend_active, height=nwell_height) # Start this half a rail width below the cell @@ -164,12 +177,12 @@ class pgate(design.design): pwell_height = self.nwell_y_offset - pwell_position.y self.add_rect(layer="pwell", offset=pwell_position, - width=self.well_width, + width=self.width + 2 * self.well_extend_active, height=pwell_height) if "vtg" in layer: self.add_rect(layer="vtg", offset=pwell_position, - width=self.well_width, + width=self.width + 2 * self.well_extend_active, height=pwell_height) def add_nwell_contact(self, pmos, pmos_pos): @@ -194,12 +207,10 @@ class pgate(design.design): self.nwell_contact = self.add_via_center(layers=layer_stack, offset=contact_offset, implant_type="n", - well_type="n") - if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=contact_offset) + well_type="n", + directions=("V", "V")) - self.add_rect_center(layer="m1", + self.add_rect_center(layer=self.route_layer, offset=contact_offset + vector(0, 0.5 * (self.height - contact_offset.y)), width=self.nwell_contact.mod.second_layer_width, height=self.height - contact_offset.y) @@ -249,13 +260,10 @@ class pgate(design.design): self.pwell_contact= self.add_via_center(layers=layer_stack, offset=contact_offset, implant_type="p", - well_type="p") - - if hasattr(self, "li_stack"): - self.add_via_center(layers=self.li_stack, - offset=contact_offset) - - self.add_rect_center(layer="m1", + well_type="p", + directions=("V", "V")) + + self.add_rect_center(layer=self.route_layer, offset=contact_offset.scale(1, 0.5), width=self.pwell_contact.mod.second_layer_width, height=contact_offset.y) @@ -279,13 +287,33 @@ class pgate(design.design): # offset=implant_offset, # width=implant_width, # height=implant_height) + + def route_supply_rails(self): + """ Add vdd/gnd rails to the top and bottom. """ + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, 0), + width=self.width) + + self.add_layout_pin_rect_center(text="vdd", + layer=self.route_layer, + offset=vector(0.5 * self.width, self.height), + width=self.width) def determine_width(self): """ Determine the width based on the well contacts (assumed to be on the right side) """ + + # It was already set or is left as default (minimum) # Width is determined by well contact and spacing and allowing a supply via between each cell - self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width - self.well_width = self.width + 2 * self.nwell_enclose_active - # Height is an input parameter, so it is not recomputed. + if self.add_wells: + width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width + # Height is an input parameter, so it is not recomputed. + else: + max_active_xoffset = self.find_highest_layer_coords("active").x + max_route_xoffset = self.find_highest_layer_coords(self.route_layer).x + 0.5 * self.m1_space + width = max(max_active_xoffset, max_route_xoffset) + + self.width = width @staticmethod def bin_width(tx_type, target_width): @@ -307,16 +335,20 @@ class pgate(design.design): base_bins = [] scaled_bins = [] scaling_factors = [] - scaled_bins.append(bins[-1]) - base_bins.append(bins[-1]) - scaling_factors.append(1) - for width in bins[0:-1]: + + for width in bins: m = math.ceil(target_width / width) base_bins.append(width) scaling_factors.append(m) scaled_bins.append(m * width) - - select = bisect_left(scaled_bins, target_width) + + select = -1 + for i in reversed(range(0, len(scaled_bins))): + if abs(target_width - scaled_bins[i])/target_width <= 1-accuracy_requirement: + select = i + break + if select == -1: + debug.error("failed to bin tx size {}, try reducing accuracy requirement".format(target_width), 1) scaling_factor = scaling_factors[select] scaled_bin = scaled_bins[select] selected_bin = base_bins[select] @@ -346,4 +378,4 @@ class pgate(design.design): return(scaled_bins) def bin_accuracy(self, ideal_width, width): - return abs(1-(ideal_width - width)/ideal_width) \ No newline at end of file + return abs(1-(ideal_width - width)/ideal_width) From fb3acae9087de2da778d2d032a962649e681cf79 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jun 2020 09:44:30 -0700 Subject: [PATCH 353/521] PEP8 format testutils. --- compiler/tests/testutils.py | 136 ++++++++++++++++++------------------ 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 4cae1a9c..eb75fc44 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -5,23 +5,21 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import unittest,warnings -import pdb,traceback -import sys,os,glob,copy -import shutil +import unittest +import sys, os, glob sys.path.append(os.getenv("OPENRAM_HOME")) from globals import OPTS import debug + class openram_test(unittest.TestCase): """ Base unit test that we have some shared classes in. """ - def local_drc_check(self, w): self.reset() - tempgds = "{0}{1}.gds".format(OPTS.openram_temp,w.name) + tempgds = "{0}{1}.gds".format(OPTS.openram_temp, w.name) w.gds_write(tempgds) import verify @@ -36,8 +34,8 @@ class openram_test(unittest.TestCase): self.reset() - tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name) - tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name) + tempspice = "{0}{1}.sp".format(OPTS.openram_temp, a.name) + tempgds = "{0}{1}.gds".format(OPTS.openram_temp, a.name) a.lvs_write(tempspice) # cannot write gds in netlist_only mode @@ -56,34 +54,36 @@ class openram_test(unittest.TestCase): # Only allow DRC to fail and LVS to pass if we are using magic if "magic" in OPTS.drc_exe and lvs_result == 0 and drc_result != 0: - #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) - #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) - #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) + # import shutil + # zip_file = "/tmp/{0}_{1}".format(a.name, os.getpid()) + # debug.info(0, "Archiving failed files to {}.zip".format(zip_file)) + # shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) debug.warning("DRC failed but LVS passed: {}".format(a.name)) - #self.fail("DRC failed but LVS passed: {}".format(a.name)) + # self.fail("DRC failed but LVS passed: {}".format(a.name)) elif drc_result != 0: - #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) - #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) - #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) + # import shutil + # zip_file = "/tmp/{0}_{1}".format(a.name, os.getpid()) + # debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) + # shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) self.fail("DRC failed: {}".format(a.name)) if lvs_result != 0: - #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) - #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) - #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) + # import shutil + # zip_file = "/tmp/{0}_{1}".format(a.name, os.getpid()) + # debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) + # shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) self.fail("LVS mismatch: {}".format(a.name)) - # For debug... - #import pdb; pdb.set_trace() + # import pdb; pdb.set_trace() if OPTS.purge_temp: self.cleanup() def run_pex(self, a, output=None): if output == None: output = OPTS.openram_temp + a.name + ".pex.netlist" - tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name) - tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name) + tempspice = "{0}{1}.sp".format(OPTS.openram_temp, a.name) + tempgds = "{0}{1}.gds".format(OPTS.openram_temp, a.name) import verify result=verify.run_pex(a.name, tempgds, tempspice, output=output, final_verification=False) @@ -97,8 +97,8 @@ class openram_test(unittest.TestCase): """ debug.info(1, "Finding feasible period for current test.") delay_obj.set_load_slew(load, slew) - test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period. - delay_obj.analysis_init(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1)) + test_port = delay_obj.read_ports[0] # Only test one port, assumes other ports have similar period. + delay_obj.analysis_init(probe_address="1" * sram.addr_size, probe_data=sram.word_size - 1) delay_obj.find_feasible_period_one_port(test_port) return delay_obj.period @@ -130,29 +130,27 @@ class openram_test(unittest.TestCase): for k in data.keys(): if type(data[k])==list: for i in range(len(data[k])): - if not self.isclose(k,data[k][i],golden_data[k][i],error_tolerance): + if not self.isclose(k, data[k][i], golden_data[k][i], error_tolerance): data_matches = False else: - if not self.isclose(k,data[k],golden_data[k],error_tolerance): + if not self.isclose(k, data[k], golden_data[k], error_tolerance): data_matches = False if not data_matches: import pprint data_string=pprint.pformat(data) - debug.error("Results exceeded {:.1f}% tolerance compared to golden results:\n".format(error_tolerance*100)+data_string) + debug.error("Results exceeded {:.1f}% tolerance compared to golden results:\n".format(error_tolerance * 100) + data_string) return data_matches - - - def isclose(self,key,value,actual_value,error_tolerance=1e-2): + def isclose(self, key, value, actual_value, error_tolerance=1e-2): """ This is used to compare relative values. """ import debug - relative_diff = self.relative_diff(value,actual_value) + relative_diff = self.relative_diff(value, actual_value) check = relative_diff <= error_tolerance if check: - debug.info(2,"CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key,value,actual_value,relative_diff*100)) + debug.info(2, "CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key, value, actual_value, relative_diff * 100)) return True else: - debug.error("NOT CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key,value,actual_value,relative_diff*100)) + debug.error("NOT CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key, value, actual_value, relative_diff * 100)) return False def relative_diff(self, value1, value2): @@ -169,18 +167,14 @@ class openram_test(unittest.TestCase): # Get normalization value norm_value = abs(max(value1, value2)) - # Edge case where greater is a zero - if norm_value == 0: - min_value = abs(min(value1, value2)) return abs(value1 - value2) / norm_value - - def relative_compare(self, value,actual_value,error_tolerance): + def relative_compare(self, value, actual_value, error_tolerance): """ This is used to compare relative values. """ if (value==actual_value): # if we don't need a relative comparison! return True - return (abs(value - actual_value) / max(value,actual_value) <= error_tolerance) + return (abs(value - actual_value) / max(value, actual_value) <= error_tolerance) def isapproxdiff(self, filename1, filename2, error_tolerance=0.001): """Compare two files. @@ -218,23 +212,22 @@ class openram_test(unittest.TestCase): line_num+=1 line1 = fp1.readline().decode('utf-8') line2 = fp2.readline().decode('utf-8') - #print("line1:",line1) - #print("line2:",line2) + # print("line1:", line1) + # print("line2:", line2) # 1. Find all of the floats using a regex line1_floats=rx.findall(line1) line2_floats=rx.findall(line2) - debug.info(3,"line1_floats: "+str(line1_floats)) - debug.info(3,"line2_floats: "+str(line2_floats)) - + debug.info(3, "line1_floats: " + str(line1_floats)) + debug.info(3, "line2_floats: " + str(line2_floats)) # 2. Remove the floats from the string for f in line1_floats: - line1=line1.replace(f,"",1) + line1=line1.replace(f, "", 1) for f in line2_floats: - line2=line2.replace(f,"",1) - #print("line1:",line1) - #print("line2:",line2) + line2=line2.replace(f, "", 1) + # print("line1:", line1) + # print("line2:", line2) # 3. Convert to floats rather than strings line1_floats = [float(x) for x in line1_floats] @@ -242,29 +235,29 @@ class openram_test(unittest.TestCase): # 4. Check if remaining string matches if line1 != line2: - #Uncomment if you want to see all the individual chars of the two lines - #print(str([i for i in line1])) - #print(str([i for i in line2])) + # Uncomment if you want to see all the individual chars of the two lines + # print(str([i for i in line1])) + # print(str([i for i in line2])) if mismatches==0: - debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2)) + debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1, filename2)) mismatches += 1 - debug.error("MISMATCH Line ({0}):\n{1}\n!=\n{2}".format(line_num,line1.rstrip('\n'),line2.rstrip('\n'))) + debug.error("MISMATCH Line ({0}):\n{1}\n!=\n{2}".format(line_num, line1.rstrip('\n'), line2.rstrip('\n'))) # 5. Now compare that the floats match elif len(line1_floats)!=len(line2_floats): if mismatches==0: - debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2)) + debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1, filename2)) mismatches += 1 - debug.error("MISMATCH Line ({0}) Length {1} != {2}".format(line_num,len(line1_floats),len(line2_floats))) + debug.error("MISMATCH Line ({0}) Length {1} != {2}".format(line_num, len(line1_floats), len(line2_floats))) else: - for (float1,float2) in zip(line1_floats,line2_floats): - relative_diff = self.relative_diff(float1,float2) + for (float1, float2) in zip(line1_floats, line2_floats): + relative_diff = self.relative_diff(float1, float2) check = relative_diff <= error_tolerance if not check: if mismatches==0: - debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2)) + debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1, filename2)) mismatches += 1 - debug.error("MISMATCH Line ({0}) Float {1} != {2} diff: {3:.1f}%".format(line_num,float1,float2,relative_diff*100)) + debug.error("MISMATCH Line ({0}) Float {1} != {2} diff: {3:.1f}%".format(line_num, float1, float2, relative_diff * 100)) # Only show the first 10 mismatch lines if not line1 and not line2 or mismatches>10: @@ -275,19 +268,18 @@ class openram_test(unittest.TestCase): # Never reached return False - - def isdiff(self,filename1,filename2): + def isdiff(self, filename1, filename2): """ This is used to compare two files and display the diff if they are different.. """ import debug import filecmp import difflib - check = filecmp.cmp(filename1,filename2) + check = filecmp.cmp(filename1, filename2) if not check: - debug.error("MISMATCH file1={0} file2={1}".format(filename1,filename2)) - f1 = open(filename1,mode="r",encoding='utf-8') + debug.error("MISMATCH file1={0} file2={1}".format(filename1, filename2)) + f1 = open(filename1, mode="r", encoding='utf-8') s1 = f1.readlines() f1.close() - f2 = open(filename2,mode="r",encoding='utf-8') + f2 = open(filename2, mode="r", encoding='utf-8') s2 = f2.readlines() f2.close() mismatches=0 @@ -302,10 +294,13 @@ class openram_test(unittest.TestCase): return False return False else: - debug.info(2,"MATCH {0} {1}".format(filename1,filename2)) + debug.info(2, "MATCH {0} {1}".format(filename1, filename2)) return True + def dbg(): + import pdb; pdb.set_trace() + def header(filename, technology): # Skip the header for gitlab regression import getpass @@ -319,14 +314,18 @@ def header(filename, technology): print("|=========" + tst.center(60) + "=========|") print("|=========" + technology.center(60) + "=========|") print("|=========" + filename.center(60) + "=========|") - from globals import OPTS + from globals import OPTS print("|=========" + OPTS.openram_temp.center(60) + "=========|") print("|==============================================================================|") + def debugTestRunner(post_mortem=None): """unittest runner doing post mortem debugging on failing tests""" + import pdb + import traceback if post_mortem is None and not OPTS.purge_temp: post_mortem = pdb.post_mortem + class DebugTestResult(unittest.TextTestResult): def addError(self, test, err): # called before tearDown() @@ -334,9 +333,10 @@ def debugTestRunner(post_mortem=None): if post_mortem: post_mortem(err[2]) super(DebugTestResult, self).addError(test, err) + def addFailure(self, test, err): traceback.print_exception(*err) - if post_mortem: + if post_mortem: post_mortem(err[2]) super(DebugTestResult, self).addFailure(test, err) return unittest.TextTestRunner(resultclass=DebugTestResult) From 68ffb94d2e36ae22f5ff3198577d0489798b6bdd Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jun 2020 09:55:57 -0700 Subject: [PATCH 354/521] Rename 05 test to 14 --- ...a_pbitcell_array_test.py => 14_replica_pbitcell_array_test.py} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename compiler/tests/{05_replica_pbitcell_array_test.py => 14_replica_pbitcell_array_test.py} (100%) diff --git a/compiler/tests/05_replica_pbitcell_array_test.py b/compiler/tests/14_replica_pbitcell_array_test.py similarity index 100% rename from compiler/tests/05_replica_pbitcell_array_test.py rename to compiler/tests/14_replica_pbitcell_array_test.py From 2e7f9395f2e3022b5cd086ddf461888b9f8dbf04 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jun 2020 09:57:16 -0700 Subject: [PATCH 355/521] Rename 05 test to 14 --- .../tests/05_replica_bitcell_array_test.py | 38 ------------------- .../tests/14_replica_bitcell_array_test.py | 9 ++++- 2 files changed, 7 insertions(+), 40 deletions(-) delete mode 100755 compiler/tests/05_replica_bitcell_array_test.py diff --git a/compiler/tests/05_replica_bitcell_array_test.py b/compiler/tests/05_replica_bitcell_array_test.py deleted file mode 100755 index d229b99c..00000000 --- a/compiler/tests/05_replica_bitcell_array_test.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California -# All rights reserved. -# -import unittest -from testutils import * -import sys,os -sys.path.append(os.getenv("OPENRAM_HOME")) -import globals -from globals import OPTS -from sram_factory import factory -import debug - -class replica_bitcell_array_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 0 - OPTS.num_w_ports = 0 - - factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) - self.local_check(a) - - globals.end_openram() - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index 19413cd5..d229b99c 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -19,10 +19,15 @@ class replica_bitcell_array_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - debug.info(2, "Testing 4x4 array for 6t_cell") + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + + factory.reset() + debug.info(2, "Testing 4x4 array for bitcell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) self.local_check(a) - + globals.end_openram() # run the test from the command line From a62b85a6b154941158552b430166e4e9462299f5 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jun 2020 11:29:31 -0700 Subject: [PATCH 356/521] Update mirroring in port_data for bitcell mirrored arrays --- compiler/modules/port_data.py | 21 ++++++++----------- compiler/modules/precharge_array.py | 6 +++--- compiler/modules/sense_amp_array.py | 20 ++++++++---------- .../modules/single_level_column_mux_array.py | 6 +++--- compiler/modules/write_driver_array.py | 5 +++-- compiler/modules/write_mask_and_array.py | 4 ++-- ...ngle_level_column_mux_array_1rw_1r_test.py | 4 ++-- ...le_level_column_mux_array_pbitcell_test.py | 8 +++---- .../tests/08_precharge_array_1rw_1r_test.py | 16 ++++++-------- compiler/tests/08_precharge_array_test.py | 3 +-- compiler/tests/09_sense_amp_array_test.py | 1 - compiler/tests/18_port_data_1rw_1r_test.py | 1 + 12 files changed, 43 insertions(+), 52 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 5e7ed8e5..106f2e85 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -178,14 +178,17 @@ class port_data(design.design): # Extra column +1 is for RBL # Precharge will be shifted left if needed + # Column offset is set to port so extra column can be on left or right + # and mirroring happens correctly self.precharge_array = factory.create(module_type="precharge_array", columns=self.num_cols + 1, - port=self.port, bitcell_bl=self.bl_names[self.port], - bitcell_br=self.br_names[self.port]) + bitcell_br=self.br_names[self.port], + column_offset=self.port - 1) self.add_mod(self.precharge_array) if self.port in self.read_ports: + # RBLs don't get a sense amp self.sense_amp_array = factory.create(module_type="sense_amp_array", word_size=self.word_size, words_per_row=self.words_per_row) @@ -194,9 +197,9 @@ class port_data(design.design): self.sense_amp_array = None if self.col_addr_size > 0: + # RBLs dont get a col mux self.column_mux_array = factory.create(module_type="column_mux_array", columns=self.num_cols, - port=self.port, word_size=self.word_size, bitcell_bl=self.bl_names[self.port], bitcell_br=self.br_names[self.port]) @@ -205,17 +208,18 @@ class port_data(design.design): self.column_mux_array = None if self.port in self.write_ports: + # RBLs dont get a write driver self.write_driver_array = factory.create(module_type="write_driver_array", columns=self.num_cols, word_size=self.word_size, write_size=self.write_size) self.add_mod(self.write_driver_array) if self.write_size is not None: + # RBLs don't get a write mask self.write_mask_and_array = factory.create(module_type="write_mask_and_array", columns=self.num_cols, word_size=self.word_size, - write_size=self.write_size, - port = self.port) + write_size=self.write_size) self.add_mod(self.write_mask_and_array) else: self.write_mask_and_array = None @@ -248,13 +252,6 @@ class port_data(design.design): self.precharge = factory.create(module_type="precharge", bitcell_bl=self.bl_names[0], bitcell_br=self.br_names[0]) - # We create a dummy here to get bl/br names to add those pins to this - # module, which happens before we create the real precharge_array - self.precharge_array = factory.create(module_type="precharge_array", - columns=self.num_cols + 1, - port=self.port, - bitcell_bl=self.bl_names[self.port], - bitcell_br=self.br_names[self.port]) def create_precharge_array(self): """ Creating Precharge """ diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 2acb1063..84f27fba 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -18,16 +18,16 @@ class precharge_array(design.design): of bit line columns, height is the height of the bit-cell array. """ - def __init__(self, name, columns, port, size=1, bitcell_bl="bl", bitcell_br="br"): + def __init__(self, name, columns, size=1, bitcell_bl="bl", bitcell_br="br", column_offset=0): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br)) self.columns = columns self.size = size - self.port = port self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br + self.column_offset = column_offset self.create_netlist() if not OPTS.netlist_only: @@ -106,7 +106,7 @@ class precharge_array(design.design): xoffset = 0 for i in range(self.columns): tempx = xoffset - if cell_properties.bitcell.mirror.y and (i + 1 + self.port) % 2: + if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2: mirror = "MY" tempx = tempx + self.pc_cell.width else: diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index cb413c45..c532c54a 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -20,7 +20,7 @@ class sense_amp_array(design.design): Dynamically generated sense amp array for all bitlines. """ - def __init__(self, name, word_size, words_per_row): + def __init__(self, name, word_size, words_per_row, column_offset=0): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("word_size {0}".format(word_size)) @@ -28,6 +28,7 @@ class sense_amp_array(design.design): self.word_size = word_size self.words_per_row = words_per_row + self.column_offset = column_offset self.row_size = self.word_size * self.words_per_row self.create_netlist() @@ -102,25 +103,22 @@ class sense_amp_array(design.design): def place_sense_amp_array(self): from tech import cell_properties if self.bitcell.width > self.amp.width: - amp_spacing = self.bitcell.width * self.words_per_row + amp_spacing = self.bitcell.width else: - amp_spacing = self.amp.width * self.words_per_row + amp_spacing = self.amp.width - for i in range(0, self.word_size): - xoffset = amp_spacing * i + for i in range(0, self.row_size, self.words_per_row): + index = int(i / self.words_per_row) + xoffset = i * amp_spacing - # align the xoffset to the grid of bitcells. This way we - # know when to do the mirroring. - grid_x = int(xoffset / self.amp.width) - - if cell_properties.bitcell.mirror.y and grid_x % 2: + if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2: mirror = "MY" xoffset = xoffset + self.amp.width else: mirror = "" amp_position = vector(xoffset, 0) - self.local_insts[i].place(offset=amp_position, mirror=mirror) + self.local_insts[index].place(offset=amp_position, mirror=mirror) def add_layout_pins(self): for i in range(len(self.local_insts)): diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 3d80525a..cc38cb45 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -20,17 +20,17 @@ class single_level_column_mux_array(design.design): Array of column mux to read the bitlines through the 6T. """ - def __init__(self, name, columns, port, word_size, bitcell_bl="bl", bitcell_br="br"): + def __init__(self, name, columns, word_size, bitcell_bl="bl", bitcell_br="br", column_offset=0): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("cols: {0} word_size: {1} bl: {2} br: {3}".format(columns, word_size, bitcell_bl, bitcell_br)) self.columns = columns - self.port = port self.word_size = word_size self.words_per_row = int(self.columns / self.word_size) self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br + self.column_offset = column_offset if "li" in layer: self.col_mux_stack = self.li_stack @@ -118,7 +118,7 @@ class single_level_column_mux_array(design.design): # For every column, add a pass gate for col_num in range(self.columns): xoffset = col_num * self.mux.width - if cell_properties.bitcell.mirror.y and (col_num + self.port) % 2: + if cell_properties.bitcell.mirror.y and (col_num + self.column_offset) % 2: mirror = "MY" xoffset = xoffset + self.mux.width else: diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 49e830e2..105cacc0 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -18,7 +18,7 @@ class write_driver_array(design.design): Dynamically generated write driver array of all bitlines. """ - def __init__(self, name, columns, word_size, write_size=None): + def __init__(self, name, columns, word_size, write_size=None, column_offset=0): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) @@ -27,6 +27,7 @@ class write_driver_array(design.design): self.columns = columns self.word_size = word_size self.write_size = write_size + self.column_offset = column_offset self.words_per_row = int(columns / word_size) if self.write_size: @@ -128,7 +129,7 @@ class write_driver_array(design.design): index = int(i / self.words_per_row) xoffset = i * self.driver_spacing - if cell_properties.bitcell.mirror.y and i % 2: + if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2: mirror = "MY" xoffset = xoffset + self.driver.width else: diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index e660d519..c949fe58 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -18,7 +18,7 @@ class write_mask_and_array(design.design): The write mask AND array goes between the write driver array and the sense amp array. """ - def __init__(self, name, columns, word_size, write_size, port=0): + def __init__(self, name, columns, word_size, write_size, column_offset=0): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) @@ -28,7 +28,7 @@ class write_mask_and_array(design.design): self.columns = columns self.word_size = word_size self.write_size = write_size - self.port = port + self.column_offset self.words_per_row = int(columns / word_size) self.num_wmasks = int(word_size / write_size) diff --git a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py index a8d804c9..2a3a8f87 100755 --- a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py +++ b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py @@ -26,11 +26,11 @@ class single_level_column_mux_test(openram_test): OPTS.num_w_ports = 0 debug.info(1, "Testing sample for 4-way column_mux_array port 0") - a = factory.create(module_type="single_level_column_mux_array", columns=8, port=0, word_size=2, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array port 1") - a = factory.create(module_type="single_level_column_mux_array", columns=8, port=0, word_size=2, bitcell_bl="bl1", bitcell_br="br1") + a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py b/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py index 7feb067e..663ff075 100755 --- a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py +++ b/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py @@ -29,19 +29,19 @@ class single_level_column_mux_pbitcell_test(openram_test): factory.reset() debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") - a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=8, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array in multi-port") - a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)") - a = factory.create(module_type="single_level_column_mux_array", columns=32, port=0, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)") - a = factory.create(module_type="single_level_column_mux_array", columns=32, port=3, word_size=4, bitcell_bl="bl2", bitcell_br="br2") + a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2", column_offset=3) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/08_precharge_array_1rw_1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py index dde36b23..7d54e02b 100755 --- a/compiler/tests/08_precharge_array_1rw_1r_test.py +++ b/compiler/tests/08_precharge_array_1rw_1r_test.py @@ -28,18 +28,14 @@ class precharge_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 factory.reset() - debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell") - pc = factory.create(module_type="precharge_array", columns=3, port=0, bitcell_bl="bl0", bitcell_br="br0") + debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)") + pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(pc) + + debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 1)") + pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0", column_offset=1) self.local_check(pc) - # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") - # pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0") - # self.local_check(pc) - - # debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)") - # pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2") - # self.local_check(pc) - globals.end_openram() # run the test from the command line diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index c3b823b3..47843ca3 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -21,9 +21,8 @@ class precharge_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - # check precharge array in single port debug.info(2, "Checking 3 column precharge") - pc = factory.create(module_type="precharge_array", columns=3, port=0) + pc = factory.create(module_type="precharge_array", columns=3) self.local_check(pc) globals.end_openram() diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index 459113f2..c71a75e8 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -21,7 +21,6 @@ class sense_amp_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1) self.local_check(a) diff --git a/compiler/tests/18_port_data_1rw_1r_test.py b/compiler/tests/18_port_data_1rw_1r_test.py index 8081416e..3d415ec0 100755 --- a/compiler/tests/18_port_data_1rw_1r_test.py +++ b/compiler/tests/18_port_data_1rw_1r_test.py @@ -13,6 +13,7 @@ from globals import OPTS from sram_factory import factory import debug + class port_data_1rw_1r_test(openram_test): def runTest(self): From 4fef632dceb4ad9cb5d6f4ab29bbdaacf7f837af Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jun 2020 12:13:41 -0700 Subject: [PATCH 357/521] Fix syntax error --- compiler/modules/write_mask_and_array.py | 2 +- compiler/tests/07_single_level_column_mux_array_test.py | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index c949fe58..9c077ed7 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -28,7 +28,7 @@ class write_mask_and_array(design.design): self.columns = columns self.word_size = word_size self.write_size = write_size - self.column_offset + self.column_offset = column_offset self.words_per_row = int(columns / word_size) self.num_wmasks = int(word_size / write_size) diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index ff7ec1c9..b1f74eba 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -21,15 +21,15 @@ class single_level_column_mux_test(openram_test): globals.init_openram(config_file) debug.info(1, "Testing sample for 2-way column_mux_array") - a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=8) + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8) self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array") - a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=4) + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4) self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array") - a = factory.create(module_type="single_level_column_mux_array", columns=32, port=0, word_size=4) + a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4) self.local_check(a) globals.end_openram() From 00b51f546478b6a509541b4b5713a460d1d922bd Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jun 2020 13:49:32 -0700 Subject: [PATCH 358/521] PEP8 format replica_bitcell_array --- compiler/modules/replica_bitcell_array.py | 148 ++++++++++------------ 1 file changed, 69 insertions(+), 79 deletions(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index ff2260d3..05cb1ac6 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -32,8 +32,10 @@ class replica_bitcell_array(design.design): self.right_rbl = right_rbl self.bitcell_ports = bitcell_ports - debug.check(left_rbl+right_rbl==len(self.all_ports),"Invalid number of RBLs for port configuration.") - debug.check(left_rbl+right_rbl==len(self.bitcell_ports),"Bitcell ports must match total RBLs.") + debug.check(left_rbl + right_rbl == len(self.all_ports), + "Invalid number of RBLs for port configuration.") + debug.check(left_rbl + right_rbl == len(self.bitcell_ports), + "Bitcell ports must match total RBLs.") # Two dummy rows/cols plus replica for each port self.extra_rows = 2 + left_rbl + right_rbl @@ -45,8 +47,7 @@ class replica_bitcell_array(design.design): # We don't offset this because we need to align # the replica bitcell in the control logic - #self.offset_all_coordinates() - + # self.offset_all_coordinates() def create_netlist(self): """ Create and connect the netlist """ @@ -90,15 +91,15 @@ class replica_bitcell_array(design.design): # Replica bitlines self.replica_columns = {} - for bit in range(self.left_rbl+self.right_rbl): + for bit in range(self.left_rbl + self.right_rbl): # Creating left_rbl if bit1 port) for port in range(self.left_rbl): # Make names for all RBLs - wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))] + wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x), port) for x in range(len(self.cell.get_all_wl_names()))] # Keep track of the pin that is the RBL self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]] self.replica_col_wl_names.extend(wl_names) # Regular WLs self.replica_col_wl_names.extend(self.bitcell_array_wl_names) # Right port WLs (one dummy for each port when we allow >1 port) - for port in range(self.left_rbl,self.left_rbl+self.right_rbl): + for port in range(self.left_rbl, self.left_rbl + self.right_rbl): # Make names for all RBLs - wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))] + wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x), port) for x in range(len(self.cell.get_all_wl_names()))] # Keep track of the pin that is the RBL self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]] self.replica_col_wl_names.extend(wl_names) @@ -195,14 +195,13 @@ class replica_bitcell_array(design.design): # Left/right dummy columns are connected identically to the replica column self.dummy_col_wl_names = self.replica_col_wl_names - # Per port bitline names self.replica_bl_names = {} self.replica_wl_names = {} # Array of all port bitline names - for port in range(self.left_rbl+self.right_rbl): - left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x),port) for x in range(len(self.all_ports))] - right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x),port) for x in range(len(self.all_ports))] + for port in range(self.left_rbl + self.right_rbl): + left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x), port) for x in range(len(self.all_ports))] + right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x), port) for x in range(len(self.all_ports))] # Keep track of the left pins that are the RBL self.rbl_bl_names[port]=left_names[self.bitcell_ports[port]] self.rbl_br_names[port]=right_names[self.bitcell_ports[port]] @@ -210,28 +209,25 @@ class replica_bitcell_array(design.design): bl_names = [x for t in zip(left_names, right_names) for x in t] self.replica_bl_names[port] = bl_names - wl_names = ["rbl_{0}_{1}".format(x,port) for x in self.cell.get_all_wl_names()] - #wl_names[port] = "rbl_wl{}".format(port) + wl_names = ["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()] self.replica_wl_names[port] = wl_names - # External pins self.add_pin_list(self.bitcell_array_bl_names, "INOUT") # Need to sort by port order since dictionary values may not be in order bl_names = [self.rbl_bl_names[x] for x in sorted(self.rbl_bl_names.keys())] br_names = [self.rbl_br_names[x] for x in sorted(self.rbl_br_names.keys())] - for (bl_name,br_name) in zip(bl_names,br_names): - self.add_pin(bl_name,"OUTPUT") - self.add_pin(br_name,"OUTPUT") + for (bl_name, br_name) in zip(bl_names, br_names): + self.add_pin(bl_name, "OUTPUT") + self.add_pin(br_name, "OUTPUT") self.add_pin_list(self.bitcell_array_wl_names, "INPUT") # Need to sort by port order since dictionary values may not be in order wl_names = [self.rbl_wl_names[x] for x in sorted(self.rbl_wl_names.keys())] for pin_name in wl_names: - self.add_pin(pin_name,"INPUT") + self.add_pin(pin_name, "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - def create_instances(self): """ Create the module instances used in this design """ @@ -247,77 +243,75 @@ class replica_bitcell_array(design.design): # Replica columns self.replica_col_inst = {} - for port in range(self.left_rbl+self.right_rbl): + for port in range(self.left_rbl + self.right_rbl): self.replica_col_inst[port]=self.add_inst(name="replica_col_{}".format(port), - mod=self.replica_columns[port]) + mod=self.replica_columns[port]) self.connect_inst(self.replica_bl_names[port] + self.replica_col_wl_names + supplies) - # Dummy rows under the bitcell array (connected with with the replica cell wl) self.dummy_row_replica_inst = {} - for port in range(self.left_rbl+self.right_rbl): + for port in range(self.left_rbl + self.right_rbl): self.dummy_row_replica_inst[port]=self.add_inst(name="dummy_row_{}".format(port), mod=self.dummy_row) self.connect_inst(self.dummy_row_bl_names + self.replica_wl_names[port] + supplies) - # Top/bottom dummy rows or col caps self.dummy_row_bot_inst=self.add_inst(name="dummy_row_bot", mod=self.edge_row) - self.connect_inst(self.dummy_row_bl_names + [x+"_bot" for x in self.dummy_cell_wl_names] + supplies) + self.connect_inst(self.dummy_row_bl_names + [x + "_bot" for x in self.dummy_cell_wl_names] + supplies) self.dummy_row_top_inst=self.add_inst(name="dummy_row_top", mod=self.edge_row) - self.connect_inst(self.dummy_row_bl_names + [x+"_top" for x in self.dummy_cell_wl_names] + supplies) - + self.connect_inst(self.dummy_row_bl_names + [x + "_top" for x in self.dummy_cell_wl_names] + supplies) # Left/right Dummy columns self.dummy_col_left_inst=self.add_inst(name="dummy_col_left", mod=self.edge_col_left) - self.connect_inst([x+"_left" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies) + self.connect_inst([x + "_left" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies) self.dummy_col_right_inst=self.add_inst(name="dummy_col_right", - mod=self.edge_col_right) - self.connect_inst([x+"_right" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies) + mod=self.edge_col_right) + self.connect_inst([x + "_right" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies) def create_layout(self): - self.height = (self.row_size+self.extra_rows)*self.dummy_row.height - self.width = (self.column_size+self.extra_cols)*self.cell.width + self.height = (self.row_size + self.extra_rows) * self.dummy_row.height + self.width = (self.column_size + self.extra_cols) * self.cell.width # This is a bitcell x bitcell offset to scale offset = vector(self.cell.width, self.cell.height) - self.bitcell_array_inst.place(offset=[0,0]) + self.bitcell_array_inst.place(offset=[0, 0]) # To the left of the bitcell array for bit in range(self.left_rbl): - self.replica_col_inst[bit].place(offset=offset.scale(-bit-1,-self.left_rbl-1)) + self.replica_col_inst[bit].place(offset=offset.scale(-bit - 1, -self.left_rbl - 1)) # To the right of the bitcell array for bit in range(self.right_rbl): - self.replica_col_inst[self.left_rbl+bit].place(offset=offset.scale(bit,-self.left_rbl-1)+self.bitcell_array_inst.lr()) + self.replica_col_inst[self.left_rbl + bit].place(offset=offset.scale(bit, -self.left_rbl - 1) + self.bitcell_array_inst.lr()) + # FIXME: These depend on the array size itself # Far top dummy row (first row above array is NOT flipped) - flip_dummy = self.right_rbl%2 - self.dummy_row_top_inst.place(offset=offset.scale(0,self.right_rbl+flip_dummy)+self.bitcell_array_inst.ul(), + flip_dummy = self.right_rbl % 2 + self.dummy_row_top_inst.place(offset=offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul(), mirror="MX" if flip_dummy else "R0") + # FIXME: These depend on the array size itself # Far bottom dummy row (first row below array IS flipped) - flip_dummy = (self.left_rbl+1)%2 - self.dummy_row_bot_inst.place(offset=offset.scale(0,-self.left_rbl-1+flip_dummy), + flip_dummy = (self.left_rbl + 1) % 2 + self.dummy_row_bot_inst.place(offset=offset.scale(0, -self.left_rbl - 1 + flip_dummy), mirror="MX" if flip_dummy else "R0") # Far left dummy col - self.dummy_col_left_inst.place(offset=offset.scale(-self.left_rbl-1,-self.left_rbl-1)) + self.dummy_col_left_inst.place(offset=offset.scale(-self.left_rbl - 1, -self.left_rbl - 1)) # Far right dummy col - self.dummy_col_right_inst.place(offset=offset.scale(self.right_rbl,-self.left_rbl-1)+self.bitcell_array_inst.lr()) + self.dummy_col_right_inst.place(offset=offset.scale(self.right_rbl, -self.left_rbl - 1) + self.bitcell_array_inst.lr()) # Replica dummy rows for bit in range(self.left_rbl): - self.dummy_row_replica_inst[bit].place(offset=offset.scale(0,-bit-bit%2), - mirror="R0" if bit%2 else "MX") + self.dummy_row_replica_inst[bit].place(offset=offset.scale(0, -bit - bit % 2), + mirror="R0" if bit % 2 else "MX") for bit in range(self.right_rbl): - self.dummy_row_replica_inst[self.left_rbl+bit].place(offset=offset.scale(0,bit+bit%2)+self.bitcell_array_inst.ul(), - mirror="MX" if bit%2 else "R0") + self.dummy_row_replica_inst[self.left_rbl + bit].place(offset=offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul(), + mirror="MX" if bit % 2 else "R0") - - self.translate_all(offset.scale(-1-self.left_rbl,-1-self.left_rbl)) + self.translate_all(offset.scale(-1 - self.left_rbl, -1 - self.left_rbl)) self.add_layout_pins() @@ -325,7 +319,6 @@ class replica_bitcell_array(design.design): self.DRC_LVS() - def add_layout_pins(self): """ Add the layout pins """ @@ -338,7 +331,7 @@ class replica_bitcell_array(design.design): for pin in pin_list: self.add_layout_pin(text=pin_name, layer=pin.layer, - offset=pin.ll().scale(0,1), + offset=pin.ll().scale(0, 1), width=self.width, height=pin.height()) for bitline in self.bitcell_array_bl_names: @@ -347,17 +340,16 @@ class replica_bitcell_array(design.design): for pin in pin_list: self.add_layout_pin(text=pin_name, layer=pin.layer, - offset=pin.ll().scale(1,0), + offset=pin.ll().scale(1, 0), width=pin.width(), height=self.height) - # Replica wordlines - for port in range(self.left_rbl+self.right_rbl): + for port in range(self.left_rbl + self.right_rbl): inst = self.replica_col_inst[port] - for (pin_name,wl_name) in zip(self.cell.get_all_wl_names(),self.replica_wl_names[port]): + for (pin_name, wl_name) in zip(self.cell.get_all_wl_names(), self.replica_wl_names[port]): # +1 for dummy row - pin_bit = port+1 + pin_bit = port + 1 # +row_size if above the array if port>=self.left_rbl: pin_bit += self.row_size @@ -367,7 +359,7 @@ class replica_bitcell_array(design.design): if wl_name in self.rbl_wl_names.values(): self.add_layout_pin(text=wl_name, layer=pin.layer, - offset=pin.ll().scale(0,1), + offset=pin.ll().scale(0, 1), width=self.width, height=pin.height()) @@ -416,8 +408,6 @@ class replica_bitcell_array(design.design): def analytical_power(self, corner, load): """Power of Bitcell array and bitline in nW.""" - from tech import drc, parameter - # Dynamic Power from Bitline bl_wire = self.gen_bl_wire() cell_load = 2 * bl_wire.return_input_cap() @@ -425,10 +415,10 @@ class replica_bitcell_array(design.design): freq = spice["default_event_frequency"] bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing) - #Calculate the bitcell power which currently only includes leakage + # Calculate the bitcell power which currently only includes leakage cell_power = self.cell.analytical_power(corner, load) - #Leakage power grows with entire array and bitlines. + # Leakage power grows with entire array and bitlines. total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size, cell_power.leakage * self.column_size * self.row_size) return total_power @@ -439,13 +429,13 @@ class replica_bitcell_array(design.design): else: height = self.height bl_pos = 0 - bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_m1")) + bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1")) bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell return bl_wire def get_wordline_cin(self): """Get the relative input capacitance from the wordline connections in all the bitcell""" - #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns + # A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns bitcell_wl_cin = self.cell.get_wl_cin() total_cin = bitcell_wl_cin * self.column_size return total_cin @@ -457,9 +447,9 @@ class replica_bitcell_array(design.design): def graph_exclude_replica_col_bits(self): """Exclude all replica/dummy cells in the replica columns except the replica bit.""" - for port in range(self.left_rbl+self.right_rbl): + for port in range(self.left_rbl + self.right_rbl): self.replica_columns[port].exclude_all_but_replica() def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" - return self.bitcell_array.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col) + return self.bitcell_array.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, row, col) From 551499670809b0293def390d77e8c28e3a30cfed Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jun 2020 15:09:22 -0700 Subject: [PATCH 359/521] Auto-generate port dependent cell names. --- compiler/globals.py | 13 ++--- compiler/modules/col_cap_array.py | 4 +- compiler/modules/dummy_array.py | 9 ++-- compiler/modules/replica_column.py | 50 +++++++++---------- compiler/modules/row_cap_array.py | 2 +- compiler/options.py | 5 +- compiler/sram_factory.py | 4 +- .../04_single_level_column_mux_1rw_1r_test.py | 4 +- .../tests/05_bitcell_1rw_1r_array_test.py | 4 +- .../06_hierarchical_decoder_1rw_1r_test.py | 4 +- .../06_hierarchical_decoder_pbitcell_test.py | 4 +- ...6_hierarchical_predecode2x4_1rw_1r_test.py | 3 +- ...hierarchical_predecode2x4_pbitcell_test.py | 4 +- ...6_hierarchical_predecode3x8_1rw_1r_test.py | 4 +- ...hierarchical_predecode3x8_pbitcell_test.py | 4 +- ...ngle_level_column_mux_array_1rw_1r_test.py | 4 +- .../tests/08_precharge_array_1rw_1r_test.py | 2 +- .../08_wordline_driver_array_1rw_1r_test.py | 2 +- .../14_replica_bitcell_1rw_1r_array_test.py | 12 ++--- compiler/tests/18_port_address_1rw_1r_test.py | 4 +- compiler/tests/18_port_data_1rw_1r_test.py | 4 +- compiler/tests/19_single_bank_1rw_1r_test.py | 4 +- compiler/tests/19_single_bank_1w_1r_test.py | 5 +- .../tests/19_single_bank_wmask_1rw_1r_test.py | 4 ++ .../tests/20_psram_1bank_2mux_1rw_1w_test.py | 3 +- .../tests/20_psram_1bank_2mux_1w_1r_test.py | 3 +- compiler/tests/20_psram_1bank_2mux_test.py | 6 +-- .../tests/20_psram_1bank_4mux_1rw_1r_test.py | 3 +- .../tests/20_sram_1bank_2mux_1rw_1r_test.py | 4 +- .../tests/20_sram_1bank_2mux_1w_1r_test.py | 4 +- .../tests/20_sram_1bank_8mux_1rw_1r_test.py | 6 +-- .../tests/20_sram_1bank_nomux_1rw_1r_test.py | 4 +- .../22_sram_1rw_1r_1bank_nomux_func_test.py | 4 +- .../tests/22_sram_wmask_1w_1r_func_test.py | 7 +-- 34 files changed, 82 insertions(+), 121 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index 92780c1a..c9469330 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -214,25 +214,18 @@ def setup_bitcell(): if OPTS.num_r_ports > 0: ports += "{}r".format(OPTS.num_r_ports) - OPTS.bitcell = "bitcell_"+ports - OPTS.replica_bitcell = "replica_bitcell_"+ports - OPTS.dummy_bitcell = "dummy_bitcell_"+ports - else: - OPTS.replica_bitcell = "replica_" + OPTS.bitcell - OPTS.replica_bitcell = "dummy_" + OPTS.bitcell + if ports != "": + OPTS.bitcell_suffix = "_" + ports + OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix # See if bitcell exists try: __import__(OPTS.bitcell) - __import__(OPTS.replica_bitcell) - __import__(OPTS.dummy_bitcell) except ImportError: # Use the pbitcell if we couldn't find a custom bitcell # or its custom replica bitcell # Use the pbitcell (and give a warning if not in unit test mode) OPTS.bitcell = "pbitcell" - OPTS.replica_bitcell = "replica_pbitcell" - OPTS.replica_bitcell = "dummy_pbitcell" if not OPTS.is_unit_test: debug.warning("Using the parameterized bitcell which may have suboptimal density.") debug.info(1, "Using bitcell: {}".format(OPTS.bitcell)) diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index 3119f4e5..d74ab80a 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -8,6 +8,7 @@ from sram_factory import factory from globals import OPTS from tech import cell_properties + class col_cap_array(bitcell_base_array): """ Generate a dummy row/column for the replica array. @@ -35,8 +36,7 @@ class col_cap_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ - # self.dummy_cell = factory.create(module_type="col_cap_bitcell_1rw_1r") # TODO: make module_type generic - self.dummy_cell = factory.create(module_type="col_cap_bitcell") + self.dummy_cell = factory.create(module_type="col_cap_{}".format(OPTS.bitcell)) self.add_mod(self.dummy_cell) self.cell = factory.create(module_type="bitcell") diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index de15d0ce..f4b240da 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -38,20 +38,19 @@ class dummy_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ - self.dummy_cell = factory.create(module_type="dummy_bitcell") + self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell)) self.add_mod(self.dummy_cell) self.cell = factory.create(module_type="bitcell") - def create_instances(self): """ Create the module instances used in this design """ self.cell_inst = {} for col in range(self.column_size): for row in range(self.row_size): name = "bit_r{0}_c{1}".format(row, col) - self.cell_inst[row,col]=self.add_inst(name=name, - mod=self.dummy_cell) + self.cell_inst[row, col]=self.add_inst(name=name, + mod=self.dummy_cell) self.connect_inst(self.get_bitcell_pins(col, row)) def input_load(self): @@ -60,7 +59,7 @@ class dummy_array(bitcell_base_array): def get_wordline_cin(self): """Get the relative input capacitance from the wordline connections in all the bitcell""" - #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns + # A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns bitcell_wl_cin = self.cell.get_wl_cin() total_cin = bitcell_wl_cin * self.column_size return total_cin diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 4ea1b7df..afe87497 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -5,12 +5,12 @@ # import debug import design -from tech import drc, cell_properties -import contact +from tech import cell_properties from sram_factory import factory from vector import vector from globals import OPTS + class replica_column(design.design): """ Generate a replica bitline column for the replica array. @@ -29,11 +29,12 @@ class replica_column(design.design): self.right_rbl = right_rbl self.replica_bit = replica_bit # left, right, regular rows plus top/bottom dummy cells - self.total_size = self.left_rbl+rows+self.right_rbl+2 + self.total_size = self.left_rbl + rows + self.right_rbl + 2 self.column_offset = column_offset - debug.check(replica_bit!=0 and replica_bit!=rows,"Replica bit cannot be the dummy row.") - debug.check(replica_bit<=left_rbl or replica_bit>=self.total_size-right_rbl-1, + debug.check(replica_bit != 0 and replica_bit != rows, + "Replica bit cannot be the dummy row.") + debug.check(replica_bit <= left_rbl or replica_bit >= self.total_size - right_rbl - 1, "Replica bit cannot be in the regular array.") self.create_netlist() @@ -46,7 +47,7 @@ class replica_column(design.design): self.create_instances() def create_layout(self): - self.height = self.total_size*self.cell.height + self.height = self.total_size * self.cell.height self.width = self.cell.width self.place_instances() @@ -58,25 +59,25 @@ class replica_column(design.design): for bl_name in self.cell.get_all_bitline_names(): # In the replica column, these are only outputs! - self.add_pin("{0}_{1}".format(bl_name,0), "OUTPUT") + self.add_pin("{0}_{1}".format(bl_name, 0), "OUTPUT") for row in range(self.total_size): for wl_name in self.cell.get_all_wl_names(): - self.add_pin("{0}_{1}".format(wl_name,row), "INPUT") + self.add_pin("{0}_{1}".format(wl_name, row), "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") def add_modules(self): - self.replica_cell = factory.create(module_type="replica_bitcell") + self.replica_cell = factory.create(module_type="replica_{}".format(OPTS.bitcell)) self.add_mod(self.replica_cell) - self.dummy_cell = factory.create(module_type="dummy_bitcell") + self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell)) self.add_mod(self.dummy_cell) try: - edge_module_type = ("col_cap_bitcell" if cell_properties.bitcell.end_caps else "dummy_bitcell") + edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy") except AttributeError: - edge_module_type = "dummy_bitcell" - self.edge_cell = factory.create(module_type=edge_module_type) + edge_module_type = "dummy" + self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell) self.add_mod(self.edge_cell) # Used for pin names only self.cell = factory.create(module_type="bitcell") @@ -94,7 +95,7 @@ class replica_column(design.design): # Top/bottom cell are always dummy cells. # Regular array cells are replica cells (>left_rbl and self.left_rbl and row self.left_rbl and row < self.total_size - self.right_rbl - 1): self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell) self.connect_inst(self.get_bitcell_pins(0, row)) @@ -118,7 +119,7 @@ class replica_column(design.design): from tech import cell_properties # Flip the mirrors if we have an odd number of replica+dummy rows at the bottom # so that we will start with mirroring rather than not mirroring - rbl_offset = (self.left_rbl+1)%2 + rbl_offset = (self.left_rbl + 1) %2 # if our bitcells are mirrored on the y axis, check if we are in global # column that needs to be flipped. @@ -129,12 +130,10 @@ class replica_column(design.design): xoffset = self.replica_cell.width for row in range(self.total_size): - dir_x = False - name = "bit_r{0}_{1}".format(row,"rbl") - if cell_properties.bitcell.mirror.x and (row+rbl_offset)%2: - dir_x = True + # name = "bit_r{0}_{1}".format(row, "rbl") + dir_x = cell_properties.bitcell.mirror.x and (row + rbl_offset) % 2 - offset = vector(xoffset,self.cell.height*(row+(row+rbl_offset)%2)) + offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2)) if dir_x and dir_y: dir_key = "XY" @@ -174,9 +173,9 @@ class replica_column(design.design): for row in range(row_range_min, row_range_max): for wl_name in self.cell.get_all_wl_names(): wl_pin = self.cell_inst[row].get_pin(wl_name) - self.add_layout_pin(text="{0}_{1}".format(wl_name,row), + self.add_layout_pin(text="{0}_{1}".format(wl_name, row), layer=wl_pin.layer, - offset=wl_pin.ll().scale(0,1), + offset=wl_pin.ll().scale(0, 1), width=self.width, height=wl_pin.height()) @@ -194,10 +193,10 @@ class replica_column(design.design): pin_names = self.cell.get_all_bitline_names() for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(col)) + bitcell_pins.append(pin + "_{0}".format(col)) pin_names = self.cell.get_all_wl_names() for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(row)) + bitcell_pins.append(pin + "_{0}".format(row)) bitcell_pins.append("vdd") bitcell_pins.append("gnd") @@ -211,12 +210,11 @@ class replica_column(design.design): pin_names = self.cell.get_all_bitline_names() for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(col)) + bitcell_pins.append(pin + "_{0}".format(col)) bitcell_pins.append("vdd") return bitcell_pins - def exclude_all_but_replica(self): """Excludes all bits except the replica cell (self.replica_bit).""" diff --git a/compiler/modules/row_cap_array.py b/compiler/modules/row_cap_array.py index c9a6b4f7..2c7d4677 100644 --- a/compiler/modules/row_cap_array.py +++ b/compiler/modules/row_cap_array.py @@ -35,7 +35,7 @@ class row_cap_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ - self.dummy_cell = factory.create(module_type="row_cap_bitcell_1rw_1r") # TODO: make module_type generic + self.dummy_cell = factory.create(module_type="row_cap_{}".format(OPTS.bitcell)) self.add_mod(self.dummy_cell) self.cell = factory.create(module_type="bitcell") diff --git a/compiler/options.py b/compiler/options.py index 646b2a68..fb738169 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -124,26 +124,23 @@ class options(optparse.Values): purge_temp = True # These are the default modules that can be over-riden + bitcell_suffix = "" bank_select = "bank_select" bitcell_array = "bitcell_array" bitcell = "bitcell" - col_cap_bitcell = "col_cap_bitcell" column_mux_array = "single_level_column_mux_array" control_logic = "control_logic" decoder = "hierarchical_decoder" delay_chain = "delay_chain" dff_array = "dff_array" dff = "dff" - dummy_bitcell = "dummy_bitcell" inv_dec = "pinv" nand2_dec = "pnand2" nand3_dec = "pnand3" nand4_dec = "pnand4" # Not available right now precharge_array = "precharge_array" ptx = "ptx" - replica_bitcell = "replica_bitcell" replica_bitline = "replica_bitline" - row_cap_bitcell = "row_cap_bitcell" sense_amp_array = "sense_amp_array" sense_amp = "sense_amp" tri_gate_array = "tri_gate_array" diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 46eed3d4..0e9721c7 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -77,8 +77,8 @@ class sram_factory: """ tech_module_type, tm_overridden = self.get_techmodule_type(module_type) user_module_type, um_overridden = self.get_usermodule_type(module_type) - #print(module_type, tech_module_type, tm_overridden) - #print(module_type, user_module_type, um_overridden) + # print(module_type, tech_module_type, tm_overridden) + # print(module_type, user_module_type, um_overridden) # overridden user modules have priority if um_overridden: diff --git a/compiler/tests/04_single_level_column_mux_1rw_1r_test.py b/compiler/tests/04_single_level_column_mux_1rw_1r_test.py index 69b31cc6..a7e79e9b 100755 --- a/compiler/tests/04_single_level_column_mux_1rw_1r_test.py +++ b/compiler/tests/04_single_level_column_mux_1rw_1r_test.py @@ -22,11 +22,11 @@ class single_level_column_mux_1rw_1r_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - + globals.setup_bitcell() + debug.info(2, "Checking column mux port 0") tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 3426f0c5..0683d127 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -23,12 +23,10 @@ class bitcell_1rw_1r_array_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() debug.info(2, "Testing 4x4 array for cell_1rw_1r") a = factory.create(module_type="bitcell_array", cols=4, rows=4) diff --git a/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py index 5b317e6e..844160a6 100755 --- a/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py @@ -23,11 +23,11 @@ class hierarchical_decoder_1rw_1r_test(openram_test): globals.init_openram(config_file) # Use the 2 port cell since it is usually bigger/easier - OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - + globals.setup_bitcell() + # Checks 2x4 and 2-input NAND decoder debug.info(1, "Testing 16 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=16) diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py index 094e8b2e..e1605067 100755 --- a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py @@ -21,11 +21,11 @@ class hierarchical_decoder_pbitcell_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check hierarchical decoder for multi-port - OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - + globals.setup_bitcell() + factory.reset() debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=16) diff --git a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py index 6512238f..a3ae2ed2 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py @@ -22,11 +22,10 @@ class hierarchical_predecode2x4_1rw_1r_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - # Use the 2 port cell since it is usually bigger/easier - OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() debug.info(1, "Testing sample for hierarchy_predecode2x4") a = factory.create(module_type="hierarchical_predecode2x4") diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py index b5532891..0f70ddb1 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py @@ -22,11 +22,11 @@ class hierarchical_predecode2x4_pbitcell_test(openram_test): globals.init_openram(config_file) # checking hierarchical precode 2x4 for multi-port - OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - + globals.setup_bitcell() + debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)") a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) diff --git a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py index 466a7e40..c0653243 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py @@ -23,11 +23,11 @@ class hierarchical_predecode3x8_1rw_1r_test(openram_test): globals.init_openram(config_file) # Use the 2 port cell since it is usually bigger/easier - OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - + globals.setup_bitcell() + debug.info(1, "Testing sample for hierarchy_predecode3x8") a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py index 1d5ab41b..9170d5c0 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py @@ -22,11 +22,11 @@ class hierarchical_predecode3x8_pbitcell_test(openram_test): globals.init_openram(config_file) # checking hierarchical precode 3x8 for multi-port - OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - + globals.setup_bitcell() + debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)") a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) diff --git a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py index 2a3a8f87..c758e788 100755 --- a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py +++ b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py @@ -20,11 +20,11 @@ class single_level_column_mux_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - + globals.setup_bitcell() + debug.info(1, "Testing sample for 4-way column_mux_array port 0") a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) diff --git a/compiler/tests/08_precharge_array_1rw_1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py index 7d54e02b..c5efb59b 100755 --- a/compiler/tests/08_precharge_array_1rw_1r_test.py +++ b/compiler/tests/08_precharge_array_1rw_1r_test.py @@ -22,10 +22,10 @@ class precharge_1rw_1r_test(openram_test): globals.init_openram(config_file) # check precharge array in multi-port - OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() factory.reset() debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)") diff --git a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py index 7c97ff75..cf1810d8 100755 --- a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py +++ b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py @@ -23,10 +23,10 @@ class wordline_driver_array_1rw_1r_test(openram_test): globals.init_openram(config_file) # Use the 2 port cell since it is usually bigger/easier - OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() # check wordline driver for single port debug.info(2, "Checking driver") diff --git a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py index d746eabc..3f869255 100755 --- a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py @@ -19,21 +19,17 @@ class replica_bitcell_array_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" - OPTS.col_cap_bitcell="col_cap_bitcell_1rw_1r" - OPTS.row_cap_bitcell="row_cap_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - + globals.setup_bitcell() + debug.info(2, "Testing 4x4 array for cell_1rw_1r") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0,1]) + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0, 1]) self.local_check(a) debug.info(2, "Testing 4x4 array for cell_1rw_1r") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0,1]) + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1]) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/18_port_address_1rw_1r_test.py b/compiler/tests/18_port_address_1rw_1r_test.py index 33bff4ed..ff09dec9 100755 --- a/compiler/tests/18_port_address_1rw_1r_test.py +++ b/compiler/tests/18_port_address_1rw_1r_test.py @@ -21,11 +21,11 @@ class port_address_1rw_1r_test(openram_test): globals.init_openram(config_file) # Use the 2 port cell since it is usually bigger/easier - OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - + globals.setup_bitcell() + debug.info(1, "Port address 16 rows") a = factory.create("port_address", cols=16, rows=16) self.local_check(a) diff --git a/compiler/tests/18_port_data_1rw_1r_test.py b/compiler/tests/18_port_data_1rw_1r_test.py index 3d415ec0..3a7687d6 100755 --- a/compiler/tests/18_port_data_1rw_1r_test.py +++ b/compiler/tests/18_port_data_1rw_1r_test.py @@ -21,11 +21,11 @@ class port_data_1rw_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - + globals.setup_bitcell() + c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index b3e18407..22f83f29 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -22,12 +22,10 @@ class single_bank_1rw_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index c1228e5a..e3a2d886 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -22,13 +22,10 @@ class single_bank_1w_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1w_1r" - OPTS.replica_bitcell = "replica_bitcell_1w_1r" - OPTS.dummy_bitcell="dummy_bitcell_1w_1r" - OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py index d08ff8cc..ddb97905 100755 --- a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py @@ -22,6 +22,10 @@ class single_bank_wmask_1rw_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=8, write_size=4, diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index 599cb2ce..f521851b 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -24,11 +24,10 @@ class psram_1bank_2mux_1rw_1w_test(openram_test): from sram_config import sram_config OPTS.bitcell = "pbitcell" - OPTS.replica_bitcell="replica_pbitcell" - OPTS.dummy_bitcell="dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 1 OPTS.num_r_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 30b951fb..35912823 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -24,11 +24,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test): from sram_config import sram_config OPTS.bitcell = "pbitcell" - OPTS.replica_bitcell="replica_pbitcell" - OPTS.dummy_bitcell="dummy_pbitcell" OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 44272b2d..92403cd1 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -22,14 +22,12 @@ class psram_1bank_2mux_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "pbitcell" - OPTS.replica_bitcell="replica_pbitcell" - OPTS.dummy_bitcell="dummy_pbitcell" - # testing layout of sram using pbitcell with 1 RW port (a 6T-cell equivalent) + OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 49e1a125..145d1723 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -24,11 +24,10 @@ class psram_1bank_4mux_1rw_1r_test(openram_test): from sram_config import sram_config OPTS.bitcell = "pbitcell" - OPTS.replica_bitcell="replica_pbitcell" - OPTS.dummy_bitcell="dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=64, diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index a8d635ba..0a2b7d32 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -22,12 +22,10 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index bf572700..2c4e29e6 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -23,12 +23,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1w_1r" - OPTS.replica_bitcell="replica_bitcell_1w_1r" - OPTS.dummy_bitcell="dummy_bitcell_1w_1r" OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index 69a623d2..1e4df34d 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -22,13 +22,11 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - + globals.setup_bitcell() + c = sram_config(word_size=2, num_words=128, num_banks=1) diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index f9b96b84..a516b4f0 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -22,12 +22,10 @@ class sram_1bank_nomux_1rw_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=16, diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index d271d1e5..f2958f9f 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -24,12 +24,10 @@ class psram_1bank_nomux_func_test(openram_test): OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 + globals.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload diff --git a/compiler/tests/22_sram_wmask_1w_1r_func_test.py b/compiler/tests/22_sram_wmask_1w_1r_func_test.py index 50acd5bf..b5d83654 100755 --- a/compiler/tests/22_sram_wmask_1w_1r_func_test.py +++ b/compiler/tests/22_sram_wmask_1w_1r_func_test.py @@ -26,14 +26,11 @@ class sram_wmask_1w_1r_func_test(openram_test): OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False - OPTS.bitcell = "bitcell_1w_1r" - OPTS.replica_bitcell = "replica_bitcell_1w_1r" - OPTS.dummy_bitcell = "dummy_bitcell_1w_1r" - OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 - + globals.setup_bitcell() + # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer From 0837432d4538b75e74a522092a1d51ebc3667ff6 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jun 2020 16:47:22 -0700 Subject: [PATCH 360/521] Wordline route layers and (optional) via. --- compiler/modules/bank.py | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 92e4e8cd..d9659cd5 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -798,22 +798,34 @@ class bank(design.design): for row in range(self.num_rows): # The mid guarantees we exit the input cell to the right. - driver_wl_pos = self.port_address_inst[port].get_pin("wl_{}".format(row)).rc() - bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port] + "_{}".format(row)).lc() + driver_wl_pin = self.port_address_inst[port].get_pin("wl_{}".format(row)) + driver_wl_pos = driver_wl_pin.rc() + bitcell_wl_pin = self.bitcell_array_inst.get_pin(self.wl_names[port] + "_{}".format(row)) + bitcell_wl_pos = bitcell_wl_pin.lc() mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].rx() + 0.5 * self.bitcell_array_inst.lx(), 0) mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0.5, 1) - self.add_path("m1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) + self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) + self.add_via_stack_center(from_layer=driver_wl_pin.layer, + to_layer=bitcell_wl_pin.layer, + offset=bitcell_wl_pos, + directions=("H", "H")) def route_port_address_right(self, port): """ Connecting Wordline driver output to Bitcell WL connection """ for row in range(self.num_rows): # The mid guarantees we exit the input cell to the right. - driver_wl_pos = self.port_address_inst[port].get_pin("wl_{}".format(row)).lc() - bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port] + "_{}".format(row)).rc() + driver_wl_pin = self.port_address_inst[port].get_pin("wl_{}".format(row)) + driver_wl_pos = driver_wl_pin.lc() + bitcell_wl_pin = self.bitcell_array_inst.get_pin(self.wl_names[port] + "_{}".format(row)) + bitcell_wl_pos = bitcell_wl_pin.rc() mid1 = driver_wl_pos.scale(0, 1) + vector(0.5 * self.port_address_inst[port].lx() + 0.5 * self.bitcell_array_inst.rx(), 0) mid2 = mid1.scale(1, 0) + bitcell_wl_pos.scale(0, 1) - self.add_path("m1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) + self.add_path(driver_wl_pin.layer, [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) + self.add_via_stack_center(from_layer=driver_wl_pin.layer, + to_layer=bitcell_wl_pin.layer, + offset=bitcell_wl_pos, + directions=("H", "H")) def route_column_address_lines(self, port): """ Connecting the select lines of column mux to the address bus """ From ef940e0dc5ab64350f5f8817a988a9c082c9a21e Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Mon, 8 Jun 2020 05:02:04 +0000 Subject: [PATCH 361/521] Fixes for functional test of spare cols --- compiler/characterizer/simulation.py | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 9027fca1..064eb2c5 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -131,7 +131,6 @@ class simulation(): debug.error("Non-binary data string",1) bit -= 1 - def add_address(self, address, port): """ Add the array of address values """ debug.check(len(address)==self.addr_size, "Invalid address size.") @@ -193,7 +192,7 @@ class simulation(): self.add_control_one_port(port, "write") self.add_data(data,port) self.add_address(address,port) - self.add_wmask(wmask,port) + self.add_wmask(wmask,port) self.add_spare_wen("1" * self.num_spare_cols, port) #Add noops to all other ports. @@ -213,9 +212,8 @@ class simulation(): self.cycle_times.append(self.t_current) self.t_current += self.period self.add_control_one_port(port, "read") - self.add_address(address, port) - self.add_spare_wen("0" * self.num_spare_cols, port) - + self.add_address(address, port) + # If the port is also a readwrite then add # the same value as previous cycle if port in self.write_ports: @@ -227,6 +225,7 @@ class simulation(): self.add_wmask(self.wmask_value[port][-1], port) except: self.add_wmask("0"*self.num_wmasks, port) + self.add_spare_wen("0" * self.num_spare_cols, port) #Add noops to all other ports. for unselected_port in self.all_ports: @@ -269,7 +268,7 @@ class simulation(): self.add_control_one_port(port, "read") self.add_address(address, port) - self.add_spare_wen("0" * self.num_spare_cols, port) + # If the port is also a readwrite then add # the same value as previous cycle if port in self.write_ports: @@ -280,14 +279,13 @@ class simulation(): try: self.add_wmask(self.wmask_value[port][-1], port) except: - self.add_wmask("0"*self.num_wmasks, port) - + self.add_wmask("0"*self.num_wmasks, port) + self.add_spare_wen("0" * self.num_spare_cols, port) def add_noop_one_port(self, port): """ Add the control values for a noop to a single port. Does not increment the period. """ self.add_control_one_port(port, "noop") - self.add_spare_wen("0" * self.num_spare_cols, port) - + try: self.add_address(self.addr_value[port][-1], port) except: @@ -304,7 +302,8 @@ class simulation(): self.add_wmask(self.wmask_value[port][-1], port) except: self.add_wmask("0"*self.num_wmasks, port) - + self.add_spare_wen("0" * self.num_spare_cols, port) + def add_noop_clock_one_port(self, port): """ Add the control values for a noop to a single port. Increments the period. """ debug.info(2, 'Clock only on port {}'.format(port)) From 300522a1a80c6346bf11e0d9185a3f387fe861e6 Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Mon, 8 Jun 2020 14:31:46 +0000 Subject: [PATCH 362/521] Change spare enable pins offset to lower right --- compiler/modules/write_driver_array.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 510325bb..22a75218 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -7,6 +7,7 @@ # import design import debug +from tech import drc from sram_factory import factory from vector import vector from globals import OPTS @@ -239,9 +240,7 @@ class write_driver_array(design.design): en_pin = inst.get_pin(inst.mod.en_name) self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks), layer="m1", - offset=en_pin.ll(), - width=self.driver.width - en_pin.width()) - + offset=en_pin.lr() + vector(-drc("minwidth_m1"),0)) elif self.num_spare_cols and not self.write_size: # shorten enable rail to accomodate those for spare write drivers @@ -258,9 +257,8 @@ class write_driver_array(design.design): en_pin = inst.get_pin(inst.mod.en_name) self.add_layout_pin(text=self.en_name + "_{0}".format(i + 1), layer="m1", - offset=en_pin.ll(), - width=self.driver.width - en_pin.width()) - + offset=en_pin.lr() + vector(-drc("minwidth_m1"),0)) + else: inst = self.driver_insts[0] self.add_layout_pin(text=self.en_name, From c39c0efd398e0877088ee80c04c24dbda62bf85f Mon Sep 17 00:00:00 2001 From: Aditi Sinha Date: Mon, 8 Jun 2020 16:38:18 +0000 Subject: [PATCH 363/521] Updated spare col tests --- .../09_sense_amp_array_spare_cols_test.py | 10 ++-- .../10_write_driver_array_spare_cols_test.py | 10 ++-- ...rite_driver_array_wmask_spare_cols_test.py | 4 +- .../tests/18_port_data_spare_cols_test.py | 3 +- .../tests/19_single_bank_spare_cols_test.py | 2 +- ..._sram_1bank_2mux_1rw_1r_spare_cols_test.py | 21 ++++--- ...0_sram_1bank_2mux_1w_1r_spare_cols_test.py | 23 ++++---- ...0_sram_1bank_2mux_wmask_spare_cols_test.py | 22 +++---- ...sram_1bank_nomux_1rw_1r_spare_cols_test.py | 18 +++--- .../20_sram_1bank_nomux_spare_cols_test.py | 2 +- ...0_sram_1bank_nomux_wmask_sparecols_test.py | 57 +++++++++++++++++++ 11 files changed, 112 insertions(+), 60 deletions(-) create mode 100755 compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py diff --git a/compiler/tests/09_sense_amp_array_spare_cols_test.py b/compiler/tests/09_sense_amp_array_spare_cols_test.py index 1eabe196..d8da1dc5 100755 --- a/compiler/tests/09_sense_amp_array_spare_cols_test.py +++ b/compiler/tests/09_sense_amp_array_spare_cols_test.py @@ -15,18 +15,18 @@ from globals import OPTS from sram_factory import factory import debug -class sense_amp_test(openram_test): +class sense_amp_array_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check sense amp array for single port - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 and num_spare_cols=3") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1, num_spare_cols=3) self.local_check(a) - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4") + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 and num_spare_cols=2") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=2) self.local_check(a) @@ -37,11 +37,11 @@ class sense_amp_test(openram_test): OPTS.num_r_ports = 0 factory.reset() - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2, num_spare_cols=2 (multi-port case)") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2, num_spare_cols=2) self.local_check(a) - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4, num_spare_cols=3 (multi-port case)") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=3) self.local_check(a) diff --git a/compiler/tests/10_write_driver_array_spare_cols_test.py b/compiler/tests/10_write_driver_array_spare_cols_test.py index c5e7132f..8b1256d0 100755 --- a/compiler/tests/10_write_driver_array_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_spare_cols_test.py @@ -15,18 +15,18 @@ from globals import OPTS from sram_factory import factory import debug -class write_driver_test(openram_test): +class write_driver_array_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check write driver array for single port - debug.info(2, "Testing write_driver_array for columns=8, word_size=8") + debug.info(2, "Testing write_driver_array for columns=8, word_size=8 and num_spare_cols=3") a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3) self.local_check(a) - debug.info(2, "Testing write_driver_array for columns=16, word_size=8") + debug.info(2, "Testing write_driver_array for columns=16, word_size=8 and num_spare_cols=3") a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3) self.local_check(a) @@ -37,11 +37,11 @@ class write_driver_test(openram_test): OPTS.num_r_ports = 0 factory.reset() - debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") + debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case and num_spare_cols=3") a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3) self.local_check(a) - debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") + debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case and num_spare_cols=3") a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3) self.local_check(a) diff --git a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py index be85665e..8a1e4788 100755 --- a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py @@ -17,7 +17,7 @@ from sram_factory import factory import debug -class write_driver_test(openram_test): +class write_driver_array_wmask_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -33,7 +33,7 @@ class write_driver_test(openram_test): self.local_check(a) debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4") - a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4) + a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4, num_spare_cols=3) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py index 1695f861..8c08ad0a 100755 --- a/compiler/tests/18_port_data_spare_cols_test.py +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -22,8 +22,7 @@ class port_data_spare_cols_test(openram_test): c = sram_config(word_size=8, num_words=16, - num_spare_rows=1, - num_spare_cols=1) + num_spare_cols=3) c.words_per_row=1 factory.reset() diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py index fc247bcd..52eeea52 100755 --- a/compiler/tests/19_single_bank_spare_cols_test.py +++ b/compiler/tests/19_single_bank_spare_cols_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class single_bank_test(openram_test): +class single_bank_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py index d087a47b..6adb3e8e 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py @@ -15,19 +15,17 @@ from globals import OPTS from sram_factory import factory import debug -class sram_1bank_2mux_1rw_1r_test(openram_test): +class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -38,13 +36,14 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): c.recompute_sizes() debug.info(1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " - "row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py index 349f5374..987a297e 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py @@ -15,20 +15,18 @@ from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") -class psram_1bank_2mux_1w_1r_test(openram_test): +#@unittest.skip("SKIPPING 20_sram_1bank_2mux_1w_1r_spare_cols_test, odd supply routing error") +class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1w_1r" - OPTS.replica_bitcell="replica_bitcell_1w_1r" - OPTS.dummy_bitcell="dummy_bitcell_1w_1r" OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -39,13 +37,14 @@ class psram_1bank_2mux_1w_1r_test(openram_test): c.recompute_sizes() debug.info(1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " - "row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py index 0e9c74c3..0488b93e 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py @@ -16,9 +16,8 @@ from globals import OPTS from sram_factory import factory import debug - -# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_test") -class sram_1bank_2mux_wmask_test(openram_test): +# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_spare_cols_test") +class sram_1bank_2mux_wmask_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -34,14 +33,15 @@ class sram_1bank_2mux_wmask_test(openram_test): c.recompute_sizes() debug.info(1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} bit writes, {} words per " - "row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.write_size, - c.words_per_row, - c.num_banks)) + "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.write_size, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py index 575fc51f..dbeca8aa 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py @@ -22,12 +22,10 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=16, @@ -39,13 +37,13 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): debug.info(1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_spare_cols, - c.num_banks)) + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py index 14001c19..135518e3 100755 --- a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py @@ -17,7 +17,7 @@ from sram_factory import factory import debug -# @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_test") +# @unittest.skip("SKIPPING 20_sram_1bank_nomux_spare_cols_test") class sram_1bank_nomux_spare_cols_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py new file mode 100755 index 00000000..e22122bd --- /dev/null +++ b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os + +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_sparecols_test, not working yet") +class sram_1bank_nomux_wmask_sparecols_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + c = sram_config(word_size=8, + write_size=4, + num_words=16, + num_spare_cols=3, + num_banks=1) + + c.words_per_row = 1 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} bit writes, {} words per " + "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.write_size, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 9cc36c6d3a0386492b0ecf4b2ac3a88594257b4c Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 8 Jun 2020 11:01:14 -0700 Subject: [PATCH 364/521] Bus code converted to pins. Fix layers on control signal routes in bank. --- compiler/base/hierarchy_layout.py | 60 +++++++++--------- compiler/modules/bank.py | 71 ++++++++++------------ compiler/modules/control_logic.py | 36 +++++------ compiler/modules/hierarchical_decoder.py | 10 +-- compiler/modules/hierarchical_predecode.py | 16 ++--- compiler/modules/precharge_array.py | 1 + compiler/pgates/precharge.py | 12 +++- 7 files changed, 105 insertions(+), 101 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 12a9826e..d3b84ca5 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -219,8 +219,6 @@ class layout(): if not height: height = drc["minwidth_{}".format(layer)] lpp = techlayer[layer] - if abs(offset[0]-5.16250)<0.01 and abs(offset[1]-8.70750)<0.01: - import pdb; pdb.set_trace() self.objs.append(geometry.rectangle(lpp, offset, width, @@ -838,51 +836,57 @@ class layout(): if not pitch: pitch = getattr(self, "{}_pitch".format(layer)) - line_positions = {} + pins = {} if vertical: for i in range(len(names)): line_offset = offset + vector(i * pitch, 0) if make_pins: - self.add_layout_pin(text=names[i], - layer=layer, - offset=line_offset, - height=length) + new_pin = self.add_layout_pin(text=names[i], + layer=layer, + offset=line_offset, + height=length) else: - self.add_rect(layer=layer, - offset=line_offset, - height=length) - line_positions[names[i]] = line_offset + vector(half_minwidth, 0) + rect = self.add_rect(layer=layer, + offset=line_offset, + height=length) + new_pin = pin_layout(names[i], + [rect.ll(), rect.ur()], + layer) + + pins[names[i]] = new_pin else: for i in range(len(names)): line_offset = offset + vector(0, i * pitch + half_minwidth) if make_pins: - self.add_layout_pin(text=names[i], - layer=layer, - offset=line_offset, - width=length) + new_pin = self.add_layout_pin(text=names[i], + layer=layer, + offset=line_offset, + width=length) else: - self.add_rect(layer=layer, - offset=line_offset, - width=length) - # Make this the center of the rail - line_positions[names[i]] = line_offset + vector(0.5 * length, - half_minwidth) + rect = self.add_rect(layer=layer, + offset=line_offset, + width=length) + new_pin = pin_layout(names[i], + [rect.ll(), rect.ur()], + layer) + + pins[names[i]] = new_pin - return line_positions + return pins - def connect_horizontal_bus(self, mapping, inst, bus_offsets, + def connect_horizontal_bus(self, mapping, inst, bus_pins, layer_stack=("m1", "via1", "m2")): """ Horizontal version of connect_bus. """ - self.connect_bus(mapping, inst, bus_offsets, layer_stack, True) + self.connect_bus(mapping, inst, bus_pins, layer_stack, True) - def connect_vertical_bus(self, mapping, inst, bus_offsets, + def connect_vertical_bus(self, mapping, inst, bus_pins, layer_stack=("m1", "via1", "m2")): """ Vertical version of connect_bus. """ - self.connect_bus(mapping, inst, bus_offsets, layer_stack, False) + self.connect_bus(mapping, inst, bus_pins, layer_stack, False) - def connect_bus(self, mapping, inst, bus_offsets, layer_stack, horizontal): + def connect_bus(self, mapping, inst, bus_pins, layer_stack, horizontal): """ Connect a mapping of pin -> name for a bus. This could be replaced with a channel router in the future. @@ -898,7 +902,7 @@ class layout(): for (pin_name, bus_name) in mapping: pin = inst.get_pin(pin_name) pin_pos = pin.center() - bus_pos = bus_offsets[bus_name] + bus_pos = bus_pins[bus_name].center() if horizontal: # up/down then left/right diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index d9659cd5..36fecfc4 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -593,7 +593,7 @@ class bank(design.design): # Connect the inverter output to the central bus out_pos = self.bank_select_inst[port].get_pin(gated_bank_sel_signals[signal]).rc() name = self.control_signals[port][signal] - bus_pos = vector(self.bus_xoffset[port][name].x, out_pos.y) + bus_pos = vector(self.bus_pins[port][name].cx(), out_pos.y) self.add_path("m3", [out_pos, bus_pos]) self.add_via_center(layers=self.m2_stack, offset=bus_pos) @@ -628,19 +628,19 @@ class bank(design.design): # Overall central bus width. It includes all the column mux lines, # and control lines. - self.bus_xoffset = [None] * len(self.all_ports) + self.bus_pins = [None] * len(self.all_ports) # Port 0 # The bank is at (0,0), so this is to the left of the y-axis. # 2 pitches on the right for vias/jogs to access the inputs control_bus_offset = vector(-self.m3_pitch * self.num_control_lines[0] - self.m3_pitch, self.min_y_offset) # The control bus is routed up to two pitches below the bitcell array control_bus_length = self.main_bitcell_array_bottom - self.min_y_offset - 2 * self.m1_pitch - self.bus_xoffset[0] = self.create_bus(layer="m2", - offset=control_bus_offset, - names=self.control_signals[0], - length=control_bus_length, - vertical=True, - make_pins=(self.num_banks==1)) + self.bus_pins[0] = self.create_bus(layer="m2", + offset=control_bus_offset, + names=self.control_signals[0], + length=control_bus_length, + vertical=True, + make_pins=(self.num_banks==1)) # Port 1 if len(self.all_ports)==2: @@ -649,12 +649,12 @@ class bank(design.design): control_bus_offset = vector(self.bitcell_array_right + self.m3_pitch, self.max_y_offset - control_bus_length) # The bus for the right port is reversed so that the rbl_wl is closest to the array - self.bus_xoffset[1] = self.create_bus(layer="m2", - offset=control_bus_offset, - names=list(reversed(self.control_signals[1])), - length=control_bus_length, - vertical=True, - make_pins=(self.num_banks==1)) + self.bus_pins[1] = self.create_bus(layer="m2", + offset=control_bus_offset, + names=list(reversed(self.control_signals[1])), + length=control_bus_length, + vertical=True, + make_pins=(self.num_banks==1)) def route_port_data_to_bitcell_array(self, port): """ Routing of BL and BR between port data and bitcell array """ @@ -919,39 +919,32 @@ class bank(design.design): # pre-decoder and this connection is in metal3 connection = [] connection.append((self.prefix + "p_en_bar{}".format(port), - self.port_data_inst[port].get_pin("p_en_bar").lc(), - self.port_data_inst[port].get_pin("p_en_bar").layer)) + self.port_data_inst[port].get_pin("p_en_bar"))) rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]) connection.append((self.prefix + "wl_en{}".format(port), - self.bitcell_array_inst.get_pin(rbl_wl_name).lc(), - self.bitcell_array_inst.get_pin(rbl_wl_name).layer)) + self.bitcell_array_inst.get_pin(rbl_wl_name))) if port in self.write_ports: - if port % 2: - connection.append((self.prefix + "w_en{}".format(port), - self.port_data_inst[port].get_pin("w_en").rc(), - self.port_data_inst[port].get_pin("w_en").layer)) - else: - connection.append((self.prefix + "w_en{}".format(port), - self.port_data_inst[port].get_pin("w_en").lc(), - self.port_data_inst[port].get_pin("w_en").layer)) + connection.append((self.prefix + "w_en{}".format(port), + self.port_data_inst[port].get_pin("w_en"))) if port in self.read_ports: connection.append((self.prefix + "s_en{}".format(port), - self.port_data_inst[port].get_pin("s_en").lc(), - self.port_data_inst[port].get_pin("s_en").layer)) + self.port_data_inst[port].get_pin("s_en"))) - for (control_signal, pin_pos, pin_layer) in connection: - if port==0: - y_offset = self.min_y_offset - else: - y_offset = self.max_y_offset - control_pos = vector(self.bus_xoffset[port][control_signal].x, y_offset) - if pin_layer == "m1": - self.add_wire(self.m1_stack, [control_pos, pin_pos]) - elif pin_layer == "m3": - self.add_wire(self.m2_stack[::-1], [control_pos, pin_pos]) + for (control_signal, pin) in connection: + control_pin = self.bus_pins[port][control_signal] + control_pos = vector(control_pin.cx(), pin.cy()) + # If the y doesn't overlap the bus, add a segment + if pin.cy() < control_pin.by(): + self.add_path("m2", [control_pos, control_pin.bc()]) + elif pin.cy() > control_pin.uy(): + self.add_path("m2", [control_pos, control_pin.uc()]) + self.add_path(pin.layer, [control_pos, pin.center()]) + self.add_via_stack_center(from_layer=pin.layer, + to_layer="m2", + offset=control_pos) # clk to wordline_driver control_signal = self.prefix + "wl_en{}".format(port) @@ -961,7 +954,7 @@ class bank(design.design): else: pin_pos = self.port_address_inst[port].get_pin("wl_en").bc() mid_pos = pin_pos - vector(0, 2 * self.m2_gap) # to route down to the top of the bus - control_x_offset = self.bus_xoffset[port][control_signal].x + control_x_offset = self.bus_pins[port][control_signal].cx() control_pos = vector(control_x_offset, mid_pos.y) self.add_wire(self.m1_stack, [pin_pos, mid_pos, control_pos]) self.add_via_center(layers=self.m1_stack, diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 078dc3ae..c4d9f034 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -384,10 +384,10 @@ class control_logic(design.design): height = self.control_logic_center.y - self.m2_pitch offset = vector(self.ctrl_dff_array.width, 0) - self.rail_offsets = self.create_vertical_bus("m2", - offset, - self.internal_bus_list, - height) + self.input_bus = self.create_vertical_bus("m2", + offset, + self.internal_bus_list, + height) def create_instances(self): """ Create all the instances """ @@ -493,7 +493,7 @@ class control_logic(design.design): # Connect to the rail level with the vdd rail # Use pen since it is in every type of control logic vdd_ypos = self.p_en_bar_nand_inst.get_pin("vdd").by() - in_pos = vector(self.rail_offsets["rbl_bl_delay"].x, vdd_ypos) + in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos) mid1 = vector(out_pos.x, in_pos.y) self.add_wire(self.m1_stack, [out_pos, mid1, in_pos]) self.add_via_center(layers=self.m1_stack, @@ -548,7 +548,7 @@ class control_logic(design.design): def route_gated_clk_bar(self): clkbuf_map = zip(["A"], ["clk_buf"]) - self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets) + self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.input_bus) out_pos = self.clk_bar_inst.get_pin("Z").center() in_pos = self.gated_clk_bar_inst.get_pin("A").center() @@ -558,7 +558,7 @@ class control_logic(design.design): clkbuf_map = zip(["B"], ["cs"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, - self.rail_offsets, + self.input_bus, self.m2_stack[::-1]) # The pin is on M1, so we need another via as well b_pin = self.gated_clk_bar_inst.get_pin("B") @@ -586,12 +586,12 @@ class control_logic(design.design): clkbuf_map = zip(["A", "B"], ["clk_buf", "cs"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, - self.rail_offsets) + self.input_bus) clkbuf_map = zip(["Z"], ["gated_clk_buf"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, - self.rail_offsets, + self.input_bus, self.m2_stack[::-1]) # The pin is on M1, so we need another via as well z_pin = self.gated_clk_buf_inst.get_pin("Z") @@ -614,7 +614,7 @@ class control_logic(design.design): def route_wlen(self): wlen_map = zip(["A"], ["gated_clk_bar"]) - self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets) + self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus) self.connect_output(self.wl_en_inst, "Z", "wl_en") @@ -639,7 +639,7 @@ class control_logic(design.design): def route_pen(self): in_map = zip(["A", "B"], ["gated_clk_buf", "rbl_bl_delay"]) - self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.rail_offsets) + self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.input_bus) out_pin = self.p_en_bar_nand_inst.get_pin("Z") out_pos = out_pin.center() @@ -682,7 +682,7 @@ class control_logic(design.design): input_name = "cs" sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name]) - self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets) + self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.input_bus) self.connect_output(self.s_en_gate_inst, "Z", "s_en") @@ -706,7 +706,7 @@ class control_logic(design.design): self.route_output_to_bus_jogged(self.rbl_bl_delay_inv_inst, "rbl_bl_delay_bar") rbl_map = zip(["A"], ["rbl_bl_delay"]) - self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets) + self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.input_bus) def create_wen_row(self): @@ -738,7 +738,7 @@ class control_logic(design.design): input_name = "cs" wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"]) - self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.rail_offsets) + self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus) self.connect_output(self.w_en_gate_inst, "Z", "w_en") @@ -761,13 +761,13 @@ class control_logic(design.design): dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) else: dff_out_map = zip(["dout_bar_0"], ["cs"]) - self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets, self.m2_stack[::-1]) + self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.input_bus, self.m2_stack[::-1]) # Connect the clock rail to the other clock rail # by routing in the supply rail track to avoid channel conflicts in_pos = self.ctrl_dff_inst.get_pin("clk").uc() mid_pos = in_pos + vector(0, self.and2.height) - rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y) + rail_pos = vector(self.input_bus["clk_buf"].cx(), mid_pos.y) self.add_wire(self.m1_stack, [in_pos, mid_pos, rail_pos]) self.add_via_center(layers=self.m1_stack, offset=rail_pos) @@ -1001,8 +1001,8 @@ class control_logic(design.design): # Connect this at the bottom of the buffer out_pos = inst.get_pin("Z").center() mid1 = vector(out_pos.x, out_pos.y - 0.25 * inst.mod.height) - mid2 = vector(self.rail_offsets[name].x, mid1.y) - bus_pos = self.rail_offsets[name] + mid2 = vector(self.input_bus[name].cx(), mid1.y) + bus_pos = self.input_bus[name].center() self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) # The pin is on M1, so we need another via as well self.add_via_center(layers=self.m1_stack, diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index fbf8ef29..bb2b37ab 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -209,7 +209,7 @@ class hierarchical_decoder(design.design): for i in range(2): index = pre_num * 2 + i - input_pos = self.input_bus["addr_{}".format(index)] + input_pos = self.input_bus["addr_{}".format(index)].center() in_name = "in_{}".format(i) decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name) @@ -223,7 +223,7 @@ class hierarchical_decoder(design.design): for i in range(3): index = pre_num * 3 + i + self.no_of_pre2x4 * 2 - input_pos = self.input_bus["addr_{}".format(index)] + input_pos = self.input_bus["addr_{}".format(index)].center() in_name = "in_{}".format(i) decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name) @@ -572,7 +572,7 @@ class hierarchical_decoder(design.design): """ pin_pos = pin.center() - rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y) + rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y) self.add_path(self.input_layer, [rail_pos, pin_pos]) self.add_via_stack_center(from_layer=self.bus_layer, @@ -595,11 +595,11 @@ class hierarchical_decoder(design.design): pin_pos = pin.rc() mid_point1 = vector(x_offset, pin_pos.y) mid_point2 = vector(x_offset, y_offset) - rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y) + rail_pos = vector(self.predecode_bus[rail_name].cx(), mid_point2.y) self.add_path(self.output_layer, [pin_pos, mid_point1, mid_point2, rail_pos]) # pin_pos = pin.center() - # rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y) + # rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y) # self.add_path(self.output_layer, [pin_pos, rail_pos]) self.add_via_stack_center(from_layer=pin.layer, to_layer=self.output_layer, diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index d998d882..03d866fb 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -202,15 +202,15 @@ class hierarchical_predecode(design.design): y_offset = pin.cy() in_pin = "in_{}".format(num) a_pin = "A_{}".format(num) - in_pos = vector(self.input_rails[in_pin].x, y_offset) - a_pos = vector(self.decode_rails[a_pin].x, y_offset) + in_pos = vector(self.input_rails[in_pin].cx(), y_offset) + a_pos = vector(self.decode_rails[a_pin].cx(), y_offset) self.add_path(self.input_layer, [in_pos, a_pos]) self.add_via_stack_center(from_layer=self.input_layer, to_layer=self.bus_layer, - offset=[self.input_rails[in_pin].x, y_offset]) + offset=[self.input_rails[in_pin].cx(), y_offset]) self.add_via_stack_center(from_layer=self.input_layer, to_layer=self.bus_layer, - offset=[self.decode_rails[a_pin].x, y_offset]) + offset=[self.decode_rails[a_pin].cx(), y_offset]) def route_output_and(self): """ @@ -240,12 +240,12 @@ class hierarchical_predecode(design.design): # since this is where the p/n devices are and there are no # pins in the and gates. if OPTS.tech_name == "s8": - rail_pos = vector(self.decode_rails[out_pin].x, inv_out_pos.y) + rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y) self.add_path(self.output_layer, [inv_out_pos, rail_pos]) else: y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0) - rail_pos = vector(self.decode_rails[out_pin].x, y_offset) + rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset) self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) self.add_via_stack_center(from_layer=inv_out_pin.layer, @@ -259,7 +259,7 @@ class hierarchical_predecode(design.design): # route input pin = self.inv_inst[inv_num].get_pin("A") inv_in_pos = pin.center() - in_pos = vector(self.input_rails[in_pin].x, inv_in_pos.y) + in_pos = vector(self.input_rails[in_pin].cx(), inv_in_pos.y) self.add_path(self.input_layer, [in_pos, inv_in_pos]) self.add_via_stack_center(from_layer=pin.layer, to_layer=self.input_layer, @@ -290,7 +290,7 @@ class hierarchical_predecode(design.design): for rail_pin, gate_pin in zip(index_lst, gate_lst): pin = self.and_inst[k].get_pin(gate_pin) pin_pos = pin.center() - rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y) + rail_pos = vector(self.decode_rails[rail_pin].cx(), pin_pos.y) self.add_path(self.input_layer, [rail_pos, pin_pos]) self.add_via_stack_center(from_layer=self.input_layer, to_layer=self.bus_layer, diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 84f27fba..2cf4718a 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -10,6 +10,7 @@ import debug from vector import vector from sram_factory import factory from globals import OPTS +from tech import layer class precharge_array(design.design): diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index cfc2a688..76fc8676 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -13,7 +13,7 @@ from tech import parameter from vector import vector from globals import OPTS from sram_factory import factory -from tech import drc +from tech import drc, layer class precharge(design.design): @@ -38,10 +38,16 @@ class precharge(design.design): if self.bitcell_bl_pin.layer == "m1": self.bitline_layer = "m1" - self.en_layer = "m2" + if "li" in layer: + self.en_layer = "li" + else: + self.en_layer = "m2" else: self.bitline_layer = "m2" - self.en_layer = "m1" + if "li" in layer: + self.en_layer = "li" + else: + self.en_layer = "m1" # Creates the netlist and layout # Since it has variable height, it is not a pgate. From 8c6d5b49bee22effd09b3b1c6ea2a2d0ab67fe42 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 13:09:52 -0700 Subject: [PATCH 365/521] Consider diffusion spacing in active offset --- compiler/pgates/ptx.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index f6716a1f..d52925ec 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -216,7 +216,8 @@ class ptx(design.design): nwell_enclose_active = 0 # Use the max of either so that the poly gates will align properly well_enclose_active = max(pwell_enclose_active, - nwell_enclose_active) + nwell_enclose_active, + self.active_space) self.active_offset = vector([well_enclose_active] * 2) # Well enclosure of active, ensure minwidth as well From 157926960b51631f6ff8d6a74862280fd2d3f93c Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 13:48:16 -0700 Subject: [PATCH 366/521] Flip freepdk45 flop, dff_buf route layer change --- compiler/modules/dff_buf.py | 50 +++++++++++++-------------- technology/freepdk45/gds_lib/dff.gds | Bin 22528 -> 22182 bytes 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 0366b10b..81629771 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -7,7 +7,7 @@ # import debug import design -from tech import parameter +from tech import parameter, layer from tech import cell_properties as props from vector import vector from globals import OPTS @@ -52,7 +52,6 @@ class dff_buf(design.design): def create_layout(self): self.place_instances() self.width = self.inv2_inst.rx() - self.height = self.dff.height self.route_wires() self.add_layout_pins() @@ -120,39 +119,37 @@ class dff_buf(design.design): except AttributeError: pass self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing + self.well_extend_active, 0)) - + # Add INV2 to the right self.inv2_inst.place(vector(self.inv1_inst.rx(), 0)) def route_wires(self): + if "li" in layer: + self.route_layer = "li" + else: + self.route_layer = "m1" + # Route dff q to inv1 a q_pin = self.dff_inst.get_pin("Q") a1_pin = self.inv1_inst.get_pin("A") - mid_x_offset = 0.5 * (a1_pin.cx() + q_pin.cx()) - mid1 = vector(mid_x_offset, q_pin.cy()) - mid2 = vector(mid_x_offset, a1_pin.cy()) - self.add_path("m3", [q_pin.center(), mid1, mid2, a1_pin.center()]) - self.add_via_center(layers=self.m2_stack, - offset=q_pin.center()) - self.add_via_center(layers=self.m2_stack, - offset=a1_pin.center()) - self.add_via_center(layers=self.m1_stack, - offset=a1_pin.center()) + mid1 = vector(a1_pin.cx(), q_pin.cy()) + self.add_path(q_pin.layer, [q_pin.center(), mid1, a1_pin.center()]) + self.add_via_stack_center(from_layer=a1_pin.layer, + to_layer=q_pin.layer, + offset=a1_pin.center()) # Route inv1 z to inv2 a z1_pin = self.inv1_inst.get_pin("Z") a2_pin = self.inv2_inst.get_pin("A") - mid_x_offset = 0.5 * (z1_pin.cx() + a2_pin.cx()) - self.mid_qb_pos = vector(mid_x_offset, z1_pin.cy()) - mid2 = vector(mid_x_offset, a2_pin.cy()) - self.add_path("m1", [z1_pin.center(), self.mid_qb_pos, mid2, a2_pin.center()]) + self.mid_qb_pos = vector(0.5 * (z1_pin.cx() + a2_pin.cx()), z1_pin.cy()) + self.add_zjog(z1_pin.layer, z1_pin.center(), a2_pin.center()) def add_layout_pins(self): # Continous vdd rail along with label. vdd_pin=self.dff_inst.get_pin("vdd") self.add_layout_pin(text="vdd", - layer="m1", + layer=vdd_pin.layer, offset=vdd_pin.ll(), width=self.width, height=vdd_pin.height()) @@ -160,7 +157,7 @@ class dff_buf(design.design): # Continous gnd rail along with label. gnd_pin=self.dff_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="m1", + layer=gnd_pin.layer, offset=gnd_pin.ll(), width=self.width, height=vdd_pin.height()) @@ -185,17 +182,20 @@ class dff_buf(design.design): self.add_layout_pin_rect_center(text="Q", layer="m2", offset=q_pos) - self.add_path("m1", [dout_pin.center(), mid_pos, q_pos]) - self.add_via_center(layers=self.m1_stack, - offset=q_pos) + self.add_path(self.route_layer, [dout_pin.center(), mid_pos, q_pos]) + self.add_via_stack_center(from_layer=dout_pin.layer, + to_layer="m2", + offset=q_pos) qb_pos = self.mid_qb_pos + vector(0, self.m2_pitch) self.add_layout_pin_rect_center(text="Qb", layer="m2", offset=qb_pos) - self.add_path("m1", [self.mid_qb_pos, qb_pos]) - self.add_via_center(layers=self.m1_stack, - offset=qb_pos) + self.add_path(self.route_layer, [self.mid_qb_pos, qb_pos]) + a2_pin = self.inv2_inst.get_pin("A") + self.add_via_stack_center(from_layer=a2_pin.layer, + to_layer="m2", + offset=qb_pos) def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" diff --git a/technology/freepdk45/gds_lib/dff.gds b/technology/freepdk45/gds_lib/dff.gds index 526a1861149039682e51578ccf5624d908940ae9..2a6004d145d7ef077006b8a6b4a6abce4d37eef4 100644 GIT binary patch literal 22182 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mrg Date: Tue, 9 Jun 2020 13:48:47 -0700 Subject: [PATCH 367/521] Remove stdc layer --- compiler/base/hierarchy_layout.py | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index d3b84ca5..4485f622 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -695,8 +695,8 @@ class layout(): # we should add a boundary just for DRC in some technologies if not self.is_library_cell and not self.bounding_box: # If there is a boundary layer, and we didn't create one, add one. - if "stdc" in techlayer.keys(): - boundary_layer = "stdc" + if "boundary" in techlayer.keys(): + boundary_layer = "boundary" boundary = [self.find_lowest_coords(), self.find_highest_coords()] debug.check(boundary[0] and boundary[1], "No shapes to make a boundary.") @@ -1259,10 +1259,7 @@ class layout(): if OPTS.netlist_only: return - if "stdc" in techlayer.keys(): - boundary_layer = "stdc" - else: - boundary_layer = "boundary" + boundary_layer = "boundary" if not ur: self.bounding_box = self.add_rect(layer=boundary_layer, offset=ll, From a28e747a02bad32b46039391c018aa16fd9477be Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 15:28:50 -0700 Subject: [PATCH 368/521] Fix precharge offset. Move well rules to design class. --- compiler/base/design.py | 14 +++++++ compiler/pgates/precharge.py | 8 +--- compiler/pgates/ptx.py | 20 ++------- compiler/tests/04_precharge_1rw_1r_test.py | 47 ++++++++++++++++++++++ 4 files changed, 66 insertions(+), 23 deletions(-) create mode 100755 compiler/tests/04_precharge_1rw_1r_test.py diff --git a/compiler/base/design.py b/compiler/base/design.py index 7a570b28..1fded37e 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -172,6 +172,20 @@ class design(hierarchy_design): self.well_extend_active = max(self.well_extend_active, self.nwell_extend_active) if "pwell" in layer: self.well_extend_active = max(self.well_extend_active, self.pwell_extend_active) + + # The active offset is due to the well extension + if "pwell" in layer: + self.pwell_enclose_active = drc("pwell_enclose_active") + else: + self.pwell_enclose_active = 0 + if "nwell" in layer: + self.nwell_enclose_active = drc("nwell_enclose_active") + else: + self.nwell_enclose_active = 0 + # Use the max of either so that the poly gates will align properly + self.well_enclose_active = max(self.pwell_enclose_active, + self.nwell_enclose_active, + self.active_space) # These are for debugging previous manual rules if False: diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 76fc8676..07b4f21b 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -149,13 +149,9 @@ class precharge(design.design): # Compute the other pmos2 location, # but determining offset to overlap the source and drain pins overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll() - # This is how much the contact is placed inside the ptx active - contact_xdiff = self.pmos.get_pin("S").lx() # adds the lower pmos to layout - bl_xoffset = self.bitcell_bl_pin.lx() - self.lower_pmos_position = vector(max(bl_xoffset - contact_xdiff, - self.nwell_enclose_active), + self.lower_pmos_position = vector(self.well_enclose_active + 0.5 * self.m1_width, self.initial_yoffset) self.lower_pmos_inst.place(self.lower_pmos_position) @@ -218,7 +214,7 @@ class precharge(design.design): # adds the contact from active to metal1 offset_height = self.upper_pmos1_inst.uy() + \ - 0.5 * contact.active_contact.height + \ + contact.active_contact.height + \ self.nwell_extend_active self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) + \ vector(0, offset_height) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index d52925ec..6fba247e 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -205,29 +205,15 @@ class ptx(design.design): # Poly height must include poly extension over active self.poly_height = self.tx_width + 2 * self.poly_extend_active - # The active offset is due to the well extension - if "pwell" in layer: - pwell_enclose_active = drc("pwell_enclose_active") - else: - pwell_enclose_active = 0 - if "nwell" in layer: - nwell_enclose_active = drc("nwell_enclose_active") - else: - nwell_enclose_active = 0 - # Use the max of either so that the poly gates will align properly - well_enclose_active = max(pwell_enclose_active, - nwell_enclose_active, - self.active_space) - self.active_offset = vector([well_enclose_active] * 2) + self.active_offset = vector([self.well_enclose_active] * 2) # Well enclosure of active, ensure minwidth as well well_name = "{}well".format(self.well_type) if well_name in layer: well_width_rule = drc("minwidth_" + well_name) - well_enclose_active = drc(well_name + "_enclose_active") - self.well_width = max(self.active_width + 2 * well_enclose_active, + self.well_width = max(self.active_width + 2 * self.well_enclose_active, well_width_rule) - self.well_height = max(self.active_height + 2 * well_enclose_active, + self.well_height = max(self.active_height + 2 * self.well_enclose_active, well_width_rule) # We are going to shift the 0,0, so include that in the width and height self.height = self.well_height - self.active_offset.y diff --git a/compiler/tests/04_precharge_1rw_1r_test.py b/compiler/tests/04_precharge_1rw_1r_test.py new file mode 100755 index 00000000..4765c77c --- /dev/null +++ b/compiler/tests/04_precharge_1rw_1r_test.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class precharge_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + # check precharge array in multi-port + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Checking precharge for 1rw1r port 0") + tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + factory.reset() + debug.info(2, "Checking precharge for 1rw1r port 1") + tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(tx) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 580b0601b5d637ec2ff06919350972c3536bf251 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 16:04:39 -0700 Subject: [PATCH 369/521] Unskip 20_psram_1bank_4mux_1rw_1r_test --- compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 145d1723..ecbd0863 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -15,7 +15,6 @@ from globals import OPTS from sram_factory import factory import debug -@unittest.skip("SKIPPING 20_psram_1bank_4mux_1rw_1r_test - Matt sucks, don't do this") class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): From fd49d3ed6ae263d873fabbaeae3e2dd935367a56 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 16:09:15 -0700 Subject: [PATCH 370/521] Add tech specific skip tests for making new techs. --- .gitlab-ci.yml | 16 ++++----- compiler/tests/regress.py | 18 ++++++++-- compiler/tests/skip_tests_s8.txt | 56 ++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+), 11 deletions(-) create mode 100644 compiler/tests/skip_tests_s8.txt diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 27431cb2..02778d35 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -25,14 +25,14 @@ scn4m_subm: - .coverage.* expire_in: 1 week -# s8: -# stage: test -# script: -# - coverage run -p $OPENRAM_HOME/tests/regress.py -t s8 -# artifacts: -# paths: -# - .coverage.* -# expire_in: 1 week +s8: + stage: test + script: + - coverage run -p $OPENRAM_HOME/tests/regress.py -t s8 + artifacts: + paths: + - .coverage.* + expire_in: 1 week coverage: stage: coverage diff --git a/compiler/tests/regress.py b/compiler/tests/regress.py index e60b010d..80754d0e 100755 --- a/compiler/tests/regress.py +++ b/compiler/tests/regress.py @@ -12,6 +12,7 @@ import unittest import sys,os sys.path.append(os.getenv("OPENRAM_HOME")) import globals +import debug (OPTS, args) = globals.parse_args() del sys.argv[1:] @@ -22,14 +23,25 @@ header(__file__, OPTS.tech_name) # get a list of all files in the tests directory files = os.listdir(sys.path[0]) +# load a file with all tests to skip in a given technology +# since tech_name is dynamically loaded, we can't use @skip directives +try: + skip_file = open("skip_tests_{}.txt".format(OPTS.tech_name), "r") + skip_tests = skip_file.read().splitlines() + for st in skip_tests: + debug.warning("Skipping: " + st) +except FileNotFoundError: + skip_tests = [] + # assume any file that ends in "test.py" in it is a regression test nametest = re.compile("test\.py$", re.IGNORECASE) -tests = list(filter(nametest.search, files)) -tests.sort() +all_tests = list(filter(nametest.search, files)) +filtered_tests = list(filter(lambda i: i not in skip_tests, all_tests)) +filtered_tests.sort() # import all of the modules filenameToModuleName = lambda f: os.path.splitext(f)[0] -moduleNames = map(filenameToModuleName, tests) +moduleNames = map(filenameToModuleName, filtered_tests) modules = map(__import__, moduleNames) suite = unittest.TestSuite() load = unittest.defaultTestLoader.loadTestsFromModule diff --git a/compiler/tests/skip_tests_s8.txt b/compiler/tests/skip_tests_s8.txt new file mode 100644 index 00000000..8e0f1746 --- /dev/null +++ b/compiler/tests/skip_tests_s8.txt @@ -0,0 +1,56 @@ +04_dummy_pbitcell_test.py +04_pbitcell_test.py +04_precharge_pbitcell_test.py +04_replica_pbitcell_test.py +04_single_level_column_mux_pbitcell_test.py +05_pbitcell_array_test.py +06_hierarchical_decoder_pbitcell_test.py +06_hierarchical_predecode2x4_pbitcell_test.py +06_hierarchical_predecode3x8_pbitcell_test.py +07_single_level_column_mux_array_pbitcell_test.py +08_wordline_driver_array_pbitcell_test.py +09_sense_amp_array_test_pbitcell.py +10_write_driver_array_pbitcell_test.py +10_write_driver_array_wmask_pbitcell_test.py +10_write_mask_and_array_pbitcell_test.py +14_replica_pbitcell_array_test.py +19_bank_select_pbitcell_test.py +05_bitcell_1rw_1r_array_test.py +05_bitcell_array_test.py +05_dummy_array_test.py +05_pbitcell_array_test.py +06_hierarchical_decoder_pbitcell_test.py +06_hierarchical_decoder_test.py +06_hierarchical_predecode2x4_pbitcell_test.py +06_hierarchical_predecode2x4_test.py +06_hierarchical_predecode3x8_pbitcell_test.py +06_hierarchical_predecode3x8_test.py +06_hierarchical_predecode4x16_test.py +04_dummy_pbitcell_test.py +04_pbitcell_test.py +04_precharge_pbitcell_test.py +04_replica_pbitcell_test.py +04_single_level_column_mux_pbitcell_test.py +05_bitcell_1rw_1r_array_test.py +05_bitcell_array_test.py +05_dummy_array_test.py +05_pbitcell_array_test.py +05_pbitcell_array_test.py +06_hierarchical_decoder_pbitcell_test.py +06_hierarchical_decoder_pbitcell_test.py +06_hierarchical_decoder_test.py +06_hierarchical_predecode2x4_pbitcell_test.py +06_hierarchical_predecode2x4_pbitcell_test.py +06_hierarchical_predecode2x4_test.py +06_hierarchical_predecode3x8_pbitcell_test.py +06_hierarchical_predecode3x8_pbitcell_test.py +06_hierarchical_predecode3x8_test.py +06_hierarchical_predecode4x16_test.py +07_single_level_column_mux_array_pbitcell_test.py +08_wordline_driver_array_pbitcell_test.py +09_sense_amp_array_test_pbitcell.py +10_write_driver_array_pbitcell_test.py +10_write_driver_array_wmask_pbitcell_test.py +10_write_mask_and_array_pbitcell_test.py +14_replica_pbitcell_array_test.py +19_bank_select_pbitcell_test.py From c6b875146d40b6779f907bffb78141aafed5a261 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 16:33:59 -0700 Subject: [PATCH 371/521] Use local skip file --- compiler/tests/regress.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/tests/regress.py b/compiler/tests/regress.py index 80754d0e..e13d250a 100755 --- a/compiler/tests/regress.py +++ b/compiler/tests/regress.py @@ -12,7 +12,6 @@ import unittest import sys,os sys.path.append(os.getenv("OPENRAM_HOME")) import globals -import debug (OPTS, args) = globals.parse_args() del sys.argv[1:] @@ -26,7 +25,8 @@ files = os.listdir(sys.path[0]) # load a file with all tests to skip in a given technology # since tech_name is dynamically loaded, we can't use @skip directives try: - skip_file = open("skip_tests_{}.txt".format(OPTS.tech_name), "r") + skip_file_name = "skip_tests_{}.txt".format(OPTS.tech_name) + skip_file = open(skip_file_name, "r") skip_tests = skip_file.read().splitlines() for st in skip_tests: debug.warning("Skipping: " + st) From e6babc301daa9956d745d72f4bc3568d8fff62a9 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 16:34:15 -0700 Subject: [PATCH 372/521] Incrase space for pnand gates --- compiler/pgates/pnand2.py | 6 +++--- compiler/pgates/pnand3.py | 11 +++++------ 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 51581e61..5816adcf 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -177,9 +177,9 @@ class pnand2(pgate.pgate): # Top of NMOS drain - nmos_pin = self.nmos2_inst.get_pin("D") - bottom_pin_offset = nmos_pin.uy() - self.inputA_yoffset = bottom_pin_offset + self.m1_pitch + bottom_pin = self.nmos2_inst.get_pin("D") + self.inputA_yoffset = max(bottom_pin.uy() + self.m1_pitch, + self.nmos2_inst.uy() + self.poly_to_active) self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 6cbd7cca..fa028246 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -212,10 +212,9 @@ class pnand3(pgate.pgate): pmos_drain_bottom = self.pmos1_inst.get_pin("D").by() self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space - # This is a more compact offset, but the bottom one works better in the decoders to "center" the pins - # in the height of the gates - self.inputA_yoffset = self.output_yoffset - 0.5 * self.route_layer_width - self.route_layer_space - # self.inputA_yoffset = self.output_yoffset - self.m1_pitch + bottom_pin = self.nmos1_inst.get_pin("D") + self.inputA_yoffset = max(bottom_pin.uy() + self.m1_pitch, + self.nmos1_inst.uy() + self.poly_to_active) self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, @@ -223,14 +222,14 @@ class pnand3(pgate.pgate): position="left") # Put B right on the well line - self.inputB_yoffset = self.inputA_yoffset - self.m1_pitch + self.inputB_yoffset = self.inputA_yoffset + self.m1_pitch self.route_input_gate(self.pmos2_inst, self.nmos2_inst, self.inputB_yoffset, "B", position="center") - self.inputC_yoffset = self.inputB_yoffset - self.m1_pitch + self.inputC_yoffset = self.inputB_yoffset + self.m1_pitch self.route_input_gate(self.pmos3_inst, self.nmos3_inst, self.inputC_yoffset, From 14782914b33330181e89d3cd150774d3786ed83b Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 16:40:59 -0700 Subject: [PATCH 373/521] Remove vertical pand gates --- compiler/tests/04_pand2_test.py | 4 ---- compiler/tests/04_pand3_test.py | 4 ---- 2 files changed, 8 deletions(-) diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index 21a0a38e..f7e5f304 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -29,10 +29,6 @@ class pand2_test(openram_test): a = pand2.pand2(name="pand2x4", size=4) self.local_check(a) - debug.info(2, "Testing vertical pand2 gate 4x") - a = pand2.pand2(name="pand2x4", size=4, vertical=True) - self.local_check(a) - globals.end_openram() # instantiate a copdsay of the class to actually run the test diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index f851077b..e58f1ee9 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -29,10 +29,6 @@ class pand3_test(openram_test): a = pand3.pand3(name="pand3x4", size=4) self.local_check(a) - debug.info(2, "Testing vertical pand3 gate 4x") - a = pand3.pand3(name="pand3x4", size=4, vertical=True) - self.local_check(a) - globals.end_openram() # instantiate a copdsay of the class to actually run the test From 064fe34edf55fbb1c358598652d26820d6b86d67 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 17:16:35 -0700 Subject: [PATCH 374/521] Fix pinvbuf layers --- compiler/pgates/pinvbuf.py | 42 ++++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index fe376bc4..5b286e9b 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -9,7 +9,7 @@ import debug import pgate from vector import vector from sram_factory import factory - +from tech import layer class pinvbuf(pgate.pgate): """ @@ -111,33 +111,45 @@ class pinvbuf(pgate.pgate): mirror="MX") def route_wires(self): + if "li" in layer: + route_stack = self.li_stack + else: + route_stack = self.m1_stack + # inv1 Z to inv2 A z1_pin = self.inv1_inst.get_pin("Z") a2_pin = self.inv2_inst.get_pin("A") mid_point = vector(z1_pin.cx(), a2_pin.cy()) - self.add_path("m1", [z1_pin.center(), mid_point, a2_pin.center()]) + self.add_path(z1_pin.layer, [z1_pin.center(), mid_point, a2_pin.center()]) + self.add_via_stack_center(from_layer=z1_pin.layer, + to_layer=a2_pin.layer, + offset=a2_pin.center()) # inv2 Z to inv3 A z2_pin = self.inv2_inst.get_pin("Z") a3_pin = self.inv3_inst.get_pin("A") mid_point = vector(z2_pin.cx(), a3_pin.cy()) - self.add_path("m1", [z2_pin.center(), mid_point, a3_pin.center()]) + self.add_path(z2_pin.layer, [z2_pin.center(), mid_point, a3_pin.center()]) + self.add_via_stack_center(from_layer=z2_pin.layer, + to_layer=a3_pin.layer, + offset=a3_pin.center()) # inv1 Z to inv4 A (up and over) z1_pin = self.inv1_inst.get_pin("Z") a4_pin = self.inv4_inst.get_pin("A") mid_point = vector(z1_pin.cx(), a4_pin.cy()) - self.add_wire(self.m1_stack, + self.add_wire(route_stack, [z1_pin.center(), mid_point, a4_pin.center()]) - self.add_via_center(layers=self.m1_stack, - offset=z1_pin.center()) + self.add_via_stack_center(from_layer=z1_pin.layer, + to_layer=route_stack[2], + offset=z1_pin.center()) def add_layout_pins(self): # Continous vdd rail along with label. vdd_pin = self.inv1_inst.get_pin("vdd") self.add_layout_pin(text="vdd", - layer="m1", + layer=vdd_pin.layer, offset=vdd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) @@ -145,7 +157,7 @@ class pinvbuf(pgate.pgate): # Continous vdd rail along with label. gnd_pin = self.inv4_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="m1", + layer=gnd_pin.layer, offset=gnd_pin.ll().scale(0, 1), width=self.width, height=gnd_pin.height()) @@ -153,31 +165,25 @@ class pinvbuf(pgate.pgate): # Continous gnd rail along with label. gnd_pin = self.inv1_inst.get_pin("gnd") self.add_layout_pin(text="gnd", - layer="m1", + layer=gnd_pin.layer, offset=gnd_pin.ll().scale(0, 1), width=self.width, height=vdd_pin.height()) z_pin = self.inv4_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", - layer="m2", + layer=z_pin.layer, offset=z_pin.center()) - self.add_via_center(layers=self.m1_stack, - offset=z_pin.center()) zb_pin = self.inv3_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Zb", - layer="m2", + layer=zb_pin.layer, offset=zb_pin.center()) - self.add_via_center(layers=self.m1_stack, - offset=zb_pin.center()) a_pin = self.inv1_inst.get_pin("A") self.add_layout_pin_rect_center(text="A", - layer="m2", + layer=a_pin.layer, offset=a_pin.center()) - self.add_via_center(layers=self.m1_stack, - offset=a_pin.center()) def determine_clk_buf_stage_efforts(self, external_cout, inp_is_rise=False): """Get the stage efforts of the clk -> clk_buf path""" From d4fc88124ad6f9127e9c2179a06a92e166409846 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 9 Jun 2020 17:18:19 -0700 Subject: [PATCH 375/521] Rename dff_buf test --- compiler/tests/{11_dff_buf_test.py => 04_dff_buf_test.py} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename compiler/tests/{11_dff_buf_test.py => 04_dff_buf_test.py} (100%) diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/04_dff_buf_test.py similarity index 100% rename from compiler/tests/11_dff_buf_test.py rename to compiler/tests/04_dff_buf_test.py From c119e60e797a2fecbcd32d2690a9343626269ec1 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 10:14:52 -0700 Subject: [PATCH 376/521] Add more s8 skip tests --- .../tests/09_sense_amp_array_1rw_1r_test.py | 48 ++++++++++++ compiler/tests/skip_tests_s8.txt | 78 +++++++++++-------- 2 files changed, 94 insertions(+), 32 deletions(-) create mode 100755 compiler/tests/09_sense_amp_array_1rw_1r_test.py diff --git a/compiler/tests/09_sense_amp_array_1rw_1r_test.py b/compiler/tests/09_sense_amp_array_1rw_1r_test.py new file mode 100755 index 00000000..a8ed4d2f --- /dev/null +++ b/compiler/tests/09_sense_amp_array_1rw_1r_test.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class sense_amp_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1) + self.local_check(a) + + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2) + self.local_check(a) + + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4") + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/skip_tests_s8.txt b/compiler/tests/skip_tests_s8.txt index 8e0f1746..9f60d65e 100644 --- a/compiler/tests/skip_tests_s8.txt +++ b/compiler/tests/skip_tests_s8.txt @@ -3,18 +3,6 @@ 04_precharge_pbitcell_test.py 04_replica_pbitcell_test.py 04_single_level_column_mux_pbitcell_test.py -05_pbitcell_array_test.py -06_hierarchical_decoder_pbitcell_test.py -06_hierarchical_predecode2x4_pbitcell_test.py -06_hierarchical_predecode3x8_pbitcell_test.py -07_single_level_column_mux_array_pbitcell_test.py -08_wordline_driver_array_pbitcell_test.py -09_sense_amp_array_test_pbitcell.py -10_write_driver_array_pbitcell_test.py -10_write_driver_array_wmask_pbitcell_test.py -10_write_mask_and_array_pbitcell_test.py -14_replica_pbitcell_array_test.py -19_bank_select_pbitcell_test.py 05_bitcell_1rw_1r_array_test.py 05_bitcell_array_test.py 05_dummy_array_test.py @@ -26,31 +14,57 @@ 06_hierarchical_predecode3x8_pbitcell_test.py 06_hierarchical_predecode3x8_test.py 06_hierarchical_predecode4x16_test.py -04_dummy_pbitcell_test.py -04_pbitcell_test.py -04_precharge_pbitcell_test.py -04_replica_pbitcell_test.py -04_single_level_column_mux_pbitcell_test.py -05_bitcell_1rw_1r_array_test.py -05_bitcell_array_test.py -05_dummy_array_test.py -05_pbitcell_array_test.py -05_pbitcell_array_test.py -06_hierarchical_decoder_pbitcell_test.py -06_hierarchical_decoder_pbitcell_test.py -06_hierarchical_decoder_test.py -06_hierarchical_predecode2x4_pbitcell_test.py -06_hierarchical_predecode2x4_pbitcell_test.py -06_hierarchical_predecode2x4_test.py -06_hierarchical_predecode3x8_pbitcell_test.py -06_hierarchical_predecode3x8_pbitcell_test.py -06_hierarchical_predecode3x8_test.py -06_hierarchical_predecode4x16_test.py 07_single_level_column_mux_array_pbitcell_test.py 08_wordline_driver_array_pbitcell_test.py 09_sense_amp_array_test_pbitcell.py 10_write_driver_array_pbitcell_test.py +10_write_driver_array_test.py 10_write_driver_array_wmask_pbitcell_test.py +10_write_driver_array_wmask_test.py 10_write_mask_and_array_pbitcell_test.py +10_write_mask_and_array_test.py 14_replica_pbitcell_array_test.py +18_port_address_test.py +18_port_data_test.py +18_port_data_wmask_test.py 19_bank_select_pbitcell_test.py +20_psram_1bank_2mux_1rw_1w_test.py +20_psram_1bank_2mux_1rw_1w_wmask_test.py +20_psram_1bank_2mux_1w_1r_test.py +20_psram_1bank_2mux_test.py +20_psram_1bank_4mux_1rw_1r_test.py +20_sram_1bank_2mux_1w_1r_test.py +20_sram_1bank_2mux_test.py +20_sram_1bank_2mux_wmask_test.py +20_sram_1bank_32b_1024_wmask_test.py +20_sram_1bank_4mux_test.py +20_sram_1bank_8mux_test.py +20_sram_1bank_nomux_test.py +20_sram_1bank_nomux_wmask_test.py +20_sram_2bank_test.py +21_hspice_delay_test.py +21_hspice_setuphold_test.py +21_model_delay_test.py +21_ngspice_delay_test.py +21_ngspice_setuphold_test.py +22_psram_1bank_2mux_func_test.py +22_psram_1bank_4mux_func_test.py +22_psram_1bank_8mux_func_test.py +22_psram_1bank_nomux_func_test.py +22_sram_1bank_2mux_func_test.py +22_sram_1bank_4mux_func_test.py +22_sram_1bank_8mux_func_test.py +22_sram_1bank_nomux_func_test.py +22_sram_1rw_1r_1bank_nomux_func_test.py +22_sram_wmask_func_test.py +23_lib_sram_model_corners_test.py +23_lib_sram_model_test.py +23_lib_sram_prune_test.py +23_lib_sram_test.py +24_lef_sram_test.py +25_verilog_sram_test.py +26_hspice_pex_pinv_test.py +26_ngspice_pex_pinv_test.py +26_pex_test.py +30_openram_back_end_test.py +30_openram_front_end_test.py From 5e3332453b2925c689ac2c034cb1a65a10b0cc16 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 10:15:23 -0700 Subject: [PATCH 377/521] Allow power pins to start on any layer besides m1 --- compiler/base/hierarchy_layout.py | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 4485f622..362c0f9e 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1304,13 +1304,10 @@ class layout(): pin.ll(), pin.width(), pin.height()) - elif pin.layer == "m1": - self.add_power_pin(name, pin.center()) - else: - debug.warning("{0} pins of {1} should be on {2} or metal1 for "\ - "supply router." - .format(name, inst.name, self.pwr_grid_layer)) + else: + self.add_power_pin(name, pin.center(), start_layer=pin.layer) + def add_power_pin(self, name, loc, size=[1, 1], directions=None, start_layer="m1"): """ Add a single power pin from the lowest power_grid layer down to M1 (or li) at From 10be2d08b5eac5e532e14366f5d143bb479337ba Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 10:23:05 -0700 Subject: [PATCH 378/521] Full path to skip tests file --- compiler/tests/regress.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/tests/regress.py b/compiler/tests/regress.py index e13d250a..3fd5d6eb 100755 --- a/compiler/tests/regress.py +++ b/compiler/tests/regress.py @@ -25,7 +25,7 @@ files = os.listdir(sys.path[0]) # load a file with all tests to skip in a given technology # since tech_name is dynamically loaded, we can't use @skip directives try: - skip_file_name = "skip_tests_{}.txt".format(OPTS.tech_name) + skip_file_name = "{0}/tests/skip_tests_{1}.txt".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) skip_file = open(skip_file_name, "r") skip_tests = skip_file.read().splitlines() for st in skip_tests: From f2c45a230ed929e1d08b7e9fee5c020490a44fe3 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 11:00:00 -0700 Subject: [PATCH 379/521] Add new replica column test. Add more skip tests. --- .../tests/14_replica_column_1rw_1r_test.py | 46 +++++++++++++++++++ compiler/tests/skip_tests_s8.txt | 17 +++++++ 2 files changed, 63 insertions(+) create mode 100755 compiler/tests/14_replica_column_1rw_1r_test.py diff --git a/compiler/tests/14_replica_column_1rw_1r_test.py b/compiler/tests/14_replica_column_1rw_1r_test.py new file mode 100755 index 00000000..3c1a0e1e --- /dev/null +++ b/compiler/tests/14_replica_column_1rw_1r_test.py @@ -0,0 +1,46 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class replica_column_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing replica column for 6t_cell") + a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1) + self.local_check(a) + + debug.info(2, "Testing replica column for 6t_cell") + a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=1, replica_bit=6) + self.local_check(a) + + debug.info(2, "Testing replica column for 6t_cell") + a = factory.create(module_type="replica_column", rows=4, left_rbl=2, right_rbl=0, replica_bit=2) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/skip_tests_s8.txt b/compiler/tests/skip_tests_s8.txt index 9f60d65e..68a6549b 100644 --- a/compiler/tests/skip_tests_s8.txt +++ b/compiler/tests/skip_tests_s8.txt @@ -16,18 +16,35 @@ 06_hierarchical_predecode4x16_test.py 07_single_level_column_mux_array_pbitcell_test.py 08_wordline_driver_array_pbitcell_test.py +08_wordline_driver_array_test.py 09_sense_amp_array_test_pbitcell.py +09_sense_amp_array_test.py 10_write_driver_array_pbitcell_test.py 10_write_driver_array_test.py 10_write_driver_array_wmask_pbitcell_test.py 10_write_driver_array_wmask_test.py 10_write_mask_and_array_pbitcell_test.py 10_write_mask_and_array_test.py +12_tri_gate_array_test.py 14_replica_pbitcell_array_test.py +14_replica_bitcell_array_test.py +14_replica_column_test.py +14_replica_column_1rw_1r_test.py 18_port_address_test.py 18_port_data_test.py 18_port_data_wmask_test.py 19_bank_select_pbitcell_test.py +19_bank_select_test.py +19_psingle_bank_test.py +19_bank_select_pbitcell_test.py +19_pmulti_bank_test.py +19_multi_bank_test.py +19_psingle_bank_test.py +19_single_bank_1w_1r_test.py +19_single_bank_wmask_1rw_1r_test.py +19_single_bank_1rw_1r_test.py +19_single_bank_test.py +19_single_bank_wmask_test.py 20_psram_1bank_2mux_1rw_1w_test.py 20_psram_1bank_2mux_1rw_1w_wmask_test.py 20_psram_1bank_2mux_1w_1r_test.py From 469cd260b954cd191a9291eca69e61170dbf2bea Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 14:54:20 -0700 Subject: [PATCH 380/521] Change bitcell array name to match --- ...ell_1rw_1r_array_test.py => 05_bitcell_array_1rw_1r_test.py} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename compiler/tests/{05_bitcell_1rw_1r_array_test.py => 05_bitcell_array_1rw_1r_test.py} (96%) diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_array_1rw_1r_test.py similarity index 96% rename from compiler/tests/05_bitcell_1rw_1r_array_test.py rename to compiler/tests/05_bitcell_array_1rw_1r_test.py index 0683d127..0e7d5665 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_array_1rw_1r_test.py @@ -17,7 +17,7 @@ import debug #@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test") -class bitcell_1rw_1r_array_test(openram_test): +class bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) From bfd1abc79f738177c393b0137d5455bcc9d5cf2b Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 14:58:55 -0700 Subject: [PATCH 381/521] Replica column pins start at 0 height. --- compiler/modules/replica_column.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index afe87497..603bebfe 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -154,7 +154,7 @@ class replica_column(design.design): bl_pin = self.cell_inst[0].get_pin(bl_name) self.add_layout_pin(text=bl_name, layer=bl_pin.layer, - offset=bl_pin.ll(), + offset=bl_pin.ll().scale(1, 0), width=bl_pin.width(), height=self.height) From 78c66d7c3453b7bca2774012998381fd3e892c73 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 15:00:29 -0700 Subject: [PATCH 382/521] Disable CI for s8 to commit to dev --- .gitlab-ci.yml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 02778d35..27431cb2 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -25,14 +25,14 @@ scn4m_subm: - .coverage.* expire_in: 1 week -s8: - stage: test - script: - - coverage run -p $OPENRAM_HOME/tests/regress.py -t s8 - artifacts: - paths: - - .coverage.* - expire_in: 1 week +# s8: +# stage: test +# script: +# - coverage run -p $OPENRAM_HOME/tests/regress.py -t s8 +# artifacts: +# paths: +# - .coverage.* +# expire_in: 1 week coverage: stage: coverage From 0b4b5e713361277beb10cd69e51cab1d4e33afc6 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 16:19:24 -0700 Subject: [PATCH 383/521] More exact input spacing in pnand3 --- compiler/pgates/pnand3.py | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index fa028246..31024d82 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -12,7 +12,7 @@ from vector import vector import logical_effort from sram_factory import factory from globals import OPTS - +import contact class pnand3(pgate.pgate): """ @@ -209,12 +209,21 @@ class pnand3(pgate.pgate): def route_inputs(self): """ Route the A and B and C inputs """ + # We can use this pitch because the contacts and overlap won't be adjacent + non_contact_pitch = 0.5 * self.m1_width + self.m1_space + 0.5 * contact.poly_contact.second_layer_height pmos_drain_bottom = self.pmos1_inst.get_pin("D").by() self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space bottom_pin = self.nmos1_inst.get_pin("D") - self.inputA_yoffset = max(bottom_pin.uy() + self.m1_pitch, - self.nmos1_inst.uy() + self.poly_to_active) + # active contact metal to poly contact metal spacing + active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height + # active diffusion to poly contact spacing + # doesn't use nmos uy because that is calculated using offset + poly height + active_to_poly_contact = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height \ + + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height + + self.inputA_yoffset = max(active_contact_to_poly_contact, + active_to_poly_contact) self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, @@ -222,14 +231,14 @@ class pnand3(pgate.pgate): position="left") # Put B right on the well line - self.inputB_yoffset = self.inputA_yoffset + self.m1_pitch + self.inputB_yoffset = self.inputA_yoffset + non_contact_pitch self.route_input_gate(self.pmos2_inst, self.nmos2_inst, self.inputB_yoffset, "B", position="center") - self.inputC_yoffset = self.inputB_yoffset + self.m1_pitch + self.inputC_yoffset = self.inputB_yoffset + non_contact_pitch self.route_input_gate(self.pmos3_inst, self.nmos3_inst, self.inputC_yoffset, From fdf92d0da1fdcc88b8c0119600e80aed8ad534b5 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 16:41:26 -0700 Subject: [PATCH 384/521] Rename test 14 --- ...1r_array_test.py => 14_replica_bitcell_array_1rw_1r_test.py} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename compiler/tests/{14_replica_bitcell_1rw_1r_array_test.py => 14_replica_bitcell_array_1rw_1r_test.py} (95%) diff --git a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py similarity index 95% rename from compiler/tests/14_replica_bitcell_1rw_1r_array_test.py rename to compiler/tests/14_replica_bitcell_array_1rw_1r_test.py index 3f869255..a36fc80f 100755 --- a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py @@ -13,7 +13,7 @@ from globals import OPTS from sram_factory import factory import debug -class replica_bitcell_array_test(openram_test): +class replica_bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) From 196e5998c8753f410bf31a01dc351231cdda4a99 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 16:52:51 -0700 Subject: [PATCH 385/521] Half poly space per cell at top and bottom. --- compiler/pgates/pgate.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index a8c45641..7ff73092 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -46,7 +46,8 @@ class pgate(design.design): # This is the space from a S/D contact to the supply rail contact_to_vdd_rail_space = 0.5 * self.m1_width + self.m1_space # This is a poly-to-poly of a flipped cell - poly_to_poly_gate_space = self.poly_extend_active + self.poly_space + poly_to_poly_gate_space = self.poly_extend_active + 0.5 * self.poly_space + self.top_bottom_space = max(contact_to_vdd_rail_space, poly_to_poly_gate_space) From f973dd6a5cbc0d7d28df9b1640471909ec8ba0a2 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 11 Jun 2020 11:53:34 -0700 Subject: [PATCH 386/521] Save LVS model with no u too for Calibre --- compiler/pgates/ptx.py | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 6fba247e..d6aa4235 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -127,12 +127,12 @@ class ptx(design.design): area_sd = 2.5 * self.poly_width * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width if OPTS.tech_name == "s8": - # s8 technology is in microns + # s8 technology is in microns, also needs mult parameter (self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) - main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], - self.mults, - self.tx_width, - drc("minwidth_poly")) + main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3}".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly")) # Perimeters are in microns # Area is in u since it is microns square area_str = "pd={0:.2f} ps={0:.2f} as={1:.2f}u ad={1:.2f}u".format(perimeter_sd, @@ -149,11 +149,17 @@ class ptx(design.design): # LVS lib is always in SI units if os.path.exists(OPTS.openram_tech + "lvs_lib"): - self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], - self.mults, - self.tx_width, - drc("minwidth_poly")) - + if OPTS.tech_name == "s8": + # s8 requires mult parameter too + self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult={1}".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly")) + else: + self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly")) def setup_layout_constants(self): """ From 098219d56c9bf8127ba45dc69739f7ebc494595c Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 11 Jun 2020 11:53:59 -0700 Subject: [PATCH 387/521] Add npc enclosure to poly contacts --- compiler/base/contact.py | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 14dbf76e..cc1ca27a 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -7,7 +7,7 @@ # import hierarchy_design import debug -from tech import drc +from tech import drc, layer import tech from vector import vector from sram_factory import factory @@ -44,7 +44,8 @@ class contact(hierarchy_design.hierarchy_design): self.add_comment("well_type: {}\n".format(well_type)) self.is_well_contact = implant_type == well_type - + + # If we have a special tap layer, use it self.layer_stack = layer_stack self.dimensions = dimensions @@ -196,17 +197,19 @@ class contact(hierarchy_design.hierarchy_design): if "npc" not in tech.layer: return + npc_enclose_poly = drc("npc_enclose_poly") + npc_enclose_offset = vector(npc_enclose_poly, npc_enclose_poly) # Only add for poly layers if self.first_layer_name == "poly": self.add_rect(layer="npc", - offset=self.first_layer_position, - width=self.first_layer_width, - height=self.first_layer_height) + offset=self.first_layer_position - npc_enclose_offset, + width=self.first_layer_width + 2 * npc_enclose_poly, + height=self.first_layer_height + 2 * npc_enclose_poly) elif self.second_layer_name == "poly": self.add_rect(layer="npc", - offset=self.second_layer_position, - width=self.second_layer_width, - height=self.second_layer_height) + offset=self.second_layer_position - npc_enclose_offset, + width=self.second_layer_width + 2 * npc_enclose_poly, + height=self.second_layer_height + 2 * npc_enclose_poly) def create_first_layer_enclosure(self): # this is if the first and second layers are different @@ -218,7 +221,11 @@ class contact(hierarchy_design.hierarchy_design): self.first_layer_minwidth) self.first_layer_height = max(self.contact_array_height + 2 * self.first_layer_vertical_enclosure, self.first_layer_minwidth) - self.add_rect(layer=self.first_layer_name, + if self.is_well_contact and self.first_layer_name == "active" and "tap" in layer: + first_layer_name = "tap" + else: + first_layer_name = self.first_layer_name + self.add_rect(layer=first_layer_name, offset=self.first_layer_position, width=self.first_layer_width, height=self.first_layer_height) From 089331ced3ca8fc55e680c99af4dff090115fcef Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 11 Jun 2020 11:54:16 -0700 Subject: [PATCH 388/521] Add stdc bounding box too --- compiler/base/hierarchy_layout.py | 45 +++++++++++++++++++------------ 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 362c0f9e..244d7842 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -695,14 +695,19 @@ class layout(): # we should add a boundary just for DRC in some technologies if not self.is_library_cell and not self.bounding_box: # If there is a boundary layer, and we didn't create one, add one. + boundary_layers = [] if "boundary" in techlayer.keys(): - boundary_layer = "boundary" - boundary = [self.find_lowest_coords(), - self.find_highest_coords()] - debug.check(boundary[0] and boundary[1], "No shapes to make a boundary.") + boundary_layers.append("boundary") + if "stdc" in techlayer.keys(): + boundary_layers.append("stdc") + boundary = [self.find_lowest_coords(), + self.find_highest_coords()] + debug.check(boundary[0] and boundary[1], "No shapes to make a boundary.") - height = boundary[1][1] - boundary[0][1] - width = boundary[1][0] - boundary[0][0] + height = boundary[1][1] - boundary[0][1] + width = boundary[1][0] - boundary[0][0] + + for boundary_layer in boundary_layers: (layer_number, layer_purpose) = techlayer[boundary_layer] gds_layout.addBox(layerNumber=layer_number, purposeNumber=layer_purpose, @@ -1259,17 +1264,23 @@ class layout(): if OPTS.netlist_only: return - boundary_layer = "boundary" - if not ur: - self.bounding_box = self.add_rect(layer=boundary_layer, - offset=ll, - height=self.height, - width=self.width) - else: - self.bounding_box = self.add_rect(layer=boundary_layer, - offset=ll, - height=ur.y - ll.y, - width=ur.x - ll.x) + boundary_layers = [] + if "stdc" in techlayer.keys(): + boundary_layers.append("stdc") + if "boundary" in techlayer.keys(): + boundary_layers.append("boundary") + # Save the last one as self.bounding_box + for boundary_layer in boundary_layers: + if not ur: + self.bounding_box = self.add_rect(layer=boundary_layer, + offset=ll, + height=self.height, + width=self.width) + else: + self.bounding_box = self.add_rect(layer=boundary_layer, + offset=ll, + height=ur.y - ll.y, + width=ur.x - ll.x) def add_enclosure(self, insts, layer="nwell"): """ Add a layer that surrounds the given instances. Useful From 1a2e0046b103007cf7d40a4b757424866033cddf Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 11 Jun 2020 11:54:34 -0700 Subject: [PATCH 389/521] Add contact to gate spacing for precharge --- compiler/pgates/precharge.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 07b4f21b..f366e5b4 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -195,7 +195,10 @@ class precharge(design.design): # adds the en contact to connect the gates to the en rail pin_offset = self.lower_pmos_inst.get_pin("G").lr() # This is an extra space down for some techs with contact to active spacing - offset = pin_offset - vector(0, self.poly_space) + contact_space = max(self.poly_space, + self.contact_to_gate) + 0.5 * contact.poly_contact.first_layer_height + print(self.contact_to_gate) + offset = pin_offset - vector(0, contact_space) self.add_via_stack_center(from_layer="poly", to_layer=self.en_layer, offset=offset) From 7ad2d54a69e008aa7d65acce25618fdd5131cc15 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 11 Jun 2020 11:54:51 -0700 Subject: [PATCH 390/521] Add pin and label purposes --- compiler/base/pin_layout.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index f18956a8..f758a903 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -367,8 +367,17 @@ class pin_layout: + str(self.width()) + "x" + str(self.height()) + " @ " + str(self.ll())) (layer_num, purpose) = layer[self.layer] + try: + from tech import pin_purpose + except ImportError: + pin_purpose = purpose + try: + from tech import label_purpose + except ImportError: + label_purpose = purpose + newLayout.addBox(layerNumber=layer_num, - purposeNumber=purpose, + purposeNumber=pin_purpose, offsetInMicrons=self.ll(), width=self.width(), height=self.height(), @@ -378,7 +387,7 @@ class pin_layout: # imported into Magic. newLayout.addText(text=self.name, layerNumber=layer_num, - purposeNumber=purpose, + purposeNumber=label_purpose, offsetInMicrons=self.center(), magnification=GDS["zoom"], rotate=None) From 8d52794c32f5bbccd24082e09b4a6eddbb5b729e Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 11 Jun 2020 11:57:52 -0700 Subject: [PATCH 391/521] Remove printf in precharge --- compiler/pgates/precharge.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index f366e5b4..0a948ff8 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -197,7 +197,6 @@ class precharge(design.design): # This is an extra space down for some techs with contact to active spacing contact_space = max(self.poly_space, self.contact_to_gate) + 0.5 * contact.poly_contact.first_layer_height - print(self.contact_to_gate) offset = pin_offset - vector(0, contact_space) self.add_via_stack_center(from_layer="poly", to_layer=self.en_layer, From e9780ea599567c7c94aa595d51eb5818511044ca Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 11 Jun 2020 15:03:36 -0700 Subject: [PATCH 392/521] Add non-preferred directions for channel routes --- compiler/base/hierarchy_layout.py | 17 ++++++++++++++--- compiler/modules/bank.py | 11 +++++++++-- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 244d7842..4b6c044d 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1043,7 +1043,8 @@ class layout(): mid = vector(pin.center().x, trunk_offset.y) self.add_path(self.vertical_layer, [pin.center(), mid]) self.add_via_center(layers=layer_stack, - offset=mid) + offset=mid, + directions=self.directions) def add_vertical_trunk_route(self, pins, @@ -1083,7 +1084,8 @@ class layout(): mid = vector(trunk_offset.x, pin.center().y) self.add_path(self.horizontal_layer, [pin.center(), mid]) self.add_via_center(layers=layer_stack, - offset=mid) + offset=mid, + directions=self.directions) def create_channel_route(self, netlist, offset, @@ -1146,7 +1148,8 @@ class layout(): overlaps = (not vertical and x_overlap) or (vertical and y_overlap) return overlaps - if not directions: + self.directions = directions + if not directions or directions == "pref": # Use the preferred layer directions if self.get_preferred_direction(layer_stack[0]) == "V": self.vertical_layer = layer_stack[0] @@ -1154,6 +1157,14 @@ class layout(): else: self.vertical_layer = layer_stack[2] self.horizontal_layer = layer_stack[0] + elif directions == "nonpref": + # Use the preferred layer directions + if self.get_preferred_direction(layer_stack[0]) == "V": + self.vertical_layer = layer_stack[2] + self.horizontal_layer = layer_stack[0] + else: + self.vertical_layer = layer_stack[0] + self.horizontal_layer = layer_stack[2] else: # Use the layer directions specified to the router rather than # the preferred directions diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index af14c0ca..12fcb6dd 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -9,7 +9,7 @@ import debug import design from sram_factory import factory from math import log, ceil -from tech import drc +from tech import drc, layer from vector import vector from globals import OPTS @@ -879,9 +879,16 @@ class bank(design.design): column_mux_pins = [self.port_data_inst[port].get_pin(x) for x in sel_names] route_map = list(zip(decode_pins, column_mux_pins)) + if "li" in layer: + stack = self.li_stack + directions = "nonpref" + else: + stack = self.m1_stack + directions = "pref" self.create_vertical_channel_route(route_map, offset, - self.m1_stack) + stack, + directions=directions) def add_lvs_correspondence_points(self): """ From 54e4d147f614abdae8d16d27682c46426a0b2365 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 11 Jun 2020 15:03:50 -0700 Subject: [PATCH 393/521] Rail to ptx spacing based on routing layer not m1 --- compiler/pgates/pgate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 67ba4a18..da359174 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -44,7 +44,7 @@ class pgate(design.design): self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer)) # This is the space from a S/D contact to the supply rail - contact_to_vdd_rail_space = 0.5 * self.m1_width + self.m1_space + contact_to_vdd_rail_space = 0.5 * self.route_layer_width + self.route_layer_space # This is a poly-to-poly of a flipped cell poly_to_poly_gate_space = self.poly_extend_active + 0.5 * self.poly_space From 443b8fbe23b7738bc1866a1aa102dd37e030c941 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 12 Jun 2020 14:23:26 -0700 Subject: [PATCH 394/521] Change s8 to sky130 --- compiler/base/hierarchy_layout.py | 2 +- compiler/characterizer/stimuli.py | 2 +- compiler/custom/and2_dec.py | 4 ++-- compiler/custom/and3_dec.py | 4 ++-- compiler/custom/and4_dec.py | 4 ++-- compiler/globals.py | 3 +++ compiler/modules/bitcell_base_array.py | 2 +- compiler/modules/hierarchical_decoder.py | 4 ++-- compiler/modules/hierarchical_predecode.py | 8 ++++---- compiler/modules/port_data.py | 4 ++-- compiler/modules/wordline_driver_array.py | 2 +- compiler/pgates/pgate.py | 2 +- compiler/pgates/pinv.py | 6 +++--- compiler/pgates/pinv_dec.py | 6 +++--- compiler/pgates/pnand2.py | 2 +- compiler/pgates/pnand3.py | 2 +- compiler/pgates/pnor2.py | 2 +- compiler/pgates/precharge.py | 2 +- compiler/pgates/ptx.py | 8 ++++---- compiler/pgates/wordline_driver.py | 4 ++-- compiler/verify/magic.py | 2 +- 21 files changed, 39 insertions(+), 36 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 4b6c044d..3f77c41d 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1348,7 +1348,7 @@ class layout(): offset=loc, directions=directions) # Hack for min area - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": width = round_to_grid(sqrt(drc["minarea_m3"])) height = round_to_grid(drc["minarea_m3"]/width) else: diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index b5a143cf..e5f225dc 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -254,7 +254,7 @@ class stimuli(): includes = self.device_models + [circuit] self.sf.write("* {} process corner\n".format(self.process)) - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": libraries = self.device_libraries for item in list(libraries): if os.path.isfile(item[0]): diff --git a/compiler/custom/and2_dec.py b/compiler/custom/and2_dec.py index b764bb83..e6f314c4 100644 --- a/compiler/custom/and2_dec.py +++ b/compiler/custom/and2_dec.py @@ -87,7 +87,7 @@ class and2_dec(design.design): def route_supply_rails(self): """ Add vdd/gnd rails to the top, (middle), and bottom. """ - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": for name in ["vdd", "gnd"]: for inst in [self.nand_inst, self.inv_inst]: self.copy_layout_pin(inst, name) @@ -105,7 +105,7 @@ class and2_dec(design.design): # nand Z to inv A z1_pin = self.nand_inst.get_pin("Z") a2_pin = self.inv_inst.get_pin("A") - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": mid1_point = vector(a2_pin.cx(), z1_pin.cy()) else: mid1_point = vector(z1_pin.cx(), a2_pin.cy()) diff --git a/compiler/custom/and3_dec.py b/compiler/custom/and3_dec.py index 89cc84f8..207d545b 100644 --- a/compiler/custom/and3_dec.py +++ b/compiler/custom/and3_dec.py @@ -86,7 +86,7 @@ class and3_dec(design.design): def route_supply_rails(self): """ Add vdd/gnd rails to the top, (middle), and bottom. """ - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": for name in ["vdd", "gnd"]: for inst in [self.nand_inst, self.inv_inst]: self.copy_layout_pin(inst, name) @@ -104,7 +104,7 @@ class and3_dec(design.design): # nand Z to inv A z1_pin = self.nand_inst.get_pin("Z") a2_pin = self.inv_inst.get_pin("A") - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": mid1_point = vector(a2_pin.cx(), z1_pin.cy()) else: mid1_point = vector(z1_pin.cx(), a2_pin.cy()) diff --git a/compiler/custom/and4_dec.py b/compiler/custom/and4_dec.py index f99c048f..9c68f78b 100644 --- a/compiler/custom/and4_dec.py +++ b/compiler/custom/and4_dec.py @@ -89,7 +89,7 @@ class and4_dec(design.design): def route_supply_rails(self): """ Add vdd/gnd rails to the top, (middle), and bottom. """ - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": for name in ["vdd", "gnd"]: for inst in [self.nand_inst, self.inv_inst]: self.copy_layout_pin(inst, name) @@ -107,7 +107,7 @@ class and4_dec(design.design): # nand Z to inv A z1_pin = self.nand_inst.get_pin("Z") a2_pin = self.inv_inst.get_pin("A") - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": mid1_point = vector(a2_pin.cx(), z1_pin.cy()) else: mid1_point = vector(z1_pin.cx(), a2_pin.cy()) diff --git a/compiler/globals.py b/compiler/globals.py index eea73c6a..a192ebc9 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -99,6 +99,9 @@ def parse_args(): # Alias SCMOS to 180nm if OPTS.tech_name == "scmos": OPTS.tech_name = "scn4m_subm" + # Alias s8 to sky130 + if OPTS.tech_name == "s8": + OPTS.tech_name = "sky130" return (options, args) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 9b46a192..e601208b 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -102,7 +102,7 @@ class bitcell_base_array(design.design): height=wl_pin.height()) # For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space - # Default uses prefered directions for each layer; this cell property is only currently used by s8 tech (03/20) + # Default uses prefered directions for each layer; this cell property is only currently used by sky130 tech (03/20) try: bitcell_power_pin_directions = cell_properties.bitcell_power_pin_directions except AttributeError: diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index bb2b37ab..c4a4cd68 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -159,7 +159,7 @@ class hierarchical_decoder(design.design): # Inputs to cells are on input layer # Outputs from cells are on output layer - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": self.bus_layer = "m1" self.bus_directions = "nonpref" self.bus_pitch = self.m1_pitch @@ -525,7 +525,7 @@ class hierarchical_decoder(design.design): must-connects next level up. """ - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": for n in ["vdd", "gnd"]: pins = self.and_inst[0].get_pins(n) for pin in pins: diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 03d866fb..44075656 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -78,7 +78,7 @@ class hierarchical_predecode(design.design): # Inputs to cells are on input layer # Outputs from cells are on output layer - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": self.bus_layer = "m1" self.bus_directions = None self.bus_pitch = self.m1_pitch @@ -239,7 +239,7 @@ class hierarchical_predecode(design.design): # add output so that it is just below the vdd or gnd rail # since this is where the p/n devices are and there are no # pins in the and gates. - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y) self.add_path(self.output_layer, [inv_out_pos, rail_pos]) else: @@ -309,8 +309,8 @@ class hierarchical_predecode(design.design): def route_vdd_gnd(self): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ - # In s8, we use hand-made decoder cells with vertical power - if OPTS.tech_name == "s8": + # In sky130, we use hand-made decoder cells with vertical power + if OPTS.tech_name == "sky130": for n in ["vdd", "gnd"]: # This makes a wire from top to bottom for both inv and and gates for i in [self.inv_inst, self.and_inst]: diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 3f0505d5..e370b891 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -588,7 +588,7 @@ class port_data(design.design): # This could be a channel route, but in some techs the bitlines # are too close together. - elif OPTS.tech_name == "s8": + elif OPTS.tech_name == "sky130": self.connect_bitlines(inst1=inst1, inst1_bls_template=inst1_bls_templ, inst2=inst2, @@ -646,7 +646,7 @@ class port_data(design.design): # This could be a channel route, but in some techs the bitlines # are too close together. - elif OPTS.tech_name == "s8": + elif OPTS.tech_name == "sky130": self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size, inst1_bls_template=inst1_bls_templ, diff --git a/compiler/modules/wordline_driver_array.py b/compiler/modules/wordline_driver_array.py index e3d7c4f9..e8a3c110 100644 --- a/compiler/modules/wordline_driver_array.py +++ b/compiler/modules/wordline_driver_array.py @@ -68,7 +68,7 @@ class wordline_driver_array(design.design): Add a pin for each row of vdd/gnd which are must-connects next level up. """ - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": for name in ["vdd", "gnd"]: supply_pins = self.wld_inst[0].get_pins(name) for pin in supply_pins: diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index da359174..09074960 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -14,7 +14,7 @@ from tech import layer, drc from vector import vector from globals import OPTS -if(OPTS.tech_name == "s8"): +if(OPTS.tech_name == "sky130"): from tech import nmos_bins, pmos_bins, accuracy_requirement diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 5e1aab7b..de0ba8e4 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -19,7 +19,7 @@ import logical_effort from sram_factory import factory from errors import drc_error -if(OPTS.tech_name == "s8"): +if(OPTS.tech_name == "sky130"): from tech import nmos_bins, pmos_bins, accuracy_requirement @@ -88,7 +88,7 @@ class pinv(pgate.pgate): self.tx_mults = 1 self.nmos_width = self.nmos_size * drc("minwidth_tx") self.pmos_width = self.pmos_size * drc("minwidth_tx") - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) return @@ -133,7 +133,7 @@ class pinv(pgate.pgate): # Determine the number of mults for each to fit width # into available space - if OPTS.tech_name != "s8": + if OPTS.tech_name != "sky130": self.nmos_width = self.nmos_size * drc("minwidth_tx") self.pmos_width = self.pmos_size * drc("minwidth_tx") nmos_required_mults = max(int(ceil(self.nmos_width / nmos_height_available)), 1) diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py index efc21074..f12a620b 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/pgates/pinv_dec.py @@ -13,7 +13,7 @@ from vector import vector from globals import OPTS from sram_factory import factory -if(OPTS.tech_name == "s8"): +if(OPTS.tech_name == "sky130"): from tech import nmos_bins, pmos_bins, accuracy_requirement @@ -36,7 +36,7 @@ class pinv_dec(pinv.pinv): # Inputs to cells are on input layer # Outputs from cells are on output layer - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": self.supply_layer = "m1" else: self.supply_layer = "m2" @@ -53,7 +53,7 @@ class pinv_dec(pinv.pinv): self.tx_mults = 1 self.nmos_width = self.nmos_size * drc("minwidth_tx") self.pmos_width = self.pmos_size * drc("minwidth_tx") - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) return diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 5816adcf..3a9e2db7 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -37,7 +37,7 @@ class pnand2(pgate.pgate): debug.check(size == 1, "Size 1 pnand2 is only supported now.") self.tx_mults = 1 - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 31024d82..3a9d4221 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -40,7 +40,7 @@ class pnand3(pgate.pgate): "Size 1 pnand3 is only supported now.") self.tx_mults = 1 - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 2126e86c..3cceb7f4 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -37,7 +37,7 @@ class pnor2(pgate.pgate): debug.check(size==1, "Size 1 pnor2 is only supported now.") self.tx_mults = 1 - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 0a948ff8..fdce1a35 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -86,7 +86,7 @@ class precharge(design.design): """ Initializes the upper and lower pmos """ - if(OPTS.tech_name == "s8"): + if(OPTS.tech_name == "sky130"): (self.ptx_width, self.ptx_mults) = pgate.bin_width("pmos", self.ptx_width) self.pmos = factory.create(module_type="ptx", width=self.ptx_width, diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index d6aa4235..fb215d78 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -126,8 +126,8 @@ class ptx(design.design): # be decided in the layout later. area_sd = 2.5 * self.poly_width * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width - if OPTS.tech_name == "s8": - # s8 technology is in microns, also needs mult parameter + if OPTS.tech_name == "sky130": + # sky130 technology is in microns, also needs mult parameter (self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3}".format(spice[self.tx_type], self.mults, @@ -149,8 +149,8 @@ class ptx(design.design): # LVS lib is always in SI units if os.path.exists(OPTS.openram_tech + "lvs_lib"): - if OPTS.tech_name == "s8": - # s8 requires mult parameter too + if OPTS.tech_name == "sky130": + # sky130 requires mult parameter too self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult={1}".format(spice[self.tx_type], self.mults, self.tx_width, diff --git a/compiler/pgates/wordline_driver.py b/compiler/pgates/wordline_driver.py index a817941b..c8cf1326 100644 --- a/compiler/pgates/wordline_driver.py +++ b/compiler/pgates/wordline_driver.py @@ -89,7 +89,7 @@ class wordline_driver(design.design): def route_supply_rails(self): """ Add vdd/gnd rails to the top, (middle), and bottom. """ - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": for name in ["vdd", "gnd"]: for inst in [self.nand_inst, self.driver_inst]: self.copy_layout_pin(inst, name) @@ -110,7 +110,7 @@ class wordline_driver(design.design): # nand Z to inv A z1_pin = self.nand_inst.get_pin("Z") a2_pin = self.driver_inst.get_pin("A") - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": mid1_point = vector(a2_pin.cx(), z1_pin.cy()) else: mid1_point = vector(z1_pin.cx(), a2_pin.cy()) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 1d3562cc..59346ace 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -68,7 +68,7 @@ def write_magic_script(cell_name, extract=False, final_verification=False): if final_verification: f.write(pre + "extract unique all\n".format(cell_name)) # Hack to work around unit scales in SkyWater - if OPTS.tech_name=="s8": + if OPTS.tech_name=="sky130": f.write(pre + "extract style ngspice(si)\n") f.write(pre + "extract\n".format(cell_name)) # f.write(pre + "ext2spice hierarchy on\n") From 33a32101c9831465ed0e98cd7251acc77ead348a Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 12 Jun 2020 15:23:51 -0700 Subject: [PATCH 395/521] DRC and LVS fixes for pinv_dec --- compiler/base/hierarchy_design.py | 3 +- compiler/modules/dff_buf.py | 8 +++--- compiler/pgates/pinv_dec.py | 40 +++++++++++++++++++++------ compiler/pgates/ptx.py | 31 +++++++++++---------- compiler/tests/04_pinv_dec_1x_test.py | 5 ++++ 5 files changed, 60 insertions(+), 27 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index bb57ae3e..87331315 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -27,7 +27,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # If we have a separate lvs directory, then all the lvs files # should be in there (all or nothing!) lvs_dir = OPTS.openram_tech + "lvs_lib/" - if os.path.exists(lvs_dir): + # Calibre will do the scaling in s8 + if os.path.exists(lvs_dir): # and OPTS.lvs_exe[0]!="calibre": self.lvs_file = lvs_dir + name + ".sp" else: self.lvs_file = self.sp_file diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 81629771..a1e54a4d 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -133,7 +133,7 @@ class dff_buf(design.design): q_pin = self.dff_inst.get_pin("Q") a1_pin = self.inv1_inst.get_pin("A") mid1 = vector(a1_pin.cx(), q_pin.cy()) - self.add_path(q_pin.layer, [q_pin.center(), mid1, a1_pin.center()]) + self.add_path(q_pin.layer, [q_pin.center(), mid1, a1_pin.center()], width=q_pin.height()) self.add_via_stack_center(from_layer=a1_pin.layer, to_layer=q_pin.layer, offset=a1_pin.center()) @@ -177,8 +177,8 @@ class dff_buf(design.design): height=din_pin.height()) dout_pin = self.inv2_inst.get_pin("Z") - mid_pos = dout_pin.center() + vector(self.m1_nonpref_pitch, 0) - q_pos = mid_pos - vector(0, self.m2_pitch) + mid_pos = dout_pin.center() + vector(self.m2_nonpref_pitch, 0) + q_pos = mid_pos - vector(0, 2 * self.m2_nonpref_pitch) self.add_layout_pin_rect_center(text="Q", layer="m2", offset=q_pos) @@ -187,7 +187,7 @@ class dff_buf(design.design): to_layer="m2", offset=q_pos) - qb_pos = self.mid_qb_pos + vector(0, self.m2_pitch) + qb_pos = self.mid_qb_pos + vector(0, 2 * self.m2_nonpref_pitch) self.add_layout_pin_rect_center(text="Qb", layer="m2", offset=qb_pos) diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py index f12a620b..10c8d2fb 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/pgates/pinv_dec.py @@ -109,15 +109,15 @@ class pinv_dec(pinv.pinv): self.add_rect(layer="pwell", offset=ll, width=ur.x - ll.x, - height=self.height - ll.y) + height=self.height - ll.y + 0.5 * self.pwell_contact.height + self.well_enclose_active) if "nwell" in layer: ll = self.pmos_inst.ll() - self.pmos_inst.mod.active_offset ur = self.pmos_inst.ur() + self.pmos_inst.mod.active_offset self.add_rect(layer="nwell", - offset=ll - vector(self.nwell_enclose_active, 0), - width=ur.x - ll.x + self.nwell_enclose_active, - height=self.height - ll.y + 2 * self.nwell_enclose_active) + offset=ll, + width=ur.x - ll.x, + height=self.height - ll.y + 0.5 * self.nwell_contact.height + self.well_enclose_active) def place_ptx(self): """ @@ -125,15 +125,14 @@ class pinv_dec(pinv.pinv): # offset so that the input contact is over from the left edge by poly spacing x_offset = self.nmos.active_offset.y + contact.poly_contact.width + self.poly_space - # center the transistor in the y-dimension + # bottom of the transistor in the y-dimension y_offset = self.nmos.width + self.active_space self.nmos_pos = vector(x_offset, y_offset) - self.nmos_inst.place(self.nmos_pos) self.nmos_inst.place(self.nmos_pos, rotate=270) # place PMOS so it is half a poly spacing down from the top - xoffset = self.nmos_inst.height + 2 * self.poly_extend_active + 2 * self.well_extend_active + drc("pwell_to_nwell") - self.pmos_pos = self.nmos_pos + vector(xoffset, 0) + xoffset = self.nmos_inst.rx() + 2 * self.poly_extend_active + 2 * self.well_extend_active + drc("pwell_to_nwell") + self.pmos_pos = vector(xoffset, y_offset) self.pmos_inst.place(self.pmos_pos, rotate=270) @@ -142,6 +141,31 @@ class pinv_dec(pinv.pinv): nmos_drain_pos = self.nmos_inst.get_pin("D").center() self.output_pos = vector(0.5 * (pmos_drain_pos.x + nmos_drain_pos.x), nmos_drain_pos.y) + if OPTS.tech_name == "s8": + self.add_implants() + + def add_implants(self): + """ + Add top-to-bottom implants for adjacency issues in s8. + """ + # Route to the bottom + ll = (self.nmos_inst.ll() - vector(2 * [self.implant_enclose_active])).scale(1, 0) + # Don't route to the top + ur = self.nmos_inst.ur() + vector(self.implant_enclose_active, 0) + self.add_rect("nimplant", + ll, + ur.x - ll.x, + ur.y - ll.y) + + # Route to the bottom + ll = (self.pmos_inst.ll() - vector(2 * [self.implant_enclose_active])).scale(1, 0) + # Don't route to the top + ur = self.pmos_inst.ur() + vector(self.implant_enclose_active, 0) + self.add_rect("pimplant", + ll, + ur.x - ll.x, + ur.y - ll.y) + def route_outputs(self): """ Route the output (drains) together. diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index fb215d78..c4c53a70 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -16,6 +16,7 @@ import os from globals import OPTS from pgate import pgate + class ptx(design.design): """ This module generates gds and spice of a parametrically NMOS or @@ -24,6 +25,10 @@ class ptx(design.design): given width. Total width is therefore mults*width. Options allow you to connect the fingered gates and active for parallel devices. The add_*_contact option tells which layer to bring source/drain up to. + + ll, ur, width and height refer to the active area. + Wells and poly may extend beyond this. + """ def __init__(self, name="", @@ -221,15 +226,13 @@ class ptx(design.design): well_width_rule) self.well_height = max(self.active_height + 2 * self.well_enclose_active, well_width_rule) - # We are going to shift the 0,0, so include that in the width and height - self.height = self.well_height - self.active_offset.y - self.width = self.well_width - self.active_offset.x else: - # The well is not included in the height and width - self.height = self.poly_height - self.width = self.active_width self.well_height = self.height self.well_width = self.width + + # We are going to shift the 0,0, so include that in the width and height + self.height = self.active_height + self.width = self.active_width # This is the center of the first active contact offset (centered vertically) self.contact_offset = self.active_offset + vector(0.5 * self.active_contact.width, @@ -353,18 +356,18 @@ class ptx(design.design): """ Adding the diffusion (active region = diffusion region) """ - self.add_rect(layer="active", - offset=self.active_offset, - width=self.active_width, - height=self.active_height) + self.active = self.add_rect(layer="active", + offset=self.active_offset, + width=self.active_width, + height=self.active_height) # If the implant must enclose the active, shift offset # and increase width/height enclose_width = self.implant_enclose_active enclose_offset = [enclose_width] * 2 - self.add_rect(layer="{}implant".format(self.implant_type), - offset=self.active_offset - enclose_offset, - width=self.active_width + 2 * enclose_width, - height=self.active_height + 2 * enclose_width) + self.implant = self.add_rect(layer="{}implant".format(self.implant_type), + offset=self.active_offset - enclose_offset, + width=self.active_width + 2 * enclose_width, + height=self.active_height + 2 * enclose_width) def add_well_implant(self): """ diff --git a/compiler/tests/04_pinv_dec_1x_test.py b/compiler/tests/04_pinv_dec_1x_test.py index 8876ab58..92772616 100755 --- a/compiler/tests/04_pinv_dec_1x_test.py +++ b/compiler/tests/04_pinv_dec_1x_test.py @@ -21,6 +21,11 @@ class pinv_dec_1x_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + debug.info(2, "Checking 1x size decoder inverter") tx = factory.create(module_type="pinv_dec", size=1) self.local_check(tx) From 8f1dc7eeea4b664bfc44bb1a3d4960e29b7a694b Mon Sep 17 00:00:00 2001 From: mrg Date: Sat, 13 Jun 2020 06:50:53 -0700 Subject: [PATCH 396/521] Include mirror/rotate on translate_all boundary update --- compiler/base/hierarchy_layout.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 3f77c41d..4716c15c 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -55,14 +55,17 @@ class layout(): # GDS layout ############################################################ def offset_all_coordinates(self): - """ This function is called after everything is placed to - shift the origin in the lowest left corner """ + """ + This function is called after everything is placed to + shift the origin in the lowest left corner + """ offset = self.find_lowest_coords() self.translate_all(offset) return offset def get_gate_offset(self, x_offset, height, inv_num): - """Gets the base offset and y orientation of stacked rows of gates + """ + Gets the base offset and y orientation of stacked rows of gates assuming a minwidth metal1 vdd/gnd rail. Input is which gate in the stack from 0..n """ @@ -120,6 +123,7 @@ class layout(): highesty2 = max(inst.uy() for inst in self.insts) else: highestx2 = highesty2 = None + if highestx1 == None and highestx2 == None: return None elif highestx1 == None: @@ -188,7 +192,7 @@ class layout(): inst.offset = vector(inst.offset - offset) # The instances have a precomputed boundary that we need to update. if inst.__class__.__name__ == "instance": - inst.compute_boundary(inst.offset) + inst.compute_boundary(inst.offset, inst.mirror, inst.rotate) for pin_name in self.pin_map.keys(): # All the pins are absolute coordinates that need to be updated. pin_list = self.pin_map[pin_name] From 91f20f2cf6055d6934df2e017b15a94891ae04e2 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 14 Jun 2020 14:09:45 -0700 Subject: [PATCH 397/521] Better centering of pinv_dec --- compiler/pgates/pinv_dec.py | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py index 10c8d2fb..10265f24 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/pgates/pinv_dec.py @@ -8,7 +8,7 @@ import contact import pinv import debug -from tech import drc, parameter +from tech import drc, parameter, layer from vector import vector from globals import OPTS from sram_factory import factory @@ -102,31 +102,30 @@ class pinv_dec(pinv.pinv): def extend_wells(self): """ Extend bottom to top for each well. """ - from tech import layer if "pwell" in layer: - ll = self.nmos_inst.ll() - self.nmos_inst.mod.active_offset - ur = self.nmos_inst.ur() + self.nmos_inst.mod.active_offset + ll = (self.nmos_inst.ll() - vector(2 * [self.well_enclose_active])).scale(1, 0) + ur = self.nmos_inst.ur() + vector(2 * [self.well_enclose_active]) self.add_rect(layer="pwell", offset=ll, width=ur.x - ll.x, height=self.height - ll.y + 0.5 * self.pwell_contact.height + self.well_enclose_active) if "nwell" in layer: - ll = self.pmos_inst.ll() - self.pmos_inst.mod.active_offset - ur = self.pmos_inst.ur() + self.pmos_inst.mod.active_offset + ll = (self.pmos_inst.ll() - vector(2 * [self.well_enclose_active])).scale(1, 0) + ur = self.pmos_inst.ur() + vector(2 * [self.well_enclose_active]) self.add_rect(layer="nwell", offset=ll, width=ur.x - ll.x, height=self.height - ll.y + 0.5 * self.nwell_contact.height + self.well_enclose_active) - + def place_ptx(self): """ """ + # center the transistors in the y-dimension (it is rotated, so use the width) + y_offset = 0.5 * (self.height - self.nmos.width) + self.nmos.width # offset so that the input contact is over from the left edge by poly spacing x_offset = self.nmos.active_offset.y + contact.poly_contact.width + self.poly_space - # bottom of the transistor in the y-dimension - y_offset = self.nmos.width + self.active_space self.nmos_pos = vector(x_offset, y_offset) self.nmos_inst.place(self.nmos_pos, rotate=270) @@ -206,7 +205,7 @@ class pinv_dec(pinv.pinv): self.add_via_stack_center(offset=contact_pos, from_layer=self.active_stack[2], to_layer=self.supply_layer) - + def route_supply_rails(self): pin = self.nmos_inst.get_pin("S") source_pos = pin.center() From 443c401561f7337f7361a576ba1578c0cfe2579d Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 14 Jun 2020 14:17:04 -0700 Subject: [PATCH 398/521] pnand2 B input spaced from top --- compiler/pgates/pnand2.py | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 3a9e2db7..c3e9a515 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -12,6 +12,7 @@ from globals import OPTS from vector import vector import logical_effort from sram_factory import factory +import contact class pnand2(pgate.pgate): @@ -177,11 +178,26 @@ class pnand2(pgate.pgate): # Top of NMOS drain - bottom_pin = self.nmos2_inst.get_pin("D") - self.inputA_yoffset = max(bottom_pin.uy() + self.m1_pitch, - self.nmos2_inst.uy() + self.poly_to_active) - - self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch + bottom_pin = self.nmos1_inst.get_pin("D") + # active contact metal to poly contact metal spacing + active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height + # active diffusion to poly contact spacing + # doesn't use nmos uy because that is calculated using offset + poly height + active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height + active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height + active_to_poly_contact2 = active_top + drc("contact_to_gate") + 0.5 * self.route_layer_width + self.inputA_yoffset = max(active_contact_to_poly_contact, + active_to_poly_contact, + active_to_poly_contact2) + + self.route_input_gate(self.pmos1_inst, + self.nmos1_inst, + self.inputA_yoffset, + "A", + position="center") + + # self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch + self.inputB_yoffset = self.output_yoffset - self.route_layer_pitch # This will help with the wells and the input/output placement self.route_input_gate(self.pmos2_inst, @@ -189,19 +205,13 @@ class pnand2(pgate.pgate): self.inputB_yoffset, "B", position="center") - - self.route_input_gate(self.pmos1_inst, - self.nmos1_inst, - self.inputA_yoffset, - "A", - position="center") def route_output(self): """ Route the Z output """ # One routing track layer below the PMOS contacts route_layer_offset = 0.5 * self.route_layer_width + self.route_layer_space - output_yoffset = self.pmos1_inst.get_pin("D").by() - route_layer_offset + self.output_yoffset = self.pmos1_inst.get_pin("D").by() - route_layer_offset # PMOS1 drain @@ -213,7 +223,7 @@ class pnand2(pgate.pgate): # Output pin out_offset = vector(nmos_pin.cx() + self.route_layer_pitch, - output_yoffset) + self.output_yoffset) # This routes on M2 # # Midpoints of the L routes go horizontal first then vertical From 8e8a97cc4b05b1cbe0884549d1d17d3d7ecef9f2 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 14 Jun 2020 14:17:35 -0700 Subject: [PATCH 399/521] Add correct boundary to SRAM --- compiler/sram/sram_base.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 8002b2f1..89ecfaaf 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -124,6 +124,8 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] + self.add_boundary(ll=vector(0, 0), + ur=vector(self.width, self.height)) start_time = datetime.datetime.now() # We only enable final verification if we have routed the design @@ -142,7 +144,7 @@ class sram_base(design, verilog, lef): for inst in self.insts: self.copy_power_pins(inst, "vdd") self.copy_power_pins(inst, "gnd") - + if not OPTS.route_supplies: # Do not route the power supply (leave as must-connect pins) return From 7dc33285a77bc5b2735049aeac13a472e1b20060 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 14 Jun 2020 14:18:08 -0700 Subject: [PATCH 400/521] Add contact to gate design rule to max for spacing inputs --- compiler/pgates/pnand3.py | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 3a9d4221..e227d7af 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -14,6 +14,7 @@ from sram_factory import factory from globals import OPTS import contact + class pnand3(pgate.pgate): """ This module generates gds of a parametrically sized 2-input nand. @@ -219,11 +220,13 @@ class pnand3(pgate.pgate): active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height # active diffusion to poly contact spacing # doesn't use nmos uy because that is calculated using offset + poly height - active_to_poly_contact = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height \ - + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height - + active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height + active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height + active_to_poly_contact2 = active_top + drc("contact_to_gate") + 0.5 * self.route_layer_width self.inputA_yoffset = max(active_contact_to_poly_contact, - active_to_poly_contact) + active_to_poly_contact, + active_to_poly_contact2) + self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, From 9930b5f3f60b213c24d7d0f8437ba2dabd2c08e4 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 14 Jun 2020 14:18:25 -0700 Subject: [PATCH 401/521] Do not run tapless unit tests --- compiler/tests/04_pnand2_test.py | 8 ++++---- compiler/tests/04_pnand3_test.py | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index 77a6932c..ae0668ae 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -25,10 +25,10 @@ class pnand2_test(openram_test): tx = factory.create(module_type="pnand2", size=1) self.local_check(tx) - debug.info(2, "Checking 2-input nand gate") - tx = factory.create(module_type="pnand2", size=1, add_wells=False) - # Only DRC because well contacts will fail LVS - self.local_drc_check(tx) + # debug.info(2, "Checking 2-input nand gate") + # tx = factory.create(module_type="pnand2", size=1, add_wells=False) + # # Only DRC because well contacts will fail LVS + # self.local_drc_check(tx) globals.end_openram() diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index 82bf1846..c03e32d6 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -25,10 +25,10 @@ class pnand3_test(openram_test): tx = factory.create(module_type="pnand3", size=1) self.local_check(tx) - debug.info(2, "Checking 3-input nand gate") - tx = factory.create(module_type="pnand3", size=1, add_wells=False) - # Only DRC because well contacts will fail LVS - self.local_drc_check(tx) + # debug.info(2, "Checking 3-input nand gate") + # tx = factory.create(module_type="pnand3", size=1, add_wells=False) + # # Only DRC because well contacts will fail LVS + # self.local_drc_check(tx) globals.end_openram() From 78be9f367a3efa6c7df338766500d5d82a78bbd3 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 14 Jun 2020 15:52:09 -0700 Subject: [PATCH 402/521] Add brain-dead router pins to perimeter --- compiler/base/hierarchy_layout.py | 42 +++++++++++- compiler/modules/control_logic.py | 2 +- compiler/sram/sram_1bank.py | 110 ++++++++++++++++++++++-------- 3 files changed, 123 insertions(+), 31 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 4716c15c..c9b6a7a8 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1354,7 +1354,7 @@ class layout(): # Hack for min area if OPTS.tech_name == "sky130": width = round_to_grid(sqrt(drc["minarea_m3"])) - height = round_to_grid(drc["minarea_m3"]/width) + height = round_to_grid(drc["minarea_m3"] / width) else: width = via.width height = via.height @@ -1364,6 +1364,46 @@ class layout(): width=width, height=height) + def add_perimeter_pin(self, name, pin, side, bbox): + """ + Add a pin along the perimeter side specified by the bbox with + the given name and layer from the pin starting location. + """ + (ll, ur) = bbox + left = ll.x + bottom = ll.y + right = ur.x + top = ur.y + + pin_loc = pin.center() + if side == "left": + peri_pin_loc = vector(left, pin_loc.y) + layer = "m3" + elif side == "right": + layer = "m3" + peri_pin_loc = vector(right, pin_loc.x) + elif side == "top": + layer = "m4" + peri_pin_loc = vector(pin_loc.x, top) + elif side == "bottom": + layer = "m4" + peri_pin_loc = vector(pin_loc.x, bottom) + + self.add_via_stack_center(from_layer=pin.layer, + to_layer=layer, + offset=pin_loc) + + self.add_path(layer, + [pin_loc, peri_pin_loc]) + + self.add_via_stack_center(from_layer=layer, + to_layer="m4", + offset=peri_pin_loc) + + self.add_layout_pin_rect_center(text=name, + layer="m4", + offset=peri_pin_loc) + def add_power_ring(self, bbox): """ Create vdd and gnd power rings around an area of the bounding box diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 64fc4fc8..b85a0d4a 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -1005,7 +1005,7 @@ class control_logic(design.design): def route_output_to_bus_jogged(self, inst, name): # Connect this at the bottom of the buffer out_pos = inst.get_pin("Z").center() - mid1 = vector(out_pos.x, out_pos.y - 0.25 * inst.mod.height) + mid1 = vector(out_pos.x, out_pos.y - 0.4 * inst.mod.height) mid2 = vector(self.input_bus[name].cx(), mid1.y) bus_pos = self.input_bus[name].center() self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index eb0fe3ad..d1398307 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -246,46 +246,100 @@ class sram_1bank(sram_base): """ Add the top-level pins for a single bank SRAM with control. """ - for port in self.all_ports: - # Connect the control pins as inputs - for signal in self.control_logic_inputs[port] + ["clk"]: - self.copy_layout_pin(self.control_logic_insts[port], - signal, - signal + "{}".format(port)) + highest_coord = self.find_highest_coords() + lowest_coord = self.find_lowest_coords() + bbox = [lowest_coord, highest_coord] + + + for port in self.all_ports: + # Depending on the port, use the bottom/top or left/right sides + # Port 0 is left/bottom + # Port 1 is right/top + bottom_or_top = "bottom" if port==0 else "top" + left_or_right = "left" if port==0 else "right" + + # Connect the control pins as inputs + for signal in self.control_logic_inputs[port]: + if signal == "clk": + continue + self.add_perimeter_pin(name=signal + "{}".format(port), + pin=self.control_logic_insts[port].get_pin(signal), + side=left_or_right, + bbox=bbox) + # self.copy_layout_pin(self.control_logic_insts[port], + # signal, + # signal + "{}".format(port)) + + self.add_perimeter_pin(name="clk{}".format(port), + pin=self.control_logic_insts[port].get_pin("clk"), + side=bottom_or_top, + bbox=bbox) + + # Data output pins go to BOTTOM/TOP if port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): - self.copy_layout_pin(self.bank_inst, - "dout{0}_{1}".format(port, bit), - "dout{0}[{1}]".format(port, bit)) + self.add_perimeter_pin(name="dout{0}[{1}]".format(port, bit), + pin=self.bank_inst.get_pin("dout{0}_{1}".format(port, bit)), + side=bottom_or_top, + bbox=bbox) + # self.copy_layout_pin(self.bank_inst, + # "dout{0}_{1}".format(port, bit), + # "dout{0}[{1}]".format(port, bit)) - # Lower address bits + # Lower address bits go to BOTTOM/TOP for bit in range(self.col_addr_size): - self.copy_layout_pin(self.col_addr_dff_insts[port], - "din_{}".format(bit), - "addr{0}[{1}]".format(port, bit)) - # Upper address bits + self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit), + pin=self.col_addr_dff_insts[port].get_pin("din_{}".format(bit)), + side=bottom_or_top, + bbox=bbox) + # self.copy_layout_pin(self.col_addr_dff_insts[port], + # "din_{}".format(bit), + # "addr{0}[{1}]".format(port, bit)) + + # Upper address bits go to LEFT/RIGHT for bit in range(self.row_addr_size): - self.copy_layout_pin(self.row_addr_dff_insts[port], - "din_{}".format(bit), - "addr{0}[{1}]".format(port, bit + self.col_addr_size)) + self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit + self.col_addr_size), + pin=self.row_addr_dff_insts[port].get_pin("din_{}".format(bit)), + side=left_or_right, + bbox=bbox) + # self.copy_layout_pin(self.row_addr_dff_insts[port], + # "din_{}".format(bit), + # "addr{0}[{1}]".format(port, bit + self.col_addr_size)) + # Data input pins go to BOTTOM/TOP if port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): - self.copy_layout_pin(self.data_dff_insts[port], - "din_{}".format(bit), - "din{0}[{1}]".format(port, bit)) + self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit), + pin=self.data_dff_insts[port].get_pin("din_{}".format(bit)), + side=bottom_or_top, + bbox=bbox) + # self.copy_layout_pin(self.data_dff_insts[port], + # "din_{}".format(bit), + # "din{0}[{1}]".format(port, bit)) + # Write mask pins go to BOTTOM/TOP + if port in self.write_ports: if self.write_size: for bit in range(self.num_wmasks): - self.copy_layout_pin(self.wmask_dff_insts[port], - "din_{}".format(bit), - "wmask{0}[{1}]".format(port, bit)) - + self.add_perimeter_pin(name="wmask{0}[{1}]".format(port, bit), + pin=self.wmask_dff_insts[port].get_pin("din_{}".format(bit)), + side=bottom_or_top, + bbox=bbox) + # self.copy_layout_pin(self.wmask_dff_insts[port], + # "din_{}".format(bit), + # "wmask{0}[{1}]".format(port, bit)) + + # Spare wen pins go to BOTTOM/TOP + if port in self.write_ports: for bit in range(self.num_spare_cols): - self.copy_layout_pin(self.spare_wen_dff_insts[port], - "din_{}".format(bit), - "spare_wen{0}[{1}]".format(port, bit)) + self.add_perimeter_pin(name="spare_wen{0}[{1}]".format(port, bit), + pin=self.spare_wen_dff_insts[port].get_pin("din_{}".format(bit)), + side=left_or_right, + bbox=bbox) + # self.copy_layout_pin(self.spare_wen_dff_insts[port], + # "din_{}".format(bit), + # "spare_wen{0}[{1}]".format(port, bit)) def route_layout(self): """ Route a single bank SRAM """ @@ -314,8 +368,6 @@ class sram_1bank(sram_base): # This is the actual input to the SRAM for port in self.all_ports: - self.copy_layout_pin(self.control_logic_insts[port], "clk", "clk{}".format(port)) - # Connect all of these clock pins to the clock in the central bus # This is something like a "spine" clock distribution. The two spines # are clk_buf and clk_buf_bar From 52ee7b0a19e7895eb0b4898193ef1f1586b41240 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 14 Jun 2020 16:44:10 -0700 Subject: [PATCH 403/521] Disable perimeter pins and make an option --- compiler/options.py | 4 ++ compiler/sram/sram_1bank.py | 130 ++++++++++++++++++++---------------- 2 files changed, 78 insertions(+), 56 deletions(-) diff --git a/compiler/options.py b/compiler/options.py index ac61e8f3..6ecfa6ae 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -123,6 +123,10 @@ class options(optparse.Values): analytical_delay = True # Purge the temp directory after a successful # run (doesn't purge on errors, anyhow) + + # Route the input/output pins to the perimeter + perimeter_pins = False + purge_temp = True # These are the default modules that can be over-riden diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index d1398307..bb8c0a7d 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -9,7 +9,7 @@ import debug from vector import vector from sram_base import sram_base from contact import m2_via - +from globals import OPTS class sram_1bank(sram_base): """ @@ -246,7 +246,6 @@ class sram_1bank(sram_base): """ Add the top-level pins for a single bank SRAM with control. """ - highest_coord = self.find_highest_coords() lowest_coord = self.find_lowest_coords() bbox = [lowest_coord, highest_coord] @@ -263,83 +262,102 @@ class sram_1bank(sram_base): for signal in self.control_logic_inputs[port]: if signal == "clk": continue - self.add_perimeter_pin(name=signal + "{}".format(port), - pin=self.control_logic_insts[port].get_pin(signal), - side=left_or_right, - bbox=bbox) - # self.copy_layout_pin(self.control_logic_insts[port], - # signal, - # signal + "{}".format(port)) + if OPTS.perimeter_pins: + self.add_perimeter_pin(name=signal + "{}".format(port), + pin=self.control_logic_insts[port].get_pin(signal), + side=left_or_right, + bbox=bbox) + else: + self.copy_layout_pin(self.control_logic_insts[port], + signal, + signal + "{}".format(port)) - self.add_perimeter_pin(name="clk{}".format(port), - pin=self.control_logic_insts[port].get_pin("clk"), - side=bottom_or_top, - bbox=bbox) + if OPTS.perimeter_pins: + self.add_perimeter_pin(name="clk{}".format(port), + pin=self.control_logic_insts[port].get_pin("clk"), + side=bottom_or_top, + bbox=bbox) + else: + self.copy_layout_pin(self.control_logic_insts[port], + "clk", + "clk{}".format(port)) # Data output pins go to BOTTOM/TOP if port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): - self.add_perimeter_pin(name="dout{0}[{1}]".format(port, bit), - pin=self.bank_inst.get_pin("dout{0}_{1}".format(port, bit)), - side=bottom_or_top, - bbox=bbox) - # self.copy_layout_pin(self.bank_inst, - # "dout{0}_{1}".format(port, bit), - # "dout{0}[{1}]".format(port, bit)) + if OPTS.perimeter_pins: + self.add_perimeter_pin(name="dout{0}[{1}]".format(port, bit), + pin=self.bank_inst.get_pin("dout{0}_{1}".format(port, bit)), + side=bottom_or_top, + bbox=bbox) + else: + self.copy_layout_pin(self.bank_inst, + "dout{0}_{1}".format(port, bit), + "dout{0}[{1}]".format(port, bit)) # Lower address bits go to BOTTOM/TOP for bit in range(self.col_addr_size): - self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit), - pin=self.col_addr_dff_insts[port].get_pin("din_{}".format(bit)), - side=bottom_or_top, - bbox=bbox) - # self.copy_layout_pin(self.col_addr_dff_insts[port], - # "din_{}".format(bit), - # "addr{0}[{1}]".format(port, bit)) + if OPTS.perimeter_pins: + self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit), + pin=self.col_addr_dff_insts[port].get_pin("din_{}".format(bit)), + side=bottom_or_top, + bbox=bbox) + else: + self.copy_layout_pin(self.col_addr_dff_insts[port], + "din_{}".format(bit), + "addr{0}[{1}]".format(port, bit)) # Upper address bits go to LEFT/RIGHT for bit in range(self.row_addr_size): - self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit + self.col_addr_size), - pin=self.row_addr_dff_insts[port].get_pin("din_{}".format(bit)), - side=left_or_right, - bbox=bbox) - # self.copy_layout_pin(self.row_addr_dff_insts[port], - # "din_{}".format(bit), - # "addr{0}[{1}]".format(port, bit + self.col_addr_size)) - + if OPTS.perimeter_pins: + self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit + self.col_addr_size), + pin=self.row_addr_dff_insts[port].get_pin("din_{}".format(bit)), + side=left_or_right, + bbox=bbox) + else: + self.copy_layout_pin(self.row_addr_dff_insts[port], + "din_{}".format(bit), + "addr{0}[{1}]".format(port, bit + self.col_addr_size)) + # Data input pins go to BOTTOM/TOP if port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): - self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit), - pin=self.data_dff_insts[port].get_pin("din_{}".format(bit)), - side=bottom_or_top, - bbox=bbox) - # self.copy_layout_pin(self.data_dff_insts[port], - # "din_{}".format(bit), - # "din{0}[{1}]".format(port, bit)) + if OPTS.perimeter_pins: + self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit), + pin=self.data_dff_insts[port].get_pin("din_{}".format(bit)), + side=bottom_or_top, + bbox=bbox) + else: + self.copy_layout_pin(self.data_dff_insts[port], + "din_{}".format(bit), + "din{0}[{1}]".format(port, bit)) # Write mask pins go to BOTTOM/TOP if port in self.write_ports: if self.write_size: for bit in range(self.num_wmasks): - self.add_perimeter_pin(name="wmask{0}[{1}]".format(port, bit), - pin=self.wmask_dff_insts[port].get_pin("din_{}".format(bit)), - side=bottom_or_top, - bbox=bbox) - # self.copy_layout_pin(self.wmask_dff_insts[port], - # "din_{}".format(bit), - # "wmask{0}[{1}]".format(port, bit)) + if OPTS.perimeter_pins: + self.add_perimeter_pin(name="wmask{0}[{1}]".format(port, bit), + pin=self.wmask_dff_insts[port].get_pin("din_{}".format(bit)), + side=bottom_or_top, + bbox=bbox) + else: + self.copy_layout_pin(self.wmask_dff_insts[port], + "din_{}".format(bit), + "wmask{0}[{1}]".format(port, bit)) # Spare wen pins go to BOTTOM/TOP if port in self.write_ports: for bit in range(self.num_spare_cols): - self.add_perimeter_pin(name="spare_wen{0}[{1}]".format(port, bit), - pin=self.spare_wen_dff_insts[port].get_pin("din_{}".format(bit)), - side=left_or_right, - bbox=bbox) - # self.copy_layout_pin(self.spare_wen_dff_insts[port], - # "din_{}".format(bit), - # "spare_wen{0}[{1}]".format(port, bit)) + if OPTS.perimeter_pins: + self.add_perimeter_pin(name="spare_wen{0}[{1}]".format(port, bit), + pin=self.spare_wen_dff_insts[port].get_pin("din_{}".format(bit)), + side=left_or_right, + bbox=bbox) + else: + self.copy_layout_pin(self.spare_wen_dff_insts[port], + "din_{}".format(bit), + "spare_wen{0}[{1}]".format(port, bit)) def route_layout(self): """ Route a single bank SRAM """ From 02352c35d766ba69035aa5fff85571aed0513a5d Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 14 Jun 2020 17:10:32 -0700 Subject: [PATCH 404/521] Fix hard coded layer in wmask --- compiler/modules/write_mask_and_array.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 9c077ed7..581f9484 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -126,7 +126,7 @@ class write_mask_and_array(design.design): for supply in ["gnd", "vdd"]: supply_pin_left = self.and2_insts[0].get_pin(supply) supply_pin_right = self.and2_insts[self.num_wmasks - 1].get_pin(supply) - self.add_path("m1", [supply_pin_left.lc(), supply_pin_right.rc()]) + self.add_path(supply_pin_left.layer, [supply_pin_left.lc(), supply_pin_right.rc()]) def get_cin(self): """Get the relative capacitance of all the input connections in the bank""" From 6c04166876eb2ced5c3ebb96ba893f98cd0933e7 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 06:05:05 -0700 Subject: [PATCH 405/521] Update port data wmask tests --- .../tests/18_port_data_wmask_1rw_1r_test.py | 114 ++++++++++++++++++ compiler/tests/18_port_data_wmask_test.py | 2 +- 2 files changed, 115 insertions(+), 1 deletion(-) create mode 100755 compiler/tests/18_port_data_wmask_1rw_1r_test.py diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py new file mode 100755 index 00000000..52d1c4fb --- /dev/null +++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py @@ -0,0 +1,114 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import unittest +from testutils import * +import sys, os + +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class port_data_wmask_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + c = sram_config(word_size=16, + write_size=4, + num_words=16) + + c.words_per_row = 1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + c.num_words = 32 + c.words_per_row = 2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + c.num_words = 64 + c.words_per_row = 4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + c.num_words = 128 + c.words_per_row = 8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + OPTS.bitcell = "bitcell_1w_1r" + OPTS.num_rw_ports = 0 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + c.num_words = 16 + c.words_per_row = 1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + # + c.num_words = 32 + c.words_per_row = 2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.num_words = 64 + c.words_per_row = 4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.word_size = 8 + c.num_words = 128 + c.words_per_row = 8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index f670990e..1c650c74 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -15,7 +15,7 @@ from sram_factory import factory import debug -class port_data_test(openram_test): +class port_data_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) From 79b3b9a8b0b231461032333591137dd15f6e8996 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 10:06:04 -0700 Subject: [PATCH 406/521] Switch input/output layers for predecodes --- compiler/modules/hierarchical_predecode.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 44075656..d6cf7388 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -83,9 +83,9 @@ class hierarchical_predecode(design.design): self.bus_directions = None self.bus_pitch = self.m1_pitch self.bus_space = 1.5 * self.m1_space - self.input_layer = "li" - self.output_layer = "m2" - self.output_layer_pitch = self.m2_pitch + self.input_layer = "m2" + self.output_layer = "li" + self.output_layer_pitch = self.li_pitch else: self.bus_layer = "m2" self.bus_directions = None @@ -234,12 +234,12 @@ class hierarchical_predecode(design.design): in_pin = "in_{}".format(inv_num) inv_out_pin = self.inv_inst[inv_num].get_pin("Z") - inv_out_pos = inv_out_pin.rc() + inv_out_pos = inv_out_pin.lr() # add output so that it is just below the vdd or gnd rail # since this is where the p/n devices are and there are no # pins in the and gates. - if OPTS.tech_name == "sky130": + if False and OPTS.tech_name == "sky130": rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y) self.add_path(self.output_layer, [inv_out_pos, rail_pos]) else: From 6e0008403e63e879f7615b5769a49b7f56af8f2d Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 10:06:17 -0700 Subject: [PATCH 407/521] Update new tech name --- compiler/pgates/pinv_dec.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py index 10265f24..3960f1bf 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/pgates/pinv_dec.py @@ -140,7 +140,7 @@ class pinv_dec(pinv.pinv): nmos_drain_pos = self.nmos_inst.get_pin("D").center() self.output_pos = vector(0.5 * (pmos_drain_pos.x + nmos_drain_pos.x), nmos_drain_pos.y) - if OPTS.tech_name == "s8": + if OPTS.tech_name == "sky130": self.add_implants() def add_implants(self): From 355474ce2c1b2cf23f9e81431e2457d94a836cd3 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 10:07:00 -0700 Subject: [PATCH 408/521] Playing around with pnand2 pin spacing rules --- compiler/pgates/pnand2.py | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index c3e9a515..12323885 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -176,11 +176,10 @@ class pnand2(pgate.pgate): def route_inputs(self): """ Route the A and B inputs """ - # Top of NMOS drain bottom_pin = self.nmos1_inst.get_pin("D") # active contact metal to poly contact metal spacing - active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height + active_contact_to_poly_contact = bottom_pin.uy() + self.route_layer_space + 0.5 * contact.poly_contact.second_layer_height # active diffusion to poly contact spacing # doesn't use nmos uy because that is calculated using offset + poly height active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height @@ -196,8 +195,15 @@ class pnand2(pgate.pgate): "A", position="center") - # self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch - self.inputB_yoffset = self.output_yoffset - self.route_layer_pitch + self.inputB_yoffset = self.inputA_yoffset + 2 * self.m3_pitch + # # active contact metal to poly contact metal spacing + # active_contact_to_poly_contact = self.output_yoffset - self.route_layer_space - 0.5 * contact.poly_contact.second_layer_height + # active_bottom = self.pmos1_inst.by() + # active_to_poly_contact = active_bottom - self.poly_to_active - 0.5 * contact.poly_contact.first_layer_height + # active_to_poly_contact2 = active_bottom - drc("contact_to_gate") - 0.5 * self.route_layer_width + # self.inputB_yoffset = min(active_contact_to_poly_contact, + # active_to_poly_contact, + # active_to_poly_contact2) # This will help with the wells and the input/output placement self.route_input_gate(self.pmos2_inst, @@ -210,7 +216,7 @@ class pnand2(pgate.pgate): """ Route the Z output """ # One routing track layer below the PMOS contacts - route_layer_offset = 0.5 * self.route_layer_width + self.route_layer_space + route_layer_offset = 0.5 * contact.poly_contact.second_layer_height + self.route_layer_space self.output_yoffset = self.pmos1_inst.get_pin("D").by() - route_layer_offset From 4cb827c3d7a647ee64c82d31d4314beb737891c6 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 10:08:07 -0700 Subject: [PATCH 409/521] Add redundant implant for s8 --- compiler/pgates/single_level_column_mux.py | 36 ++++++++++++++++------ 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 96935158..b594f2e4 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -11,7 +11,7 @@ from tech import drc, layer from vector import vector from sram_factory import factory import logical_effort -from utils import round_to_grid +from globals import OPTS class single_level_column_mux(pgate.pgate): @@ -113,18 +113,21 @@ class single_level_column_mux(pgate.pgate): # This aligns it directly above the other tx with gates abutting nmos_upper_position = nmos_lower_position \ - + vector(0, self.nmos.active_height + max(self.active_space,self.poly_space)) + + vector(0, self.nmos.active_height + max(self.active_space, self.poly_space)) self.nmos_upper = self.add_inst(name="mux_tx2", mod=self.nmos, offset=nmos_upper_position) self.connect_inst(["br", "sel", "br_out", "gnd"]) + if OPTS.tech_name == "sky130": + self.add_implants() + def connect_poly(self): """ Connect the poly gate of the two pass transistors """ # offset is the top of the lower nmos' diffusion # height is the distance between the nmos' diffusions, which depends on max(self.active_space,self.poly_space) - offset = self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active) + offset = self.nmos_lower.get_pin("G").ul() - vector(0, self.poly_extend_active) height = self.nmos_upper.get_pin("G").by() + self.poly_extend_active - offset.y self.add_rect(layer="poly", offset=offset, @@ -183,13 +186,26 @@ class single_level_column_mux(pgate.pgate): vector(nmos_lower_s_pin.cx(), br_out_pin.uy()), nmos_lower_s_pin.center()]) # halfway up, move over - mid1 = br_pin.bc().scale(1,0.5) \ - + nmos_lower_d_pin.uc().scale(0,0.5) - mid2 = br_pin.bc().scale(0,0.5) \ - + nmos_lower_d_pin.uc().scale(1,0.5) + mid1 = br_pin.bc().scale(1, 0.5) \ + + nmos_lower_d_pin.uc().scale(0, 0.5) + mid2 = br_pin.bc().scale(0, 0.5) \ + + nmos_lower_d_pin.uc().scale(1, 0.5) self.add_path(self.col_mux_stack[2], [br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()]) - + + def add_implants(self): + """ + Add top-to-bottom implants for adjacency issues in s8. + """ + # Route to the bottom + ll = (self.nmos_lower.ll() - vector(2 * [self.implant_enclose_active])).scale(1, 0) + # Don't route to the top + ur = self.nmos_upper.ur() + vector(self.implant_enclose_active, 0) + self.add_rect("nimplant", + ll, + ur.x - ll.x, + ur.y - ll.y) + def add_pn_wells(self): """ Add a well and implant over the whole cell. Also, add the @@ -209,8 +225,8 @@ class single_level_column_mux(pgate.pgate): offset=active_pos) # Add the M1->..->power_grid_layer stack - self.add_power_pin(name = "gnd", - loc = active_pos, + self.add_power_pin(name="gnd", + loc=active_pos, start_layer="m1") # Add well enclosure over all the tx and contact From a862cf3cb21deff9c097f2d7bc51130906ee03e6 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 10:17:54 -0700 Subject: [PATCH 410/521] Test more single level col mux configs --- ...ingle_level_column_mux_array_1rw_1r_test.py | 18 +++++++++++++++++- .../07_single_level_column_mux_array_test.py | 2 +- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py index c758e788..209133aa 100755 --- a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py +++ b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py @@ -7,7 +7,7 @@ # All rights reserved. # from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -25,6 +25,14 @@ class single_level_column_mux_test(openram_test): OPTS.num_w_ports = 0 globals.setup_bitcell() + debug.info(1, "Testing sample for 2-way column_mux_array port 0") + a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 2-way column_mux_array port 1") + a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(a) + debug.info(1, "Testing sample for 4-way column_mux_array port 0") a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) @@ -33,6 +41,14 @@ class single_level_column_mux_test(openram_test): a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) + debug.info(1, "Testing sample for 8-way column_mux_array port 0") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=2, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array port 1") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(a) + globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index b1f74eba..c0476a4f 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -7,7 +7,7 @@ # All rights reserved. # from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS From e331d6fae8d776bc142263bb0ee9d22eddbf28d8 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 10:25:53 -0700 Subject: [PATCH 411/521] Permute bus order to avoid conflict in control_logic --- compiler/modules/control_logic.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index b85a0d4a..d857f24d 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -363,7 +363,7 @@ class control_logic(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "clk_buf", "we_bar", "cs"] + self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] elif self.port_type == "r": self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"] else: From abb5ff7bae279d70ab81ddc43d4dd6d294b0d48d Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 10:30:27 -0700 Subject: [PATCH 412/521] Separate route conditions for s8 --- compiler/modules/hierarchical_decoder.py | 1 - compiler/modules/hierarchical_predecode.py | 15 +++++++-------- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index c4a4cd68..8830d397 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -11,7 +11,6 @@ import math from sram_factory import factory from vector import vector from globals import OPTS -from errors import drc_error class hierarchical_decoder(design.design): diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index d6cf7388..f2274c6e 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -234,19 +234,18 @@ class hierarchical_predecode(design.design): in_pin = "in_{}".format(inv_num) inv_out_pin = self.inv_inst[inv_num].get_pin("Z") - inv_out_pos = inv_out_pin.lr() # add output so that it is just below the vdd or gnd rail # since this is where the p/n devices are and there are no # pins in the and gates. - if False and OPTS.tech_name == "sky130": - rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y) - self.add_path(self.output_layer, [inv_out_pos, rail_pos]) + if OPTS.tech_name == "sky130": + inv_out_pos = inv_out_pin.lr() else: - y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch - right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0) - rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset) - self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) + inv_out_pos = inv_out_pin.rc() + y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch + right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0) + rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset) + self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) self.add_via_stack_center(from_layer=inv_out_pin.layer, to_layer=self.output_layer, From 7dfc462ef67e259a07d66773e2da66172457e9be Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 13:58:26 -0700 Subject: [PATCH 413/521] Add magic filter before calibre for sky130 --- compiler/options.py | 2 ++ compiler/verify/__init__.py | 30 ++++++++++++++++++------------ compiler/verify/calibre.py | 26 +++++++++++++++++--------- compiler/verify/magic.py | 25 +++++++++++++++++++++++++ 4 files changed, 62 insertions(+), 21 deletions(-) diff --git a/compiler/options.py b/compiler/options.py index 6ecfa6ae..976595ad 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -110,6 +110,8 @@ class options(optparse.Values): drc_exe = None lvs_exe = None pex_exe = None + # For sky130, we need magic for filtering. + magic_exe = None # Should we print out the banner at startup print_banner = True diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index 59df42db..a28581d8 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -18,27 +18,27 @@ If not, OpenRAM will continue as if nothing happened! import os import debug from globals import OPTS -from globals import find_exe from globals import get_tool from tech import drc_name from tech import lvs_name from tech import pex_name -import sys -debug.info(1,"Initializing verify...") +debug.info(1, "Initializing verify...") if not OPTS.check_lvsdrc: - debug.info(1,"LVS/DRC/PEX disabled.") + debug.info(1, "LVS/DRC/PEX disabled.") OPTS.drc_exe = None OPTS.lvs_exe = None OPTS.pex_exe = None else: - debug.info(1, "Finding DRC/LVS/PEX tools.") - OPTS.drc_exe = get_tool("DRC", ["calibre","assura","magic"], drc_name) - OPTS.lvs_exe = get_tool("LVS", ["calibre","assura","netgen"], lvs_name) - OPTS.pex_exe = get_tool("PEX", ["calibre","magic"], pex_name) + debug.info(1, "Finding DRC/LVS/PEX tools.") + OPTS.drc_exe = get_tool("DRC", ["calibre", "assura", "magic"], drc_name) + OPTS.lvs_exe = get_tool("LVS", ["calibre", "assura", "netgen"], lvs_name) + OPTS.pex_exe = get_tool("PEX", ["calibre", "magic"], pex_name) + if OPTS.tech_name == "sky130": + OPTS.magic_exe = get_tool("GDS", ["magic"], None) -if OPTS.drc_exe == None: +if not OPTS.drc_exe: from .none import run_drc, print_drc_stats elif "calibre"==OPTS.drc_exe[0]: from .calibre import run_drc, print_drc_stats @@ -49,7 +49,7 @@ elif "magic"==OPTS.drc_exe[0]: else: debug.warning("Did not find a supported DRC tool.") -if OPTS.lvs_exe == None: +if not OPTS.lvs_exe: from .none import run_lvs, print_lvs_stats elif "calibre"==OPTS.lvs_exe[0]: from .calibre import run_lvs, print_lvs_stats @@ -61,7 +61,7 @@ else: debug.warning("Did not find a supported LVS tool.") -if OPTS.pex_exe == None: +if not OPTS.pex_exe: from .none import run_pex,print_pex_stats elif "calibre"==OPTS.pex_exe[0]: from .calibre import run_pex,print_pex_stats @@ -69,4 +69,10 @@ elif "magic"==OPTS.pex_exe[0]: from .magic import run_pex,print_pex_stats else: debug.warning("Did not find a supported PEX tool.") - + +if OPTS.tech_name == "sky130": + if "magic"==OPTS.magic_exe[0]: + from .magic import filter_gds + else: + debug.warning("Did not find Magic.") + diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 8abca448..1b9d296e 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -20,16 +20,16 @@ Calibre means pointing the code to the proper DRC and LVS rule files. import os import shutil import re -import time import debug from globals import OPTS -from run_script import * +from run_script import run_script # Keep track of statistics num_drc_runs = 0 num_lvs_runs = 0 num_pex_runs = 0 + def write_calibre_drc_script(cell_name, extract, final_verification): """ Write a Calibre runset file and script to run DRC """ # the runset file contains all the options to run calibre @@ -67,6 +67,7 @@ def write_calibre_drc_script(cell_name, extract, final_verification): os.system("chmod u+x {}".format(run_file)) return drc_runset + def write_calibre_lvs_script(cell_name, final_verification): """ Write a Calibre runset file and script to run LVS """ @@ -80,7 +81,7 @@ def write_calibre_lvs_script(cell_name, final_verification): 'lvsSourcePath': cell_name + ".sp", 'lvsSourcePrimary': cell_name, 'lvsSourceSystem': 'SPICE', - 'lvsSpiceFile': "extracted.sp", + 'lvsSpiceFile': "{}.spice".format(cell_name), 'lvsPowerNames': 'vdd', 'lvsGroundNames': 'gnd', 'lvsIncludeSVRFCmds': 1, @@ -130,8 +131,9 @@ def write_calibre_lvs_script(cell_name, final_verification): return lvs_runset -def write_calibre_pex_script(cell_name, extract, output, final_verification): +def write_calibre_pex_script(cell_name, extract, output, final_verification): + """ Write a pex script that can either just extract the netlist or the netlist+parasitics """ if output == None: output = name + ".pex.netlist" @@ -150,10 +152,9 @@ def write_calibre_pex_script(cell_name, extract, output, final_verification): 'pexRunDir': OPTS.openram_temp, 'pexLayoutPaths': cell_name + ".gds", 'pexLayoutPrimary': cell_name, - #'pexSourcePath' : OPTS.openram_temp+"extracted.sp", 'pexSourcePath': cell_name + ".sp", 'pexSourcePrimary': cell_name, - 'pexReportFile': cell_name + ".lvs.report", + 'pexReportFile': cell_name + ".pex.report", 'pexPexNetlistFile': cell_name + ".pex.netlist", 'pexPexReportFile': cell_name + ".pex.report", 'pexMaskDBFile': cell_name + ".maskdb", @@ -179,6 +180,7 @@ def write_calibre_pex_script(cell_name, extract, output, final_verification): return pex_runset + def run_drc(cell_name, gds_name, extract=False, final_verification=False): """Run DRC check on a given top-level name which is implemented in gds_name.""" @@ -186,9 +188,15 @@ def run_drc(cell_name, gds_name, extract=False, final_verification=False): global num_drc_runs num_drc_runs += 1 - # Copy file to local dir if it isn't already - if os.path.dirname(gds_name)!=OPTS.openram_temp.rstrip('/'): - shutil.copy(gds_name, OPTS.openram_temp) + # Filter the layouts through magic as a GDS filter for nsdm/psdm/nwell merging + if OPTS.tech_name == "sky130": + shutil.copy(gds_name, OPTS.openram_temp + "temp.gds") + from magic import filter_gds + filter_gds(cell_name, OPTS.openram_temp + "temp.gds", gds_name) + else: + # Copy file to local dir if it isn't already + if os.path.dirname(gds_name)!=OPTS.openram_temp.rstrip('/'): + shutil.copy(gds_name, OPTS.openram_temp) drc_runset = write_calibre_drc_script(cell_name, extract, final_verification) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 59346ace..d19537a5 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -33,6 +33,31 @@ num_lvs_runs = 0 num_pex_runs = 0 +def filter_gds(cell_name, input_gds, output_gds): + """ Run the gds through magic for any layer processing """ + global OPTS + + run_file = OPTS.openram_temp + "run_filter.sh" + f = open(run_file, "w") + f.write("#!/bin/sh\n") + f.write("{} -dnull -noconsole << EOF\n".format(OPTS.magic_exe[1])) + f.write("gds polygon subcell true\n") + f.write("gds warning default\n") + f.write("gds read {}\n".format(input_gds)) + f.write("load {}\n".format(cell_name)) + f.write("cellname delete \\(UNNAMED\\)\n") + #f.write("writeall force\n") + f.write("select top cell\n") + f.write("gds write {}\n".format(output_gds)) + f.write("quit -noprompt\n") + f.write("EOF\n") + + f.close() + os.system("chmod u+x {}".format(run_file)) + + (outfile, errfile, resultsfile) = run_script(cell_name, "filter") + + def write_magic_script(cell_name, extract=False, final_verification=False): """ Write a magic script to perform DRC and optionally extraction. """ From 69f56212451979103987bca315b172f719a11383 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 18 Jun 2020 14:54:36 -0700 Subject: [PATCH 414/521] Save raw file from ngspice --- compiler/characterizer/stimuli.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index e5f225dc..70152a54 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -303,9 +303,9 @@ class stimuli(): valid_retcode=0 else: # ngspice 27+ supports threading with "set num_threads=4" in the stimulus file or a .spiceinit - cmd = "{0} -b -o {2}timing.lis {1}".format(OPTS.spice_exe, - temp_stim, - OPTS.openram_temp) + cmd = "{0} -b -r {2}timing.raw -o {2}timing.lis {1}".format(OPTS.spice_exe, + temp_stim, + OPTS.openram_temp) # for some reason, ngspice-25 returns 1 when it only has acceptable warnings valid_retcode=1 From 403ea17039a6eac68f4ce751fefc8260e2c7fc3f Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 18 Jun 2020 14:55:01 -0700 Subject: [PATCH 415/521] PEP8 formatting --- compiler/characterizer/functional.py | 136 +++++++++++++-------------- 1 file changed, 64 insertions(+), 72 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 8d07a61a..2c391e38 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -5,23 +5,18 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import sys,re,shutil -import copy import collections -from design import design import debug -import math -import tech import random from .stimuli import * from .charutils import * -import utils from globals import OPTS from .simulation import simulation # from .delay import delay import graph_util from sram_factory import factory + class functional(simulation): """ Functions to write random data values to a random address then read them back and check @@ -60,7 +55,6 @@ class functional(simulation): self.read_check = [] self.read_results = [] - def run(self, feasible_period=None): if feasible_period: #period defaults to tech.py feasible period otherwise. self.period = feasible_period @@ -85,11 +79,11 @@ class functional(simulation): for port in self.all_ports: checks = [] if port in self.read_ports: - checks.append((self.addr_value[port],"addr")) + checks.append((self.addr_value[port], "addr")) if port in self.write_ports: - checks.append((self.data_value[port],"data")) - checks.append((self.wmask_value[port],"wmask")) - checks.append((self.spare_wen_value[port],"spare_wen")) + checks.append((self.data_value[port], "data")) + checks.append((self.wmask_value[port], "wmask")) + checks.append((self.spare_wen_value[port], "spare_wen")) for (val, name) in checks: debug.check(len(self.cycle_times)==len(val), @@ -108,15 +102,15 @@ class functional(simulation): r_ops = ["noop", "read"] # First cycle idle is always an idle cycle - comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, "0"*self.num_wmasks, 0, self.t_current) + comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current) self.add_noop_all_ports(comment) # 1. Write all the write ports first to seed a bunch of locations. for port in self.write_ports: addr = self.gen_addr() word = self.gen_data() - comment = self.gen_cycle_comment("write", word, addr, "1"*self.num_wmasks, port, self.t_current) - self.add_write_one_port(comment, addr, word, "1"*self.num_wmasks, port) + comment = self.gen_cycle_comment("write", word, addr, "1" * self.num_wmasks, port, self.t_current) + self.add_write_one_port(comment, addr, word, "1" * self.num_wmasks, port) self.stored_words[addr] = word # All other read-only ports are noops. @@ -135,7 +129,7 @@ class functional(simulation): if port in self.write_ports: self.add_noop_one_port(port) else: - comment = self.gen_cycle_comment("read", word, addr, "0"*self.num_wmasks, port, self.t_current) + comment = self.gen_cycle_comment("read", word, addr, "0" * self.num_wmasks, port, self.t_current) self.add_read_one_port(comment, addr, port) self.add_read_check(word, port) self.cycle_times.append(self.t_current) @@ -164,13 +158,13 @@ class functional(simulation): self.add_noop_one_port(port) else: word = self.gen_data() - comment = self.gen_cycle_comment("write", word, addr, "1"*self.num_wmasks, port, self.t_current) - self.add_write_one_port(comment, addr, word, "1"*self.num_wmasks, port) + comment = self.gen_cycle_comment("write", word, addr, "1" * self.num_wmasks, port, self.t_current) + self.add_write_one_port(comment, addr, word, "1" * self.num_wmasks, port) self.stored_words[addr] = word w_addrs.append(addr) elif op == "partial_write": # write only to a word that's been written to - (addr,old_word) = self.get_data() + (addr, old_word) = self.get_data() # two ports cannot write to the same address if addr in w_addrs: self.add_noop_one_port(port) @@ -183,7 +177,7 @@ class functional(simulation): self.stored_words[addr] = new_word w_addrs.append(addr) else: - (addr,word) = random.choice(list(self.stored_words.items())) + (addr, word) = random.choice(list(self.stored_words.items())) # The write driver is not sized sufficiently to drive through the two # bitcell access transistors to the read port. So, for now, we do not allow # a simultaneous write and read to the same address on different ports. This @@ -191,7 +185,7 @@ class functional(simulation): if addr in w_addrs: self.add_noop_one_port(port) else: - comment = self.gen_cycle_comment("read", word, addr, "0"*self.num_wmasks, port, self.t_current) + comment = self.gen_cycle_comment("read", word, addr, "0" * self.num_wmasks, port, self.t_current) self.add_read_one_port(comment, addr, port) self.add_read_check(word, port) @@ -199,7 +193,7 @@ class functional(simulation): self.t_current += self.period # Last cycle idle needed to correctly measure the value on the second to last clock edge - comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, "0"*self.num_wmasks, 0, self.t_current) + comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current) self.add_noop_all_ports(comment) def gen_masked_data(self, old_word, word, wmask): @@ -213,7 +207,7 @@ class functional(simulation): if wmask[bit] == "0": lower = bit * self.write_size upper = lower + self.write_size - 1 - new_word = new_word[:lower] + old_word[lower:upper+1] + new_word[upper + 1:] + new_word = new_word[:lower] + old_word[lower:upper + 1] + new_word[upper + 1:] return new_word @@ -223,7 +217,7 @@ class functional(simulation): self.check except: self.check = 0 - self.read_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, self.check]) + self.read_check.append([word, "{0}{1}".format(self.dout_name, port), self.t_current + self.period, self.check]) self.check += 1 def read_stim_results(self): @@ -231,7 +225,7 @@ class functional(simulation): for (word, dout_port, eo_period, check) in self.read_check: sp_read_value = "" for bit in range(self.word_size + self.num_spare_cols): - value = parse_spice_list("timing", "v{0}.{1}ck{2}".format(dout_port.lower(),bit,check)) + value = parse_spice_list("timing", "v{0}.{1}ck{2}".format(dout_port.lower(), bit, check)) if value > self.v_high: sp_read_value = "1" + sp_read_value elif value < self.v_low: @@ -282,25 +276,24 @@ class functional(simulation): # wmask must be reversed since a python list goes right to left and sram bits go left to right. return wmask[::-1] - def gen_data(self): """ Generates a random word to write. """ if not self.num_spare_cols: - random_value = random.randint(0,(2**(self.word_size))-1) + random_value = random.randint(0, (2 ** self.word_size) - 1) else: - random_value1 = random.randint(0,(2**(self.word_size))-1) - random_value2 = random.randint(0,(2**(self.num_spare_cols))-1) + random_value1 = random.randint(0, (2 ** self.word_size) - 1) + random_value2 = random.randint(0, (2 ** self.num_spare_cols) - 1) random_value = random_value1 + random_value2 - data_bits = self.convert_to_bin(random_value,False) + data_bits = self.convert_to_bin(random_value, False) return data_bits def gen_addr(self): """ Generates a random address value to write to. """ if self.num_spare_rows==0: - random_value = random.randint(0,(2**self.addr_size)-1) + random_value = random.randint(0, (2 ** self.addr_size) - 1) else: - random_value = random.randint(0,((2**(self.addr_size-1)-1))+(self.num_spare_rows * self.words_per_row)) - addr_bits = self.convert_to_bin(random_value,True) + random_value = random.randint(0, ((2 ** (self.addr_size - 1) - 1)) + (self.num_spare_rows * self.words_per_row)) + addr_bits = self.convert_to_bin(random_value, True) return addr_bits def get_data(self): @@ -308,36 +301,36 @@ class functional(simulation): # Used for write masks since they should be writing to previously written addresses addr = random.choice(list(self.stored_words.keys())) word = self.stored_words[addr] - return (addr,word) + return (addr, word) - def convert_to_bin(self,value,is_addr): + def convert_to_bin(self, value, is_addr): """ Converts addr & word to usable binary values. """ - new_value = str.replace(bin(value),"0b","") + new_value = str.replace(bin(value), "0b", "") if(is_addr): expected_value = self.addr_size else: expected_value = self.word_size + self.num_spare_cols - for i in range (expected_value - len(new_value)): + for i in range(expected_value - len(new_value)): new_value = "0" + new_value - #print("Binary Conversion: {} to {}".format(value, new_value)) - return new_value + # print("Binary Conversion: {} to {}".format(value, new_value)) + return new_value def write_functional_stimulus(self): """ Writes SPICE stimulus. """ temp_stim = "{0}/stim.sp".format(OPTS.openram_temp) - self.sf = open(temp_stim,"w") + self.sf = open(temp_stim, "w") self.sf.write("* Functional test stimulus file for {}ns period\n\n".format(self.period)) - self.stim = stimuli(self.sf,self.corner) + self.stim = stimuli(self.sf, self.corner) - #Write include statements + # Write include statements self.stim.write_include(self.sp_file) - #Write Vdd/Gnd statements + # Write Vdd/Gnd statements self.sf.write("\n* Global Power Supplies\n") self.stim.write_supply() - #Instantiate the SRAM + # Instantiate the SRAM self.sf.write("\n* Instantiation of the SRAM\n") self.stim.inst_model(pins=self.pins, model_name=self.sram.name) @@ -362,7 +355,7 @@ class functional(simulation): for comment in self.fn_cycle_comments: self.sf.write("*{}\n".format(comment)) - # Generate data input bits + # Generate data input bits self.sf.write("\n* Generation of data and address signals\n") for port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): @@ -378,10 +371,10 @@ class functional(simulation): # Generate control signals self.sf.write("\n * Generation of control signals\n") for port in self.all_ports: - self.stim.gen_pwl("CSB{}".format(port), self.cycle_times , self.csb_values[port], self.period, self.slew, 0.05) + self.stim.gen_pwl("CSB{}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05) for port in self.readwrite_ports: - self.stim.gen_pwl("WEB{}".format(port), self.cycle_times , self.web_values[port], self.period, self.slew, 0.05) + self.stim.gen_pwl("WEB{}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05) # Generate wmask bits for port in self.write_ports: @@ -416,11 +409,11 @@ class functional(simulation): # Generate dout value measurements self.sf.write("\n * Generation of dout measurements\n") for (word, dout_port, eo_period, check) in self.read_check: - t_intital = eo_period - 0.01*self.period - t_final = eo_period + 0.01*self.period + t_intital = eo_period - 0.01 * self.period + t_final = eo_period + 0.01 * self.period for bit in range(self.word_size + self.num_spare_cols): - self.stim.gen_meas_value(meas_name="V{0}_{1}ck{2}".format(dout_port,bit,check), - dout="{0}_{1}".format(dout_port,bit), + self.stim.gen_meas_value(meas_name="V{0}_{1}ck{2}".format(dout_port, bit, check), + dout="{0}_{1}".format(dout_port, bit), t_intital=t_intital, t_final=t_final) @@ -450,7 +443,7 @@ class functional(simulation): # Generate new graph every analysis as edges might change depending on test bit self.graph = graph_util.timing_graph() self.sram_spc_name = "X{}".format(self.sram.name) - self.sram.build_graph(self.graph,self.sram_spc_name,self.pins) + self.sram.build_graph(self.graph, self.sram_spc_name, self.pins) # FIXME: refactor to share with delay.py def set_internal_spice_names(self): @@ -458,17 +451,17 @@ class functional(simulation): # For now, only testing these using first read port. port = self.read_ports[0] - self.graph.get_all_paths('{}{}'.format("clk", port), + self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, 0).lower()) - self.sen_name = self.get_sen_name(self.graph.all_paths) - debug.info(2,"s_en name = {}".format(self.sen_name)) + self.sen_name = self.get_sen_name(self.graph.all_paths) + debug.info(2, "s_en name = {}".format(self.sen_name)) - self.bl_name,self.br_name = self.get_bl_name(self.graph.all_paths, port) - debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) + self.bl_name, self.br_name = self.get_bl_name(self.graph.all_paths, port) + debug.info(2, "bl name={}, br name={}".format(self.bl_name, self.br_name)) - self.q_name,self.qbar_name = self.get_bit_name() - debug.info(2,"q name={}\nqbar name={}".format(self.q_name,self.qbar_name)) + self.q_name, self.qbar_name = self.get_bit_name() + debug.info(2, "q name={}\nqbar name={}".format(self.q_name, self.qbar_name)) def get_bit_name(self): """ Get a bit cell name """ @@ -476,10 +469,10 @@ class functional(simulation): storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - q_name = cell_name+'.'+str(storage_names[0]) - qbar_name = cell_name+'.'+str(storage_names[1]) + q_name = cell_name + '.' + str(storage_names[0]) + qbar_name = cell_name + '.' + str(storage_names[1]) - return (q_name,qbar_name) + return (q_name, qbar_name) # FIXME: refactor to share with delay.py def get_sen_name(self, paths): @@ -489,29 +482,28 @@ class functional(simulation): """ sa_mods = factory.get_mods(OPTS.sense_amp) - # Any sense amp instantiated should be identical, any change to that + # Any sense amp instantiated should be identical, any change to that # will require some identification to determine the mod desired. debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - return sen_name + return sen_name # FIXME: refactor to share with delay.py def get_bl_name(self, paths, port): """Gets the signal name associated with the bitlines in the bank.""" - cell_mod = factory.create(module_type=OPTS.bitcell) + cell_mod = factory.create(module_type=OPTS.bitcell) cell_bl = cell_mod.get_bl_name(port) cell_br = cell_mod.get_br_name(port) - bl_found = False # Only a single path should contain a single s_en name. Anything else is an error. bl_names = [] exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - return bl_names[0], bl_names[1] + return bl_names[0], bl_names[1] def get_bl_name_search_exclusions(self): """Gets the mods as a set which should be excluded while searching for name.""" @@ -520,9 +512,9 @@ class functional(simulation): # so it makes the search awkward return set(factory.get_mods(OPTS.replica_bitline)) - def get_alias_in_path(self, paths, int_net, mod, exclusion_set=None): + def get_alias_in_path(self, paths, int_net, mod, exclusion_set=None): """ - Finds a single alias for the int_net in given paths. + Finds a single alias for the int_net in given paths. More or less hits cause an error """ @@ -530,14 +522,14 @@ class functional(simulation): for path in paths: aliases = self.sram.find_aliases(self.sram_spc_name, self.pins, path, int_net, mod, exclusion_set) if net_found and len(aliases) >= 1: - debug.error('Found multiple paths with {} net.'.format(int_net),1) + debug.error('Found multiple paths with {} net.'.format(int_net), 1) elif len(aliases) > 1: - debug.error('Found multiple {} nets in single path.'.format(int_net),1) + debug.error('Found multiple {} nets in single path.'.format(int_net), 1) elif not net_found and len(aliases) == 1: path_net_name = aliases[0] net_found = True if not net_found: - debug.error("Could not find {} net in timing paths.".format(int_net),1) + debug.error("Could not find {} net in timing paths.".format(int_net), 1) - return path_net_name + return path_net_name From 231f90f4923510f7691d537a12a10ddc11af14e2 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 19 Jun 2020 06:47:46 -0700 Subject: [PATCH 416/521] Fix missing space in ptx spice line --- compiler/pgates/ptx.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index c4c53a70..fb127158 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -134,7 +134,7 @@ class ptx(design.design): if OPTS.tech_name == "sky130": # sky130 technology is in microns, also needs mult parameter (self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) - main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3}".format(spice[self.tx_type], + main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], self.mults, self.tx_width, drc("minwidth_poly")) From 94c480911b9f3027a647b4f076494f8412c9b8ea Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 19 Jun 2020 07:09:15 -0700 Subject: [PATCH 417/521] ngspice raw save doesn't work with measures --- compiler/characterizer/stimuli.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 70152a54..11dc449a 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -302,10 +302,12 @@ class stimuli(): OPTS.openram_temp) valid_retcode=0 else: - # ngspice 27+ supports threading with "set num_threads=4" in the stimulus file or a .spiceinit - cmd = "{0} -b -r {2}timing.raw -o {2}timing.lis {1}".format(OPTS.spice_exe, - temp_stim, - OPTS.openram_temp) + # ngspice 27+ supports threading with "set num_threads=4" in the stimulus file or a .spiceinit + # Measurements can't be made with a raw file set in ngspice + # -r {2}timing.raw + cmd = "{0} -b -o {2}timing.lis {1}".format(OPTS.spice_exe, + temp_stim, + OPTS.openram_temp) # for some reason, ngspice-25 returns 1 when it only has acceptable warnings valid_retcode=1 From 617a84d4b89d8210a289524985b77da337b1a5a3 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 19 Jun 2020 07:15:27 -0700 Subject: [PATCH 418/521] Fix output name of magic gds filter --- compiler/verify/calibre.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 1b9d296e..d4f31960 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -192,7 +192,7 @@ def run_drc(cell_name, gds_name, extract=False, final_verification=False): if OPTS.tech_name == "sky130": shutil.copy(gds_name, OPTS.openram_temp + "temp.gds") from magic import filter_gds - filter_gds(cell_name, OPTS.openram_temp + "temp.gds", gds_name) + filter_gds(cell_name, OPTS.openram_temp + "temp.gds", OPTS.openram_temp + cell_name + ".gds") else: # Copy file to local dir if it isn't already if os.path.dirname(gds_name)!=OPTS.openram_temp.rstrip('/'): From 239b3ea007c55123bcd6a1107b604c0d129cae0c Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 19 Jun 2020 08:49:48 -0700 Subject: [PATCH 419/521] Make wmask test a 1rw/1r --- ...k_1w_1r_func_test.py => 22_sram_1rw_1r_wmask_func_test.py} | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) rename compiler/tests/{22_sram_wmask_1w_1r_func_test.py => 22_sram_1rw_1r_wmask_func_test.py} (97%) diff --git a/compiler/tests/22_sram_wmask_1w_1r_func_test.py b/compiler/tests/22_sram_1rw_1r_wmask_func_test.py similarity index 97% rename from compiler/tests/22_sram_wmask_1w_1r_func_test.py rename to compiler/tests/22_sram_1rw_1r_wmask_func_test.py index b5d83654..07cff70e 100755 --- a/compiler/tests/22_sram_wmask_1w_1r_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_wmask_func_test.py @@ -26,8 +26,8 @@ class sram_wmask_1w_1r_func_test(openram_test): OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False - OPTS.num_rw_ports = 0 - OPTS.num_w_ports = 1 + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 globals.setup_bitcell() From 5872f553e1b02cd385cf788c2b99b269ae5e7b15 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 19 Jun 2020 08:53:35 -0700 Subject: [PATCH 420/521] Rename tests for consistency --- ...nomux_func_test.py => 22_sram_1bank_nomux_1rw_1r_func_test.py} | 0 ...wmask_func_test.py => 22_sram_1bank_wmask_1rw_1r_func_test.py} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename compiler/tests/{22_sram_1rw_1r_1bank_nomux_func_test.py => 22_sram_1bank_nomux_1rw_1r_func_test.py} (100%) rename compiler/tests/{22_sram_1rw_1r_wmask_func_test.py => 22_sram_1bank_wmask_1rw_1r_func_test.py} (100%) diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py similarity index 100% rename from compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py rename to compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py diff --git a/compiler/tests/22_sram_1rw_1r_wmask_func_test.py b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py similarity index 100% rename from compiler/tests/22_sram_1rw_1r_wmask_func_test.py rename to compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py From a2d160dbf5ec8d8bbcc254db071a80b3ee48c075 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 19 Jun 2020 13:40:45 -0700 Subject: [PATCH 421/521] Copy magic config for filter code --- compiler/verify/magic.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index d19537a5..e20c0499 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -37,6 +37,14 @@ def filter_gds(cell_name, input_gds, output_gds): """ Run the gds through magic for any layer processing """ global OPTS + # Copy .magicrc file into temp dir + magic_file = OPTS.openram_tech + "mag_lib/.magicrc" + if os.path.exists(magic_file): + shutil.copy(magic_file, OPTS.openram_temp) + else: + debug.warning("Could not locate .magicrc file: {}".format(magic_file)) + + run_file = OPTS.openram_temp + "run_filter.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") From 208c6526534e4abfd69b0e1ca147f4d90440965b Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Fri, 19 Jun 2020 13:59:33 -0700 Subject: [PATCH 422/521] added error for sky130 with invalid x mirroring (for lvs) --- compiler/modules/replica_column.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 603bebfe..3a58668c 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -36,6 +36,10 @@ class replica_column(design.design): "Replica bit cannot be the dummy row.") debug.check(replica_bit <= left_rbl or replica_bit >= self.total_size - right_rbl - 1, "Replica bit cannot be in the regular array.") + if OPTS.tech_name == "sky130": + debug.check(rows % 2 == 0 and (left_rbl + 1) % 2 == 0, + "sky130 currently requires rows to be even and to start with X mirroring" + + " (left_rbl must be odd) for LVS.") self.create_netlist() if not OPTS.netlist_only: From a13d5359455bff97198966d19ab233a0b6683594 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 22 Jun 2020 11:33:02 -0700 Subject: [PATCH 423/521] PEP8 cleanup --- compiler/base/hierarchy_design.py | 7 +++---- compiler/base/hierarchy_spice.py | 13 ++++++++----- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 87331315..20c40f21 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -27,8 +27,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # If we have a separate lvs directory, then all the lvs files # should be in there (all or nothing!) lvs_dir = OPTS.openram_tech + "lvs_lib/" - # Calibre will do the scaling in s8 - if os.path.exists(lvs_dir): # and OPTS.lvs_exe[0]!="calibre": + if os.path.exists(lvs_dir): self.lvs_file = lvs_dir + name + ".sp" else: self.lvs_file = self.sp_file @@ -45,7 +44,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if i.name == inst.name: break else: - debug.error("Couldn't find instance {0}".format(inst_name), -1) + debug.error("Couldn't find instance {0}".format(inst.name), -1) inst_map = inst.mod.pin_map return inst_map @@ -181,7 +180,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): """Given a list of nets, will compare the internal alias of a mod to determine if the nets have a connection to this mod's net (but not inst). """ - if exclusion_set == None: + if not exclusion_set: exclusion_set = set() try: self.name_dict diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 00d7ad44..0e41c4b0 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -10,9 +10,9 @@ import re import os import math import tech -from delay_data import * -from wire_spice_model import * -from power_data import * +from delay_data import delay_data +from wire_spice_model import wire_spice_model +from power_data import power_data import logical_effort @@ -263,7 +263,10 @@ class spice(): Recursive spice subcircuit write; Writes the spice subcircuit from the library or the dynamically generated one """ + if not self.spice: + # If spice isn't defined, we dynamically generate one. + # recursively write the modules for i in self.mods: if self.contains(i, usedMODS): @@ -316,7 +319,7 @@ class spice(): sp.write(".ENDS {0}\n".format(self.name)) else: - # write the subcircuit itself + # If spice is a hard module, output the spice file contents. # Including the file path makes the unit test fail for other users. # if os.path.isfile(self.sp_file): # sp.write("\n* {0}\n".format(self.sp_file)) @@ -356,7 +359,7 @@ class spice(): stage_effort = self.get_stage_effort(relative_cap) # If it fails, then keep running with a valid object. - if stage_effort == None: + if not stage_effort: return delay_data(0.0, 0.0) abs_delay = stage_effort.get_absolute_delay() From 54120f8405d02713fb73ab698cd22e278c266866 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 22 Jun 2020 12:35:37 -0700 Subject: [PATCH 424/521] Add option for removing subckt/instances of cells for row/col caps --- compiler/base/hierarchy_spice.py | 9 ++++++++- compiler/bitcells/col_cap_bitcell_1rw_1r.py | 1 + compiler/bitcells/row_cap_bitcell_1rw_1r.py | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 0e41c4b0..5ba60435 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -40,6 +40,8 @@ class spice(): # THE CONNECTIONS MUST MATCH THE ORDER OF THE PINS (restriction imposed by the # Spice format) self.conns = [] + # If this is set, it will out output subckt or isntances of this (for row/col caps etc.) + self.no_instances = False # Keep track of any comments to add the the spice try: self.commments @@ -264,7 +266,9 @@ class spice(): Writes the spice subcircuit from the library or the dynamically generated one """ - if not self.spice: + if self.no_instances: + return + elif not self.spice: # If spice isn't defined, we dynamically generate one. # recursively write the modules @@ -303,6 +307,9 @@ class spice(): # these are wires and paths if self.conns[i] == []: continue + # Instance with no devices in it needs no subckt/instance + if self.insts[i].mod.no_instances: + continue if lvs_netlist and hasattr(self.insts[i].mod, "lvs_device"): sp.write(self.insts[i].mod.lvs_device.format(self.insts[i].name, " ".join(self.conns[i]))) diff --git a/compiler/bitcells/col_cap_bitcell_1rw_1r.py b/compiler/bitcells/col_cap_bitcell_1rw_1r.py index 315ad23f..01818a12 100644 --- a/compiler/bitcells/col_cap_bitcell_1rw_1r.py +++ b/compiler/bitcells/col_cap_bitcell_1rw_1r.py @@ -41,3 +41,4 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base): self.height = col_cap_bitcell_1rw_1r.height self.pin_map = col_cap_bitcell_1rw_1r.pin_map self.add_pin_types(self.type_list) + self.no_instances = True diff --git a/compiler/bitcells/row_cap_bitcell_1rw_1r.py b/compiler/bitcells/row_cap_bitcell_1rw_1r.py index b50629f0..f7a3a687 100644 --- a/compiler/bitcells/row_cap_bitcell_1rw_1r.py +++ b/compiler/bitcells/row_cap_bitcell_1rw_1r.py @@ -41,3 +41,4 @@ class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base): self.height = row_cap_bitcell_1rw_1r.height self.pin_map = row_cap_bitcell_1rw_1r.pin_map self.add_pin_types(self.type_list) + self.no_instances = True From 0926eab9f54f141785f4898864985ed36b16f8a1 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 22 Jun 2020 12:55:18 -0700 Subject: [PATCH 425/521] PEP8 formatting --- compiler/modules/col_cap_array.py | 24 +++++++-------------- compiler/modules/row_cap_array.py | 35 +++++++++++-------------------- 2 files changed, 19 insertions(+), 40 deletions(-) diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index d74ab80a..ee9302d8 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -17,6 +17,7 @@ class col_cap_array(bitcell_base_array): super().__init__(cols, rows, name, column_offset) self.mirror = mirror + self.no_instances = True self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -47,8 +48,8 @@ class col_cap_array(bitcell_base_array): for col in range(self.column_size): for row in range(self.row_size): name = "bit_r{0}_c{1}".format(row, col) - self.cell_inst[row,col]=self.add_inst(name=name, - mod=self.dummy_cell) + self.cell_inst[row, col]=self.add_inst(name=name, + mod=self.dummy_cell) self.connect_inst(self.get_bitcell_pins(col, row)) def get_bitcell_pins(self, col, row): @@ -73,31 +74,20 @@ class col_cap_array(bitcell_base_array): for col in range(self.column_size): for cell_column in column_list: - bl_pin = self.cell_inst[0,col].get_pin(cell_column) - self.add_layout_pin(text=cell_column+"_{0}".format(col), + bl_pin = self.cell_inst[0, col].get_pin(cell_column) + self.add_layout_pin(text=cell_column + "_{0}".format(col), layer=bl_pin.layer, - offset=bl_pin.ll().scale(1,0), + offset=bl_pin.ll().scale(1, 0), width=bl_pin.width(), height=self.height) # Add vdd/gnd via stacks for row in range(self.row_size): for col in range(self.column_size): - inst = self.cell_inst[row,col] + inst = self.cell_inst[row, col] for pin_name in ["vdd", "gnd"]: for pin in inst.get_pins(pin_name): self.add_power_pin(name=pin.name, loc=pin.center(), start_layer=pin.layer) - - # def input_load(self): - # wl_wire = self.gen_wl_wire() - # return wl_wire.return_input_cap() - # - # def get_wordline_cin(self): - # """Get the relative input capacitance from the wordline connections in all the bitcell""" - # #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns - # bitcell_wl_cin = self.cell.get_wl_cin() - # total_cin = bitcell_wl_cin * self.column_size - # return total_cin diff --git a/compiler/modules/row_cap_array.py b/compiler/modules/row_cap_array.py index 2c7d4677..f108d86e 100644 --- a/compiler/modules/row_cap_array.py +++ b/compiler/modules/row_cap_array.py @@ -8,6 +8,7 @@ from sram_factory import factory from globals import OPTS from tech import cell_properties + class row_cap_array(bitcell_base_array): """ Generate a dummy row/column for the replica array. @@ -15,7 +16,7 @@ class row_cap_array(bitcell_base_array): def __init__(self, cols, rows, column_offset=0, mirror=0, name=""): super().__init__(cols, rows, name, column_offset) self.mirror = mirror - + self.no_instances = True self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -46,8 +47,8 @@ class row_cap_array(bitcell_base_array): for col in range(self.column_size): for row in range(1, self.row_size - 1): name = "bit_r{0}_c{1}".format(row, col) - self.cell_inst[row,col]=self.add_inst(name=name, - mod=self.dummy_cell) + self.cell_inst[row, col]=self.add_inst(name=name, + mod=self.dummy_cell) self.connect_inst(self.get_bitcell_pins(col, row)) def get_bitcell_pins(self, col, row): @@ -65,8 +66,8 @@ class row_cap_array(bitcell_base_array): def place_array(self, name_template, row_offset=0): # We increase it by a well enclosure so the precharges don't overlap our wells - self.height = self.row_size*self.cell.height - self.width = self.column_size*self.cell.width + self.height = self.row_size * self.cell.height + self.width = self.column_size * self.cell.width xoffset = 0.0 for col in range(self.column_size): @@ -74,7 +75,6 @@ class row_cap_array(bitcell_base_array): tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset) for row in range(1, self.row_size - 1): - name = name_template.format(row, col) tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset) if dir_x and dir_y: @@ -86,8 +86,8 @@ class row_cap_array(bitcell_base_array): else: dir_key = "" - self.cell_inst[row,col].place(offset=[tempx, tempy], - mirror=dir_key) + self.cell_inst[row, col].place(offset=[tempx, tempy], + mirror=dir_key) yoffset += self.cell.height xoffset += self.cell.width @@ -98,31 +98,20 @@ class row_cap_array(bitcell_base_array): for row in range(1, self.row_size - 1): for cell_row in row_list: - wl_pin = self.cell_inst[row,0].get_pin(cell_row) - self.add_layout_pin(text=cell_row+"_{0}".format(row), + wl_pin = self.cell_inst[row, 0].get_pin(cell_row) + self.add_layout_pin(text=cell_row + "_{0}".format(row), layer=wl_pin.layer, - offset=wl_pin.ll().scale(0,1), + offset=wl_pin.ll().scale(0, 1), width=self.width, height=wl_pin.height()) # Add vdd/gnd via stacks for row in range(1, self.row_size - 1): for col in range(self.column_size): - inst = self.cell_inst[row,col] + inst = self.cell_inst[row, col] for pin_name in ["vdd", "gnd"]: for pin in inst.get_pins(pin_name): self.add_power_pin(name=pin.name, loc=pin.center(), start_layer=pin.layer) - - # def input_load(self): - # wl_wire = self.gen_wl_wire() - # return wl_wire.return_input_cap() - # - # def get_wordline_cin(self): - # """Get the relative input capacitance from the wordline connections in all the bitcell""" - # #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns - # bitcell_wl_cin = self.cell.get_wl_cin() - # total_cin = bitcell_wl_cin * self.column_size - # return total_cin From 40edbfa51f62789ee822085d23839114f69adf48 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 22 Jun 2020 15:41:59 -0700 Subject: [PATCH 426/521] Error out on single port in sky130 --- compiler/bitcells/bitcell.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index 4ed2d053..e91d8c2f 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -10,7 +10,7 @@ import utils from tech import GDS, layer from tech import cell_properties as props import bitcell_base - +from globals import OPTS class bitcell(bitcell_base.bitcell_base): """ @@ -50,6 +50,8 @@ class bitcell(bitcell_base.bitcell_base): self.pin_map = bitcell.pin_map self.add_pin_types(self.type_list) self.nets_match = self.do_nets_exist(self.storage_nets) + + debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells") def get_all_wl_names(self): """ Creates a list of all wordline pin names """ From 92fc30005c028db65376e784c57df1fb5d8043eb Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 22 Jun 2020 16:55:49 -0700 Subject: [PATCH 427/521] Use factory in and_dec tests --- compiler/tests/04_and2_dec_test.py | 11 +++++++---- compiler/tests/04_and3_dec_test.py | 11 +++++++---- compiler/tests/04_and4_dec_test.py | 13 ++++++++----- 3 files changed, 22 insertions(+), 13 deletions(-) diff --git a/compiler/tests/04_and2_dec_test.py b/compiler/tests/04_and2_dec_test.py index 355d3b15..97ac5749 100755 --- a/compiler/tests/04_and2_dec_test.py +++ b/compiler/tests/04_and2_dec_test.py @@ -23,10 +23,13 @@ class and2_dec_test(openram_test): global verify import verify - import and2_dec - - debug.info(2, "Testing and2 gate 4x") - a = and2_dec.and2_dec(name="and2x4", size=4) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing and2_dec gate") + a = factory.create(module_type="and2_dec") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_and3_dec_test.py b/compiler/tests/04_and3_dec_test.py index 7794f36b..ec83335b 100755 --- a/compiler/tests/04_and3_dec_test.py +++ b/compiler/tests/04_and3_dec_test.py @@ -23,10 +23,13 @@ class and3_dec_test(openram_test): global verify import verify - import and3_dec - - debug.info(2, "Testing and3 gate 4x") - a = and3_dec.and3_dec(name="and3x4", size=4) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing and3_dec gate") + a = factory.create(module_type="and3_dec") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_and4_dec_test.py b/compiler/tests/04_and4_dec_test.py index 7794f36b..bdd91c40 100755 --- a/compiler/tests/04_and4_dec_test.py +++ b/compiler/tests/04_and4_dec_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class and3_dec_test(openram_test): +class and4_dec_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -23,10 +23,13 @@ class and3_dec_test(openram_test): global verify import verify - import and3_dec - - debug.info(2, "Testing and3 gate 4x") - a = and3_dec.and3_dec(name="and3x4", size=4) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing and4_dec gate") + a = factory.create(module_type="and4_dec") self.local_check(a) globals.end_openram() From 7ea3366ef1b554b326202460a05001882b4d1389 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 22 Jun 2020 16:58:01 -0700 Subject: [PATCH 428/521] Disable magic filter in sky130 --- compiler/verify/calibre.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index d4f31960..0a975599 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -189,7 +189,7 @@ def run_drc(cell_name, gds_name, extract=False, final_verification=False): num_drc_runs += 1 # Filter the layouts through magic as a GDS filter for nsdm/psdm/nwell merging - if OPTS.tech_name == "sky130": + if OPTS.tech_name == "sky130" and False: shutil.copy(gds_name, OPTS.openram_temp + "temp.gds") from magic import filter_gds filter_gds(cell_name, OPTS.openram_temp + "temp.gds", OPTS.openram_temp + cell_name + ".gds") From 1a528f9739db719eded519d0afc682d2a3988fcc Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Jun 2020 10:08:28 -0700 Subject: [PATCH 429/521] Skip and4_dec test --- compiler/tests/04_and4_dec_test.py | 2 ++ compiler/tests/{skip_tests_s8.txt => skip_tests_sky130.txt} | 0 2 files changed, 2 insertions(+) rename compiler/tests/{skip_tests_s8.txt => skip_tests_sky130.txt} (100%) diff --git a/compiler/tests/04_and4_dec_test.py b/compiler/tests/04_and4_dec_test.py index bdd91c40..ffd7788a 100755 --- a/compiler/tests/04_and4_dec_test.py +++ b/compiler/tests/04_and4_dec_test.py @@ -15,6 +15,8 @@ from globals import OPTS from sram_factory import factory import debug + +@unittest.skip("SKIPPING 04_and4_dec_test") class and4_dec_test(openram_test): def runTest(self): diff --git a/compiler/tests/skip_tests_s8.txt b/compiler/tests/skip_tests_sky130.txt similarity index 100% rename from compiler/tests/skip_tests_s8.txt rename to compiler/tests/skip_tests_sky130.txt From 031862c7495c20518a717fd55005ca98a5eeb226 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Jun 2020 11:56:50 -0700 Subject: [PATCH 430/521] Add metal enclosure to base case of center via stack. --- compiler/base/hierarchy_layout.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index c9b6a7a8..9331f31d 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -599,6 +599,10 @@ class layout(): """ if from_layer == to_layer: + # In the case where we have no vias added, make sure that there is at least + # a metal enclosure. This helps with center-line path routing. + self.add_rect_center(layer=from_layer, + offset=offset) return last_via from_id = layer_indices[from_layer] From e849a9b973e3c316838140aa955db5ce08fb29c1 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Jun 2020 14:53:24 -0700 Subject: [PATCH 431/521] Use different LVS libs based on tech and sky130 --- compiler/base/hierarchy_design.py | 8 ++++++-- compiler/pgates/ptx.py | 28 +++++++++++++--------------- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 20c40f21..ac3fb30b 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -11,7 +11,7 @@ import verify import debug import os from globals import OPTS - +import tech class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): """ @@ -26,7 +26,11 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # If we have a separate lvs directory, then all the lvs files # should be in there (all or nothing!) - lvs_dir = OPTS.openram_tech + "lvs_lib/" + try: + lvs_subdir = tech.lvs_lib + except AttributeError: + lvs_subdir = "lvs_lib" + lvs_dir = OPTS.openram_tech + lvs_subdir + "/" if os.path.exists(lvs_dir): self.lvs_file = lvs_dir + name + ".sp" else: diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index fb127158..9af08e61 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -131,8 +131,8 @@ class ptx(design.design): # be decided in the layout later. area_sd = 2.5 * self.poly_width * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width - if OPTS.tech_name == "sky130": - # sky130 technology is in microns, also needs mult parameter + if OPTS.tech_name == "sky130" and OPTS.lvs_exe[0] == "calibre": + # sky130 simulation cannot use the mult parameter in simulation (self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], self.mults, @@ -152,19 +152,17 @@ class ptx(design.design): self.spice_device = main_str + area_str self.spice.append("\n* ptx " + self.spice_device) - # LVS lib is always in SI units - if os.path.exists(OPTS.openram_tech + "lvs_lib"): - if OPTS.tech_name == "sky130": - # sky130 requires mult parameter too - self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult={1}".format(spice[self.tx_type], - self.mults, - self.tx_width, - drc("minwidth_poly")) - else: - self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], - self.mults, - self.tx_width, - drc("minwidth_poly")) + if OPTS.tech_name == "sky130" and OPTS.lvs_exe[0] == "calibre": + # sky130 requires mult parameter too + self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult={1}".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly")) + else: + self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly")) def setup_layout_constants(self): """ From 83001e1ab51e97d269194ffccf30e809c34e8094 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Jun 2020 15:39:26 -0700 Subject: [PATCH 432/521] PEP8 formatting --- compiler/base/hierarchy_spice.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 5ba60435..5a15fce5 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -215,7 +215,7 @@ class spice(): # We don't define self.lvs and will use self.spice if dynamically created # or they are the same file - if self.lvs_file!=self.sp_file and os.path.isfile(self.lvs_file): + if self.lvs_file != self.sp_file and os.path.isfile(self.lvs_file): debug.info(3, "opening {0}".format(self.lvs_file)) f = open(self.lvs_file) self.lvs = f.readlines() From cfa234a4d0307643f1da33bae846189d3fee3862 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Jun 2020 15:39:42 -0700 Subject: [PATCH 433/521] Extra space between decoders for well spacing --- compiler/modules/hierarchical_decoder.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 8830d397..3233bdc8 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -152,7 +152,7 @@ class hierarchical_decoder(design.design): self.predecoder_width = self.pre2_4.width # How much space between each predecoder - self.predecoder_spacing = self.and2.height + self.predecoder_spacing = 2 * self.and2.height self.predecoder_height = self.pre2_4.height * self.no_of_pre2x4 + self.pre3_8.height * self.no_of_pre3x8 \ + (self.no_of_pre2x4 + self.no_of_pre3x8 - 1) * self.predecoder_spacing From 22c821f5d868865910d4bffb82f8e23a0bf01373 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Jun 2020 15:40:00 -0700 Subject: [PATCH 434/521] Change port_address test to 256 for riscv --- compiler/tests/18_port_address_1rw_1r_test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/tests/18_port_address_1rw_1r_test.py b/compiler/tests/18_port_address_1rw_1r_test.py index ff09dec9..caf2cb96 100755 --- a/compiler/tests/18_port_address_1rw_1r_test.py +++ b/compiler/tests/18_port_address_1rw_1r_test.py @@ -30,8 +30,8 @@ class port_address_1rw_1r_test(openram_test): a = factory.create("port_address", cols=16, rows=16) self.local_check(a) - debug.info(1, "Port address 512 rows") - a = factory.create("port_address", cols=256, rows=512) + debug.info(1, "Port address 256 rows") + a = factory.create("port_address", cols=256, rows=256) self.local_check(a) globals.end_openram() From 4e83e8c648025c40898b785a29898228e2fd1966 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Tue, 23 Jun 2020 18:13:17 -0700 Subject: [PATCH 435/521] added contact to locali for wmask --- compiler/modules/write_mask_and_array.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 581f9484..f337ab7a 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -10,7 +10,7 @@ import debug from sram_factory import factory from vector import vector from globals import OPTS - +from tech import layer class write_mask_and_array(design.design): """ @@ -93,7 +93,7 @@ class write_mask_and_array(design.design): self.width = self.bitcell.width * self.columns self.height = self.and2.height - + for i in range(self.num_wmasks): base = vector(i * self.wmask_en_len, 0) self.and2_insts[i].place(base) @@ -121,16 +121,17 @@ class write_mask_and_array(design.design): for supply in ["gnd", "vdd"]: supply_pin=self.and2_insts[i].get_pin(supply) - self.add_power_pin(supply, supply_pin.center()) + if "li" in layer: + self.add_power_pin(supply, supply_pin.center(), start_layer="li", directions = ("H", "H")) + else: + self.add_power_pin(supply, supply_pin.center()) for supply in ["gnd", "vdd"]: supply_pin_left = self.and2_insts[0].get_pin(supply) supply_pin_right = self.and2_insts[self.num_wmasks - 1].get_pin(supply) self.add_path(supply_pin_left.layer, [supply_pin_left.lc(), supply_pin_right.rc()]) - + def get_cin(self): """Get the relative capacitance of all the input connections in the bank""" # The enable is connected to an and2 for every row. return self.and2.get_cin() * len(self.and2_insts) - - From 22ed725a35446fe3f10d9509d1f11d6d85f56cf9 Mon Sep 17 00:00:00 2001 From: Joey Kunzler Date: Tue, 23 Jun 2020 18:16:14 -0700 Subject: [PATCH 436/521] made 1rw_1r tests for write driver and wmask, fixed typo in portdata_wmask_1rw_1r_test --- .../10_write_driver_array_1rw_1r_test.py | 44 ++++++++++++++++ .../10_write_mask_and_array_1rw_1r_test.py | 51 +++++++++++++++++++ .../tests/18_port_data_wmask_1rw_1r_test.py | 5 ++ 3 files changed, 100 insertions(+) create mode 100644 compiler/tests/10_write_driver_array_1rw_1r_test.py create mode 100644 compiler/tests/10_write_mask_and_array_1rw_1r_test.py diff --git a/compiler/tests/10_write_driver_array_1rw_1r_test.py b/compiler/tests/10_write_driver_array_1rw_1r_test.py new file mode 100644 index 00000000..4acbf053 --- /dev/null +++ b/compiler/tests/10_write_driver_array_1rw_1r_test.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class write_driver_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing write_driver_array for columns=8, word_size=8") + a = factory.create(module_type="write_driver_array", columns=8, word_size=8) + self.local_check(a) + + debug.info(2, "Testing write_driver_array for columns=16, word_size=8") + a = factory.create(module_type="write_driver_array", columns=16, word_size=8) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py new file mode 100644 index 00000000..73988db9 --- /dev/null +++ b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os + +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class write_mask_and_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4") + a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4) + self.local_check(a) + + debug.info(2, "Testing write_mask_and_array for columns=16, word_size=16, write_size=4") + a = factory.create(module_type="write_mask_and_array", columns=16, word_size=16, write_size=4) + self.local_check(a) + + debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2") + a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2) + self.local_check(a) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py index 52d1c4fb..74aa7fc0 100755 --- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py +++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py @@ -22,6 +22,11 @@ class port_data_wmask_1rw_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + c = sram_config(word_size=16, write_size=4, num_words=16) From b3d1161957aa0a13f0af5b2764f8c53070dab151 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 08:19:25 -0700 Subject: [PATCH 437/521] Add u+x permissions to new tests --- compiler/tests/10_write_driver_array_1rw_1r_test.py | 0 compiler/tests/10_write_mask_and_array_1rw_1r_test.py | 0 2 files changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 compiler/tests/10_write_driver_array_1rw_1r_test.py mode change 100644 => 100755 compiler/tests/10_write_mask_and_array_1rw_1r_test.py diff --git a/compiler/tests/10_write_driver_array_1rw_1r_test.py b/compiler/tests/10_write_driver_array_1rw_1r_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py old mode 100644 new mode 100755 From a32b5b13e8852a9f68fafbe8fc888aa18fca2160 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 08:26:15 -0700 Subject: [PATCH 438/521] Rename nwell yoffset for consistency --- compiler/pgates/pgate.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 09074960..104d7a06 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -150,7 +150,7 @@ class pgate(design.design): """ Extend the n/p wells to cover whole cell """ # This should match the cells in the cell library - self.nwell_y_offset = 0.48 * self.height + self.nwell_yoffset = 0.48 * self.height full_height = self.height + 0.5 * self.m1_width # FIXME: float rounding problem @@ -158,8 +158,8 @@ class pgate(design.design): # Add a rail width to extend the well to the top of the rail nwell_max_offset = max(self.find_highest_layer_coords("nwell").y, full_height) - nwell_position = vector(0, self.nwell_y_offset) - vector(self.well_extend_active, 0) - nwell_height = nwell_max_offset - self.nwell_y_offset + nwell_position = vector(0, self.nwell_yoffset) - vector(self.well_extend_active, 0) + nwell_height = nwell_max_offset - self.nwell_yoffset self.add_rect(layer="nwell", offset=nwell_position, width=self.width + 2 * self.well_extend_active, @@ -175,7 +175,7 @@ class pgate(design.design): pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y, -0.5 * self.m1_width) pwell_position = vector(-self.well_extend_active, pwell_min_offset) - pwell_height = self.nwell_y_offset - pwell_position.y + pwell_height = self.nwell_yoffset - pwell_position.y self.add_rect(layer="pwell", offset=pwell_position, width=self.width + 2 * self.well_extend_active, From cddb16dabce5c1d945c9bb80a21ea871ca564a5f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 09:17:39 -0700 Subject: [PATCH 439/521] Separate active and poly contact to gate rule --- compiler/base/design.py | 3 ++- compiler/pgates/pnand2.py | 4 ++-- compiler/pgates/pnand3.py | 7 +++---- compiler/pgates/precharge.py | 2 +- compiler/pgates/ptx.py | 6 +++--- technology/freepdk45/tech/tech.py | 4 ++-- technology/scn4m_subm/tech/tech.py | 4 ++-- 7 files changed, 15 insertions(+), 15 deletions(-) diff --git a/compiler/base/design.py b/compiler/base/design.py index 1fded37e..2b2d7711 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -205,7 +205,8 @@ class design(hierarchy_design): print("poly_to_active", self.poly_to_active) print("poly_extend_active", self.poly_extend_active) print("poly_to_contact", self.poly_to_contact) - print("contact_to_gate", self.contact_to_gate) + print("active_contact_to_gate", self.active_contact_to_gate) + print("poly_contact_to_gate", self.poly_contact_to_gate) print("well_enclose_active", self.well_enclose_active) print("implant_enclose_active", self.implant_enclose_active) print("implant_space", self.implant_space) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 12323885..9cc530c0 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -184,7 +184,7 @@ class pnand2(pgate.pgate): # doesn't use nmos uy because that is calculated using offset + poly height active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height - active_to_poly_contact2 = active_top + drc("contact_to_gate") + 0.5 * self.route_layer_width + active_to_poly_contact2 = active_top + self.poly_contact_to_gate + 0.5 * self.route_layer_width self.inputA_yoffset = max(active_contact_to_poly_contact, active_to_poly_contact, active_to_poly_contact2) @@ -200,7 +200,7 @@ class pnand2(pgate.pgate): # active_contact_to_poly_contact = self.output_yoffset - self.route_layer_space - 0.5 * contact.poly_contact.second_layer_height # active_bottom = self.pmos1_inst.by() # active_to_poly_contact = active_bottom - self.poly_to_active - 0.5 * contact.poly_contact.first_layer_height - # active_to_poly_contact2 = active_bottom - drc("contact_to_gate") - 0.5 * self.route_layer_width + # active_to_poly_contact2 = active_bottom - self.poly_contact_to_gate - 0.5 * self.route_layer_width # self.inputB_yoffset = min(active_contact_to_poly_contact, # active_to_poly_contact, # active_to_poly_contact2) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index e227d7af..03652b9b 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -222,7 +222,7 @@ class pnand3(pgate.pgate): # doesn't use nmos uy because that is calculated using offset + poly height active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height - active_to_poly_contact2 = active_top + drc("contact_to_gate") + 0.5 * self.route_layer_width + active_to_poly_contact2 = active_top + self.poly_contact_to_gate + 0.5 * self.route_layer_width self.inputA_yoffset = max(active_contact_to_poly_contact, active_to_poly_contact, active_to_poly_contact2) @@ -233,15 +233,14 @@ class pnand3(pgate.pgate): "A", position="left") - # Put B right on the well line - self.inputB_yoffset = self.inputA_yoffset + non_contact_pitch + self.inputB_yoffset = self.inputA_yoffset + 1.2 * self.m3_pitch self.route_input_gate(self.pmos2_inst, self.nmos2_inst, self.inputB_yoffset, "B", position="center") - self.inputC_yoffset = self.inputB_yoffset + non_contact_pitch + self.inputC_yoffset = self.inputB_yoffset + 1.2 * self.m3_pitch self.route_input_gate(self.pmos3_inst, self.nmos3_inst, self.inputC_yoffset, diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index fdce1a35..dc016cab 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -196,7 +196,7 @@ class precharge(design.design): pin_offset = self.lower_pmos_inst.get_pin("G").lr() # This is an extra space down for some techs with contact to active spacing contact_space = max(self.poly_space, - self.contact_to_gate) + 0.5 * contact.poly_contact.first_layer_height + self.poly_contact_to_gate) + 0.5 * contact.poly_contact.first_layer_height offset = pin_offset - vector(0, contact_space) self.add_via_stack_center(from_layer="poly", to_layer=self.en_layer, diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 9af08e61..8be003b2 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -196,7 +196,7 @@ class ptx(design.design): # This is the spacing between the poly gates self.min_poly_pitch = self.poly_space + self.poly_width self.contacted_poly_pitch = self.poly_space + contact.poly_contact.width - self.contact_pitch = 2 * self.contact_to_gate + self.poly_width + self.contact_width + self.contact_pitch = 2 * self.active_contact_to_gate + self.poly_width + self.contact_width self.poly_pitch = max(self.min_poly_pitch, self.contacted_poly_pitch, self.contact_pitch) @@ -206,7 +206,7 @@ class ptx(design.design): # Active width is determined by enclosure on both ends and contacted pitch, # at least one poly and n-1 poly pitches self.active_width = 2 * self.end_to_contact + self.active_contact.width \ - + 2 * self.contact_to_gate + self.poly_width + (self.mults - 1) * self.poly_pitch + + 2 * self.active_contact_to_gate + self.poly_width + (self.mults - 1) * self.poly_pitch # Active height is just the transistor width self.active_height = self.tx_width @@ -321,7 +321,7 @@ class ptx(design.design): """ # poly is one contacted spacing from the end and down an extension poly_offset = self.contact_offset \ - + vector(0.5 * self.active_contact.width + 0.5 * self.poly_width + self.contact_to_gate, 0) + + vector(0.5 * self.active_contact.width + 0.5 * self.poly_width + self.active_contact_to_gate, 0) # poly_positions are the bottom center of the poly gates self.poly_positions = [] diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index c0379e44..6de01254 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -234,9 +234,9 @@ drc.add_enclosure("active", enclosure = 0.005) # CONTACT.6 Minimum spacing of contact and gate -drc["contact_to_gate"] = 0.0375 #changed from 0.035 +drc["active_contact_to_gate"] = 0.0375 #changed from 0.035 # CONTACT.7 Minimum spacing of contact and poly -drc["contact_to_poly"] = 0.090 +drc["poly_contact_to_gate"] = 0.090 # CONTACT.1 Minimum width of contact # CONTACT.2 Minimum spacing of contact diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 745b381e..55826ec5 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -217,9 +217,9 @@ drc.add_enclosure("active", layer = "contact", enclosure = _lambda_) # Reserved for other technologies -drc["contact_to_gate"] = 2*_lambda_ +drc["active_contact_to_gate"] = 2*_lambda_ # 5.4 Minimum spacing to gate of transistor -drc["contact_to_poly"] = 2*_lambda_ +drc["poly_contact_to_gate"] = 2*_lambda_ # 6.1 Exact contact size # 5.3 Minimum contact spacing From 13409083301834f77115e4abd3a417dff5009e4f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 09:24:26 -0700 Subject: [PATCH 440/521] Remove fudge factor for pin spacing --- compiler/pgates/pnand3.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 03652b9b..1fd5146f 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -233,14 +233,14 @@ class pnand3(pgate.pgate): "A", position="left") - self.inputB_yoffset = self.inputA_yoffset + 1.2 * self.m3_pitch + self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch self.route_input_gate(self.pmos2_inst, self.nmos2_inst, self.inputB_yoffset, "B", position="center") - self.inputC_yoffset = self.inputB_yoffset + 1.2 * self.m3_pitch + self.inputC_yoffset = self.inputB_yoffset + self.m3_pitch self.route_input_gate(self.pmos3_inst, self.nmos3_inst, self.inputC_yoffset, From 98ec9442c61966cd602eebfddf68990dcddcdc30 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 10:00:00 -0700 Subject: [PATCH 441/521] Add npc enclosure for pnand2, pnand3, pnor2 --- compiler/pgates/pgate.py | 27 +++++++++++++++++++++++++++ compiler/pgates/pnand2.py | 4 ++++ compiler/pgates/pnand3.py | 3 +++ compiler/pgates/pnor2.py | 3 +++ 4 files changed, 37 insertions(+) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 104d7a06..bb105f36 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -43,6 +43,9 @@ class pgate(design.design): self.route_layer_space = getattr(self, "{}_space".format(self.route_layer)) self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer)) + # hack for enclosing input pin with npc + self.input_pin_vias = [] + # This is the space from a S/D contact to the supply rail contact_to_vdd_rail_space = 0.5 * self.route_layer_width + self.route_layer_space # This is a poly-to-poly of a flipped cell @@ -132,6 +135,8 @@ class pgate(design.design): offset=contact_offset, directions=directions) + self.input_pin_vias.append(via) + self.add_layout_pin_rect_center(text=name, layer=self.route_layer, offset=contact_offset, @@ -146,6 +151,28 @@ class pgate(design.design): height=contact.poly_contact.first_layer_width, width=left_gate_offset.x - contact_offset.x) + def enclose_npc(self): + """ Enclose the poly contacts with npc layer """ + ll = None + ur = None + for via in self.input_pin_vias: + # Find ll/ur + if not ll: + ll = via.ll() + else: + ll = ll.min(via.ll()) + if not ur: + ur = via.ur() + else: + ur = ur.max(via.ur()) + + npc_enclose_poly = drc("npc_enclose_poly") + npc_enclose_offset = vector(npc_enclose_poly, npc_enclose_poly) + self.add_rect(layer="npc", + offset=ll - npc_enclose_offset, + width=(ur.x - ll.x) + 2 * npc_enclose_poly, + height=(ur.y - ll.y) + 2 * npc_enclose_poly) + def extend_wells(self): """ Extend the n/p wells to cover whole cell """ diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 9cc530c0..6a65f721 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -212,6 +212,10 @@ class pnand2(pgate.pgate): "B", position="center") + if OPTS.tech_name == "sky130": + self.enclose_npc() + + def route_output(self): """ Route the Z output """ diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 1fd5146f..0c2bc081 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -246,6 +246,9 @@ class pnand3(pgate.pgate): self.inputC_yoffset, "C", position="right") + + if OPTS.tech_name == "sky130": + self.enclose_npc() def route_output(self): """ Route the Z output """ diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 3cceb7f4..7f75ddd1 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -211,6 +211,9 @@ class pnor2(pgate.pgate): self.output_yoffset = self.inputA_yoffset + self.m1_nonpref_pitch + if OPTS.tech_name == "sky130": + self.enclose_npc() + def route_output(self): """ Route the Z output """ # PMOS2 (right) drain From 93d65e84e1ae95a4c754520a3fe42caccdc1894e Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 10:26:49 -0700 Subject: [PATCH 442/521] Fix power pin layer problems in delay line --- compiler/modules/delay_chain.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index ad9bc1cc..c07395f5 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -178,10 +178,14 @@ class delay_chain(design.design): load_list = self.load_inst_map[inst] for pin_name in ["vdd", "gnd"]: pin = load_list[0].get_pin(pin_name) - self.add_power_pin(pin_name, pin.rc() - vector(self.m1_pitch, 0)) + self.add_power_pin(pin_name, + pin.rc() - vector(self.m1_pitch, 0), + start_layer=pin.layer) - pin = load_list[-1].get_pin(pin_name) - self.add_power_pin(pin_name, pin.rc() - vector(0.5 * self.m1_pitch, 0)) + pin = load_list[-2].get_pin(pin_name) + self.add_power_pin(pin_name, + pin.rc() - vector(self.m1_pitch, 0), + start_layer=pin.layer) def add_layout_pins(self): From 4bc3df8931602269c242457ceed2f95c4da8e4eb Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 11:54:36 -0700 Subject: [PATCH 443/521] Add get_tx_insts and expand add_enclosure --- compiler/base/hierarchy_layout.py | 75 +++++++++++++++++++++++-------- 1 file changed, 57 insertions(+), 18 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 9331f31d..f90b3129 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -269,6 +269,23 @@ class layout(): width, end.y - start.y) + def get_tx_insts(self, tx_type=None): + """ + Return a list of the instances of given tx type. + """ + tx_list = [] + for i in self.insts: + try: + if tx_type and i.mod.tx_type == tx_type: + tx_list.append(i) + elif not tx_type: + if i.mod.tx_type == "nmos" or i.mod.tx_type == "pmos": + tx_list.append(i) + except AttributeError: + pass + + return tx_list + def get_pin(self, text): """ Return the pin or list of pins @@ -1301,26 +1318,48 @@ class layout(): height=ur.y - ll.y, width=ur.x - ll.x) - def add_enclosure(self, insts, layer="nwell"): - """ Add a layer that surrounds the given instances. Useful + def add_enclosure(self, insts, layer="nwell", extend=0, leftx=None, rightx=None, topy=None, boty=None): + """ + Add a layer that surrounds the given instances. Useful for creating wells, for example. Doesn't check for minimum widths or - spacings.""" + spacings. Extra arg can force a dimension to one side left/right top/bot. + """ - xmin = insts[0].lx() - ymin = insts[0].by() - xmax = insts[0].rx() - ymax = insts[0].uy() - for inst in insts: - xmin = min(xmin, inst.lx()) - ymin = min(ymin, inst.by()) - xmax = max(xmax, inst.rx()) - ymax = max(ymax, inst.uy()) - - self.add_rect(layer=layer, - offset=vector(xmin, ymin), - width=xmax - xmin, - height=ymax - ymin) + if leftx != None: + xmin = leftx + else: + xmin = insts[0].lx() + for inst in insts: + xmin = min(xmin, inst.lx()) + xmin = xmin - extend + if boty != None: + ymin = boty + else: + ymin = insts[0].by() + for inst in insts: + ymin = min(ymin, inst.by()) + ymin = ymin - extend + if rightx != None: + xmax = rightx + else: + xmax = insts[0].rx() + for inst in insts: + xmax = max(xmax, inst.rx()) + xmax = xmax + extend + if topy != None: + ymax = topy + else: + ymax = insts[0].uy() + for inst in insts: + ymax = max(ymax, inst.uy()) + ymax = ymax + extend + rect = self.add_rect(layer=layer, + offset=vector(xmin, ymin), + width=xmax - xmin, + height=ymax - ymin) + return rect + def copy_power_pins(self, inst, name): """ This will copy a power pin if it is on the lowest power_grid layer. @@ -1337,7 +1376,7 @@ class layout(): else: self.add_power_pin(name, pin.center(), start_layer=pin.layer) - + def add_power_pin(self, name, loc, size=[1, 1], directions=None, start_layer="m1"): """ Add a single power pin from the lowest power_grid layer down to M1 (or li) at From e694622f2809bc588d94b0a28040534cd93fd293 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 11:54:59 -0700 Subject: [PATCH 444/521] use add_enclosure to extend implants --- compiler/pgates/pgate.py | 59 ++++++++++++++++++++++++---------------- 1 file changed, 35 insertions(+), 24 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index bb105f36..9fa8c916 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -135,8 +135,6 @@ class pgate(design.design): offset=contact_offset, directions=directions) - self.input_pin_vias.append(via) - self.add_layout_pin_rect_center(text=name, layer=self.route_layer, offset=contact_offset, @@ -151,27 +149,7 @@ class pgate(design.design): height=contact.poly_contact.first_layer_width, width=left_gate_offset.x - contact_offset.x) - def enclose_npc(self): - """ Enclose the poly contacts with npc layer """ - ll = None - ur = None - for via in self.input_pin_vias: - # Find ll/ur - if not ll: - ll = via.ll() - else: - ll = ll.min(via.ll()) - if not ur: - ur = via.ur() - else: - ur = ur.max(via.ur()) - - npc_enclose_poly = drc("npc_enclose_poly") - npc_enclose_offset = vector(npc_enclose_poly, npc_enclose_poly) - self.add_rect(layer="npc", - offset=ll - npc_enclose_offset, - width=(ur.x - ll.x) + 2 * npc_enclose_poly, - height=(ur.y - ll.y) + 2 * npc_enclose_poly) + return via def extend_wells(self): """ Extend the n/p wells to cover whole cell """ @@ -179,6 +157,7 @@ class pgate(design.design): # This should match the cells in the cell library self.nwell_yoffset = 0.48 * self.height full_height = self.height + 0.5 * self.m1_width + # FIXME: float rounding problem if "nwell" in layer: @@ -212,6 +191,8 @@ class pgate(design.design): offset=pwell_position, width=self.width + 2 * self.well_extend_active, height=pwell_height) + + self.extend_implants() def add_nwell_contact(self, pmos, pmos_pos): """ Add an nwell contact next to the given pmos device. """ @@ -267,6 +248,36 @@ class pgate(design.design): # Return the top of the well + def extend_implants(self): + """ + Add top-to-bottom implants for adjacency issues in s8. + """ + nmos_insts = self.get_tx_insts("nmos") + pmos_insts = self.get_tx_insts("pmos") + ntap_insts = [self.nwell_contact] + ptap_insts = [self.pwell_contact] + + self.add_enclosure(nmos_insts, + layer="nimplant", + extend=self.implant_enclose_active, + leftx=0, + boty=0) + self.add_enclosure(pmos_insts, + layer="pimplant", + extend=self.implant_enclose_active, + leftx=0, + topy=self.height) + self.add_enclosure(ntap_insts, + layer="nimplant", + extend=self.implant_enclose_active, + rightx=self.width, + topy=self.height) + self.add_enclosure(ptap_insts, + layer="pimplant", + extend=self.implant_enclose_active, + rightx=self.width, + boty=0) + def add_pwell_contact(self, nmos, nmos_pos): """ Add an pwell contact next to the given nmos device. """ @@ -295,7 +306,7 @@ class pgate(design.design): offset=contact_offset.scale(1, 0.5), width=self.pwell_contact.mod.second_layer_width, height=contact_offset.y) - + # Now add the full active and implant for the NMOS # active_offset = nmos_pos + vector(nmos.active_width,0) # This might be needed if the spacing between the actives From 6c523a75561cb3e4ff9e65b1dd0b953c4b028a37 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 11:55:44 -0700 Subject: [PATCH 445/521] use add_enclosure for npc contacts --- compiler/pgates/pnand2.py | 22 +++++++++++----------- compiler/pgates/pnand3.py | 32 ++++++++++++++++---------------- compiler/pgates/pnor2.py | 24 ++++++++++++------------ 3 files changed, 39 insertions(+), 39 deletions(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 6a65f721..3974d95b 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -189,11 +189,11 @@ class pnand2(pgate.pgate): active_to_poly_contact, active_to_poly_contact2) - self.route_input_gate(self.pmos1_inst, - self.nmos1_inst, - self.inputA_yoffset, - "A", - position="center") + apin = self.route_input_gate(self.pmos1_inst, + self.nmos1_inst, + self.inputA_yoffset, + "A", + position="center") self.inputB_yoffset = self.inputA_yoffset + 2 * self.m3_pitch # # active contact metal to poly contact metal spacing @@ -206,14 +206,14 @@ class pnand2(pgate.pgate): # active_to_poly_contact2) # This will help with the wells and the input/output placement - self.route_input_gate(self.pmos2_inst, - self.nmos2_inst, - self.inputB_yoffset, - "B", - position="center") + bpin = self.route_input_gate(self.pmos2_inst, + self.nmos2_inst, + self.inputB_yoffset, + "B", + position="center") if OPTS.tech_name == "sky130": - self.enclose_npc() + self.add_enclosure([apin, bpin], "npc", drc("npc_enclose_poly")) def route_output(self): diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 0c2bc081..ff988d88 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -227,28 +227,28 @@ class pnand3(pgate.pgate): active_to_poly_contact, active_to_poly_contact2) - self.route_input_gate(self.pmos1_inst, - self.nmos1_inst, - self.inputA_yoffset, - "A", - position="left") + apin = self.route_input_gate(self.pmos1_inst, + self.nmos1_inst, + self.inputA_yoffset, + "A", + position="left") self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch - self.route_input_gate(self.pmos2_inst, - self.nmos2_inst, - self.inputB_yoffset, - "B", - position="center") + bpin = self.route_input_gate(self.pmos2_inst, + self.nmos2_inst, + self.inputB_yoffset, + "B", + position="center") self.inputC_yoffset = self.inputB_yoffset + self.m3_pitch - self.route_input_gate(self.pmos3_inst, - self.nmos3_inst, - self.inputC_yoffset, - "C", - position="right") + cpin = self.route_input_gate(self.pmos3_inst, + self.nmos3_inst, + self.inputC_yoffset, + "C", + position="right") if OPTS.tech_name == "sky130": - self.enclose_npc() + self.add_enclosure([apin, bpin, cpin], "npc", drc("npc_enclose_poly")) def route_output(self): """ Route the Z output """ diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 7f75ddd1..908bba82 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -195,24 +195,24 @@ class pnor2(pgate.pgate): self.inputB_yoffset = bottom_pin_offset + self.m1_nonpref_pitch self.inputA_yoffset = self.inputB_yoffset + self.m1_nonpref_pitch - self.route_input_gate(self.pmos2_inst, - self.nmos2_inst, - self.inputB_yoffset, - "B", - position="right", - directions=("V", "V")) + bpin = self.route_input_gate(self.pmos2_inst, + self.nmos2_inst, + self.inputB_yoffset, + "B", + position="right", + directions=("V", "V")) # This will help with the wells and the input/output placement - self.route_input_gate(self.pmos1_inst, - self.nmos1_inst, - self.inputA_yoffset, - "A", - directions=("V", "V")) + apin = self.route_input_gate(self.pmos1_inst, + self.nmos1_inst, + self.inputA_yoffset, + "A", + directions=("V", "V")) self.output_yoffset = self.inputA_yoffset + self.m1_nonpref_pitch if OPTS.tech_name == "sky130": - self.enclose_npc() + self.add_enclosure([apin, bpin], "npc", drc("npc_enclose_poly")) def route_output(self): """ Route the Z output """ From ba92467fec2967a7f652c540c10ff80535aa3788 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 12:07:47 -0700 Subject: [PATCH 446/521] Add no well enclosure for techs without wells --- compiler/pgates/pgate.py | 62 +++++++++++++++++++++++++--------------- 1 file changed, 39 insertions(+), 23 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 9fa8c916..02a04b97 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -252,31 +252,47 @@ class pgate(design.design): """ Add top-to-bottom implants for adjacency issues in s8. """ + if self.add_wells: + rightx = None + else: + rightx = self.width + nmos_insts = self.get_tx_insts("nmos") + if len(nmos_insts) > 0: + self.add_enclosure(nmos_insts, + layer="nimplant", + extend=self.implant_enclose_active, + leftx=0, + rightx=rightx, + boty=0) + pmos_insts = self.get_tx_insts("pmos") - ntap_insts = [self.nwell_contact] - ptap_insts = [self.pwell_contact] - - self.add_enclosure(nmos_insts, - layer="nimplant", - extend=self.implant_enclose_active, - leftx=0, - boty=0) - self.add_enclosure(pmos_insts, - layer="pimplant", - extend=self.implant_enclose_active, - leftx=0, - topy=self.height) - self.add_enclosure(ntap_insts, - layer="nimplant", - extend=self.implant_enclose_active, - rightx=self.width, - topy=self.height) - self.add_enclosure(ptap_insts, - layer="pimplant", - extend=self.implant_enclose_active, - rightx=self.width, - boty=0) + if len(pmos_insts) > 0: + self.add_enclosure(pmos_insts, + layer="pimplant", + extend=self.implant_enclose_active, + leftx=0, + rightx=rightx, + topy=self.height) + + try: + ntap_insts = [self.nwell_contact] + self.add_enclosure(ntap_insts, + layer="nimplant", + extend=self.implant_enclose_active, + rightx=self.width, + topy=self.height) + except AttributeError: + pass + try: + ptap_insts = [self.pwell_contact] + self.add_enclosure(ptap_insts, + layer="pimplant", + extend=self.implant_enclose_active, + rightx=self.width, + boty=0) + except AttributeError: + pass def add_pwell_contact(self, nmos, nmos_pos): """ Add an pwell contact next to the given nmos device. """ From da900b89ba6759778942114c81068cb23d0b1c41 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Jun 2020 13:48:30 -0700 Subject: [PATCH 447/521] Only expand implants in sky130 --- compiler/pgates/pgate.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 02a04b97..809ffbd9 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -191,8 +191,9 @@ class pgate(design.design): offset=pwell_position, width=self.width + 2 * self.well_extend_active, height=pwell_height) - - self.extend_implants() + + if OPTS.tech_name == "sky130": + self.extend_implants() def add_nwell_contact(self, pmos, pmos_pos): """ Add an nwell contact next to the given pmos device. """ From 57b6d49edb4f39d4c74c0f5587eb078f101c921b Mon Sep 17 00:00:00 2001 From: jcirimel Date: Thu, 25 Jun 2020 06:32:07 -0700 Subject: [PATCH 448/521] fix pinv size bining --- compiler/pgates/pgate.py | 2 +- compiler/pgates/pinv.py | 22 ++++++++++++++++------ 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 09074960..ef1445c0 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -379,4 +379,4 @@ class pgate(design.design): return(scaled_bins) def bin_accuracy(self, ideal_width, width): - return abs(1-(ideal_width - width)/ideal_width) + return 1-abs((ideal_width - width)/ideal_width) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index de0ba8e4..1429e0c8 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -31,6 +31,9 @@ class pinv(pgate.pgate): height is usually the same as the 6t library cell and is measured from center of rail to rail. """ + # binning %error tracker + bin_count = 0 + bin_error = 0 def __init__(self, name, size=1, beta=parameter["beta"], height=None, add_wells=True): @@ -44,7 +47,7 @@ class pinv(pgate.pgate): self.nmos_size = size self.pmos_size = beta * size self.beta = beta - + pgate.pgate.__init__(self, name, height, add_wells) def create_netlist(self): @@ -166,30 +169,37 @@ class pinv(pgate.pgate): valid_pmos = [] for bin in pmos_bins: - if self.bin_accuracy(self.pmos_width, bin[0]) > accuracy_requirement: + if abs(self.bin_accuracy(self.pmos_width, bin[0])) > accuracy_requirement and abs(self.bin_accuracy(self.pmos_width, bin[0])) <= 1: valid_pmos.append(bin) valid_pmos.sort(key = operator.itemgetter(1)) valid_nmos = [] for bin in nmos_bins: - if self.bin_accuracy(self.nmos_width, bin[0]) > accuracy_requirement: + if abs(self.bin_accuracy(self.nmos_width, bin[0])) > accuracy_requirement and abs(self.bin_accuracy(self.nmos_width, bin[0])) <= 1: valid_nmos.append(bin) valid_nmos.sort(key = operator.itemgetter(1)) for bin in valid_pmos: if bin[0]/bin[1] < pmos_height_available: self.pmos_width = bin[0]/bin[1] - pmos_mults = valid_pmos[0][1] + pmos_mults = bin[1] break for bin in valid_nmos: if bin[0]/bin[1] < nmos_height_available: self.nmos_width = bin[0]/bin[1] - nmos_mults = valid_pmos[0][1] + nmos_mults = bin[1] break self.tx_mults = max(pmos_mults, nmos_mults) - + debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("pmos", self.pmos_width, pmos_mults, self.pmos_width * pmos_mults, self.pmos_size * drc("minwidth_tx"))) + debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("nmos", self.nmos_width, nmos_mults, self.nmos_width * nmos_mults, self.nmos_size * drc("minwidth_tx"))) + pinv.bin_count += 1 + pinv.bin_error += abs((self.pmos_width * pmos_mults) - (self.pmos_size * drc("minwidth_tx"))/(self.pmos_size * drc("minwidth_tx"))) + pinv.bin_count += 1 + pinv.bin_error += abs((self.nmos_width * nmos_mults) - (self.nmos_size * drc("minwidth_tx"))/(self.nmos_size * drc("minwidth_tx"))) + debug.info(2, "pinv bin count: {0} pinv bin error: {1} percent error {2}".format(pinv.bin_count, pinv.bin_error, pinv.bin_error/pinv.bin_count)) + def add_ptx(self): """ Create the PMOS and NMOS transistors. """ self.nmos = factory.create(module_type="ptx", From 59562f2b92563ab718228a629854ede31523e0fe Mon Sep 17 00:00:00 2001 From: jcirimel Date: Thu, 25 Jun 2020 06:44:07 -0700 Subject: [PATCH 449/521] move accuracy_requirement from techfile to config --- compiler/options.py | 2 +- compiler/pgates/pgate.py | 4 ++-- compiler/pgates/pinv.py | 6 +++--- compiler/pgates/pinv_dec.py | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/compiler/options.py b/compiler/options.py index 976595ad..d229b96e 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -58,7 +58,7 @@ class options(optparse.Values): delay_chain_stages = 9 delay_chain_fanout_per_stage = 4 - + accuracy_requirement = 0.75 ################### # Debug options. diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 80a568fc..7f834fc4 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -15,7 +15,7 @@ from vector import vector from globals import OPTS if(OPTS.tech_name == "sky130"): - from tech import nmos_bins, pmos_bins, accuracy_requirement + from tech import nmos_bins, pmos_bins class pgate(design.design): @@ -372,7 +372,7 @@ class pgate(design.design): select = -1 for i in reversed(range(0, len(scaled_bins))): - if abs(target_width - scaled_bins[i])/target_width <= 1-accuracy_requirement: + if abs(target_width - scaled_bins[i])/target_width <= 1-OPTS.accuracy_requirement: select = i break if select == -1: diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 1429e0c8..8b512e72 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -20,7 +20,7 @@ from sram_factory import factory from errors import drc_error if(OPTS.tech_name == "sky130"): - from tech import nmos_bins, pmos_bins, accuracy_requirement + from tech import nmos_bins, pmos_bins class pinv(pgate.pgate): @@ -169,13 +169,13 @@ class pinv(pgate.pgate): valid_pmos = [] for bin in pmos_bins: - if abs(self.bin_accuracy(self.pmos_width, bin[0])) > accuracy_requirement and abs(self.bin_accuracy(self.pmos_width, bin[0])) <= 1: + if abs(self.bin_accuracy(self.pmos_width, bin[0])) > OPTS.accuracy_requirement and abs(self.bin_accuracy(self.pmos_width, bin[0])) <= 1: valid_pmos.append(bin) valid_pmos.sort(key = operator.itemgetter(1)) valid_nmos = [] for bin in nmos_bins: - if abs(self.bin_accuracy(self.nmos_width, bin[0])) > accuracy_requirement and abs(self.bin_accuracy(self.nmos_width, bin[0])) <= 1: + if abs(self.bin_accuracy(self.nmos_width, bin[0])) > OPTS.accuracy_requirement and abs(self.bin_accuracy(self.nmos_width, bin[0])) <= 1: valid_nmos.append(bin) valid_nmos.sort(key = operator.itemgetter(1)) diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py index 3960f1bf..3ce6ad80 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/pgates/pinv_dec.py @@ -14,7 +14,7 @@ from globals import OPTS from sram_factory import factory if(OPTS.tech_name == "sky130"): - from tech import nmos_bins, pmos_bins, accuracy_requirement + from tech import nmos_bins, pmos_bins class pinv_dec(pinv.pinv): From 5941e01b515b11a8b43168ea84989b4f40a7126a Mon Sep 17 00:00:00 2001 From: jcirimel Date: Thu, 25 Jun 2020 08:02:08 -0700 Subject: [PATCH 450/521] add missing parens --- compiler/pgates/pinv.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 8b512e72..aa0f7d9a 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -195,9 +195,9 @@ class pinv(pgate.pgate): debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("pmos", self.pmos_width, pmos_mults, self.pmos_width * pmos_mults, self.pmos_size * drc("minwidth_tx"))) debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("nmos", self.nmos_width, nmos_mults, self.nmos_width * nmos_mults, self.nmos_size * drc("minwidth_tx"))) pinv.bin_count += 1 - pinv.bin_error += abs((self.pmos_width * pmos_mults) - (self.pmos_size * drc("minwidth_tx"))/(self.pmos_size * drc("minwidth_tx"))) + pinv.bin_error += abs(((self.pmos_width * pmos_mults) - (self.pmos_size * drc("minwidth_tx")))/(self.pmos_size * drc("minwidth_tx"))) pinv.bin_count += 1 - pinv.bin_error += abs((self.nmos_width * nmos_mults) - (self.nmos_size * drc("minwidth_tx"))/(self.nmos_size * drc("minwidth_tx"))) + pinv.bin_error += abs(((self.nmos_width * nmos_mults) - (self.nmos_size * drc("minwidth_tx")))/(self.nmos_size * drc("minwidth_tx"))) debug.info(2, "pinv bin count: {0} pinv bin error: {1} percent error {2}".format(pinv.bin_count, pinv.bin_error, pinv.bin_error/pinv.bin_count)) def add_ptx(self): From f84ee04fa9e000da364024f557a757a9e947e8d6 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Jun 2020 14:03:59 -0700 Subject: [PATCH 451/521] Single bank passing. Parameterized gate column mux of dff height. End-cap only supply option instead of no vdd in bitcell. --- compiler/modules/bank.py | 14 ++++--- compiler/modules/bitcell_base_array.py | 16 ++++---- compiler/modules/hierarchical_decoder.py | 6 +-- compiler/modules/hierarchical_predecode.py | 44 +++++++++++----------- compiler/modules/replica_bitcell_array.py | 19 ++++++---- compiler/modules/replica_column.py | 13 +++++-- 6 files changed, 61 insertions(+), 51 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 12fcb6dd..6134b143 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -497,18 +497,20 @@ class bank(design.design): Create a 2:4 or 3:8 column address decoder. """ - # Height is a multiple of DFF so that it can be staggered - # and rows do not align with the control logic module - self.dff = factory.create(module_type="dff") + self.dff =factory.create(module_type="dff") if self.col_addr_size == 0: return elif self.col_addr_size == 1: - self.column_decoder = factory.create(module_type="pinvbuf", height=self.dff.height) + self.column_decoder = factory.create(module_type="pinvbuf", + height=self.dff.height) elif self.col_addr_size == 2: - self.column_decoder = factory.create(module_type="hierarchical_predecode2x4", height=self.dff.height) + self.column_decoder = factory.create(module_type="hierarchical_predecode2x4", + height=self.dff.height) + elif self.col_addr_size == 3: - self.column_decoder = factory.create(module_type="hierarchical_predecode3x8", height=self.dff.height) + self.column_decoder = factory.create(module_type="hierarchical_predecode3x8", + height=self.dff.height) else: # No error checking before? debug.error("Invalid column decoder?", -1) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index e601208b..6698df33 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -110,17 +110,17 @@ class bitcell_base_array(design.design): # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. try: - bitcell_no_vdd_pin = cell_properties.bitcell.no_vdd_via + end_caps_enabled = cell_properties.bitcell.end_caps except AttributeError: - bitcell_no_vdd_pin = False + end_caps_enabled = False # Add vdd/gnd via stacks - for row in range(self.row_size): - for col in range(self.column_size): - inst = self.cell_inst[row,col] - for pin_name in ["vdd", "gnd"]: - for pin in inst.get_pins(pin_name): - if not (pin_name == "vdd" and bitcell_no_vdd_pin): + if not end_caps_enabled: + for row in range(self.row_size): + for col in range(self.column_size): + inst = self.cell_inst[row, col] + for pin_name in ["vdd", "gnd"]: + for pin in inst.get_pins(pin_name): self.add_power_pin(name=pin_name, loc=pin.center(), directions=bitcell_power_pin_directions, diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 3233bdc8..141387b4 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -78,12 +78,10 @@ class hierarchical_decoder(design.design): def add_decoders(self): """ Create the decoders based on the number of pre-decodes """ - self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4", - height=self.cell_height) + self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4") self.add_mod(self.pre2_4) - self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8", - height=self.cell_height) + self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8") self.add_mod(self.pre3_8) def determine_predecodes(self, num_inputs): diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index f2274c6e..d4cb51ce 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -20,12 +20,17 @@ class hierarchical_predecode(design.design): def __init__(self, name, input_number, height=None): self.number_of_inputs = input_number + b = factory.create(module_type="bitcell") if not height: - b = factory.create(module_type="bitcell") self.cell_height = b.height - else: + self.column_decoder = False + elif height != b.height: self.cell_height = height - + self.column_decoder = True + else: + self.cell_height = b.height + self.column_decoder = False + self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) design.design.__init__(self, name) @@ -40,21 +45,21 @@ class hierarchical_predecode(design.design): def add_modules(self): """ Add the INV and AND gate modules """ - if self.number_of_inputs == 2: - self.and_mod = factory.create(module_type="and2_dec", - height=self.cell_height) - elif self.number_of_inputs == 3: - self.and_mod = factory.create(module_type="and3_dec", - height=self.cell_height) - elif self.number_of_inputs == 4: - self.and_mod = factory.create(module_type="and4_dec", - height=self.cell_height) + debug.check(self.number_of_inputs < 4, + "Invalid number of predecode inputs: {}".format(self.number_of_inputs)) + + if self.column_decoder: + and_type = "pand{}".format(self.number_of_inputs) + inv_type = "pinv" else: - debug.error("Invalid number of predecode inputs: {}".format(self.number_of_inputs), -1) + and_type = "and{}_dec".format(self.number_of_inputs) + inv_type = "inv_dec" + self.and_mod = factory.create(module_type=and_type, + height=self.cell_height) self.add_mod(self.and_mod) # This uses the pinv_dec parameterized cell - self.inv = factory.create(module_type="inv_dec", + self.inv = factory.create(module_type=inv_type, height=self.cell_height, size=1) self.add_mod(self.inv) @@ -80,7 +85,7 @@ class hierarchical_predecode(design.design): # Outputs from cells are on output layer if OPTS.tech_name == "sky130": self.bus_layer = "m1" - self.bus_directions = None + self.bus_directions = "nonpref" self.bus_pitch = self.m1_pitch self.bus_space = 1.5 * self.m1_space self.input_layer = "m2" @@ -88,7 +93,7 @@ class hierarchical_predecode(design.design): self.output_layer_pitch = self.li_pitch else: self.bus_layer = "m2" - self.bus_directions = None + self.bus_directions = "pref" self.bus_pitch = self.m2_pitch self.bus_space = self.m2_space # This requires a special jog to ensure to conflicts with the output layers @@ -238,10 +243,7 @@ class hierarchical_predecode(design.design): # add output so that it is just below the vdd or gnd rail # since this is where the p/n devices are and there are no # pins in the and gates. - if OPTS.tech_name == "sky130": - inv_out_pos = inv_out_pin.lr() - else: - inv_out_pos = inv_out_pin.rc() + inv_out_pos = inv_out_pin.rc() y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0) rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset) @@ -309,7 +311,7 @@ class hierarchical_predecode(design.design): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ # In sky130, we use hand-made decoder cells with vertical power - if OPTS.tech_name == "sky130": + if not self.column_decoder: for n in ["vdd", "gnd"]: # This makes a wire from top to bottom for both inv and and gates for i in [self.inv_inst, self.and_inst]: diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 05cb1ac6..57bb3cf9 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -380,19 +380,22 @@ class replica_bitcell_array(design.design): # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. try: - bitcell_no_vdd_pin = cell_properties.bitcell.no_vdd_via + if cell_properties.bitcell.end_caps_enabled: + supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst, + self.dummy_row_top_inst, self.dummy_row_bot_inst] + list(self.replica_col_inst.values()) + else: + supply_insts = self.insts except AttributeError: - bitcell_no_vdd_pin = False + supply_insts = self.insts for pin_name in ["vdd", "gnd"]: - for inst in self.insts: + for inst in supply_insts: pin_list = inst.get_pins(pin_name) for pin in pin_list: - if not (pin_name == "vdd" and bitcell_no_vdd_pin): - self.add_power_pin(name=pin_name, - loc=pin.center(), - directions=("V", "V"), - start_layer=pin.layer) + self.add_power_pin(name=pin_name, + loc=pin.center(), + directions=("V", "V"), + start_layer=pin.layer) def get_rbl_wl_name(self, port): """ Return the WL for the given RBL port """ diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 3a58668c..58d35e7f 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -183,11 +183,16 @@ class replica_column(design.design): width=self.width, height=wl_pin.height()) - # For every second row and column, add a via for gnd and vdd - for row in range(row_range_min, row_range_max): - inst = self.cell_inst[row] + # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. + if end_caps_enabled: + supply_insts = [self.cell_inst[0], self.cell_inst[self.total_size - 1]] + else: + supply_insts = self.cell_inst.values() + + for inst in supply_insts: for pin_name in ["vdd", "gnd"]: - self.copy_layout_pin(inst, pin_name) + if pin_name in inst.mod.pins: + self.copy_layout_pin(inst, pin_name) def get_bitcell_pins(self, col, row): """ Creates a list of connections in the bitcell, From 66df659ad464352d1305ce7014aa66ce38c514c9 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Jun 2020 14:25:48 -0700 Subject: [PATCH 452/521] Col decoders are anything not bitcell pitch. --- compiler/modules/hierarchical_decoder.py | 6 ++++-- compiler/modules/hierarchical_predecode.py | 11 +++++------ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 141387b4..3233bdc8 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -78,10 +78,12 @@ class hierarchical_decoder(design.design): def add_decoders(self): """ Create the decoders based on the number of pre-decodes """ - self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4") + self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4", + height=self.cell_height) self.add_mod(self.pre2_4) - self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8") + self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8", + height=self.cell_height) self.add_mod(self.pre3_8) def determine_predecodes(self, num_inputs): diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index d4cb51ce..a89f5fa6 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -24,12 +24,11 @@ class hierarchical_predecode(design.design): if not height: self.cell_height = b.height self.column_decoder = False - elif height != b.height: - self.cell_height = height - self.column_decoder = True else: - self.cell_height = b.height - self.column_decoder = False + self.cell_height = height + # If we are pitch matched to the bitcell, it's a predecoder + # otherwise it's a column decoder (out of pgates) + self.column_decoder = (height != b.height) self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) design.design.__init__(self, name) @@ -311,7 +310,7 @@ class hierarchical_predecode(design.design): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ # In sky130, we use hand-made decoder cells with vertical power - if not self.column_decoder: + if OPTS.tech_name == "sky130" and not self.column_decoder: for n in ["vdd", "gnd"]: # This makes a wire from top to bottom for both inv and and gates for i in [self.inv_inst, self.and_inst]: From 7220b23402c396e6a6cca74757ec056349c359fd Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Jun 2020 15:34:18 -0700 Subject: [PATCH 453/521] Add riscv unit tests --- compiler/sram/sram_1bank.py | 11 +++-- compiler/tests/50_riscv_func_test.py | 65 ++++++++++++++++++++++++++++ compiler/tests/50_riscv_phys_test.py | 59 +++++++++++++++++++++++++ 3 files changed, 131 insertions(+), 4 deletions(-) create mode 100755 compiler/tests/50_riscv_func_test.py create mode 100755 compiler/tests/50_riscv_phys_test.py diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index bb8c0a7d..7d2ccfa8 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -165,7 +165,7 @@ class sram_1bank(sram_base): # The row address bits are placed above the control logic aligned on the right. x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width # It is above the control logic but below the top of the bitcell array - y_offset = max(self.control_logic_insts[port].uy(), self.bank_inst.uy() - self.row_addr_dff_insts[port].height) + y_offset = max(self.control_logic_insts[port].uy(), self.control_logic_insts[port].uy() + self.dff.height) row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port]) @@ -238,7 +238,7 @@ class sram_1bank(sram_base): # The row address bits are placed above the control logic aligned on the left. x_offset = control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width # It is below the control logic but below the bottom of the bitcell array - y_offset = min(self.control_logic_insts[port].by(), self.bank_inst.by() + self.row_addr_dff_insts[port].height) + y_offset = min(self.control_logic_insts[port].by(), self.control_logic_insts[port].by() - self.dff.height) row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY") @@ -485,11 +485,14 @@ class sram_1bank(sram_base): flop_pos = flop_pin.center() bank_pos = bank_pin.center() mid_pos = vector(bank_pos.x, flop_pos.y) - self.add_wire(self.m2_stack[::-1], - [flop_pos, mid_pos, bank_pos]) self.add_via_stack_center(from_layer=flop_pin.layer, to_layer="m3", offset=flop_pos) + self.add_path("m3", [flop_pos, mid_pos]) + self.add_via_stack_center(from_layer=bank_pin.layer, + to_layer="m3", + offset=mid_pos) + self.add_path(bank_pin.layer, [mid_pos, bank_pos]) def route_col_addr_dff(self): """ Connect the output of the col flops to the bank pins """ diff --git a/compiler/tests/50_riscv_func_test.py b/compiler/tests/50_riscv_func_test.py new file mode 100755 index 00000000..38756496 --- /dev/null +++ b/compiler/tests/50_riscv_func_test.py @@ -0,0 +1,65 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test") +class psram_1bank_nomux_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 1 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional, delay + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=256, + num_banks=1) + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + tempspice = OPTS.openram_temp + "sram.sp" + s.sp_write(tempspice) + + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, tempspice, corner) + (fail, error) = f.run() + self.assertTrue(fail,error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_phys_test.py b/compiler/tests/50_riscv_phys_test.py new file mode 100755 index 00000000..2d759c35 --- /dev/null +++ b/compiler/tests/50_riscv_phys_test.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test") +class psram_1bank_nomux_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + OPTS.route_supplies=False + OPTS.perimeter_pins=False + + c = sram_config(word_size=32, + write_size=8, + num_words=256, + num_banks=1) + + c.words_per_row=2 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From f11afaa63d057f43a2e24d9cc944c3a954a34ca8 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Jun 2020 17:30:03 -0700 Subject: [PATCH 454/521] Refactor channel route to be a design. --- compiler/base/channel_route.py | 306 ++++++++++++++++++++++++++++++ compiler/base/hierarchy_layout.py | 277 +-------------------------- 2 files changed, 315 insertions(+), 268 deletions(-) create mode 100644 compiler/base/channel_route.py diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py new file mode 100644 index 00000000..7fe1a005 --- /dev/null +++ b/compiler/base/channel_route.py @@ -0,0 +1,306 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import collections +import debug +from tech import drc +from vector import vector +import design + + +class channel_route(design.design): + + unique_id = 0 + + def __init__(self, + netlist, + offset, + layer_stack, + directions=None, + vertical=False, + add_routes=True): + """ + The net list is a list of the nets with each net being a list of pins + to be connected. The offset is the lower-left of where the + routing channel will start. This does NOT try to minimize the + number of tracks -- instead, it picks an order to avoid the + vertical conflicts between pins. The track size must be the number of + nets times the *nonpreferred* routing of the non-track layer pitch. + + """ + name = "cr_{0}".format(channel_route.unique_id) + channel_route.unique_id += 1 + design.design.__init__(self, name) + + self.netlist = netlist + self.offset = offset + self.layer_stack = layer_stack + self.directions = directions + self.vertical = vertical + self.add_routes = add_routes + + if not directions or directions == "pref": + # Use the preferred layer directions + if self.get_preferred_direction(layer_stack[0]) == "V": + self.vertical_layer = layer_stack[0] + self.horizontal_layer = layer_stack[2] + else: + self.vertical_layer = layer_stack[2] + self.horizontal_layer = layer_stack[0] + elif directions == "nonpref": + # Use the preferred layer directions + if self.get_preferred_direction(layer_stack[0]) == "V": + self.vertical_layer = layer_stack[2] + self.horizontal_layer = layer_stack[0] + else: + self.vertical_layer = layer_stack[0] + self.horizontal_layer = layer_stack[2] + else: + # Use the layer directions specified to the router rather than + # the preferred directions + debug.check(directions[0] != directions[1], "Must have unique layer directions.") + if directions[0] == "V": + self.vertical_layer = layer_stack[0] + self.horizontal_layer = layer_stack[2] + else: + self.horizontal_layer = layer_stack[0] + self.vertical_layer = layer_stack[2] + + layer_stuff = self.get_layer_pitch(self.vertical_layer) + (self.vertical_nonpref_pitch, self.vertical_pitch, self.vertical_width, self.vertical_space) = layer_stuff + + layer_stuff = self.get_layer_pitch(self.horizontal_layer) + (self.horizontal_nonpref_pitch, self.horizontal_pitch, self.horizontal_width, self.horizontal_space) = layer_stuff + + self.route() + + def remove_net_from_graph(self, pin, g): + """ + Remove the pin from the graph and all conflicts + """ + g.pop(pin, None) + + # Remove the pin from all conflicts + # FIXME: This is O(n^2), so maybe optimize it. + for other_pin, conflicts in g.items(): + if pin in conflicts: + conflicts.remove(pin) + g[other_pin]=conflicts + return g + + def vcg_nets_overlap(self, net1, net2): + """ + Check all the pin pairs on two nets and return a pin + overlap if any pin overlaps. + """ + + if self.vertical: + pitch = self.horizontal_nonpref_pitch + else: + pitch = self.vertical_nonpref_pitch + + for pin1 in net1: + for pin2 in net2: + if self.vcg_pin_overlap(pin1, pin2, pitch): + return True + + return False + + def route(self): + # FIXME: Must extend this to a horizontal conflict graph + # too if we want to minimize the + # number of tracks! + # hcg = {} + + # Initialize the vertical conflict graph (vcg) + # and make a list of all pins + vcg = collections.OrderedDict() + + # Create names for the nets for the graphs + nets = collections.OrderedDict() + index = 0 + # print(netlist) + for pin_list in self.netlist: + net_name = "n{}".format(index) + index += 1 + nets[net_name] = pin_list + + # print("Nets:") + # for net_name in nets: + # print(net_name, [x.name for x in nets[net_name]]) + + # Find the vertical pin conflicts + # FIXME: O(n^2) but who cares for now + for net_name1 in nets: + if net_name1 not in vcg.keys(): + vcg[net_name1] = [] + for net_name2 in nets: + if net_name2 not in vcg.keys(): + vcg[net_name2] = [] + # Skip yourself + if net_name1 == net_name2: + continue + if self.vcg_nets_overlap(nets[net_name1], + nets[net_name2]): + vcg[net_name2].append(net_name1) + + current_offset = self.offset + + # list of routes to do + while vcg: + # from pprint import pformat + # print("VCG:\n", pformat(vcg)) + # get a route from conflict graph with empty fanout set + net_name = None + for net_name, conflicts in vcg.items(): + if len(conflicts) == 0: + vcg = self.remove_net_from_graph(net_name, vcg) + break + else: + # FIXME: We don't support cyclic VCGs right now. + debug.error("Cyclic VCG in channel router.", -1) + + # These are the pins we'll have to connect + pin_list = nets[net_name] + # print("Routing:", net_name, [x.name for x in pin_list]) + + # Remove the net from other constriants in the VCG + vcg = self.remove_net_from_graph(net_name, vcg) + + # Add the trunk routes from the bottom up for + # horizontal or the left to right for vertical + if self.vertical: + if self.add_routes: + self.add_vertical_trunk_route(pin_list, + current_offset, + self.vertical_nonpref_pitch) + # This accounts for the via-to-via spacings + current_offset += vector(self.horizontal_nonpref_pitch, 0) + else: + if self.add_routes: + self.add_horizontal_trunk_route(pin_list, + current_offset, + self.horizontal_nonpref_pitch) + # This accounts for the via-to-via spacings + current_offset += vector(0, self.vertical_nonpref_pitch) + + # Return the size of the channel + if self.vertical: + self.width = 0 + self.height = current_offset.y + return current_offset.y + self.vertical_nonpref_pitch - self.offset.y + else: + self.width = current_offset.x + self.height = 0 + return current_offset.x + self.horizontal_nonpref_pitch - self.offset.x + + def get_layer_pitch(self, layer): + """ Return the track pitch on a given layer """ + try: + # FIXME: Using non-pref pitch here due to overlap bug in VCG constraints. + # It should just result in inefficient channel width but will work. + pitch = getattr(self, "{}_pitch".format(layer)) + nonpref_pitch = getattr(self, "{}_nonpref_pitch".format(layer)) + space = getattr(self, "{}_space".format(layer)) + except AttributeError: + debug.error("Cannot find layer pitch.", -1) + return (nonpref_pitch, pitch, pitch - space, space) + + def add_horizontal_trunk_route(self, + pins, + trunk_offset, + pitch): + """ + Create a trunk route for all pins with + the trunk located at the given y offset. + """ + max_x = max([pin.center().x for pin in pins]) + min_x = min([pin.center().x for pin in pins]) + + # if we are less than a pitch, just create a non-preferred layer jog + if max_x - min_x <= pitch: + half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)] + + # Add the horizontal trunk on the vertical layer! + self.add_path(self.vertical_layer, + [vector(min_x - half_layer_width, trunk_offset.y), + vector(max_x + half_layer_width, trunk_offset.y)]) + + # Route each pin to the trunk + for pin in pins: + # No bend needed here + mid = vector(pin.center().x, trunk_offset.y) + self.add_path(self.vertical_layer, [pin.center(), mid]) + else: + # Add the horizontal trunk + self.add_path(self.horizontal_layer, + [vector(min_x, trunk_offset.y), + vector(max_x, trunk_offset.y)]) + + # Route each pin to the trunk + for pin in pins: + mid = vector(pin.center().x, trunk_offset.y) + self.add_path(self.vertical_layer, [pin.center(), mid]) + self.add_via_center(layers=self.layer_stack, + offset=mid, + directions=self.directions) + + def add_vertical_trunk_route(self, + pins, + trunk_offset, + pitch): + """ + Create a trunk route for all pins with the + trunk located at the given x offset. + """ + max_y = max([pin.center().y for pin in pins]) + min_y = min([pin.center().y for pin in pins]) + + # if we are less than a pitch, just create a non-preferred layer jog + if max_y - min_y <= pitch: + + half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)] + + # Add the vertical trunk on the horizontal layer! + self.add_path(self.horizontal_layer, + [vector(trunk_offset.x, min_y - half_layer_width), + vector(trunk_offset.x, max_y + half_layer_width)]) + + # Route each pin to the trunk + for pin in pins: + # No bend needed here + mid = vector(trunk_offset.x, pin.center().y) + self.add_path(self.horizontal_layer, [pin.center(), mid]) + else: + # Add the vertical trunk + self.add_path(self.vertical_layer, + [vector(trunk_offset.x, min_y), + vector(trunk_offset.x, max_y)]) + + # Route each pin to the trunk + for pin in pins: + mid = vector(trunk_offset.x, pin.center().y) + self.add_path(self.horizontal_layer, [pin.center(), mid]) + self.add_via_center(layers=self.layer_stack, + offset=mid, + directions=self.directions) + + def vcg_pin_overlap(self, pin1, pin2, pitch): + """ Check for vertical or horizontal overlap of the two pins """ + + # FIXME: If the pins are not in a row, this may break. + # However, a top pin shouldn't overlap another top pin, + # for example, so the extra comparison *shouldn't* matter. + + # Pin 1 must be in the "BOTTOM" set + x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x - pin2.center().x) < pitch + + # Pin 1 must be in the "LEFT" set + y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y - pin2.center().y) < pitch + overlaps = (not self.vertical and x_overlap) or (self.vertical and y_overlap) + return overlaps + diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index f90b3129..8720470b 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -5,7 +5,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import collections import geometry import gdsMill import debug @@ -1019,282 +1018,24 @@ class layout(): to_layer=dest_pin.layer, offset=out_pos) - def get_layer_pitch(self, layer): - """ Return the track pitch on a given layer """ - try: - # FIXME: Using non-pref pitch here due to overlap bug in VCG constraints. - # It should just result in inefficient channel width but will work. - pitch = getattr(self, "{}_pitch".format(layer)) - nonpref_pitch = getattr(self, "{}_nonpref_pitch".format(layer)) - space = getattr(self, "{}_space".format(layer)) - except AttributeError: - debug.error("Cannot find layer pitch.", -1) - return (nonpref_pitch, pitch, pitch - space, space) - - def add_horizontal_trunk_route(self, - pins, - trunk_offset, - layer_stack, - pitch): - """ - Create a trunk route for all pins with - the trunk located at the given y offset. - """ - max_x = max([pin.center().x for pin in pins]) - min_x = min([pin.center().x for pin in pins]) - - # if we are less than a pitch, just create a non-preferred layer jog - if max_x - min_x <= pitch: - half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)] - - # Add the horizontal trunk on the vertical layer! - self.add_path(self.vertical_layer, - [vector(min_x - half_layer_width, trunk_offset.y), - vector(max_x + half_layer_width, trunk_offset.y)]) - - # Route each pin to the trunk - for pin in pins: - # No bend needed here - mid = vector(pin.center().x, trunk_offset.y) - self.add_path(self.vertical_layer, [pin.center(), mid]) - else: - # Add the horizontal trunk - self.add_path(self.horizontal_layer, - [vector(min_x, trunk_offset.y), - vector(max_x, trunk_offset.y)]) - - # Route each pin to the trunk - for pin in pins: - mid = vector(pin.center().x, trunk_offset.y) - self.add_path(self.vertical_layer, [pin.center(), mid]) - self.add_via_center(layers=layer_stack, - offset=mid, - directions=self.directions) - - def add_vertical_trunk_route(self, - pins, - trunk_offset, - layer_stack, - pitch): - """ - Create a trunk route for all pins with the - trunk located at the given x offset. - """ - max_y = max([pin.center().y for pin in pins]) - min_y = min([pin.center().y for pin in pins]) - - # if we are less than a pitch, just create a non-preferred layer jog - if max_y - min_y <= pitch: - - half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)] - - # Add the vertical trunk on the horizontal layer! - self.add_path(self.horizontal_layer, - [vector(trunk_offset.x, min_y - half_layer_width), - vector(trunk_offset.x, max_y + half_layer_width)]) - - # Route each pin to the trunk - for pin in pins: - # No bend needed here - mid = vector(trunk_offset.x, pin.center().y) - self.add_path(self.horizontal_layer, [pin.center(), mid]) - else: - # Add the vertical trunk - self.add_path(self.vertical_layer, - [vector(trunk_offset.x, min_y), - vector(trunk_offset.x, max_y)]) - - # Route each pin to the trunk - for pin in pins: - mid = vector(trunk_offset.x, pin.center().y) - self.add_path(self.horizontal_layer, [pin.center(), mid]) - self.add_via_center(layers=layer_stack, - offset=mid, - directions=self.directions) - - def create_channel_route(self, netlist, - offset, - layer_stack, - directions=None, - vertical=False): - """ - The net list is a list of the nets with each net being a list of pins - to be connected. The offset is the lower-left of where the - routing channel will start. This does NOT try to minimize the - number of tracks -- instead, it picks an order to avoid the - vertical conflicts between pins. The track size must be the number of - nets times the *nonpreferred* routing of the non-track layer pitch. - - """ - def remove_net_from_graph(pin, g): - """ - Remove the pin from the graph and all conflicts - """ - g.pop(pin, None) - - # Remove the pin from all conflicts - # FIXME: This is O(n^2), so maybe optimize it. - for other_pin, conflicts in g.items(): - if pin in conflicts: - conflicts.remove(pin) - g[other_pin]=conflicts - return g - - def vcg_nets_overlap(net1, net2, vertical): - """ - Check all the pin pairs on two nets and return a pin - overlap if any pin overlaps. - """ - - if vertical: - pitch = self.horizontal_nonpref_pitch - else: - pitch = self.vertical_nonpref_pitch - - for pin1 in net1: - for pin2 in net2: - if vcg_pin_overlap(pin1, pin2, vertical, pitch): - return True - - return False - - def vcg_pin_overlap(pin1, pin2, vertical, pitch): - """ Check for vertical or horizontal overlap of the two pins """ - - # FIXME: If the pins are not in a row, this may break. - # However, a top pin shouldn't overlap another top pin, - # for example, so the extra comparison *shouldn't* matter. - - # Pin 1 must be in the "BOTTOM" set - x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x - pin2.center().x) < pitch - - # Pin 1 must be in the "LEFT" set - y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y - pin2.center().y) < pitch - overlaps = (not vertical and x_overlap) or (vertical and y_overlap) - return overlaps - - self.directions = directions - if not directions or directions == "pref": - # Use the preferred layer directions - if self.get_preferred_direction(layer_stack[0]) == "V": - self.vertical_layer = layer_stack[0] - self.horizontal_layer = layer_stack[2] - else: - self.vertical_layer = layer_stack[2] - self.horizontal_layer = layer_stack[0] - elif directions == "nonpref": - # Use the preferred layer directions - if self.get_preferred_direction(layer_stack[0]) == "V": - self.vertical_layer = layer_stack[2] - self.horizontal_layer = layer_stack[0] - else: - self.vertical_layer = layer_stack[0] - self.horizontal_layer = layer_stack[2] - else: - # Use the layer directions specified to the router rather than - # the preferred directions - debug.check(directions[0] != directions[1], "Must have unique layer directions.") - if directions[0] == "V": - self.vertical_layer = layer_stack[0] - self.horizontal_layer = layer_stack[2] - else: - self.horizontal_layer = layer_stack[0] - self.vertical_layer = layer_stack[2] - - layer_stuff = self.get_layer_pitch(self.vertical_layer) - (self.vertical_nonpref_pitch, self.vertical_pitch, self.vertical_width, self.vertical_space) = layer_stuff - - layer_stuff = self.get_layer_pitch(self.horizontal_layer) - (self.horizontal_nonpref_pitch, self.horizontal_pitch, self.horizontal_width, self.horizontal_space) = layer_stuff - - # FIXME: Must extend this to a horizontal conflict graph - # too if we want to minimize the - # number of tracks! - # hcg = {} - - # Initialize the vertical conflict graph (vcg) - # and make a list of all pins - vcg = collections.OrderedDict() - - # Create names for the nets for the graphs - nets = collections.OrderedDict() - index = 0 - # print(netlist) - for pin_list in netlist: - net_name = "n{}".format(index) - index += 1 - nets[net_name] = pin_list - - # print("Nets:") - # for net_name in nets: - # print(net_name, [x.name for x in nets[net_name]]) - - # Find the vertical pin conflicts - # FIXME: O(n^2) but who cares for now - for net_name1 in nets: - if net_name1 not in vcg.keys(): - vcg[net_name1] = [] - for net_name2 in nets: - if net_name2 not in vcg.keys(): - vcg[net_name2] = [] - # Skip yourself - if net_name1 == net_name2: - continue - if vcg_nets_overlap(nets[net_name1], - nets[net_name2], - vertical): - vcg[net_name2].append(net_name1) - - # list of routes to do - while vcg: - # from pprint import pformat - # print("VCG:\n", pformat(vcg)) - # get a route from conflict graph with empty fanout set - net_name = None - for net_name, conflicts in vcg.items(): - if len(conflicts) == 0: - vcg = remove_net_from_graph(net_name, vcg) - break - else: - # FIXME: We don't support cyclic VCGs right now. - debug.error("Cyclic VCG in channel router.", -1) - - # These are the pins we'll have to connect - pin_list = nets[net_name] - # print("Routing:", net_name, [x.name for x in pin_list]) - - # Remove the net from other constriants in the VCG - vcg = remove_net_from_graph(net_name, vcg) - - # Add the trunk routes from the bottom up for - # horizontal or the left to right for vertical - if vertical: - self.add_vertical_trunk_route(pin_list, - offset, - layer_stack, - self.vertical_nonpref_pitch) - # This accounts for the via-to-via spacings - offset += vector(self.horizontal_nonpref_pitch, 0) - else: - self.add_horizontal_trunk_route(pin_list, - offset, - layer_stack, - self.horizontal_nonpref_pitch) - # This accounts for the via-to-via spacings - offset += vector(0, self.vertical_nonpref_pitch) - def create_vertical_channel_route(self, netlist, offset, layer_stack, directions=None): """ Wrapper to create a vertical channel route """ - self.create_channel_route(netlist, offset, layer_stack, directions, vertical=True) + import channel_route + cr = channel_route.channel_route(netlist, offset, layer_stack, directions, vertical=True) + self.add_inst("vc", cr) + self.connect_inst([]) def create_horizontal_channel_route(self, netlist, offset, layer_stack, directions=None): """ Wrapper to create a horizontal channel route """ - self.create_channel_route(netlist, offset, layer_stack, directions, vertical=False) - + import channel_route + cr = channel_route.channel_route(netlist, offset, layer_stack, directions, vertical=False) + self.add_inst("hc", cr) + self.connect_inst([]) + def add_boundary(self, ll=vector(0, 0), ur=None): """ Add boundary for debugging dimensions """ if OPTS.netlist_only: From 9eb1b500eaf79ec905b3ffef4f8e0038ab17347a Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Jun 2020 17:31:23 -0700 Subject: [PATCH 455/521] Skip phys riscv test --- compiler/tests/50_riscv_phys_test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/tests/50_riscv_phys_test.py b/compiler/tests/50_riscv_phys_test.py index 2d759c35..0ae11025 100755 --- a/compiler/tests/50_riscv_phys_test.py +++ b/compiler/tests/50_riscv_phys_test.py @@ -15,8 +15,8 @@ from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test") -class psram_1bank_nomux_func_test(openram_test): +@unittest.skip("SKIPPING 50_riscv_phys_test") +class riscv_phys_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) From 76e5389c3384a8221475b5fd5e04136b991d12a2 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Jun 2020 17:43:17 -0700 Subject: [PATCH 456/521] Change riscv func test name --- compiler/tests/50_riscv_func_test.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/compiler/tests/50_riscv_func_test.py b/compiler/tests/50_riscv_func_test.py index 38756496..bb4cd6b0 100755 --- a/compiler/tests/50_riscv_func_test.py +++ b/compiler/tests/50_riscv_func_test.py @@ -15,8 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test") -class psram_1bank_nomux_func_test(openram_test): +class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) From d53abba47946890d92a78c5b8f9762ffb7c5080e Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Jun 2020 17:43:44 -0700 Subject: [PATCH 457/521] Always route the channel route since it is it's own design. --- compiler/base/channel_route.py | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py index 7fe1a005..d6048376 100644 --- a/compiler/base/channel_route.py +++ b/compiler/base/channel_route.py @@ -21,8 +21,7 @@ class channel_route(design.design): offset, layer_stack, directions=None, - vertical=False, - add_routes=True): + vertical=False): """ The net list is a list of the nets with each net being a list of pins to be connected. The offset is the lower-left of where the @@ -41,7 +40,6 @@ class channel_route(design.design): self.layer_stack = layer_stack self.directions = directions self.vertical = vertical - self.add_routes = add_routes if not directions or directions == "pref": # Use the preferred layer directions @@ -174,17 +172,15 @@ class channel_route(design.design): # Add the trunk routes from the bottom up for # horizontal or the left to right for vertical if self.vertical: - if self.add_routes: - self.add_vertical_trunk_route(pin_list, - current_offset, - self.vertical_nonpref_pitch) + self.add_vertical_trunk_route(pin_list, + current_offset, + self.vertical_nonpref_pitch) # This accounts for the via-to-via spacings current_offset += vector(self.horizontal_nonpref_pitch, 0) else: - if self.add_routes: - self.add_horizontal_trunk_route(pin_list, - current_offset, - self.horizontal_nonpref_pitch) + self.add_horizontal_trunk_route(pin_list, + current_offset, + self.horizontal_nonpref_pitch) # This accounts for the via-to-via spacings current_offset += vector(0, self.vertical_nonpref_pitch) From af4ed3dd6edcf25db3a624da5a5d503bf3619f5e Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Jun 2020 06:50:45 -0700 Subject: [PATCH 458/521] Skip riscv func test for time sake --- compiler/tests/50_riscv_func_test.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/tests/50_riscv_func_test.py b/compiler/tests/50_riscv_func_test.py index bb4cd6b0..1d5720f7 100755 --- a/compiler/tests/50_riscv_func_test.py +++ b/compiler/tests/50_riscv_func_test.py @@ -15,6 +15,7 @@ from globals import OPTS from sram_factory import factory import debug +@unittest.skip("SKIPPING 50_riscv_func_test") class riscv_func_test(openram_test): def runTest(self): From 567675ab31ea4cbd54a0380cd72ba37b84b144a5 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Jun 2020 11:47:12 -0700 Subject: [PATCH 459/521] PEP8 cleanup --- compiler/base/hierarchy_design.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index ac3fb30b..1321f06a 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -31,6 +31,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): except AttributeError: lvs_subdir = "lvs_lib" lvs_dir = OPTS.openram_tech + lvs_subdir + "/" + if os.path.exists(lvs_dir): self.lvs_file = lvs_dir + name + ".sp" else: From e23d41c1d428179c21ff7eafd11c6feea4808f7f Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Jun 2020 11:47:35 -0700 Subject: [PATCH 460/521] PEP8 cleanup --- compiler/modules/sense_amp.py | 39 ++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index ff5638ba..35fbdf42 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -8,11 +8,12 @@ import design import debug import utils -from tech import GDS,layer, parameter,drc +from tech import GDS, layer, parameter, drc from tech import cell_properties as props from globals import OPTS import logical_effort + class sense_amp(design.design): """ This module implements the single sense amp cell used in the design. It @@ -28,10 +29,10 @@ class sense_amp(design.design): props.sense_amp.pin.gnd] type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] if not OPTS.netlist_only: - (width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"]) + (width, height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"]) pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"]) else: - (width, height) = (0,0) + (width, height) = (0, 0) pin_map = [] def get_bl_names(self): @@ -61,41 +62,41 @@ class sense_amp(design.design): # FIXME: This input load will be applied to both the s_en timing and bitline timing. - #Input load for the bitlines which are connected to the source/drain of a TX. Not the selects. - from tech import spice, parameter + # Input load for the bitlines which are connected to the source/drain of a TX. Not the selects. + from tech import spice # Default is 8x. Per Samira and Hodges-Jackson book: # "Column-mux transistors driven by the decoder must be sized for optimal speed" - bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file. - return spice["min_tx_drain_c"]*(bitline_pmos_size)#ff + bitline_pmos_size = 8 # FIXME: This should be set somewhere and referenced. Probably in tech file. + return spice["min_tx_drain_c"] * bitline_pmos_size # ff def get_stage_effort(self, load): - #Delay of the sense amp will depend on the size of the amp and the output load. + # Delay of the sense amp will depend on the size of the amp and the output load. parasitic_delay = 1 - cin = (parameter["sa_inv_pmos_size"] + parameter["sa_inv_nmos_size"])/drc("minwidth_tx") - sa_size = parameter["sa_inv_nmos_size"]/drc("minwidth_tx") + cin = (parameter["sa_inv_pmos_size"] + parameter["sa_inv_nmos_size"]) / drc("minwidth_tx") + sa_size = parameter["sa_inv_nmos_size"] / drc("minwidth_tx") cc_inv_cin = cin - return logical_effort.logical_effort('column_mux', sa_size, cin, load+cc_inv_cin, parasitic_delay, False) + return logical_effort.logical_effort('column_mux', sa_size, cin, load + cc_inv_cin, parasitic_delay, False) def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" - #Power in this module currently not defined. Returns 0 nW (leakage and dynamic). + # Power in this module currently not defined. Returns 0 nW (leakage and dynamic). total_power = self.return_power() return total_power def get_en_cin(self): """Get the relative capacitance of sense amp enable gate cin""" - pmos_cin = parameter["sa_en_pmos_size"]/drc("minwidth_tx") - nmos_cin = parameter["sa_en_nmos_size"]/drc("minwidth_tx") - #sen is connected to 2 pmos isolation TX and 1 nmos per sense amp. - return 2*pmos_cin + nmos_cin + pmos_cin = parameter["sa_en_pmos_size"] / drc("minwidth_tx") + nmos_cin = parameter["sa_en_nmos_size"] / drc("minwidth_tx") + # sen is connected to 2 pmos isolation TX and 1 nmos per sense amp. + return 2 * pmos_cin + nmos_cin def get_enable_name(self): """Returns name used for enable net""" - #FIXME: A better programmatic solution to designate pins + # FIXME: A better programmatic solution to designate pins enable_name = self.en_name debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name)) return enable_name - def build_graph(self, graph, inst_name, port_nets): + def build_graph(self, graph, inst_name, port_nets): """Adds edges based on inputs/outputs. Overrides base class function.""" - self.add_graph_edges(graph, port_nets) + self.add_graph_edges(graph, port_nets) From f57eeb88eb4af97bfb4a4f8aee46aba8f9fa533b Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Jun 2020 11:47:55 -0700 Subject: [PATCH 461/521] PEP8 cleanup, multiple vdd/gnd support --- compiler/modules/sense_amp_array.py | 38 +++++++++++++---------------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 46c30c9d..5d41b2a0 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -28,7 +28,7 @@ class sense_amp_array(design.design): self.add_comment("words_per_row: {0}".format(words_per_row)) self.word_size = word_size - self.words_per_row = words_per_row + self.words_per_row = words_per_row if not num_spare_cols: self.num_spare_cols = 0 else: @@ -77,7 +77,7 @@ class sense_amp_array(design.design): self.DRC_LVS() def add_pins(self): - for i in range(0,self.word_size + self.num_spare_cols): + for i in range(0, self.word_size + self.num_spare_cols): self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT") self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT") self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT") @@ -96,7 +96,7 @@ class sense_amp_array(design.design): def create_sense_amp_array(self): self.local_insts = [] - for i in range(0,self.word_size + self.num_spare_cols): + for i in range(0, self.word_size + self.num_spare_cols): name = "sa_d{0}".format(i) self.local_insts.append(self.add_inst(name=name, mod=self.amp)) @@ -107,14 +107,10 @@ class sense_amp_array(design.design): def place_sense_amp_array(self): from tech import cell_properties - if self.bitcell.width > self.amp.width: - amp_spacing = self.bitcell.width - else: - amp_spacing = self.amp.width for i in range(0, self.row_size, self.words_per_row): index = int(i / self.words_per_row) - xoffset = i * amp_spacing + xoffset = i * self.bitcell.width if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2: mirror = "MY" @@ -126,9 +122,9 @@ class sense_amp_array(design.design): self.local_insts[index].place(offset=amp_position, mirror=mirror) # place spare sense amps (will share the same enable as regular sense amps) - for i in range(0,self.num_spare_cols): + for i in range(0, self.num_spare_cols): index = self.word_size + i - xoffset = ((self.word_size * self.words_per_row) + i) * amp_spacing + xoffset = ((self.word_size * self.words_per_row) + i) * self.bitcell.width if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2: mirror = "MY" @@ -143,17 +139,17 @@ class sense_amp_array(design.design): for i in range(len(self.local_insts)): inst = self.local_insts[i] - gnd_pin = inst.get_pin("gnd") - self.add_power_pin(name="gnd", - loc=gnd_pin.center(), - start_layer=gnd_pin.layer, - directions=("V", "V")) - - vdd_pin = inst.get_pin("vdd") - self.add_power_pin(name="vdd", - loc=vdd_pin.center(), - start_layer=vdd_pin.layer, - directions=("V", "V")) + for gnd_pin in inst.get_pins("gnd"): + self.add_power_pin(name="gnd", + loc=gnd_pin.center(), + start_layer=gnd_pin.layer, + directions=("V", "V")) + + for vdd_pin in inst.get_pins("vdd"): + self.add_power_pin(name="vdd", + loc=vdd_pin.center(), + start_layer=vdd_pin.layer, + directions=("V", "V")) bl_pin = inst.get_pin(inst.mod.get_bl_names()) br_pin = inst.get_pin(inst.mod.get_br_names()) From 94d700071751973e2c9bb93d3ce266dc658e300f Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Jun 2020 12:16:54 -0700 Subject: [PATCH 462/521] Reduce output clutter from gds write --- compiler/base/hierarchy_layout.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 8720470b..2a29be6b 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -739,7 +739,7 @@ class layout(): width=width, height=height, center=False) - debug.info(2, "Adding {0} boundary {1}".format(self.name, boundary)) + debug.info(4, "Adding {0} boundary {1}".format(self.name, boundary)) self.visited.append(self.name) From c07e20cbe4d6f2cca60b7fc836fd493e0ce433fc Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Jun 2020 14:27:16 -0700 Subject: [PATCH 463/521] Move mux select from li to m2 in sky130 --- compiler/modules/single_level_column_mux_array.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index cc38cb45..37fd4dc1 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -33,8 +33,8 @@ class single_level_column_mux_array(design.design): self.column_offset = column_offset if "li" in layer: - self.col_mux_stack = self.li_stack - self.col_mux_stack_pitch = self.m1_pitch + self.col_mux_stack = self.m1_stack[::-1] + self.col_mux_stack_pitch = self.m2_pitch else: self.col_mux_stack = self.m1_stack self.col_mux_stack_pitch = self.m1_pitch @@ -155,7 +155,7 @@ class single_level_column_mux_array(design.design): self.route_bitlines() def add_horizontal_input_rail(self): - """ Create address input rails on M1 below the mux transistors """ + """ Create address input rails below the mux transistors """ for j in range(self.words_per_row): offset = vector(0, self.route_height + (j - self.words_per_row) * self.col_mux_stack_pitch) self.add_layout_pin(text="sel_{}".format(j), @@ -177,10 +177,10 @@ class single_level_column_mux_array(design.design): # use the y offset from the sel pin and the x offset from the gate offset = vector(gate_offset.x, self.get_pin("sel_{}".format(sel_index)).cy()) - # Add the poly contact with a shift to account for the rotation - self.add_via_center(layers=self.poly_stack, - offset=offset, - directions=self.via_directions) + self.add_via_stack_center(from_layer="poly", + to_layer=self.col_mux_stack[0], + offset=offset, + directions=self.via_directions) self.add_path("poly", [offset, gate_offset]) def route_bitlines(self): From a7ee17eb2d007ba7dc4e0e84be4d81679bf61d5f Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Jun 2020 15:29:27 -0700 Subject: [PATCH 464/521] Move output of sense amp to side like other techs --- technology/freepdk45/gds_lib/sense_amp.gds | Bin 16384 -> 14702 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/technology/freepdk45/gds_lib/sense_amp.gds b/technology/freepdk45/gds_lib/sense_amp.gds index fecbfcb8cdc6af32968849ba447d240a27c92d8a..53c499f95f892bd63084ab55e93de706bd6a492d 100644 GIT binary patch delta 402 zcmZo@V0>2;$H2zG#1z3G!^p(`1jv?R;AfCwU_fRw@G!BZq^2d7=9Dlnh%mF-DIA%- z^l|V3OQjg`3%+aKG03pu)Vne6iJTGxD+2=)F9QRJW|juh?FbqozBxty6w~A!r7LP+ zwfzXSEN>ucK{OLooT-2E3kA8&Ez0@KlTDSR#Lt{LbGm?mM}QfqgoS}Yq97JYrx=d!UvAX$Y7+Pg8DkjpkWNB>fDoKsh}I4oS9@{L+%i&(zcQ-Ol1rVOuRr0q?x6G z^bZ6L5#O95e~M}HIyFV{vkV}>Bftz)#=^j$@{fT{k}WlFvWC(vC8k24U_TH8X^=TA zZxA#@e6x!3MCQrHno^NS=CIZR&0%5SkYr2GO9AQ<1Y!;b1~y(M23`g>J|>`jI$--i z#)F&*HJ<4&)R{mUCeFmW`I%Z2BiJb*hhkF;5udE2sm%&@#pFwxmQa>}mc-;7jfYU4 zpO(~Q9Zf|^B)2kc1M1cTxiuxfv}ALVRunHJ_=16Ufr9ZW5Cek`PJ_ia-!q@USP!yy h0KusJ0~q)~t4G6sH2eoL1V+=}K!!d8LmX|b2LO#IQC0u| From 2bd498c39cf1a412845bd8f93d9989770e3d62e8 Mon Sep 17 00:00:00 2001 From: mrg Date: Sat, 27 Jun 2020 08:21:30 -0700 Subject: [PATCH 465/521] Change precharge layer to m3 --- compiler/modules/precharge_array.py | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 2cf4718a..3a3b8c8b 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -75,11 +75,18 @@ class precharge_array(design.design): def add_layout_pins(self): en_bar_pin = self.pc_cell.get_pin("en_bar") - self.add_layout_pin(text="en_bar", - layer=en_bar_pin.layer, - offset=en_bar_pin.ll(), - width=self.width, - height=en_bar_pin.height()) + if en_bar_pin.layer =="li": + en_bar_layer = "m3" + else: + en_bar_layer = en_bar_pin.layer + r = self.add_layout_pin(text="en_bar", + layer=en_bar_layer, + offset=en_bar_pin.ll(), + width=self.width, + height=en_bar_pin.height()) + self.add_via_stack_center(from_layer=en_bar_pin.layer, + to_layer=en_bar_layer, + offset = r.center()) for inst in self.local_insts: self.copy_layout_pin(inst, "vdd") From 609aa98c8be449ba86308eca1536c4c0d5178f91 Mon Sep 17 00:00:00 2001 From: mrg Date: Sat, 27 Jun 2020 08:21:53 -0700 Subject: [PATCH 466/521] Move write mask pin to left of cell to avoid sense amp --- compiler/modules/write_driver_array.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 22a75218..a6eb1384 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -154,7 +154,6 @@ class write_driver_array(design.design): self.get_br_name() + "_{0}".format(index), self.en_name + "_{0}".format(i + offset), "vdd", "gnd"]) - def place_write_array(self): from tech import cell_properties if self.bitcell.width > self.driver.width: From c10a6a29c00fcf4ab47c2f3f757982b60eadbf7a Mon Sep 17 00:00:00 2001 From: mrg Date: Sat, 27 Jun 2020 08:22:16 -0700 Subject: [PATCH 467/521] Simplify precharge pin layer --- compiler/pgates/precharge.py | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index dc016cab..b3d25865 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -38,16 +38,10 @@ class precharge(design.design): if self.bitcell_bl_pin.layer == "m1": self.bitline_layer = "m1" - if "li" in layer: - self.en_layer = "li" - else: - self.en_layer = "m2" + self.en_layer = "m2" else: self.bitline_layer = "m2" - if "li" in layer: - self.en_layer = "li" - else: - self.en_layer = "m1" + self.en_layer = "m1" # Creates the netlist and layout # Since it has variable height, it is not a pgate. From 66ea559209c476804433bc12cf5e0c17cd994f88 Mon Sep 17 00:00:00 2001 From: mrg Date: Sat, 27 Jun 2020 08:23:12 -0700 Subject: [PATCH 468/521] Use channel for dffs all at once --- compiler/modules/write_mask_and_array.py | 17 +- compiler/sram/sram_1bank.py | 314 +++++++++++------------ 2 files changed, 163 insertions(+), 168 deletions(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index f337ab7a..c87d3a90 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -108,8 +108,21 @@ class write_mask_and_array(design.design): end=vector(self.width, en_pin.cy())) for i in range(self.num_wmasks): + # Route the A pin over to the left so that it doesn't conflict with the sense + # amp output which is usually in the center + a_pin = self.and2_insts[i].get_pin("A") + a_pos = a_pin.center() + in_pos = vector(self.and2_insts[i].lx(), + a_pos.y) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=in_pos) + self.add_layout_pin_rect_center(text="wmask_in_{0}".format(i), + layer="m2", + offset=in_pos) + self.add_path(a_pin.layer, [in_pos, a_pos]) + # Copy remaining layout pins - self.copy_layout_pin(self.and2_insts[i], "A", "wmask_in_{0}".format(i)) self.copy_layout_pin(self.and2_insts[i], "Z", "wmask_out_{0}".format(i)) # Add via connections to metal3 for AND array's B pin @@ -122,7 +135,7 @@ class write_mask_and_array(design.design): for supply in ["gnd", "vdd"]: supply_pin=self.and2_insts[i].get_pin(supply) if "li" in layer: - self.add_power_pin(supply, supply_pin.center(), start_layer="li", directions = ("H", "H")) + self.add_power_pin(supply, supply_pin.center(), start_layer="li", directions=("H", "H")) else: self.add_power_pin(supply, supply_pin.center()) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 7d2ccfa8..4e2be40e 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -70,93 +70,12 @@ class sram_1bank(sram_base): # If a horizontal channel, they rely on the vertical channel non-preferred (contacted) pitch. # If a vertical channel, they rely on the horizontal channel non-preferred (contacted) pitch. # So, m3 non-pref pitch means that this is routed on the m2 layer. - if self.write_size: - self.data_bus_gap = self.m4_nonpref_pitch * 2 - self.data_bus_size = self.m4_nonpref_pitch * (self.word_size + self.num_spare_cols) + self.data_bus_gap - self.wmask_bus_gap = self.m2_nonpref_pitch * 2 - self.wmask_bus_size = self.m2_nonpref_pitch * (max(self.num_wmasks + 1, self.col_addr_size + 1)) + self.wmask_bus_gap - if self.num_spare_cols: - self.spare_wen_bus_gap = self.m2_nonpref_pitch * 2 - self.spare_wen_bus_size = self.m2_nonpref_pitch * (max(self.num_spare_cols + 1, self.col_addr_size + 1)) + self.spare_wen_bus_gap - else: - self.spare_wen_bus_size = 0 - - elif self.num_spare_cols and not self.write_size: - self.data_bus_gap = self.m4_nonpref_pitch * 2 - self.data_bus_size = self.m4_nonpref_pitch * (self.word_size + self.num_spare_cols) + self.data_bus_gap - self.spare_wen_bus_gap = self.m2_nonpref_pitch * 2 - self.spare_wen_bus_size = self.m2_nonpref_pitch * (max(self.num_spare_cols + 1, self.col_addr_size + 1)) + self.spare_wen_bus_gap - - else: - self.data_bus_gap = self.m3_nonpref_pitch * 2 - self.data_bus_size = self.m3_nonpref_pitch * (max(self.word_size + 1, self.col_addr_size + 1)) + self.data_bus_gap - - self.col_addr_bus_gap = self.m2_nonpref_pitch * 2 - self.col_addr_bus_size = self.m2_nonpref_pitch * (self.col_addr_size) + self.col_addr_bus_gap + self.data_bus_gap = self.m4_nonpref_pitch * 2 + self.data_bus_size = self.m4_nonpref_pitch * (self.word_size + self.num_spare_cols + self.num_wmasks + self.col_addr_size + self.num_spare_cols) + self.data_bus_gap # Port 0 port = 0 - if port in self.write_ports: - if self.write_size: - bus_size = max(self.wmask_bus_size, self.spare_wen_bus_size) - # Add the write mask flops below the write mask AND array. - wmask_pos[port] = vector(self.bank.bank_array_ll.x, - - bus_size - self.dff.height) - self.wmask_dff_insts[port].place(wmask_pos[port]) - - # Add the data flops below the write mask flops. - data_pos[port] = vector(self.bank.bank_array_ll.x, - - self.data_bus_size - bus_size - 2 * self.dff.height) - self.data_dff_insts[port].place(data_pos[port]) - - #Add spare write enable flops to the right of write mask flops - if self.num_spare_cols: - spare_wen_pos[port] = vector(self.bank.bank_array_ll.x + self.wmask_dff_insts[port].width + self.bank.m2_gap, - - bus_size - self.dff.height) - self.spare_wen_dff_insts[port].place(spare_wen_pos[port]) - - elif self.num_spare_cols and not self.write_size: - # Add spare write enable flops below bank (lower right) - spare_wen_pos[port] = vector(self.bank.bank_array_ll.x, - - self.spare_wen_bus_size - self.dff.height) - self.spare_wen_dff_insts[port].place(spare_wen_pos[port]) - - # Add the data flops below the spare write enable flops. - data_pos[port] = vector(self.bank.bank_array_ll.x, - - self.data_bus_size - self.spare_wen_bus_size - 2 * self.dff.height) - self.data_dff_insts[port].place(data_pos[port]) - - else: - # Add the data flops below the bank to the right of the lower-left of bank array - # This relies on the lower-left of the array of the bank - # decoder in upper left, bank in upper right, sensing in lower right. - # These flops go below the sensing and leave a gap to channel route to the - # sense amps. - data_pos[port] = vector(self.bank.bank_array_ll.x, - -self.data_bus_size - self.dff.height) - self.data_dff_insts[port].place(data_pos[port]) - - else: - wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0) - data_pos[port] = vector(self.bank.bank_array_ll.x, 0) - spare_wen_pos[port] = vector(self.bank.bank_array_ll.x, 0) - - # Add the col address flops below the bank to the left of the lower-left of bank array - if self.col_addr_dff: - if self.write_size: - col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, - -bus_size - self.col_addr_dff_insts[port].height) - elif self.num_spare_cols and not self.write_size: - col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, - -self.spare_wen_bus_size - self.col_addr_dff_insts[port].height) - else: - col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, - -self.data_bus_size - self.col_addr_dff_insts[port].height) - self.col_addr_dff_insts[port].place(col_addr_pos[port]) - else: - col_addr_pos[port] = vector(self.bank.bank_array_ll.x, 0) - # This includes 2 M2 pitches for the row addr clock line. control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch, self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y - 2 * self.bank.m2_gap) @@ -169,64 +88,45 @@ class sram_1bank(sram_base): row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port]) + # Add the col address flops below the bank to the right of the control logic + x_offset = self.control_logic_insts[port].rx() + self.dff.width + y_offset = - self.data_bus_size - self.dff.height + if self.col_addr_dff: + col_addr_pos[port] = vector(x_offset, + y_offset) + self.col_addr_dff_insts[port].place(col_addr_pos[port]) + x_offset = self.col_addr_dff_insts[port].rx() + else: + col_addr_pos[port] = vector(x_offset, 0) + + if port in self.write_ports: + if self.write_size: + # Add the write mask flops below the write mask AND array. + wmask_pos[port] = vector(x_offset, + y_offset) + self.wmask_dff_insts[port].place(wmask_pos[port]) + x_offset = self.wmask_dff_insts[port].rx() + + # Add spare write enable flops to the right of write mask flops + if self.num_spare_cols: + spare_wen_pos[port] = vector(x_offset, + y_offset) + self.spare_wen_dff_insts[port].place(spare_wen_pos[port]) + x_offset = self.spare_wen_dff_insts[port].rx() + + # Add the data flops below the write mask flops. + data_pos[port] = vector(x_offset, + y_offset) + self.data_dff_insts[port].place(data_pos[port]) + + else: + wmask_pos[port] = vector(x_offset, y_offset) + data_pos[port] = vector(x_offset, y_offset) + spare_wen_pos[port] = vector(x_offset, y_offset) + if len(self.all_ports)>1: # Port 1 port = 1 - - if port in self.write_ports: - if self.write_size: - bus_size = max(self.wmask_bus_size, self.spare_wen_bus_size) - # Add the write mask flops above the write mask AND array. - wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.wmask_dff_insts[port].width, - self.bank.height + bus_size + self.dff.height) - self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") - - # Add the data flops above the write mask flops - data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.height + bus_size + self.data_bus_size + 2 * self.dff.height) - self.data_dff_insts[port].place(data_pos[port], mirror="MX") - - if self.num_spare_cols: - spare_wen_pos[port] = vector(self.bank.bank_array_ur.x - self.wmask_dff_insts[port].width - - self.spare_wen_dff_insts[port].width - self.bank.m2_gap, - self.bank.height + bus_size + self.dff.height) - self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX") - - # Place dffs when spare cols is enabled - elif self.num_spare_cols and not self.write_size: - # Spare wen flops on the upper right, below data flops - spare_wen_pos[port] = vector(self.bank.bank_array_ur.x - self.spare_wen_dff_insts[port].width, - self.bank.height + self.spare_wen_bus_size + self.dff.height) - self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX") - # Add the data flops above the spare write enable flops - data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.height + self.spare_wen_bus_size + self.data_bus_size + 2 * self.dff.height) - self.data_dff_insts[port].place(data_pos[port], mirror="MX") - - else: - # Add the data flops above the bank to the left of the upper-right of bank array - # This relies on the upper-right of the array of the bank - # decoder in upper left, bank in upper right, sensing in lower right. - # These flops go below the sensing and leave a gap to channel route to the - # sense amps. - data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.height + self.data_bus_size + self.dff.height) - self.data_dff_insts[port].place(data_pos[port], mirror="MX") - - # Add the col address flops above the bank to the right of the upper-right of bank array - if self.col_addr_dff: - if self.write_size: - col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, - self.bank.height + bus_size + self.dff.height) - elif self.num_spare_cols and not self.write_size: - col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, - self.bank.height + self.spare_wen_bus_size + self.dff.height) - else: - col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, - self.bank.height + self.data_bus_size + self.dff.height) - self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX") - else: - col_addr_pos[port] = self.bank_inst.ur() # This includes 2 M2 pitches for the row addr clock line control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2 * self.m2_pitch, @@ -242,6 +142,42 @@ class sram_1bank(sram_base): row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY") + # Add the col address flops below the bank to the right of the control logic + x_offset = self.control_logic_insts[port].lx() - 2 * self.dff.width + y_offset = self.bank.height + self.data_bus_size + self.dff.height + if self.col_addr_dff: + col_addr_pos[port] = vector(x_offset - self.col_addr_dff_insts[port].width, + y_offset) + self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX") + x_offset = self.col_addr_dff_insts[port].lx() + else: + col_addr_pos[port] = vector(x_offset, y_offset) + + if port in self.write_ports: + if self.write_size: + # Add the write mask flops below the write mask AND array. + wmask_pos[port] = vector(x_offset - self.wmask_dff_insts[port].width, + y_offset) + self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") + x_offset = self.wmask_dff_insts[port].lx() + + # Add spare write enable flops to the right of write mask flops + if self.num_spare_cols: + spare_wen_pos[port] = vector(x_offset - self.spare_wen_dff_insts[port].width, + y_offset) + self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX") + x_offset = self.spare_wen_dff_insts[port].lx() + + # Add the data flops below the write mask flops. + data_pos[port] = vector(x_offset - self.data_dff_insts[port].width, + y_offset) + self.data_dff_insts[port].place(data_pos[port], mirror="MX") + + else: + wmask_pos[port] = vector(x_offset, y_offset) + data_pos[port] = vector(x_offset, y_offset) + spare_wen_pos[port] = vector(x_offset, y_offset) + def add_layout_pins(self): """ Add the top-level pins for a single bank SRAM with control. @@ -250,7 +186,6 @@ class sram_1bank(sram_base): lowest_coord = self.find_lowest_coords() bbox = [lowest_coord, highest_coord] - for port in self.all_ports: # Depending on the port, use the bottom/top or left/right sides # Port 0 is left/bottom @@ -370,17 +305,83 @@ class sram_1bank(sram_base): self.route_row_addr_dff() - if self.col_addr_dff: - self.route_col_addr_dff() + # if self.col_addr_dff: + # self.route_col_addr_dff() - self.route_data_dff() + # self.route_data_dff() - if self.write_size: - self.route_wmask_dff() + # if self.write_size: + # self.route_wmask_dff() - if self.num_spare_cols: - self.route_spare_wen_dff() + # if self.num_spare_cols: + # self.route_spare_wen_dff() + for port in self.all_ports: + self.route_dff(port) + def route_dff(self, port): + + route_map = [] + + # column mux dff + if self.col_addr_size > 0: + dff_names = ["dout_{}".format(x) for x in range(self.col_addr_size)] + dff_pins = [self.col_addr_dff_insts[port].get_pin(x) for x in dff_names] + bank_names = ["addr{0}_{1}".format(port, x) for x in range(self.col_addr_size)] + bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + route_map.extend(list(zip(bank_pins, dff_pins))) + + # spare wen dff + if self.num_spare_cols > 0 and port in self.write_ports: + dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)] + dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names] + bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)] + bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + route_map.extend(list(zip(bank_pins, dff_pins))) + + # wmask dff + if self.num_wmasks > 0 and port in self.write_ports: + dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)] + dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names] + bank_names = ["bank_wmask{0}_{1}".format(port, x) for x in range(self.num_wmasks)] + bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + route_map.extend(list(zip(bank_pins, dff_pins))) + + if port in self.write_ports: + # data dff + dff_names = ["dout_{}".format(x) for x in range(self.word_size + self.num_spare_cols)] + dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] + bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)] + bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + route_map.extend(list(zip(bank_pins, dff_pins))) + + if self.num_wmasks > 0 and port in self.write_ports: + vertical_layer = "m4" + layer_stack = self.m3_stack + else: + vertical_layer = "m2" + layer_stack = self.m1_stack + for (pin1, pin2) in route_map: + if pin1.layer != vertical_layer: + self.add_via_stack_center(from_layer=pin1.layer, + to_layer=vertical_layer, + offset=pin1.center()) + if pin2.layer != vertical_layer: + self.add_via_stack_center(from_layer=pin2.layer, + to_layer=vertical_layer, + offset=pin2.center()) + + if port == 0: + offset = vector(self.control_logic_insts[port].rx() + self.dff.width, + - self.data_bus_size + 2 * self.m1_pitch) + else: + offset = vector(0, + self.bank.height + 2 * self.m1_space) + + if len(route_map) > 0: + self.create_horizontal_channel_route(netlist=route_map, + offset=offset, + layer_stack=layer_stack) + def route_clk(self): """ Route the clock network """ @@ -423,8 +424,7 @@ class sram_1bank(sram_base): mid_pos = vector(clk_steiner_pos.x, dff_clk_pos.y) self.add_wire(self.m2_stack[::-1], [dff_clk_pos, mid_pos, clk_steiner_pos]) - - if port in self.write_ports: + elif port in self.write_ports: data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk") data_dff_clk_pos = data_dff_clk_pin.center() mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y) @@ -436,24 +436,6 @@ class sram_1bank(sram_base): self.add_wire(self.m2_stack[::-1], [data_dff_clk_pos, mid_pos, clk_steiner_pos]) - if self.write_size: - wmask_dff_clk_pin = self.wmask_dff_insts[port].get_pin("clk") - wmask_dff_clk_pos = wmask_dff_clk_pin.center() - mid_pos = vector(clk_steiner_pos.x, wmask_dff_clk_pos.y) - # In some designs, the steiner via will be too close to the mid_pos via - # so make the wire as wide as the contacts - self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height)) - self.add_wire(self.m2_stack[::-1], [wmask_dff_clk_pos, mid_pos, clk_steiner_pos]) - - if self.num_spare_cols: - spare_wen_dff_clk_pin = self.spare_wen_dff_insts[port].get_pin("clk") - spare_wen_dff_clk_pos = spare_wen_dff_clk_pin.center() - mid_pos = vector(clk_steiner_pos.x, spare_wen_dff_clk_pos.y) - # In some designs, the steiner via will be too close to the mid_pos via - # so make the wire as wide as the contacts - self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height)) - self.add_wire(self.m2_stack[::-1], [spare_wen_dff_clk_pos, mid_pos, clk_steiner_pos]) - def route_control_logic(self): """ Route the control logic pins that are not inputs """ From 0c9f52e22f3b8a9d1107cf1ebce746ac2f17b28a Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 07:15:06 -0700 Subject: [PATCH 469/521] Realign col decoder and control by 1/4 so metal can pass over --- compiler/modules/bank.py | 11 ++++++++--- compiler/sram/sram_1bank.py | 13 +++++++++---- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 6134b143..7bbed020 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -217,11 +217,12 @@ class bank(design.design): # Place the col decoder left aligned with wordline driver # This is also placed so that it's supply rails do not align with the SRAM-level # control logic to allow control signals to easily pass over in M3 - # by placing 1/2 a cell pitch down + # by placing 1 1/4 a cell pitch down because both power connections and inputs/outputs + # may be routed in M3 or M4 x_offset = self.central_bus_width[port] + self.port_address.wordline_driver.width if self.col_addr_size > 0: x_offset += self.column_decoder.width + self.col_addr_bus_width - y_offset = 0.5 * self.dff.height + self.column_decoder.height + y_offset = 1.25 * self.dff.height + self.column_decoder.height else: y_offset = 0 self.column_decoder_offsets[port] = vector(-x_offset, -y_offset) @@ -258,10 +259,14 @@ class bank(design.design): # UPPER RIGHT QUADRANT # Place the col decoder right aligned with wordline driver # Above the bitcell array with a well spacing + # This is also placed so that it's supply rails do not align with the SRAM-level + # control logic to allow control signals to easily pass over in M3 + # by placing 1 1/4 a cell pitch down because both power connections and inputs/outputs + # may be routed in M3 or M4 x_offset = self.bitcell_array_right + self.central_bus_width[port] + self.port_address.wordline_driver.width if self.col_addr_size > 0: x_offset += self.column_decoder.width + self.col_addr_bus_width - y_offset = self.bitcell_array_top + 0.5 * self.dff.height + self.column_decoder.height + y_offset = self.bitcell_array_top + 1.25 * self.dff.height + self.column_decoder.height else: y_offset = self.bitcell_array_top self.column_decoder_offsets[port] = vector(x_offset, y_offset) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 4e2be40e..b8efd195 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -77,8 +77,10 @@ class sram_1bank(sram_base): port = 0 # This includes 2 M2 pitches for the row addr clock line. + # The delay line is aligned with the bitcell array while the control logic is aligned with the port_data + # using the control_logic_center value. control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch, - self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y - 2 * self.bank.m2_gap) + self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y) self.control_logic_insts[port].place(control_pos[port]) # The row address bits are placed above the control logic aligned on the right. @@ -129,10 +131,13 @@ class sram_1bank(sram_base): port = 1 # This includes 2 M2 pitches for the row addr clock line + # The delay line is aligned with the bitcell array while the control logic is aligned with the port_data + # using the control_logic_center value. control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2 * self.m2_pitch, - self.bank.bank_array_ur.y + self.control_logic_insts[port].height - \ - (self.control_logic_insts[port].height - self.control_logic_insts[port].mod.control_logic_center.y) - + 2 * self.bank.m2_gap) + self.bank.bank_array_ur.y + + self.control_logic_insts[port].height + - self.control_logic_insts[port].height + + self.control_logic_insts[port].mod.control_logic_center.y) self.control_logic_insts[port].place(control_pos[port], mirror="XY") # The row address bits are placed above the control logic aligned on the left. From e774314add76384d4fdaa4a31346fc3da26027e7 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 14:14:48 -0700 Subject: [PATCH 470/521] Separate write driver pins by M3 pitch --- technology/freepdk45/gds_lib/write_driver.gds | Bin 20480 -> 20332 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/technology/freepdk45/gds_lib/write_driver.gds b/technology/freepdk45/gds_lib/write_driver.gds index 86015e7a7991ff9a3775c8e11fa1fee5ce5113a1..44a67dd0e23566a60892773f14112232386bca06 100644 GIT binary patch delta 281 zcmZoz!1!h!V;ln;0~1pOgA5}R`x78rhJlZPg+U6L&A`LNmXey5SejG9z#ziRYNv2y z_R`0}2P~Ch#4q@+dB-5bic{~#I3bD}GiLuwe{5GOSKp zAO=bdDVceb|C?(-ZGB+w4rS?Bs7z+FP=xZB99$u+%{~qa`~W7% BN$UUr delta 440 zcmaDekFj9^V;ln;0}~L-FfuXl16cwL+zh4+S`5Mr91NTcTnyR_#tb}6Y$>T}iKRIu z3=AU7tab`VW-oml{LNA+M*M>Bns*E`tV|4iKz))x9U2TK$a*)%3F%BOFjr(f%K!wE zr}xLt70I!8hq89qtC(>xFtG75G4L|5@i76_>j*G2Ffdhvv_fb`2?hpc zb_NC*4H4h`!Ca4#3oJerBtKch^3r5Cdqq{Sr3^eWtWI0NMldk&fK5CN Date: Sun, 28 Jun 2020 14:28:18 -0700 Subject: [PATCH 471/521] Pick correct side of pin in channel route. --- compiler/base/channel_route.py | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py index d6048376..8a35891c 100644 --- a/compiler/base/channel_route.py +++ b/compiler/base/channel_route.py @@ -240,10 +240,18 @@ class channel_route(design.design): # Route each pin to the trunk for pin in pins: mid = vector(pin.center().x, trunk_offset.y) - self.add_path(self.vertical_layer, [pin.center(), mid]) + # Find the correct side of the pin + if pin.cy() < trunk_offset.y: + pin_pos = pin.uc() + else: + pin_pos = pin.bc() + self.add_path(self.vertical_layer, [pin_pos, mid]) self.add_via_center(layers=self.layer_stack, offset=mid, directions=self.directions) + self.add_via_stack_center(from_layer=pin.layer, + to_layer=self.vertical_layer, + offset=pin_pos) def add_vertical_trunk_route(self, pins, @@ -280,10 +288,18 @@ class channel_route(design.design): # Route each pin to the trunk for pin in pins: mid = vector(trunk_offset.x, pin.center().y) - self.add_path(self.horizontal_layer, [pin.center(), mid]) + # Find the correct side of the pin + if pin.cx() < trunk_offset.x: + pin_pos = pin.rc() + else: + pin_pos = pin.lc() + self.add_path(self.horizontal_layer, [pin_pos, mid]) self.add_via_center(layers=self.layer_stack, offset=mid, directions=self.directions) + self.add_via_stack_center(from_layer=pin.layer, + to_layer=self.horizontal_layer, + offset=pin_pos) def vcg_pin_overlap(self, pin1, pin2, pitch): """ Check for vertical or horizontal overlap of the two pins """ From 4df02dad679b92537571af123752effbb78ab4d5 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 14:28:43 -0700 Subject: [PATCH 472/521] Move spare wen_dff to the right by spare columns --- compiler/sram/sram_1bank.py | 42 ++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 24 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index b8efd195..61a0e5ef 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -109,18 +109,20 @@ class sram_1bank(sram_base): self.wmask_dff_insts[port].place(wmask_pos[port]) x_offset = self.wmask_dff_insts[port].rx() - # Add spare write enable flops to the right of write mask flops + # Add the data flops below the write mask flops. + data_pos[port] = vector(x_offset, + y_offset) + self.data_dff_insts[port].place(data_pos[port]) + x_offset = self.data_dff_insts[port].rx() + + # Add spare write enable flops to the right of data flops since the spare columns + # will be on the right if self.num_spare_cols: spare_wen_pos[port] = vector(x_offset, y_offset) self.spare_wen_dff_insts[port].place(spare_wen_pos[port]) x_offset = self.spare_wen_dff_insts[port].rx() - # Add the data flops below the write mask flops. - data_pos[port] = vector(x_offset, - y_offset) - self.data_dff_insts[port].place(data_pos[port]) - else: wmask_pos[port] = vector(x_offset, y_offset) data_pos[port] = vector(x_offset, y_offset) @@ -159,6 +161,14 @@ class sram_1bank(sram_base): col_addr_pos[port] = vector(x_offset, y_offset) if port in self.write_ports: + # Add spare write enable flops to the right of the data flops since the spare + # columns will be on the left + if self.num_spare_cols: + spare_wen_pos[port] = vector(x_offset - self.spare_wen_dff_insts[port].width, + y_offset) + self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX") + x_offset = self.spare_wen_dff_insts[port].lx() + if self.write_size: # Add the write mask flops below the write mask AND array. wmask_pos[port] = vector(x_offset - self.wmask_dff_insts[port].width, @@ -166,18 +176,12 @@ class sram_1bank(sram_base): self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") x_offset = self.wmask_dff_insts[port].lx() - # Add spare write enable flops to the right of write mask flops - if self.num_spare_cols: - spare_wen_pos[port] = vector(x_offset - self.spare_wen_dff_insts[port].width, - y_offset) - self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX") - x_offset = self.spare_wen_dff_insts[port].lx() - # Add the data flops below the write mask flops. data_pos[port] = vector(x_offset - self.data_dff_insts[port].width, y_offset) self.data_dff_insts[port].place(data_pos[port], mirror="MX") + else: wmask_pos[port] = vector(x_offset, y_offset) data_pos[port] = vector(x_offset, y_offset) @@ -360,20 +364,9 @@ class sram_1bank(sram_base): route_map.extend(list(zip(bank_pins, dff_pins))) if self.num_wmasks > 0 and port in self.write_ports: - vertical_layer = "m4" layer_stack = self.m3_stack else: - vertical_layer = "m2" layer_stack = self.m1_stack - for (pin1, pin2) in route_map: - if pin1.layer != vertical_layer: - self.add_via_stack_center(from_layer=pin1.layer, - to_layer=vertical_layer, - offset=pin1.center()) - if pin2.layer != vertical_layer: - self.add_via_stack_center(from_layer=pin2.layer, - to_layer=vertical_layer, - offset=pin2.center()) if port == 0: offset = vector(self.control_logic_insts[port].rx() + self.dff.width, @@ -580,6 +573,7 @@ class sram_1bank(sram_base): self.create_horizontal_channel_route(netlist=route_map, offset=offset, layer_stack=self.m1_stack) + def route_spare_wen_dff(self): """ Connect the output of the spare write enable flops to the spare write drivers """ # This is where the channel will start (y-dimension at least) From 225fc69420164c6754c1b5aa1eaea204efe62388 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 14:29:12 -0700 Subject: [PATCH 473/521] Use preferred routing direction --- compiler/modules/bank.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 7bbed020..ed835d43 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -888,7 +888,7 @@ class bank(design.design): route_map = list(zip(decode_pins, column_mux_pins)) if "li" in layer: stack = self.li_stack - directions = "nonpref" + directions = "pref" else: stack = self.m1_stack directions = "pref" From 709535f90fee00f0a7258aa7a7c354c81174b086 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 14:47:17 -0700 Subject: [PATCH 474/521] Fix right perimeter pin coordinate bug --- compiler/base/hierarchy_layout.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 2a29be6b..50b9f78a 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1165,7 +1165,7 @@ class layout(): layer = "m3" elif side == "right": layer = "m3" - peri_pin_loc = vector(right, pin_loc.x) + peri_pin_loc = vector(right, pin_loc.y) elif side == "top": layer = "m4" peri_pin_loc = vector(pin_loc.x, top) From 051c8d8697c35caddea0e4dba2cb6c0015e63052 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 14:47:54 -0700 Subject: [PATCH 475/521] Only add bitcells to dummy and replica rows and columns (the perimeter) --- compiler/modules/bitcell_base_array.py | 56 +++++++++----------------- 1 file changed, 18 insertions(+), 38 deletions(-) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 6698df33..e162c225 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -9,6 +9,7 @@ import debug import design from tech import cell_properties + class bitcell_base_array(design.design): """ Abstract base class for bitcell-arrays -- bitcell, dummy @@ -68,10 +69,10 @@ class bitcell_base_array(design.design): pin_names = self.cell.get_all_bitline_names() for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(col)) + bitcell_pins.append(pin + "_{0}".format(col)) pin_names = self.cell.get_all_wl_names() for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(row)) + bitcell_pins.append(pin + "_{0}".format(row)) bitcell_pins.append("vdd") bitcell_pins.append("gnd") @@ -85,46 +86,27 @@ class bitcell_base_array(design.design): for col in range(self.column_size): for cell_column in column_list: - bl_pin = self.cell_inst[0,col].get_pin(cell_column) - self.add_layout_pin(text=cell_column+"_{0}".format(col), + bl_pin = self.cell_inst[0, col].get_pin(cell_column) + self.add_layout_pin(text=cell_column + "_{0}".format(col), layer=bl_pin.layer, - offset=bl_pin.ll().scale(1,0), + offset=bl_pin.ll().scale(1, 0), width=bl_pin.width(), height=self.height) for row in range(self.row_size): for cell_row in row_list: - wl_pin = self.cell_inst[row,0].get_pin(cell_row) - self.add_layout_pin(text=cell_row+"_{0}".format(row), + wl_pin = self.cell_inst[row, 0].get_pin(cell_row) + self.add_layout_pin(text=cell_row + "_{0}".format(row), layer=wl_pin.layer, - offset=wl_pin.ll().scale(0,1), + offset=wl_pin.ll().scale(0, 1), width=self.width, height=wl_pin.height()) - # For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space - # Default uses prefered directions for each layer; this cell property is only currently used by sky130 tech (03/20) - try: - bitcell_power_pin_directions = cell_properties.bitcell_power_pin_directions - except AttributeError: - bitcell_power_pin_directions = None - - # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. - try: - end_caps_enabled = cell_properties.bitcell.end_caps - except AttributeError: - end_caps_enabled = False - - # Add vdd/gnd via stacks - if not end_caps_enabled: - for row in range(self.row_size): - for col in range(self.column_size): - inst = self.cell_inst[row, col] - for pin_name in ["vdd", "gnd"]: - for pin in inst.get_pins(pin_name): - self.add_power_pin(name=pin_name, - loc=pin.center(), - directions=bitcell_power_pin_directions, - start_layer=pin.layer) + # Copy a vdd/gnd layout pin from every column in the first row + for col in range(self.column_size): + inst = self.cell_inst[0, col] + for pin_name in ["vdd", "gnd"]: + self.copy_layout_pin(inst, pin_name) def _adjust_x_offset(self, xoffset, col, col_offset): tempx = xoffset @@ -144,11 +126,10 @@ class bitcell_base_array(design.design): dir_x = True return (tempy, dir_x) - def place_array(self, name_template, row_offset=0): # We increase it by a well enclosure so the precharges don't overlap our wells - self.height = self.row_size*self.cell.height - self.width = self.column_size*self.cell.width + self.height = self.row_size * self.cell.height + self.width = self.column_size * self.cell.width xoffset = 0.0 for col in range(self.column_size): @@ -156,7 +137,6 @@ class bitcell_base_array(design.design): tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset) for row in range(self.row_size): - name = name_template.format(row, col) tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset) if dir_x and dir_y: @@ -168,7 +148,7 @@ class bitcell_base_array(design.design): else: dir_key = "" - self.cell_inst[row,col].place(offset=[tempx, tempy], - mirror=dir_key) + self.cell_inst[row, col].place(offset=[tempx, tempy], + mirror=dir_key) yoffset += self.cell.height xoffset += self.cell.width From 20324ab3c4ceca04f379e66d27178e92bc9b9474 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 14:55:58 -0700 Subject: [PATCH 476/521] Revert write driver pin spacing --- technology/freepdk45/gds_lib/write_driver.gds | Bin 20332 -> 20480 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/technology/freepdk45/gds_lib/write_driver.gds b/technology/freepdk45/gds_lib/write_driver.gds index 44a67dd0e23566a60892773f14112232386bca06..86015e7a7991ff9a3775c8e11fa1fee5ce5113a1 100644 GIT binary patch delta 440 zcmaDekFj9^V;ln;0}~L-FfuXl16cwL+zh4+S`5Mr91NTcTnyR_#tb}6Y$>T}iKRIu z3=AU7tab`VW-oml{LNA+M*M>Bns*E`tV|4iKz))x9U2TK$a*)%3F%BOFjr(f%K!wE zr}xLt70I!8hq89qtC(>xFtG75G4L|5@i76_>j*G2Ffdhvv_fb`2?hpc zb_NC*4H4h`!Ca4#3oJerBtKch^3r5Cdqq{Sr3^eWtWI0NMldk&fK5CND}GiLuwe{5GOSKp zAO=bdDVceb|C?(-ZGB+w4rS?Bs7z+FP=xZB99$u+%{~qa`~W7% BN$UUr From 751eab202bd308b715541424fe0ca9b736ad347d Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 15:06:29 -0700 Subject: [PATCH 477/521] Move row addr flops away from predecode. Route spare wen separately on lower layer. --- compiler/sram/sram_1bank.py | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 61a0e5ef..73df61bb 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -86,7 +86,7 @@ class sram_1bank(sram_base): # The row address bits are placed above the control logic aligned on the right. x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width # It is above the control logic but below the top of the bitcell array - y_offset = max(self.control_logic_insts[port].uy(), self.control_logic_insts[port].uy() + self.dff.height) + y_offset = max(self.control_logic_insts[port].uy(), self.bank_inst.uy() - self.row_addr_dff_insts[port].height) row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port]) @@ -145,7 +145,7 @@ class sram_1bank(sram_base): # The row address bits are placed above the control logic aligned on the left. x_offset = control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width # It is below the control logic but below the bottom of the bitcell array - y_offset = min(self.control_logic_insts[port].by(), self.control_logic_insts[port].by() - self.dff.height) + y_offset = min(self.control_logic_insts[port].by(), self.bank_inst.by() + self.row_addr_dff_insts[port].height) row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY") @@ -180,8 +180,6 @@ class sram_1bank(sram_base): data_pos[port] = vector(x_offset - self.data_dff_insts[port].width, y_offset) self.data_dff_insts[port].place(data_pos[port], mirror="MX") - - else: wmask_pos[port] = vector(x_offset, y_offset) data_pos[port] = vector(x_offset, y_offset) @@ -339,14 +337,6 @@ class sram_1bank(sram_base): bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] route_map.extend(list(zip(bank_pins, dff_pins))) - # spare wen dff - if self.num_spare_cols > 0 and port in self.write_ports: - dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)] - dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names] - bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)] - bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] - route_map.extend(list(zip(bank_pins, dff_pins))) - # wmask dff if self.num_wmasks > 0 and port in self.write_ports: dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)] @@ -379,6 +369,18 @@ class sram_1bank(sram_base): self.create_horizontal_channel_route(netlist=route_map, offset=offset, layer_stack=layer_stack) + + # Route these separately because sometimes the pin pitch on the write driver is too narrow for M3 (FreePDK45) + # spare wen dff + if self.num_spare_cols > 0 and port in self.write_ports: + dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)] + dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names] + bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)] + bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + route_map = zip(bank_pins, dff_pins) + self.create_horizontal_channel_route(netlist=route_map, + offset=offset, + layer_stack=self.m1_stack) def route_clk(self): """ Route the clock network """ From 5285468380cfd20e8dc61f58a6503a883a9c131b Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 15:09:47 -0700 Subject: [PATCH 478/521] All bitcells need a vdd/gnd pin --- compiler/modules/bitcell_base_array.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index e162c225..7d241b4d 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -102,11 +102,12 @@ class bitcell_base_array(design.design): width=self.width, height=wl_pin.height()) - # Copy a vdd/gnd layout pin from every column in the first row - for col in range(self.column_size): - inst = self.cell_inst[0, col] - for pin_name in ["vdd", "gnd"]: - self.copy_layout_pin(inst, pin_name) + # Copy a vdd/gnd layout pin from every cell + for row in range(self.row_size): + for col in range(self.column_size): + inst = self.cell_inst[row, col] + for pin_name in ["vdd", "gnd"]: + self.copy_layout_pin(inst, pin_name) def _adjust_x_offset(self, xoffset, col, col_offset): tempx = xoffset From 47f541df0e07bbd66a13db7ae203e508c8ac836a Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 16:58:28 -0700 Subject: [PATCH 479/521] Fix bugs in channel route. --- compiler/base/channel_route.py | 77 +++++++++++++++------------------- 1 file changed, 34 insertions(+), 43 deletions(-) diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py index 8a35891c..5e9b9531 100644 --- a/compiler/base/channel_route.py +++ b/compiler/base/channel_route.py @@ -216,42 +216,38 @@ class channel_route(design.design): """ max_x = max([pin.center().x for pin in pins]) min_x = min([pin.center().x for pin in pins]) - + # if we are less than a pitch, just create a non-preferred layer jog - if max_x - min_x <= pitch: + non_preferred_route = max_x - min_x <= pitch + + if non_preferred_route: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)] - # Add the horizontal trunk on the vertical layer! self.add_path(self.vertical_layer, [vector(min_x - half_layer_width, trunk_offset.y), vector(max_x + half_layer_width, trunk_offset.y)]) - - # Route each pin to the trunk - for pin in pins: - # No bend needed here - mid = vector(pin.center().x, trunk_offset.y) - self.add_path(self.vertical_layer, [pin.center(), mid]) else: # Add the horizontal trunk self.add_path(self.horizontal_layer, [vector(min_x, trunk_offset.y), vector(max_x, trunk_offset.y)]) - # Route each pin to the trunk - for pin in pins: - mid = vector(pin.center().x, trunk_offset.y) - # Find the correct side of the pin - if pin.cy() < trunk_offset.y: - pin_pos = pin.uc() - else: - pin_pos = pin.bc() - self.add_path(self.vertical_layer, [pin_pos, mid]) + # Route each pin to the trunk + for pin in pins: + # Find the correct side of the pin + if pin.cy() < trunk_offset.y: + pin_pos = pin.uc() + else: + pin_pos = pin.bc() + mid = vector(pin_pos.x, trunk_offset.y) + self.add_path(self.vertical_layer, [pin_pos, mid]) + if not non_preferred_route: self.add_via_center(layers=self.layer_stack, offset=mid, directions=self.directions) - self.add_via_stack_center(from_layer=pin.layer, - to_layer=self.vertical_layer, - offset=pin_pos) + self.add_via_stack_center(from_layer=pin.layer, + to_layer=self.vertical_layer, + offset=pin_pos) def add_vertical_trunk_route(self, pins, @@ -263,43 +259,38 @@ class channel_route(design.design): """ max_y = max([pin.center().y for pin in pins]) min_y = min([pin.center().y for pin in pins]) - + # if we are less than a pitch, just create a non-preferred layer jog - if max_y - min_y <= pitch: - + non_preferred_route = max_y - min_y <= pitch + + if non_preferred_route: half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)] - # Add the vertical trunk on the horizontal layer! self.add_path(self.horizontal_layer, [vector(trunk_offset.x, min_y - half_layer_width), vector(trunk_offset.x, max_y + half_layer_width)]) - - # Route each pin to the trunk - for pin in pins: - # No bend needed here - mid = vector(trunk_offset.x, pin.center().y) - self.add_path(self.horizontal_layer, [pin.center(), mid]) else: # Add the vertical trunk self.add_path(self.vertical_layer, [vector(trunk_offset.x, min_y), vector(trunk_offset.x, max_y)]) - # Route each pin to the trunk - for pin in pins: - mid = vector(trunk_offset.x, pin.center().y) - # Find the correct side of the pin - if pin.cx() < trunk_offset.x: - pin_pos = pin.rc() - else: - pin_pos = pin.lc() - self.add_path(self.horizontal_layer, [pin_pos, mid]) + # Route each pin to the trunk + for pin in pins: + # Find the correct side of the pin + if pin.cx() < trunk_offset.x: + pin_pos = pin.rc() + else: + pin_pos = pin.lc() + mid = vector(trunk_offset.x, pin_pos.y) + self.add_path(self.horizontal_layer, [pin_pos, mid]) + if not non_preferred_route: self.add_via_center(layers=self.layer_stack, offset=mid, directions=self.directions) - self.add_via_stack_center(from_layer=pin.layer, - to_layer=self.horizontal_layer, - offset=pin_pos) + self.add_via_stack_center(from_layer=pin.layer, + to_layer=self.horizontal_layer, + offset=pin_pos) def vcg_pin_overlap(self, pin1, pin2, pitch): """ Check for vertical or horizontal overlap of the two pins """ From 5f3a45b91b41d98d99560c9a3b6f2e55fb4c98a5 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 29 Jun 2020 05:54:30 -0700 Subject: [PATCH 480/521] Compute bus size separately for ports --- compiler/sram/sram_1bank.py | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 73df61bb..ac86eb94 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -71,7 +71,19 @@ class sram_1bank(sram_base): # If a vertical channel, they rely on the horizontal channel non-preferred (contacted) pitch. # So, m3 non-pref pitch means that this is routed on the m2 layer. self.data_bus_gap = self.m4_nonpref_pitch * 2 - self.data_bus_size = self.m4_nonpref_pitch * (self.word_size + self.num_spare_cols + self.num_wmasks + self.col_addr_size + self.num_spare_cols) + self.data_bus_gap + + # Spare wen are on a separate layer so not included + self.data_bus_size = [None] * len(self.all_ports) + for port in self.all_ports: + # All ports need the col addr flops + self.data_bus_size[port] = self.col_addr_size + # Write ports need the data input flops and write mask flops + if port in self.write_ports: + self.data_bus_size[port] += self.num_wmasks + self.word_size + # Convert to length + self.data_bus_size[port] *= self.m4_nonpref_pitch + # Add the gap in unit length + self.data_bus_size[port] += self.data_bus_gap # Port 0 port = 0 @@ -92,7 +104,7 @@ class sram_1bank(sram_base): # Add the col address flops below the bank to the right of the control logic x_offset = self.control_logic_insts[port].rx() + self.dff.width - y_offset = - self.data_bus_size - self.dff.height + y_offset = - self.data_bus_size[port] - self.dff.height if self.col_addr_dff: col_addr_pos[port] = vector(x_offset, y_offset) @@ -151,7 +163,7 @@ class sram_1bank(sram_base): # Add the col address flops below the bank to the right of the control logic x_offset = self.control_logic_insts[port].lx() - 2 * self.dff.width - y_offset = self.bank.height + self.data_bus_size + self.dff.height + y_offset = self.bank.height + self.data_bus_size[port] + self.dff.height if self.col_addr_dff: col_addr_pos[port] = vector(x_offset - self.col_addr_dff_insts[port].width, y_offset) @@ -360,7 +372,7 @@ class sram_1bank(sram_base): if port == 0: offset = vector(self.control_logic_insts[port].rx() + self.dff.width, - - self.data_bus_size + 2 * self.m1_pitch) + - self.data_bus_size[port] + 2 * self.m1_pitch) else: offset = vector(0, self.bank.height + 2 * self.m1_space) @@ -507,7 +519,7 @@ class sram_1bank(sram_base): # This is where the channel will start (y-dimension at least) for port in self.write_ports: if port % 2: - offset = self.data_dff_insts[port].ll() - vector(0, self.data_bus_size) + offset = self.data_dff_insts[port].ll() - vector(0, self.data_bus_size[port]) else: offset = self.data_dff_insts[port].ul() + vector(0, self.data_bus_gap) From 1bc0775810685ba142e89a917fb7ae7455303ece Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 29 Jun 2020 10:03:24 -0700 Subject: [PATCH 481/521] Only add pins to periphery --- compiler/modules/replica_bitcell_array.py | 14 ++++---------- compiler/modules/replica_column.py | 9 ++------- 2 files changed, 6 insertions(+), 17 deletions(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 57bb3cf9..09a014ce 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -378,16 +378,10 @@ class replica_bitcell_array(design.design): width=pin.width(), height=self.height) - # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. - try: - if cell_properties.bitcell.end_caps_enabled: - supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst, - self.dummy_row_top_inst, self.dummy_row_bot_inst] + list(self.replica_col_inst.values()) - else: - supply_insts = self.insts - except AttributeError: - supply_insts = self.insts - + # vdd/gnd are only connected in the perimeter cells + # replica column should only have a vdd/gnd in the dummy cell on top/bottom + supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst, + self.dummy_row_top_inst, self.dummy_row_bot_inst] + list(self.replica_col_inst.values()) for pin_name in ["vdd", "gnd"]: for inst in supply_insts: pin_list = inst.get_pins(pin_name) diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 58d35e7f..9cd65e57 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -183,13 +183,8 @@ class replica_column(design.design): width=self.width, height=wl_pin.height()) - # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. - if end_caps_enabled: - supply_insts = [self.cell_inst[0], self.cell_inst[self.total_size - 1]] - else: - supply_insts = self.cell_inst.values() - - for inst in supply_insts: + # Supplies are only connected in the ends + for inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]: for pin_name in ["vdd", "gnd"]: if pin_name in inst.mod.pins: self.copy_layout_pin(inst, pin_name) From 07d0f3af8e031f60cf0783deb7348764fbd35667 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 29 Jun 2020 11:46:59 -0700 Subject: [PATCH 482/521] Only copy end-cap pins to the bank level --- compiler/base/hierarchy_layout.py | 4 ++-- compiler/modules/bank.py | 13 +++++++++---- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 50b9f78a..378a4657 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1101,7 +1101,7 @@ class layout(): height=ymax - ymin) return rect - def copy_power_pins(self, inst, name): + def copy_power_pins(self, inst, name, add_vias=True): """ This will copy a power pin if it is on the lowest power_grid layer. If it is on M1, it will add a power via too. @@ -1115,7 +1115,7 @@ class layout(): pin.width(), pin.height()) - else: + elif add_vias: self.add_power_pin(name, pin.center(), start_layer=pin.layer) def add_power_pin(self, name, loc, size=[1, 1], directions=None, start_layer="m1"): diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index ed835d43..e18660e3 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -132,14 +132,17 @@ class bank(design.design): # Connect the rbl to the port data pin bl_pin = self.port_data_inst[port].get_pin("rbl_bl") if port % 2: - pin_offset = bl_pin.uc() + pin_pos = bl_pin.uc() + pin_offset = pin_pos + vector(0, self.m3_pitch) left_right_offset = vector(self.max_x_offset, pin_offset.y) else: - pin_offset = bl_pin.bc() + pin_pos = bl_pin.bc() + pin_offset = pin_pos - vector(0, self.m3_pitch) left_right_offset = vector(self.min_x_offset, pin_offset.y) self.add_via_stack_center(from_layer=bl_pin.layer, to_layer="m3", offset=pin_offset) + self.add_path(bl_pin.layer, [pin_offset, pin_pos]) self.add_layout_pin_segment_center(text="rbl_bl{0}".format(port), layer="m3", start=left_right_offset, @@ -583,9 +586,11 @@ class bank(design.design): def route_supplies(self): """ Propagate all vdd/gnd pins up to this level for all modules """ + # Copy only the power pins already on the power layer + # (this won't add vias to internal bitcell pins, for example) for inst in self.insts: - self.copy_power_pins(inst, "vdd") - self.copy_power_pins(inst, "gnd") + self.copy_power_pins(inst, "vdd", add_vias=False) + self.copy_power_pins(inst, "gnd", add_vias=False) def route_bank_select(self, port): """ Route the bank select logic. """ From e97644c424d562d3dee9a1a8ca1fdb51937abe54 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 29 Jun 2020 14:42:24 -0700 Subject: [PATCH 483/521] Only do reverse lookup on valid interconnect layers since layer numbers can be shared. --- compiler/base/pin_layout.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index f758a903..dac4e525 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -8,7 +8,7 @@ import debug from tech import GDS, drc from vector import vector -from tech import layer +from tech import layer, layer_indices import math @@ -31,12 +31,15 @@ class pin_layout: debug.check(self.width() > 0, "Zero width pin.") debug.check(self.height() > 0, "Zero height pin.") + # These are the valid pin layers + valid_layers = { x: layer[x] for x in layer_indices.keys()} + # if it's a string, use the name if type(layer_name_pp) == str: self._layer = layer_name_pp # else it is required to be a lpp else: - for (layer_name, lpp) in layer.items(): + for (layer_name, lpp) in valid_layers.items(): if not lpp: continue if self.same_lpp(layer_name_pp, lpp): From 4e7e0c5954316b3d3d0ef1f0a31a6f20a94c4905 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 29 Jun 2020 15:28:16 -0700 Subject: [PATCH 484/521] Skip test in sky130 --- compiler/tests/14_replica_bitcell_array_1rw_1r_test.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py index a36fc80f..626725c4 100755 --- a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py @@ -28,9 +28,11 @@ class replica_bitcell_array_1rw_1r_test(openram_test): a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0, 1]) self.local_check(a) - debug.info(2, "Testing 4x4 array for cell_1rw_1r") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1]) - self.local_check(a) + # Sky 130 has restrictions on the symmetries + if OPTS.tech_name != "sky130": + debug.info(2, "Testing 4x4 array for cell_1rw_1r") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1]) + self.local_check(a) globals.end_openram() From bec948dcc3d08caab36e9937f73ebb55d511c0e5 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 29 Jun 2020 15:28:55 -0700 Subject: [PATCH 485/521] Fix error in when to add vias for array power --- compiler/modules/replica_bitcell_array.py | 6 +++++- compiler/modules/replica_column.py | 6 ++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 09a014ce..0c7e412e 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -381,7 +381,7 @@ class replica_bitcell_array(design.design): # vdd/gnd are only connected in the perimeter cells # replica column should only have a vdd/gnd in the dummy cell on top/bottom supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst, - self.dummy_row_top_inst, self.dummy_row_bot_inst] + list(self.replica_col_inst.values()) + self.dummy_row_top_inst, self.dummy_row_bot_inst] for pin_name in ["vdd", "gnd"]: for inst in supply_insts: pin_list = inst.get_pins(pin_name) @@ -390,6 +390,10 @@ class replica_bitcell_array(design.design): loc=pin.center(), directions=("V", "V"), start_layer=pin.layer) + + for inst in list(self.replica_col_inst.values()): + self.copy_layout_pin(inst, pin_name) + self.copy_layout_pin(inst, pin_name) def get_rbl_wl_name(self, port): """ Return the WL for the given RBL port """ diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 9cd65e57..9613e6fa 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -184,9 +184,11 @@ class replica_column(design.design): height=wl_pin.height()) # Supplies are only connected in the ends - for inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]: + for (index, inst) in self.cell_inst.items(): for pin_name in ["vdd", "gnd"]: - if pin_name in inst.mod.pins: + if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]: + self.copy_power_pins(inst, pin_name) + else: self.copy_layout_pin(inst, pin_name) def get_bitcell_pins(self, col, row): From 459e3789b815ddf7c3332d3a555dc0c912bdf6f4 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 29 Jun 2020 16:23:25 -0700 Subject: [PATCH 486/521] Change control layers in sky130. --- compiler/modules/bank.py | 32 +++++++---- compiler/modules/precharge_array.py | 28 +++++----- compiler/modules/sense_amp_array.py | 25 ++++++--- .../modules/single_level_column_mux_array.py | 56 ++++++++++--------- 4 files changed, 84 insertions(+), 57 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index e18660e3..5716986f 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -592,6 +592,18 @@ class bank(design.design): self.copy_power_pins(inst, "vdd", add_vias=False) self.copy_power_pins(inst, "gnd", add_vias=False) + # If we use the pinvbuf as the decoder, we need to add power pins. + # Other decoders already have them. + if self.col_addr_size == 1: + for port in self.all_ports: + inst = self.column_decoder_inst[port] + for pin_name in ["vdd", "gnd"]: + pin_list = inst.get_pins(pin_name) + for pin in pin_list: + self.add_power_pin(pin_name, + pin.center(), + start_layer=pin.layer) + def route_bank_select(self, port): """ Route the bank select logic. """ @@ -862,6 +874,13 @@ class bank(design.design): if not self.col_addr_size>0: return + if OPTS.tech_name == "sky130": + stack = self.m2_stack + pitch = self.m3_pitch + else: + stack = self.m1_stack + pitch = self.m2_pitch + if self.col_addr_size == 1: # Connect to sel[0] and sel[1] @@ -881,9 +900,9 @@ class bank(design.design): self.copy_layout_pin(self.column_decoder_inst[port], decoder_name, addr_name) if port % 2: - offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines * self.m2_nonpref_pitch, 0) + offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines * pitch, 0) else: - offset = self.column_decoder_inst[port].lr() + vector(self.m2_nonpref_pitch, 0) + offset = self.column_decoder_inst[port].lr() + vector(pitch, 0) decode_pins = [self.column_decoder_inst[port].get_pin(x) for x in decode_names] @@ -891,16 +910,9 @@ class bank(design.design): column_mux_pins = [self.port_data_inst[port].get_pin(x) for x in sel_names] route_map = list(zip(decode_pins, column_mux_pins)) - if "li" in layer: - stack = self.li_stack - directions = "pref" - else: - stack = self.m1_stack - directions = "pref" self.create_vertical_channel_route(route_map, offset, - stack, - directions=directions) + stack) def add_lvs_correspondence_points(self): """ diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 3a3b8c8b..d37de64f 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -30,6 +30,11 @@ class precharge_array(design.design): self.bitcell_br = bitcell_br self.column_offset = column_offset + if OPTS.tech_name == "sky130": + self.en_bar_layer = "m3" + else: + self.en_bar_layer = "m1" + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -74,21 +79,18 @@ class precharge_array(design.design): def add_layout_pins(self): - en_bar_pin = self.pc_cell.get_pin("en_bar") - if en_bar_pin.layer =="li": - en_bar_layer = "m3" - else: - en_bar_layer = en_bar_pin.layer - r = self.add_layout_pin(text="en_bar", - layer=en_bar_layer, - offset=en_bar_pin.ll(), - width=self.width, - height=en_bar_pin.height()) - self.add_via_stack_center(from_layer=en_bar_pin.layer, - to_layer=en_bar_layer, - offset = r.center()) + en_pin = self.pc_cell.get_pin("en_bar") + start_offset = en_pin.lc().scale(0, 1) + end_offset = start_offset + vector(self.width, 0) + self.add_layout_pin_segment_center(text="en_bar", + layer=self.en_bar_layer, + start=start_offset, + end=end_offset) for inst in self.local_insts: + self.add_via_stack_center(from_layer=en_pin.layer, + to_layer=self.en_bar_layer, + offset=inst.get_pin("en_bar").center()) self.copy_layout_pin(inst, "vdd") for i in range(len(self.local_insts)): diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 5d41b2a0..98cbee66 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -37,6 +37,11 @@ class sense_amp_array(design.design): self.column_offset = column_offset self.row_size = self.word_size * self.words_per_row + if OPTS.tech_name == "sky130": + self.en_layer = "m3" + else: + self.en_layer = "m1" + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -173,14 +178,18 @@ class sense_amp_array(design.design): height=dout_pin.height()) def route_rails(self): - # add sclk rail across entire array - sclk = self.amp.get_pin(self.amp.en_name) - sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0, 1) - self.add_layout_pin(text=self.en_name, - layer=sclk.layer, - offset=sclk_offset, - width=self.width, - height=drc("minwidth_" + sclk.layer)) + # Add enable across the array + en_pin = self.amp.get_pin(self.amp.en_name) + start_offset = en_pin.lc().scale(0, 1) + end_offset = start_offset + vector(self.width, 0) + self.add_layout_pin_segment_center(text=self.en_name, + layer=self.en_layer, + start=start_offset, + end=end_offset) + for inst in self.local_insts: + self.add_via_stack_center(from_layer=en_pin.layer, + to_layer=self.en_layer, + offset=inst.get_pin(self.amp.en_name).center()) def input_load(self): return self.amp.input_load() diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 37fd4dc1..8b01d111 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -32,14 +32,16 @@ class single_level_column_mux_array(design.design): self.bitcell_br = bitcell_br self.column_offset = column_offset - if "li" in layer: - self.col_mux_stack = self.m1_stack[::-1] - self.col_mux_stack_pitch = self.m2_pitch + if OPTS.tech_name == "sky130": + self.sel_layer = "m3" + self.sel_pitch = self.m3_pitch + self.bitline_layer = "m1" else: - self.col_mux_stack = self.m1_stack - self.col_mux_stack_pitch = self.m1_pitch + self.sel_layer = "m1" + self.sel_pitch = self.m2_pitch + self.bitline_layer = "m2" - if preferred_directions[self.col_mux_stack[0]] == "V": + if preferred_directions[self.sel_layer] == "V": self.via_directions = ("H", "H") else: self.via_directions = "pref" @@ -96,7 +98,7 @@ class single_level_column_mux_array(design.design): self.width = self.columns * self.mux.width # one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br # one extra route pitch is to space from the sense amp - self.route_height = (self.words_per_row + 3) * self.col_mux_stack_pitch + self.route_height = (self.words_per_row + 3) * self.sel_pitch def create_array(self): self.mux_inst = [] @@ -157,9 +159,9 @@ class single_level_column_mux_array(design.design): def add_horizontal_input_rail(self): """ Create address input rails below the mux transistors """ for j in range(self.words_per_row): - offset = vector(0, self.route_height + (j - self.words_per_row) * self.col_mux_stack_pitch) + offset = vector(0, self.route_height + (j - self.words_per_row) * self.sel_pitch) self.add_layout_pin(text="sel_{}".format(j), - layer=self.col_mux_stack[0], + layer=self.sel_layer, offset=offset, width=self.mux.width * self.columns) @@ -178,7 +180,7 @@ class single_level_column_mux_array(design.design): offset = vector(gate_offset.x, self.get_pin("sel_{}".format(sel_index)).cy()) self.add_via_stack_center(from_layer="poly", - to_layer=self.col_mux_stack[0], + to_layer=self.sel_layer, offset=offset, directions=self.via_directions) self.add_path("poly", [offset, gate_offset]) @@ -190,42 +192,44 @@ class single_level_column_mux_array(design.design): bl_offset_begin = self.mux_inst[j].get_pin("bl_out").bc() br_offset_begin = self.mux_inst[j].get_pin("br_out").bc() - bl_out_offset_begin = bl_offset_begin - vector(0, (self.words_per_row + 1) * self.col_mux_stack_pitch) - br_out_offset_begin = br_offset_begin - vector(0, (self.words_per_row + 2) * self.col_mux_stack_pitch) + bl_out_offset_begin = bl_offset_begin - vector(0, (self.words_per_row + 1) * self.sel_pitch) + br_out_offset_begin = br_offset_begin - vector(0, (self.words_per_row + 2) * self.sel_pitch) # Add the horizontal wires for the first bit if j % self.words_per_row == 0: bl_offset_end = self.mux_inst[j + self.words_per_row - 1].get_pin("bl_out").bc() br_offset_end = self.mux_inst[j + self.words_per_row - 1].get_pin("br_out").bc() - bl_out_offset_end = bl_offset_end - vector(0, (self.words_per_row + 1) * self.col_mux_stack_pitch) - br_out_offset_end = br_offset_end - vector(0, (self.words_per_row + 2) * self.col_mux_stack_pitch) + bl_out_offset_end = bl_offset_end - vector(0, (self.words_per_row + 1) * self.sel_pitch) + br_out_offset_end = br_offset_end - vector(0, (self.words_per_row + 2) * self.sel_pitch) - self.add_path(self.col_mux_stack[0], [bl_out_offset_begin, bl_out_offset_end]) - self.add_path(self.col_mux_stack[0], [br_out_offset_begin, br_out_offset_end]) + self.add_path(self.sel_layer, [bl_out_offset_begin, bl_out_offset_end]) + self.add_path(self.sel_layer, [br_out_offset_begin, br_out_offset_end]) # Extend the bitline output rails and gnd downward on the first bit of each n-way mux self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j / self.words_per_row)), - layer=self.col_mux_stack[2], + layer=self.bitline_layer, start=bl_offset_begin, end=bl_out_offset_begin) self.add_layout_pin_segment_center(text="br_out_{}".format(int(j / self.words_per_row)), - layer=self.col_mux_stack[2], + layer=self.bitline_layer, start=br_offset_begin, end=br_out_offset_begin) else: - self.add_path(self.col_mux_stack[2], [bl_out_offset_begin, bl_offset_begin]) - self.add_path(self.col_mux_stack[2], [br_out_offset_begin, br_offset_begin]) + self.add_path(self.bitline_layer, [bl_out_offset_begin, bl_offset_begin]) + self.add_path(self.bitline_layer, [br_out_offset_begin, br_offset_begin]) # This via is on the right of the wire - self.add_via_center(layers=self.col_mux_stack, - offset=bl_out_offset_begin, - directions=self.via_directions) + self.add_via_stack_center(from_layer=self.bitline_layer, + to_layer=self.sel_layer, + offset=bl_out_offset_begin, + directions=self.via_directions) # This via is on the left of the wire - self.add_via_center(layers=self.col_mux_stack, - offset=br_out_offset_begin, - directions=self.via_directions) + self.add_via_stack_center(from_layer=self.bitline_layer, + to_layer=self.sel_layer, + offset=br_out_offset_begin, + directions=self.via_directions) def get_drain_cin(self): """Get the relative capacitance of the drain of the NMOS pass TX""" From 372a8a728efb4f0a5cf4af636446626305193a16 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 29 Jun 2020 16:47:34 -0700 Subject: [PATCH 487/521] Off by one error in channel spacing --- compiler/modules/bank.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 5716986f..390d17a3 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -900,7 +900,7 @@ class bank(design.design): self.copy_layout_pin(self.column_decoder_inst[port], decoder_name, addr_name) if port % 2: - offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines * pitch, 0) + offset = self.column_decoder_inst[port].ll() - vector((self.num_col_addr_lines + 1) * pitch, 0) else: offset = self.column_decoder_inst[port].lr() + vector(pitch, 0) From c289637dabca66c3ad8660a9a976bc19920e512c Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 29 Jun 2020 23:18:31 -0700 Subject: [PATCH 488/521] Allowed sen's from multiple ports to be characterized --- compiler/base/graph_util.py | 2 ++ compiler/characterizer/delay.py | 38 +++++++++++++++++++++++++-------- 2 files changed, 31 insertions(+), 9 deletions(-) diff --git a/compiler/base/graph_util.py b/compiler/base/graph_util.py index 5d1ee692..7ad6249c 100644 --- a/compiler/base/graph_util.py +++ b/compiler/base/graph_util.py @@ -65,6 +65,8 @@ class timing_graph(): # Call the recursive helper function to print all paths self.get_all_paths_util(src_node, dest_node, visited, path) debug.info(2, "Paths found={}".format(len(self.all_paths))) + for path in self.all_paths: + debug.info(2, "Paths ={}".format(path)) if reduce_paths: self.reduce_paths() diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index b5214198..202a0751 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -69,6 +69,8 @@ class delay(simulation): self.read_meas_lists = self.create_read_port_measurement_objects() self.write_meas_lists = self.create_write_port_measurement_objects() + debug.info(1,self.write_meas_lists) + debug.info(1,self.read_meas_lists) self.check_meas_names(self.read_meas_lists+self.write_meas_lists) def check_meas_names(self, measures_lists): @@ -124,6 +126,7 @@ class delay(simulation): # Other measurements associated with the read port not included in the liberty file read_measures.append(self.create_bitline_measurement_objects()) read_measures.append(self.create_debug_measurement_objects()) + debug.info(1,"debug "+str(read_measures[-1])) read_measures.append(self.create_read_bit_measures()) return read_measures @@ -138,17 +141,17 @@ class delay(simulation): self.bitline_volt_meas = [] self.bitline_volt_meas.append(voltage_at_measure("v_bl_READ_ZERO", - self.bl_name)) + self.bl_name+"{}")) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ZERO self.bitline_volt_meas.append(voltage_at_measure("v_br_READ_ZERO", - self.br_name)) + self.br_name+"{}")) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ZERO self.bitline_volt_meas.append(voltage_at_measure("v_bl_READ_ONE", - self.bl_name)) + self.bl_name+"{}")) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ONE self.bitline_volt_meas.append(voltage_at_measure("v_br_READ_ONE", - self.br_name)) + self.br_name+"{}")) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ONE return self.bitline_volt_meas @@ -182,11 +185,12 @@ class delay(simulation): meas.targ_name_no_port)) self.dout_volt_meas[-1].meta_str = meas.meta_str - self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name, "FALL", "RISE", measure_scale=1e9) + self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9) self.sen_meas.meta_str = sram_op.READ_ZERO self.sen_meas.meta_add_delay = True + self.dout_volt_meas.append(self.sen_meas) - return self.dout_volt_meas+[self.sen_meas] + return self.dout_volt_meas def create_read_bit_measures(self): """ Adds bit measurements for read0 and read1 cycles """ @@ -265,6 +269,7 @@ class delay(simulation): self.graph = graph_util.timing_graph() self.sram_spc_name = "X{}".format(self.sram.name) self.sram.build_graph(self.graph,self.sram_spc_name,self.pins) + debug.info(1,self.graph.all_paths) def set_internal_spice_names(self): """Sets important names for characterization such as Sense amp enable and internal bit nets.""" @@ -273,13 +278,27 @@ class delay(simulation): self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) - self.sen_name = self.get_sen_name(self.graph.all_paths) + sen_with_port = self.get_sen_name(self.graph.all_paths) + if sen_with_port.endswith(str(port)): + self.sen_name = sen_with_port[:-len(str(port))] + else: + self.sen_name = sen_with_port + debug.info(2,"s_en name = {}".format(self.sen_name)) - self.bl_name,self.br_name = self.get_bl_name(self.graph.all_paths, port) + bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port) + if bl_name_port.endswith(str(port)): + self.bl_name = bl_name_port[:-len(str(port))] + else: + self.bl_name = bl_name_port + + if br_name_port.endswith(str(port)): + self.br_name = br_name_port[:-len(str(port))] + else: + self.br_name = br_name_port debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) - def get_sen_name(self, paths): + def get_sen_name(self, paths, assumed_port=None): """ Gets the signal name associated with the sense amp enable from input paths. Only expects a single path to contain the sen signal name. @@ -291,6 +310,7 @@ class delay(simulation): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) + return sen_name def get_bl_name(self, paths, port): From 0464e2df5dd0b9bfcff55ac7286a796c656f1f54 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 30 Jun 2020 01:37:52 -0700 Subject: [PATCH 489/521] Allowed bitline checks for multiple ports. --- compiler/base/graph_util.py | 2 -- compiler/characterizer/delay.py | 49 +++++++++++++++++---------------- 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/compiler/base/graph_util.py b/compiler/base/graph_util.py index 7ad6249c..5d1ee692 100644 --- a/compiler/base/graph_util.py +++ b/compiler/base/graph_util.py @@ -65,8 +65,6 @@ class timing_graph(): # Call the recursive helper function to print all paths self.get_all_paths_util(src_node, dest_node, visited, path) debug.info(2, "Paths found={}".format(len(self.all_paths))) - for path in self.all_paths: - debug.info(2, "Paths ={}".format(path)) if reduce_paths: self.reduce_paths() diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 202a0751..b647e6e9 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -69,8 +69,6 @@ class delay(simulation): self.read_meas_lists = self.create_read_port_measurement_objects() self.write_meas_lists = self.create_write_port_measurement_objects() - debug.info(1,self.write_meas_lists) - debug.info(1,self.read_meas_lists) self.check_meas_names(self.read_meas_lists+self.write_meas_lists) def check_meas_names(self, measures_lists): @@ -126,7 +124,6 @@ class delay(simulation): # Other measurements associated with the read port not included in the liberty file read_measures.append(self.create_bitline_measurement_objects()) read_measures.append(self.create_debug_measurement_objects()) - debug.info(1,"debug "+str(read_measures[-1])) read_measures.append(self.create_read_bit_measures()) return read_measures @@ -141,17 +138,17 @@ class delay(simulation): self.bitline_volt_meas = [] self.bitline_volt_meas.append(voltage_at_measure("v_bl_READ_ZERO", - self.bl_name+"{}")) + self.bl_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ZERO self.bitline_volt_meas.append(voltage_at_measure("v_br_READ_ZERO", - self.br_name+"{}")) + self.br_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ZERO self.bitline_volt_meas.append(voltage_at_measure("v_bl_READ_ONE", - self.bl_name+"{}")) + self.bl_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ONE self.bitline_volt_meas.append(voltage_at_measure("v_br_READ_ONE", - self.br_name+"{}")) + self.br_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ONE return self.bitline_volt_meas @@ -236,9 +233,10 @@ class delay(simulation): qbar_name = cell_name+'.'+str(storage_names[1]) # Bit measures, measurements times to be defined later. The measurement names must be unique - # but they is enforced externally - q_meas = voltage_at_measure("v_q_{}".format(meas_tag), q_name, has_port=False) - qbar_meas = voltage_at_measure("v_qbar_{}".format(meas_tag), qbar_name, has_port=False) + # but they is enforced externally. {} added to names to differentiate between ports allow the + # measurements are independent of the ports + q_meas = voltage_at_measure("v_q_{}{}".format(meas_tag, "{}"), q_name) + qbar_meas = voltage_at_measure("v_qbar_{}{}".format(meas_tag, "{}"), qbar_name) return {bit_polarity.NONINVERTING:q_meas, bit_polarity.INVERTING:qbar_meas} @@ -269,7 +267,6 @@ class delay(simulation): self.graph = graph_util.timing_graph() self.sram_spc_name = "X{}".format(self.sram.name) self.sram.build_graph(self.graph,self.sram_spc_name,self.pins) - debug.info(1,self.graph.all_paths) def set_internal_spice_names(self): """Sets important names for characterization such as Sense amp enable and internal bit nets.""" @@ -283,19 +280,24 @@ class delay(simulation): self.sen_name = sen_with_port[:-len(str(port))] else: self.sen_name = sen_with_port + debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.") debug.info(2,"s_en name = {}".format(self.sen_name)) bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port) - if bl_name_port.endswith(str(port)): - self.bl_name = bl_name_port[:-len(str(port))] + port_pos = -1-len(str(self.probe_data))-len(str(port)) + if bl_name_port.endswith(str(port)+"_"+str(self.probe_data)): + self.bl_name = bl_name_port[:port_pos] +"{}"+ bl_name_port[port_pos+len(str(port)):] else: self.bl_name = bl_name_port + debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") - if br_name_port.endswith(str(port)): - self.br_name = br_name_port[:-len(str(port))] + if br_name_port.endswith(str(port)+"_"+str(self.probe_data)): + port_pos = -1-len(str(self.probe_data))-len(str(port)) + self.br_name = br_name_port[:port_pos] +"{}"+ br_name_port[port_pos+len(str(port)):] else: self.br_name = br_name_port + debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) def get_sen_name(self, paths, assumed_port=None): @@ -763,13 +765,10 @@ class delay(simulation): # Loop through all targeted ports and collect delays and powers. result = [{} for i in self.all_ports] - - # First, check that the memory has the right values at the right times - if not self.check_bit_measures(self.read_bit_meas) or \ - not self.check_bit_measures(self.write_bit_meas): - return(False,{}) - for port in self.targ_write_ports: + if not self.check_bit_measures(self.write_bit_meas, port): + return(False,{}) + debug.info(2, "Checking write values for port {}".format(port)) write_port_dict = {} for measure in self.write_lib_meas: @@ -781,6 +780,10 @@ class delay(simulation): for port in self.targ_read_ports: + # First, check that the memory has the right values at the right times + if not self.check_bit_measures(self.read_bit_meas, port): + return(False,{}) + debug.info(2, "Checking read delay values for port {}".format(port)) # Check sen timing, then bitlines, then general measurements. if not self.check_sen_measure(port): @@ -857,7 +860,7 @@ class delay(simulation): return dout_success - def check_bit_measures(self, bit_measures): + def check_bit_measures(self, bit_measures, port): """ Checks the measurements which represent the internal storage voltages at the end of the read cycle. @@ -865,7 +868,7 @@ class delay(simulation): success = False for polarity, meas_list in bit_measures.items(): for meas in meas_list: - val = meas.retrieve_measure() + val = meas.retrieve_measure(port=port) debug.info(2,"{}={}".format(meas.name, val)) if type(val) != float: continue From 9b939c9a1a3c9890f299d038da47e7e420a97604 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 30 Jun 2020 07:16:05 -0700 Subject: [PATCH 490/521] DRC/LVS and errors fixes. Only enact pdb if assert fails in debug.error. Only run drc/lvs one time in parse_info by saving result. Cleanup drc/lvs output. --- compiler/base/hierarchy_design.py | 6 +++++- compiler/characterizer/lib.py | 8 ++++++-- compiler/debug.py | 2 +- compiler/verify/calibre.py | 25 +++++++++++-------------- compiler/verify/magic.py | 5 +++-- 5 files changed, 26 insertions(+), 20 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 1321f06a..b0370179 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -7,7 +7,6 @@ # import hierarchy_layout import hierarchy_spice -import verify import debug import os from globals import OPTS @@ -55,6 +54,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): def DRC_LVS(self, final_verification=False, force_check=False): """Checks both DRC and LVS for a module""" + import verify # No layout to check if OPTS.netlist_only: @@ -94,6 +94,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): def DRC(self, final_verification=False): """Checks DRC for a module""" + import verify + # Unit tests will check themselves. # Do not run if disabled in options. @@ -117,6 +119,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): def LVS(self, final_verification=False): """Checks LVS for a module""" + import verify + # Unit tests will check themselves. # Do not run if disabled in options. diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index b0df4394..92882db7 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -657,8 +657,12 @@ class lib: )) # information of checks - (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True) - datasheet.write("{0},{1},".format(drc_errors, lvs_errors)) + # run it only the first time + try: + datasheet.write("{0},{1},".format(self.drc_errors, self.lvs_errors)) + except AttributeError: + (self.drc_errors, self.lvs_errors) = self.sram.DRC_LVS(final_verification=True) + datasheet.write("{0},{1},".format(self.drc_errors, self.lvs_errors)) # write area datasheet.write(str(self.sram.width * self.sram.height) + ',') diff --git a/compiler/debug.py b/compiler/debug.py index a902bca0..f07471cc 100644 --- a/compiler/debug.py +++ b/compiler/debug.py @@ -40,7 +40,7 @@ def error(str, return_value=0): log("ERROR: file {0}: line {1}: {2}\n".format( os.path.basename(filename), line_number, str)) - if globals.OPTS.debug_level > 0: + if globals.OPTS.debug_level > 0 and return_value != 0: import pdb pdb.set_trace() assert return_value == 0 diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 0a975599..443c91ca 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -219,16 +219,14 @@ def run_drc(cell_name, gds_name, extract=False, final_verification=False): errors = int(re.split(r'\W+', results[2])[5]) # always display this summary - if errors > 0: - debug.error("{0}\tGeometries: {1}\tChecks: {2}\tErrors: {3}".format(cell_name, + result_str = "{0}\tGeometries: {1}\tChecks: {2}\tErrors: {3}".format(cell_name, geometries, rulechecks, - errors)) + errors) + if errors > 0: + debug.warning(result_str) else: - debug.info(1, "{0}\tGeometries: {1}\tChecks: {2}\tErrors: {3}".format(cell_name, - geometries, - rulechecks, - errors)) + debug.info(1, result_str) return errors @@ -307,16 +305,15 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): out_errors = len(stdouterrors) total_errors = summary_errors + out_errors + ext_errors - if total_errors > 0: - debug.error("{0}\tSummary: {1}\tOutput: {2}\tExtraction: {3}".format(cell_name, + # always display this summary + result_str = "{0}\tSummary: {1}\tOutput: {2}\tExtraction: {3}".format(cell_name, summary_errors, out_errors, - ext_errors)) + ext_errors) + if total_errors > 0: + debug.warning(result_str) else: - debug.info(1, "{0}\tSummary: {1}\tOutput: {2}\tExtraction: {3}".format(cell_name, - summary_errors, - out_errors, - ext_errors)) + debug.info(1, result_str) return total_errors diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index e20c0499..5df6e698 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -200,13 +200,14 @@ def run_drc(cell_name, gds_name, extract=True, final_verification=False): # always display this summary + result_str = "DRC Errors {0}\t{1}".format(cell_name, errors) if errors > 0: for line in results: if "error tiles" in line: debug.info(1,line.rstrip("\n")) - debug.error("DRC Errors {0}\t{1}".format(cell_name, errors)) + debug.warning(result_str) else: - debug.info(1, "DRC Errors {0}\t{1}".format(cell_name, errors)) + debug.info(1, result_str) return errors From 8cedeeb3d945c77157c9977668a33751564983e9 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 30 Jun 2020 10:57:41 -0700 Subject: [PATCH 491/521] Widen pitch of control bus in bank. --- compiler/base/hierarchy_layout.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 378a4657..c57de915 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1135,6 +1135,7 @@ class layout(): size=size, offset=loc, directions=directions) + # Hack for min area if OPTS.tech_name == "sky130": width = round_to_grid(sqrt(drc["minarea_m3"])) From eb11ac22f3c3d5a2198817d25e1be500138cf7ec Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 30 Jun 2020 10:58:09 -0700 Subject: [PATCH 492/521] Widen pitch of control bus in bank. --- compiler/modules/bank.py | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 390d17a3..158ac37b 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -316,7 +316,7 @@ class bank(design.design): self.input_control_signals = [] port_num = 0 for port in range(OPTS.num_rw_ports): - self.input_control_signals.append(["w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)]) + self.input_control_signals.append(["s_en{}".format(port_num), "w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_w_ports): self.input_control_signals.append(["w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)]) @@ -329,7 +329,7 @@ class bank(design.design): self.num_control_lines = [len(x) for x in self.input_control_signals] # The width of this bus is needed to place other modules (e.g. decoder) for each port - self.central_bus_width = [self.m2_pitch * x + self.m2_width for x in self.num_control_lines] + self.central_bus_width = [self.m3_pitch * x + self.m3_width for x in self.num_control_lines] # These will be outputs of the gaters if this is multibank, if not, normal signals. self.control_signals = [] @@ -338,6 +338,7 @@ class bank(design.design): self.control_signals.append(["gated_" + str for str in self.input_control_signals[port]]) else: self.control_signals.append(self.input_control_signals[port]) + # The central bus is the column address (one hot) and row address (binary) if self.col_addr_size>0: @@ -672,7 +673,8 @@ class bank(design.design): names=self.control_signals[0], length=control_bus_length, vertical=True, - make_pins=(self.num_banks==1)) + make_pins=(self.num_banks==1), + pitch=self.m3_pitch) # Port 1 if len(self.all_ports)==2: @@ -686,7 +688,8 @@ class bank(design.design): names=list(reversed(self.control_signals[1])), length=control_bus_length, vertical=True, - make_pins=(self.num_banks==1)) + make_pins=(self.num_banks==1), + pitch=self.m3_pitch) def route_port_data_to_bitcell_array(self, port): """ Routing of BL and BR between port data and bitcell array """ From 5626fd182e2c993ed107154c809802db28c3f68c Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 30 Jun 2020 10:58:24 -0700 Subject: [PATCH 493/521] Extra track in data bus. Remove old code. --- compiler/sram/sram_1bank.py | 146 +----------------------------------- 1 file changed, 3 insertions(+), 143 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index ac86eb94..cdc5ab92 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -73,10 +73,11 @@ class sram_1bank(sram_base): self.data_bus_gap = self.m4_nonpref_pitch * 2 # Spare wen are on a separate layer so not included - self.data_bus_size = [None] * len(self.all_ports) + # Start with 1 track minimum + self.data_bus_size = [1] * len(self.all_ports) for port in self.all_ports: # All ports need the col addr flops - self.data_bus_size[port] = self.col_addr_size + self.data_bus_size[port] += self.col_addr_size # Write ports need the data input flops and write mask flops if port in self.write_ports: self.data_bus_size[port] += self.num_wmasks + self.word_size @@ -324,16 +325,6 @@ class sram_1bank(sram_base): self.route_row_addr_dff() - # if self.col_addr_dff: - # self.route_col_addr_dff() - - # self.route_data_dff() - - # if self.write_size: - # self.route_wmask_dff() - - # if self.num_spare_cols: - # self.route_spare_wen_dff() for port in self.all_ports: self.route_dff(port) @@ -488,137 +479,6 @@ class sram_1bank(sram_base): offset=mid_pos) self.add_path(bank_pin.layer, [mid_pos, bank_pos]) - def route_col_addr_dff(self): - """ Connect the output of the col flops to the bank pins """ - for port in self.all_ports: - if port % 2: - offset = self.col_addr_dff_insts[port].ll() - vector(0, self.col_addr_bus_size) - else: - offset = self.col_addr_dff_insts[port].ul() + vector(0, self.col_addr_bus_gap) - - bus_names = ["addr_{}".format(x) for x in range(self.col_addr_size)] - col_addr_bus_offsets = self.create_horizontal_bus(layer="m1", - offset=offset, - names=bus_names, - length=self.col_addr_dff_insts[port].width) - - dff_names = ["dout_{}".format(x) for x in range(self.col_addr_size)] - data_dff_map = zip(dff_names, bus_names) - self.connect_horizontal_bus(data_dff_map, - self.col_addr_dff_insts[port], - col_addr_bus_offsets) - - bank_names = ["addr{0}_{1}".format(port, x) for x in range(self.col_addr_size)] - data_bank_map = zip(bank_names, bus_names) - self.connect_horizontal_bus(data_bank_map, - self.bank_inst, - col_addr_bus_offsets) - - def route_data_dff(self): - """ Connect the output of the data flops to the write driver """ - # This is where the channel will start (y-dimension at least) - for port in self.write_ports: - if port % 2: - offset = self.data_dff_insts[port].ll() - vector(0, self.data_bus_size[port]) - else: - offset = self.data_dff_insts[port].ul() + vector(0, self.data_bus_gap) - - dff_names = ["dout_{}".format(x) for x in range(self.word_size + self.num_spare_cols)] - dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] - if self.write_size or self.num_spare_cols: - for x in dff_names: - pin = self.data_dff_insts[port].get_pin(x) - pin_offset = pin.center() - self.add_via_center(layers=self.m1_stack, - offset=pin_offset, - directions=("V", "V")) - self.add_via_stack_center(from_layer="m2", - to_layer="m4", - offset=pin_offset) - - bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)] - bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] - if self.write_size or self.num_spare_cols: - for x in bank_names: - pin = self.bank_inst.get_pin(x) - if port % 2: - pin_offset = pin.uc() - else: - pin_offset = pin.bc() - self.add_via_stack_center(from_layer=pin.layer, - to_layer="m4", - offset=pin_offset) - - route_map = list(zip(bank_pins, dff_pins)) - if self.write_size or self.num_spare_cols: - layer_stack = self.m3_stack - else: - layer_stack = self.m1_stack - - self.create_horizontal_channel_route(netlist=route_map, - offset=offset, - layer_stack=layer_stack) - - def route_wmask_dff(self): - """ Connect the output of the wmask flops to the write mask AND array """ - # This is where the channel will start (y-dimension at least) - for port in self.write_ports: - if port % 2: - offset = self.wmask_dff_insts[port].ll() - vector(0, self.wmask_bus_size) - else: - offset = self.wmask_dff_insts[port].ul() + vector(0, self.wmask_bus_gap) - - dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)] - dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names] - for x in dff_names: - offset_pin = self.wmask_dff_insts[port].get_pin(x).center() - self.add_via_center(layers=self.m1_stack, - offset=offset_pin, - directions=("V", "V")) - - bank_names = ["bank_wmask{0}_{1}".format(port, x) for x in range(self.num_wmasks)] - bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] - for x in bank_names: - offset_pin = self.bank_inst.get_pin(x).center() - self.add_via_center(layers=self.m1_stack, - offset=offset_pin) - - route_map = list(zip(bank_pins, dff_pins)) - self.create_horizontal_channel_route(netlist=route_map, - offset=offset, - layer_stack=self.m1_stack) - - def route_spare_wen_dff(self): - """ Connect the output of the spare write enable flops to the spare write drivers """ - # This is where the channel will start (y-dimension at least) - for port in self.write_ports: - if port % 2: - # for port 0 - offset = self.spare_wen_dff_insts[port].ll() - vector(0, self.spare_wen_bus_size) - else: - offset = self.spare_wen_dff_insts[port].ul() + vector(0, self.spare_wen_bus_gap) - - dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)] - dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names] - for x in dff_names: - offset_pin = self.spare_wen_dff_insts[port].get_pin(x).center() - self.add_via_center(layers=self.m1_stack, - offset=offset_pin, - directions=("V", "V")) - - bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)] - bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] - for x in bank_names: - offset_pin = self.bank_inst.get_pin(x).center() - self.add_via_center(layers=self.m1_stack, - offset=offset_pin) - - route_map = list(zip(bank_pins, dff_pins)) - self.create_horizontal_channel_route(netlist=route_map, - offset=offset, - layer_stack=self.m1_stack) - - def add_lvs_correspondence_points(self): """ This adds some points for easier debugging if LVS goes wrong. From a48ea522539c8d8a7b1834bd8bfceaabe0a86450 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 30 Jun 2020 13:26:38 -0700 Subject: [PATCH 494/521] Add missing contact to vdd pins. --- compiler/modules/dff_array.py | 87 +++++++++++++++---------------- compiler/modules/dff_buf_array.py | 4 +- 2 files changed, 43 insertions(+), 48 deletions(-) diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 62464834..d3f9b68e 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -7,12 +7,11 @@ # import debug import design -from tech import drc -from math import log from vector import vector from sram_factory import factory from globals import OPTS + class dff_array(design.design): """ This is a simple row (or multiple rows) of flops. @@ -52,42 +51,41 @@ class dff_array(design.design): self.add_mod(self.dff) def add_pins(self): - for row in range(self.rows): + for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_din_name(row,col), "INPUT") - for row in range(self.rows): + self.add_pin(self.get_din_name(row, col), "INPUT") + for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_dout_name(row,col), "OUTPUT") + self.add_pin(self.get_dout_name(row, col), "OUTPUT") self.add_pin("clk", "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") def create_dff_array(self): self.dff_insts={} - for row in range(self.rows): + for row in range(self.rows): for col in range(self.columns): - name = "dff_r{0}_c{1}".format(row,col) - self.dff_insts[row,col]=self.add_inst(name=name, - mod=self.dff) - instance_ports = [self.get_din_name(row,col), - self.get_dout_name(row,col)] + name = "dff_r{0}_c{1}".format(row, col) + self.dff_insts[row, col]=self.add_inst(name=name, + mod=self.dff) + instance_ports = [self.get_din_name(row, col), + self.get_dout_name(row, col)] for port in self.dff.pin_names: if port != 'D' and port != 'Q': instance_ports.append(port) self.connect_inst(instance_ports) def place_dff_array(self): - for row in range(self.rows): + for row in range(self.rows): for col in range(self.columns): - name = "dff_r{0}_c{1}".format(row,col) if (row % 2 == 0): - base = vector(col*self.dff.width,row*self.dff.height) + base = vector(col * self.dff.width, row * self.dff.height) mirror = "R0" else: - base = vector(col*self.dff.width,(row+1)*self.dff.height) + base = vector(col * self.dff.width, (row + 1) * self.dff.height) mirror = "MX" - self.dff_insts[row,col].place(offset=base, - mirror=mirror) + self.dff_insts[row, col].place(offset=base, + mirror=mirror) def get_din_name(self, row, col): if self.columns == 1: @@ -95,7 +93,7 @@ class dff_array(design.design): elif self.rows == 1: din_name = "din_{0}".format(col) else: - din_name = "din_{0}_{1}".format(row,col) + din_name = "din_{0}_{1}".format(row, col) return din_name @@ -105,61 +103,58 @@ class dff_array(design.design): elif self.rows == 1: dout_name = "dout_{0}".format(col) else: - dout_name = "dout_{0}_{1}".format(row,col) + dout_name = "dout_{0}_{1}".format(row, col) return dout_name - def add_layout_pins(self): for row in range(self.rows): - for col in range(self.columns): + for col in range(self.columns): # Continous vdd rail along with label. - vdd_pin=self.dff_insts[row,col].get_pin("vdd") - self.add_power_pin("vdd", vdd_pin.center()) + vdd_pin=self.dff_insts[row, col].get_pin("vdd") + self.add_power_pin("vdd", vdd_pin.center(), start_layer=vdd_pin.layer) # Continous gnd rail along with label. - gnd_pin=self.dff_insts[row,col].get_pin("gnd") - self.add_power_pin("gnd", gnd_pin.center()) + gnd_pin=self.dff_insts[row, col].get_pin("gnd") + self.add_power_pin("gnd", gnd_pin.center(), start_layer=gnd_pin.layer) - - for row in range(self.rows): - for col in range(self.columns): - din_pin = self.dff_insts[row,col].get_pin("D") - debug.check(din_pin.layer=="m2","DFF D pin not on metal2") - self.add_layout_pin(text=self.get_din_name(row,col), + for row in range(self.rows): + for col in range(self.columns): + din_pin = self.dff_insts[row, col].get_pin("D") + debug.check(din_pin.layer == "m2", "DFF D pin not on metal2") + self.add_layout_pin(text=self.get_din_name(row, col), layer=din_pin.layer, offset=din_pin.ll(), width=din_pin.width(), height=din_pin.height()) - dout_pin = self.dff_insts[row,col].get_pin("Q") - debug.check(dout_pin.layer=="m2","DFF Q pin not on metal2") - self.add_layout_pin(text=self.get_dout_name(row,col), + dout_pin = self.dff_insts[row, col].get_pin("Q") + debug.check(dout_pin.layer == "m2", "DFF Q pin not on metal2") + self.add_layout_pin(text=self.get_dout_name(row, col), layer=dout_pin.layer, offset=dout_pin.ll(), width=dout_pin.width(), height=dout_pin.height()) - - # Create vertical spines to a single horizontal rail - clk_pin = self.dff_insts[0,0].get_pin(self.dff.clk_pin) - clk_ypos = 2*self.m3_pitch+self.m3_width - debug.check(clk_pin.layer=="m2","DFF clk pin not on metal2") + clk_pin = self.dff_insts[0, 0].get_pin(self.dff.clk_pin) + clk_ypos = 2 * self.m3_pitch + self.m3_width + debug.check(clk_pin.layer == "m2", "DFF clk pin not on metal2") self.add_layout_pin_segment_center(text="clk", layer="m3", - start=vector(0,clk_ypos), - end=vector(self.width,clk_ypos)) + start=vector(0, clk_ypos), + end=vector(self.width, clk_ypos)) for col in range(self.columns): - clk_pin = self.dff_insts[0,col].get_pin(self.dff.clk_pin) + clk_pin = self.dff_insts[0, col].get_pin(self.dff.clk_pin) # Make a vertical strip for each column self.add_rect(layer="m2", - offset=clk_pin.ll().scale(1,0), + offset=clk_pin.ll().scale(1, 0), width=self.m2_width, height=self.height) # Drop a via to the M3 pin - self.add_via_center(layers=self.m2_stack, - offset=vector(clk_pin.cx(),clk_ypos)) + self.add_via_stack_center(from_layer=clk_pin.layer, + to_layer="m3", + offset=vector(clk_pin.cx(), clk_ypos)) def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index b608cdeb..1cbd9284 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -167,11 +167,11 @@ class dff_buf_array(design.design): for col in range(self.columns): # Continous vdd rail along with label. vdd_pin=self.dff_insts[row, col].get_pin("vdd") - self.add_power_pin("vdd", vdd_pin.lc()) + self.add_power_pin("vdd", vdd_pin.lc(), start_layer=vdd_pin.layer) # Continous gnd rail along with label. gnd_pin=self.dff_insts[row, col].get_pin("gnd") - self.add_power_pin("gnd", gnd_pin.lc()) + self.add_power_pin("gnd", gnd_pin.lc(), start_layer=gnd_pin.layer) def add_layout_pins(self): From 011ac2fc05c89e678103b1e08bf74fa6a3934da9 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 30 Jun 2020 13:57:45 -0700 Subject: [PATCH 495/521] Don't route to clk to perimeter on m2 --- compiler/modules/control_logic.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index d857f24d..74fad6a5 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -523,12 +523,12 @@ class control_logic(design.design): def route_clk_buf(self): clk_pin = self.clk_buf_inst.get_pin("A") clk_pos = clk_pin.center() - self.add_layout_pin_segment_center(text="clk", - layer="m2", - start=clk_pos, - end=clk_pos.scale(1, 0)) - self.add_via_center(layers=self.m1_stack, - offset=clk_pos) + self.add_layout_pin_rect_center(text="clk", + layer="m2", + offset=clk_pos) + self.add_via_stack_center(from_layer=clk_pin.layer, + to_layer="m2", + offset=clk_pos) self.route_output_to_bus_jogged(self.clk_buf_inst, "clk_buf") From c1fedda575517f5fbc35ec36c0665811e2680a8f Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 30 Jun 2020 15:07:34 -0700 Subject: [PATCH 496/521] Modifications for min area metal. Made add_via_stack_center iterative instead of recursive. Removed add_via_stack (non-center) since it isn't used. Add min area metal during iterative via insertion. --- compiler/base/hierarchy_layout.py | 126 ++++++++++++++---------------- compiler/pgates/pwrite_driver.py | 24 +++--- 2 files changed, 69 insertions(+), 81 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index c57de915..a5272ba5 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -13,6 +13,7 @@ from tech import drc, GDS from tech import layer as techlayer from tech import layer_indices from tech import layer_stacks +from tech import preferred_directions import os from globals import OPTS from vector import vector @@ -521,7 +522,6 @@ class layout(): def get_preferred_direction(self, layer): """ Return the preferred routing directions """ - from tech import preferred_directions return preferred_directions[layer] def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None): @@ -567,24 +567,6 @@ class layout(): self.connect_inst([]) return inst - def add_via_stack(self, offset, from_layer, to_layer, - directions=None, - size=[1, 1], - implant_type=None, - well_type=None): - """ - Punch a stack of vias from a start layer to a target layer. - """ - return self.__add_via_stack_internal(offset=offset, - directions=directions, - from_layer=from_layer, - to_layer=to_layer, - via_func=self.add_via, - last_via=None, - size=size, - implant_type=implant_type, - well_type=well_type) - def add_via_stack_center(self, offset, from_layer, @@ -594,24 +576,7 @@ class layout(): implant_type=None, well_type=None): """ - Punch a stack of vias from a start layer to a target layer by the center - coordinate accounting for mirroring and rotation. - """ - return self.__add_via_stack_internal(offset=offset, - directions=directions, - from_layer=from_layer, - to_layer=to_layer, - via_func=self.add_via_center, - last_via=None, - size=size, - implant_type=implant_type, - well_type=well_type) - - def __add_via_stack_internal(self, offset, directions, from_layer, to_layer, - via_func, last_via, size, implant_type=None, well_type=None): - """ - Punch a stack of vias from a start layer to a target layer. Here we - figure out whether to punch it up or down the stack. + Punch a stack of vias from a start layer to a target layer by the center. """ if from_layer == to_layer: @@ -619,38 +584,65 @@ class layout(): # a metal enclosure. This helps with center-line path routing. self.add_rect_center(layer=from_layer, offset=offset) - return last_via + return None - from_id = layer_indices[from_layer] - to_id = layer_indices[to_layer] + via = None + cur_layer = from_layer + while cur_layer != to_layer: + from_id = layer_indices[cur_layer] + to_id = layer_indices[to_layer] - if from_id < to_id: # grow the stack up - search_id = 0 - next_id = 2 - else: # grow the stack down - search_id = 2 - next_id = 0 + if from_id < to_id: # grow the stack up + search_id = 0 + next_id = 2 + else: # grow the stack down + search_id = 2 + next_id = 0 - curr_stack = next(filter(lambda stack: stack[search_id] == from_layer, layer_stacks), None) - if curr_stack is None: - raise ValueError("Cannot create via from '{0}' to '{1}'." - "Layer '{0}' not defined".format(from_layer, to_layer)) + curr_stack = next(filter(lambda stack: stack[search_id] == cur_layer, layer_stacks), None) + + via = self.add_via_center(layers=curr_stack, + size=size, + offset=offset, + directions=directions, + implant_type=implant_type, + well_type=well_type) + + if cur_layer != from_layer: + self.add_min_area_rect_center(cur_layer, + offset, + via.mod.first_layer_width, + via.mod.first_layer_height) + + cur_layer = curr_stack[next_id] - via = via_func(layers=curr_stack, - size=size, - offset=offset, - directions=directions, - implant_type=implant_type, - well_type=well_type) - - via = self.__add_via_stack_internal(offset=offset, - directions=directions, - from_layer=curr_stack[next_id], - to_layer=to_layer, - via_func=via_func, - last_via=via, - size=size) return via + + def add_min_area_rect_center(self, + layer, + offset, + width=None, + height=None): + """ + Add a minimum area retcangle at the given point. + Either width or height should be fixed. + """ + + min_area = drc("minarea_{}".format(layer)) + if min_area == 0: + return + + min_width = drc("minwidth_{}".format(layer)) + + if preferred_directions[layer] == "V": + height = max(min_area / width, min_width) + else: + width = max(min_area / height, min_width) + + self.add_rect_center(layer=layer, + offset=offset, + width=width, + height=height) def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"): """Adds a ptx module to the design.""" @@ -1181,12 +1173,8 @@ class layout(): self.add_path(layer, [pin_loc, peri_pin_loc]) - self.add_via_stack_center(from_layer=layer, - to_layer="m4", - offset=peri_pin_loc) - self.add_layout_pin_rect_center(text=name, - layer="m4", + layer=layer, offset=peri_pin_loc) def add_power_ring(self, bbox): diff --git a/compiler/pgates/pwrite_driver.py b/compiler/pgates/pwrite_driver.py index da5eacdc..87db7b20 100644 --- a/compiler/pgates/pwrite_driver.py +++ b/compiler/pgates/pwrite_driver.py @@ -160,11 +160,11 @@ class pwrite_driver(design.design): track_xoff = self.get_m2_track(1) din_loc = self.din_inst.get_pin("A").center() - self.add_via_stack("m1", "m2", din_loc) + self.add_via_stack_center("m1", "m2", din_loc) din_track = vector(track_xoff,din_loc.y) br_in = self.br_inst.get_pin("in").center() - self.add_via_stack("m1", "m2", br_in) + self.add_via_stack_center("m1", "m2", br_in) br_track = vector(track_xoff,br_in.y) din_in = vector(track_xoff,0) @@ -181,11 +181,11 @@ class pwrite_driver(design.design): track_xoff = self.get_m4_track(self.din_bar_track) din_bar_in = self.din_inst.get_pin("Z").center() - self.add_via_stack("m1", "m3", din_bar_in) + self.add_via_stack_center("m1", "m3", din_bar_in) din_bar_track = vector(track_xoff,din_bar_in.y) bl_in = self.bl_inst.get_pin("in").center() - self.add_via_stack("m1", "m3", bl_in) + self.add_via_stack_center("m1", "m3", bl_in) bl_track = vector(track_xoff,bl_in.y) din_in = vector(track_xoff,0) @@ -204,15 +204,15 @@ class pwrite_driver(design.design): # This M2 pitch is a hack since the A and Z pins align horizontally en_bar_loc = self.en_inst.get_pin("Z").uc() en_bar_track = vector(track_xoff, en_bar_loc.y) - self.add_via_stack("m1", "m3", en_bar_loc) + self.add_via_stack_center("m1", "m3", en_bar_loc) # This is a U route to the right down then left bl_en_loc = self.bl_inst.get_pin("en_bar").center() bl_en_track = vector(track_xoff, bl_en_loc.y) - self.add_via_stack("m1", "m3", bl_en_loc) + self.add_via_stack_center("m1", "m3", bl_en_loc) br_en_loc = self.br_inst.get_pin("en_bar").center() br_en_track = vector(track_xoff, bl_en_loc.y) - self.add_via_stack("m1", "m3", br_en_loc) + self.add_via_stack_center("m1", "m3", br_en_loc) # L shape @@ -237,21 +237,21 @@ class pwrite_driver(design.design): en_loc = self.en_inst.get_pin("A").center() en_rail = vector(en_loc.x, vdd_yloc) - self.add_via_stack("m1", "m2", en_loc) + self.add_via_stack_center("m1", "m2", en_loc) self.add_path("m2", [en_loc, en_rail]) - self.add_via_stack("m2", "m3", en_rail) + self.add_via_stack_center("m2", "m3", en_rail) # Start point in the track on the pin rail en_track = vector(track_xoff, vdd_yloc) - self.add_via_stack("m3", "m4", en_track) + self.add_via_stack_center("m3", "m4", en_track) # This is a U route to the right down then left bl_en_loc = self.bl_inst.get_pin("en").center() bl_en_track = vector(track_xoff, bl_en_loc.y) - self.add_via_stack("m1", "m3", bl_en_loc) + self.add_via_stack_center("m1", "m3", bl_en_loc) br_en_loc = self.br_inst.get_pin("en").center() br_en_track = vector(track_xoff, bl_en_loc.y) - self.add_via_stack("m1", "m3", br_en_loc) + self.add_via_stack_center("m1", "m3", br_en_loc) # U shape self.add_wire(self.m3_stack, From 0a87691176ddd61679535dac5d7a7c324192f86c Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 30 Jun 2020 15:27:10 -0700 Subject: [PATCH 497/521] Run Calibre LVS even if DRC fails. --- compiler/tests/testutils.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index eb75fc44..4a58cfe2 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -48,12 +48,11 @@ class openram_test(unittest.TestCase): # if we ignore things like minimum metal area of pins drc_result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification) - # Always run LVS if we are using magic - if "magic" in OPTS.drc_exe or drc_result == 0: - lvs_result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification) + # We can still run LVS even if DRC fails in Magic OR Calibre + lvs_result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification) # Only allow DRC to fail and LVS to pass if we are using magic - if "magic" in OPTS.drc_exe and lvs_result == 0 and drc_result != 0: + if lvs_result == 0 and drc_result != 0: # import shutil # zip_file = "/tmp/{0}_{1}".format(a.name, os.getpid()) # debug.info(0, "Archiving failed files to {}.zip".format(zip_file)) From 3379f46da1d336a379697aa9cd8c0571eda3c3a1 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 30 Jun 2020 16:22:44 -0700 Subject: [PATCH 498/521] Fail unit test, but mention if LVS passes and DRC fails. --- compiler/tests/testutils.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 4a58cfe2..a8da9fb4 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -57,8 +57,7 @@ class openram_test(unittest.TestCase): # zip_file = "/tmp/{0}_{1}".format(a.name, os.getpid()) # debug.info(0, "Archiving failed files to {}.zip".format(zip_file)) # shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) - debug.warning("DRC failed but LVS passed: {}".format(a.name)) - # self.fail("DRC failed but LVS passed: {}".format(a.name)) + self.fail("DRC failed but LVS passed: {}".format(a.name)) elif drc_result != 0: # import shutil # zip_file = "/tmp/{0}_{1}".format(a.name, os.getpid()) From b07f30cb9edaed782cd746e906a81ee0d08330db Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 30 Jun 2020 16:23:07 -0700 Subject: [PATCH 499/521] Missing output via in control logic --- compiler/modules/control_logic.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 74fad6a5..78215d49 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -797,10 +797,14 @@ class control_logic(design.design): out_pin = inst.get_pin(pin_name) right_pos = out_pin.center() + vector(self.width - out_pin.cx(), 0) - self.add_layout_pin_segment_center(text=out_name, - layer="m1", - start=out_pin.center(), - end=right_pos) + + self.add_path(out_pin.layer, [out_pin.center(), right_pos]) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer="m1", + offset=right_pos) + self.add_layout_pin_rect_center(text=out_name, + layer="m1", + offset=right_pos) def route_supply(self): """ Add vdd and gnd to the instance cells """ From 3d0f29ff3a079c33b556a5219e2c9fdb1b815bcd Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Jul 2020 09:22:59 -0700 Subject: [PATCH 500/521] Fix missing via LVS issues. LVS passing for some 20 tests. --- compiler/base/hierarchy_layout.py | 13 ++++++----- compiler/modules/control_logic.py | 37 ++++++++++++++++++++----------- compiler/modules/delay_chain.py | 29 ++++++++++++------------ compiler/sram/sram_1bank.py | 7 +++++- 4 files changed, 53 insertions(+), 33 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index a5272ba5..275b69e9 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -917,8 +917,10 @@ class layout(): (horizontal_layer, via_layer, vertical_layer) = layer_stack if horizontal: route_layer = vertical_layer + bys_layer = horizontal_layer else: route_layer = horizontal_layer + bus_layer = vertical_layer for (pin_name, bus_name) in mapping: pin = inst.get_pin(pin_name) @@ -940,17 +942,18 @@ class layout(): # Connect to the pin on the instances with a via if it is # not on the right layer if pin.layer != route_layer: - self.add_via_center(layers=layer_stack, - offset=pin_pos) + self.add_via_stack_center(from_layer=pin.layer, + to_layer=route_layer, + offset=pin_pos) # FIXME: output pins tend to not be rotate, # but supply pins are. Make consistent? # We only need a via if they happened to align perfectly # so the add_wire didn't add a via if (horizontal and bus_pos.y == pin_pos.y) or (not horizontal and bus_pos.x == pin_pos.x): - self.add_via_center(layers=layer_stack, - offset=bus_pos, - rotate=90) + self.add_via_stack_center(from_layer=route_layer, + to_layer=bus_layer, + offset=bus_pos) def connect_vbus(self, src_pin, dest_pin, hlayer="m3", vlayer="m2"): """ diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 78215d49..020b90ec 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -555,9 +555,15 @@ class control_logic(design.design): clkbuf_map = zip(["A"], ["clk_buf"]) self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.input_bus) - out_pos = self.clk_bar_inst.get_pin("Z").center() - in_pos = self.gated_clk_bar_inst.get_pin("A").center() - self.add_zjog("m1", out_pos, in_pos) + out_pin = self.clk_bar_inst.get_pin("Z") + out_pos = out_pin.center() + in_pin = self.gated_clk_bar_inst.get_pin("A") + in_pos = in_pin.center() + self.add_zjog(out_pin.layer, out_pos, in_pos) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer=in_pin.layer, + offset=in_pos) + # This is the second gate over, so it needs to be on M3 clkbuf_map = zip(["B"], ["cs"]) @@ -809,23 +815,27 @@ class control_logic(design.design): def route_supply(self): """ Add vdd and gnd to the instance cells """ + if OPTS.tech_name == "sky130": + supply_layer = "li" + else: + supply_layer = "m1" max_row_x_loc = max([inst.rx() for inst in self.row_end_inst]) for inst in self.row_end_inst: pins = inst.get_pins("vdd") for pin in pins: - if pin.layer == "m1": + if pin.layer == supply_layer: row_loc = pin.rc() pin_loc = vector(max_row_x_loc, pin.rc().y) - self.add_power_pin("vdd", pin_loc) - self.add_path("m1", [row_loc, pin_loc]) + self.add_power_pin("vdd", pin_loc, start_layer=pin.layer) + self.add_path(supply_layer, [row_loc, pin_loc]) pins = inst.get_pins("gnd") for pin in pins: - if pin.layer == "m1": + if pin.layer == supply_layer: row_loc = pin.rc() pin_loc = vector(max_row_x_loc, pin.rc().y) - self.add_power_pin("gnd", pin_loc) - self.add_path("m1", [row_loc, pin_loc]) + self.add_power_pin("gnd", pin_loc, start_layer=pin.layer) + self.add_path(supply_layer, [row_loc, pin_loc]) self.copy_layout_pin(self.delay_inst, "gnd") self.copy_layout_pin(self.delay_inst, "vdd") @@ -1008,12 +1018,13 @@ class control_logic(design.design): def route_output_to_bus_jogged(self, inst, name): # Connect this at the bottom of the buffer - out_pos = inst.get_pin("Z").center() + out_pin = inst.get_pin("Z") + out_pos = out_pin.center() mid1 = vector(out_pos.x, out_pos.y - 0.4 * inst.mod.height) mid2 = vector(self.input_bus[name].cx(), mid1.y) bus_pos = self.input_bus[name].center() self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) - # The pin is on M1, so we need another via as well - self.add_via_center(layers=self.m1_stack, - offset=out_pos) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer="m2", + offset=out_pos) diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index c07395f5..c261138a 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -140,21 +140,20 @@ class delay_chain(design.design): for load in self.load_inst_map[inv]: # Drop a via on each A pin a_pin = load.get_pin("A") - self.add_via_center(layers=self.m1_stack, - offset=a_pin.center()) - self.add_via_center(layers=self.m2_stack, - offset=a_pin.center()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m3", + offset=a_pin.center()) # Route an M3 horizontal wire to the furthest z_pin = inv.get_pin("Z") a_pin = inv.get_pin("A") a_max = self.load_inst_map[inv][-1].get_pin("A") - self.add_via_center(layers=self.m1_stack, - offset=a_pin.center()) - self.add_via_center(layers=self.m1_stack, - offset=z_pin.center()) - self.add_via_center(layers=self.m2_stack, - offset=z_pin.center()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=a_pin.center()) + self.add_via_stack_center(from_layer=z_pin.layer, + to_layer="m3", + offset=z_pin.center()) self.add_path("m3", [z_pin.center(), a_max.center()]) # Route Z to the A of the next stage @@ -191,8 +190,9 @@ class delay_chain(design.design): # input is A pin of first inverter a_pin = self.driver_inst_list[0].get_pin("A") - self.add_via_center(layers=self.m1_stack, - offset=a_pin.center()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=a_pin.center()) self.add_layout_pin(text="in", layer="m2", offset=a_pin.ll().scale(1, 0), @@ -201,8 +201,9 @@ class delay_chain(design.design): # output is A pin of last load inverter last_driver_inst = self.driver_inst_list[-1] a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A") - self.add_via_center(layers=self.m1_stack, - offset=a_pin.center()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=a_pin.center()) mid_point = vector(a_pin.cx() + 3 * self.m2_width, a_pin.cy()) self.add_path("m2", [a_pin.center(), mid_point, mid_point.scale(1, 0)]) self.add_layout_pin_segment_center(text="out", diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index cdc5ab92..52cbb2a1 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -457,7 +457,12 @@ class sram_1bank(sram_base): dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) self.add_wire(self.m2_stack[::-1], [src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()]) - # self.connect_hbus(src_pin, dest_pin) + self.add_via_stack_center(from_layer=src_pin.layer, + to_layer="m2", + offset=src_pin.center()) + self.add_via_stack_center(from_layer=dest_pin.layer, + to_layer="m2", + offset=dest_pin.center()) def route_row_addr_dff(self): """ Connect the output of the row flops to the bank pins """ From bb18d05f7535c7239ce860e883d9ee9f47d58eee Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Jul 2020 11:33:25 -0700 Subject: [PATCH 501/521] Move control output via inside module instead of perimeter --- compiler/modules/control_logic.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 020b90ec..a4e26a6f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -802,15 +802,16 @@ class control_logic(design.design): """ Create an output pin on the right side from the pin of a given instance. """ out_pin = inst.get_pin(pin_name) - right_pos = out_pin.center() + vector(self.width - out_pin.cx(), 0) + out_pos = out_pin.center() + right_pos = out_pos + vector(self.width - out_pin.cx(), 0) - self.add_path(out_pin.layer, [out_pin.center(), right_pos]) self.add_via_stack_center(from_layer=out_pin.layer, - to_layer="m1", - offset=right_pos) - self.add_layout_pin_rect_center(text=out_name, - layer="m1", - offset=right_pos) + to_layer="m2", + offset=out_pos) + self.add_layout_pin_segment_center(text=out_name, + layer="m2", + start=out_pos, + end=right_pos) def route_supply(self): """ Add vdd and gnd to the instance cells """ From c340870ba0ff6c6e86da99ac1e667c27a69ae481 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Jul 2020 14:44:01 -0700 Subject: [PATCH 502/521] Channel route dout wires as well in read write ports --- compiler/base/channel_route.py | 2 +- compiler/base/hierarchy_layout.py | 6 +-- compiler/sram/sram_1bank.py | 64 ++++++++++++++++++++++--------- 3 files changed, 50 insertions(+), 22 deletions(-) diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py index 5e9b9531..cd4bbdc1 100644 --- a/compiler/base/channel_route.py +++ b/compiler/base/channel_route.py @@ -161,7 +161,7 @@ class channel_route(design.design): else: # FIXME: We don't support cyclic VCGs right now. debug.error("Cyclic VCG in channel router.", -1) - + # These are the pins we'll have to connect pin_list = nets[net_name] # print("Routing:", net_name, [x.name for x in pin_list]) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 275b69e9..8995488a 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1176,9 +1176,9 @@ class layout(): self.add_path(layer, [pin_loc, peri_pin_loc]) - self.add_layout_pin_rect_center(text=name, - layer=layer, - offset=peri_pin_loc) + return self.add_layout_pin_rect_center(text=name, + layer=layer, + offset=peri_pin_loc) def add_power_ring(self, bbox): """ diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 52cbb2a1..d2c58e49 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -81,6 +81,10 @@ class sram_1bank(sram_base): # Write ports need the data input flops and write mask flops if port in self.write_ports: self.data_bus_size[port] += self.num_wmasks + self.word_size + # This is for the din pins that get routed in the same channel + # when we have dout and din together + if port in self.readwrite_ports: + self.data_bus_size[port] += self.word_size # Convert to length self.data_bus_size[port] *= self.m4_nonpref_pitch # Add the gap in unit length @@ -237,18 +241,45 @@ class sram_1bank(sram_base): "clk", "clk{}".format(port)) - # Data output pins go to BOTTOM/TOP - if port in self.read_ports: + # Data input pins go to BOTTOM/TOP + din_ports = [] + if port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): if OPTS.perimeter_pins: + p = self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit), + pin=self.data_dff_insts[port].get_pin("din_{0}".format(bit)), + side=bottom_or_top, + bbox=bbox) + din_ports.append(p) + else: + self.copy_layout_pin(self.bank_inst, + "din{0}_{1}".format(port, bit), + "din{0}[{1}]".format(port, bit)) + + # Data output pins go to BOTTOM/TOP + if port in self.readwrite_ports and OPTS.perimeter_pins: + for bit in range(self.word_size + self.num_spare_cols): + # This should be routed next to the din pin + p = din_ports[bit] + self.add_layout_pin_rect_center(text="dout{0}[{1}]".format(port, bit), + layer=p.layer, + offset=p.center() + vector(self.m3_pitch, 0), + width=p.width(), + height=p.height()) + elif port in self.read_ports: + for bit in range(self.word_size + self.num_spare_cols): + if OPTS.perimeter_pins: + # This should have a clear route to the perimeter if there are no din routes self.add_perimeter_pin(name="dout{0}[{1}]".format(port, bit), pin=self.bank_inst.get_pin("dout{0}_{1}".format(port, bit)), side=bottom_or_top, bbox=bbox) else: - self.copy_layout_pin(self.bank_inst, - "dout{0}_{1}".format(port, bit), + self.copy_layout_pin(self.data_dff_insts[port], + "dout_{}".format(bit), "dout{0}[{1}]".format(port, bit)) + + # Lower address bits go to BOTTOM/TOP for bit in range(self.col_addr_size): @@ -274,19 +305,6 @@ class sram_1bank(sram_base): "din_{}".format(bit), "addr{0}[{1}]".format(port, bit + self.col_addr_size)) - # Data input pins go to BOTTOM/TOP - if port in self.write_ports: - for bit in range(self.word_size + self.num_spare_cols): - if OPTS.perimeter_pins: - self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit), - pin=self.data_dff_insts[port].get_pin("din_{}".format(bit)), - side=bottom_or_top, - bbox=bbox) - else: - self.copy_layout_pin(self.data_dff_insts[port], - "din_{}".format(bit), - "din{0}[{1}]".format(port, bit)) - # Write mask pins go to BOTTOM/TOP if port in self.write_ports: if self.write_size: @@ -349,12 +367,22 @@ class sram_1bank(sram_base): route_map.extend(list(zip(bank_pins, dff_pins))) if port in self.write_ports: - # data dff + # synchronized inputs from data dff dff_names = ["dout_{}".format(x) for x in range(self.word_size + self.num_spare_cols)] dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)] bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] route_map.extend(list(zip(bank_pins, dff_pins))) + + if port in self.readwrite_ports and OPTS.perimeter_pins: + # outputs from sense amp + # These are the output pins which had their pin placed on the perimeter, so route from the + # sense amp which should not align with write driver input + sram_names = ["dout{0}[{1}]".format(port, x) for x in range(self.word_size + self.num_spare_cols)] + sram_pins = [self.get_pin(x) for x in sram_names] + bank_names = ["dout{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)] + bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + route_map.extend(list(zip(bank_pins, sram_pins))) if self.num_wmasks > 0 and port in self.write_ports: layer_stack = self.m3_stack From 8cd1cba8184106944d7cc6d97131afa2dac1ce96 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Jul 2020 14:44:18 -0700 Subject: [PATCH 503/521] Fix missing via in wmask driver --- compiler/modules/port_data.py | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index e370b891..bd6b39e2 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -377,11 +377,11 @@ class port_data(design.design): temp.append("{0}_{1}".format(br_name, bit)) else: temp.append("{0}_out_{1}".format(bl_name, bit)) - temp.append("{0}_out_{1}".format(br_name, bit)) + temp.append("{0}_out_{1}".format(br_name, bit)) - for bit in range(self.num_spare_cols): + for bit in range(self.num_spare_cols): temp.append("spare{0}_{1}".format(bl_name, bit)) - temp.append("spare{0}_{1}".format(br_name, bit)) + temp.append("spare{0}_{1}".format(br_name, bit)) if self.write_size is not None: for i in range(self.num_wmasks): @@ -522,13 +522,14 @@ class port_data(design.design): wdriver_pos = wdriver_en_pin.rc() - vector(self.m2_pitch, 0) mid_pos = vector(wdriver_pos.x, wmask_pos.y) - # Add driver on mask output - self.add_via_center(layers=self.m1_stack, - offset=wmask_pos) + self.add_via_stack_center(from_layer=wmask_out_pin.layer, + to_layer="m1", + offset=wmask_pos) # Add via for the write driver array's enable input - self.add_via_center(layers=self.m1_stack, - offset=wdriver_pos) + self.add_via_stack_center(from_layer=wdriver_en_pin.layer, + to_layer="m2", + offset=wdriver_pos) # Route between write mask AND array and write driver array self.add_wire(self.m1_stack, [wmask_pos, mid_pos, wdriver_pos]) From bed2e36550d15f34a6ec9a8815a50e79c21d0f14 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Jul 2020 14:44:48 -0700 Subject: [PATCH 504/521] Simplify write mask supply via logic --- compiler/modules/write_mask_and_array.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index c87d3a90..d48aefef 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -134,10 +134,7 @@ class write_mask_and_array(design.design): for supply in ["gnd", "vdd"]: supply_pin=self.and2_insts[i].get_pin(supply) - if "li" in layer: - self.add_power_pin(supply, supply_pin.center(), start_layer="li", directions=("H", "H")) - else: - self.add_power_pin(supply, supply_pin.center()) + self.add_power_pin(supply, supply_pin.center(), start_layer=supply_pin.layer) for supply in ["gnd", "vdd"]: supply_pin_left = self.and2_insts[0].get_pin(supply) From d48f48324855c441f83583fd760c98d9e09f3287 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 1 Jul 2020 15:10:20 -0700 Subject: [PATCH 505/521] Fix swapped instance bug in perimeter pins. --- compiler/sram/sram_1bank.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index d2c58e49..a9731ed5 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -252,8 +252,8 @@ class sram_1bank(sram_base): bbox=bbox) din_ports.append(p) else: - self.copy_layout_pin(self.bank_inst, - "din{0}_{1}".format(port, bit), + self.copy_layout_pin(self.data_dff_insts[port], + "din_{}".format(bit), "din{0}[{1}]".format(port, bit)) # Data output pins go to BOTTOM/TOP @@ -275,8 +275,8 @@ class sram_1bank(sram_base): side=bottom_or_top, bbox=bbox) else: - self.copy_layout_pin(self.data_dff_insts[port], - "dout_{}".format(bit), + self.copy_layout_pin(self.bank_inst, + "dout{0}_{1}".format(port, bit), "dout{0}[{1}]".format(port, bit)) From 119bd94689dfac8ed7be26f917b4f4d077be055d Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 2 Jul 2020 15:43:23 -0700 Subject: [PATCH 506/521] Fixed warnings with single port characterization. Cleaned up some signal names. --- compiler/characterizer/delay.py | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index b647e6e9..20188625 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -235,8 +235,9 @@ class delay(simulation): # Bit measures, measurements times to be defined later. The measurement names must be unique # but they is enforced externally. {} added to names to differentiate between ports allow the # measurements are independent of the ports - q_meas = voltage_at_measure("v_q_{}{}".format(meas_tag, "{}"), q_name) - qbar_meas = voltage_at_measure("v_qbar_{}{}".format(meas_tag, "{}"), qbar_name) + q_meas = voltage_at_measure("v_q_{}".format(meas_tag), q_name) + qbar_meas = voltage_at_measure("v_qbar_{}".format(meas_tag), qbar_name) + debug.info(1,"meas name:{}".format(q_meas.name)) return {bit_polarity.NONINVERTING:q_meas, bit_polarity.INVERTING:qbar_meas} @@ -286,15 +287,19 @@ class delay(simulation): bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port) port_pos = -1-len(str(self.probe_data))-len(str(port)) + if bl_name_port.endswith(str(port)+"_"+str(self.probe_data)): self.bl_name = bl_name_port[:port_pos] +"{}"+ bl_name_port[port_pos+len(str(port)):] + elif not bl_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0 + self.bl_name = bl_name_port else: self.bl_name = bl_name_port debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") if br_name_port.endswith(str(port)+"_"+str(self.probe_data)): - port_pos = -1-len(str(self.probe_data))-len(str(port)) self.br_name = br_name_port[:port_pos] +"{}"+ br_name_port[port_pos+len(str(port)):] + elif not br_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0 + self.br_name = br_name_port else: self.br_name = br_name_port debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") From fb34338fdfc52c3ab0daeb6a5a559cee00372432 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 2 Jul 2020 18:00:02 -0700 Subject: [PATCH 507/521] Removed debug statements --- compiler/characterizer/delay.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 20188625..b7faaec3 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -237,7 +237,6 @@ class delay(simulation): # measurements are independent of the ports q_meas = voltage_at_measure("v_q_{}".format(meas_tag), q_name) qbar_meas = voltage_at_measure("v_qbar_{}".format(meas_tag), qbar_name) - debug.info(1,"meas name:{}".format(q_meas.name)) return {bit_polarity.NONINVERTING:q_meas, bit_polarity.INVERTING:qbar_meas} From 282f944b2f06709870e6a4b8f6fcf03fe95957a2 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 3 Jul 2020 06:55:35 -0700 Subject: [PATCH 508/521] Also write .lvs file since it can be different the .sp --- compiler/openram.py | 2 +- compiler/sram/sram.py | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/compiler/openram.py b/compiler/openram.py index cf18f97b..4989feff 100755 --- a/compiler/openram.py +++ b/compiler/openram.py @@ -57,7 +57,7 @@ c = sram_config(word_size=OPTS.word_size, num_spare_rows=OPTS.num_spare_rows) debug.print_raw("Words per row: {}".format(c.words_per_row)) -output_extensions = ["sp", "v", "lib", "py", "html", "log"] +output_extensions = ["lvs", "sp", "v", "lib", "py", "html", "log"] # Only output lef/gds if back-end if not OPTS.netlist_only: output_extensions.extend(["lef", "gds"]) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index 8863c299..1ec7d636 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -88,6 +88,13 @@ class sram(): self.sp_write(spname) print_time("Spice writing", datetime.datetime.now(), start_time) + # Save the LVS file + start_time = datetime.datetime.now() + spname = OPTS.output_path + self.s.name + ".lvs" + debug.print_raw("LVS: Writing to {0}".format(spname)) + self.lvs_write(spname) + print_time("LVS writing", datetime.datetime.now(), start_time) + # Save the extracted spice file if OPTS.use_pex: import verify From 27166c75f08cf633d4fe039668bc823677e2e584 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 3 Jul 2020 07:00:56 -0700 Subject: [PATCH 509/521] Don't remove temp files during regular openram runs. --- compiler/base/hierarchy_design.py | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index b0370179..001093dd 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -85,8 +85,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): "LVS failed for {0} with {1} errors(s)".format(self.name, num_lvs_errors)) - os.remove(tempspice) - os.remove(tempgds) + if OPTS.purge_temp: + os.remove(tempspice) + os.remove(tempgds) return (num_drc_errors, num_lvs_errors) else: @@ -111,7 +112,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): "DRC failed for {0} with {1} error(s)".format(self.name, num_errors)) - os.remove(tempgds) + if OPTS.purge_temp: + os.remove(tempgds) return num_errors else: @@ -137,8 +139,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): debug.check(num_errors == 0, "LVS failed for {0} with {1} error(s)".format(self.name, num_errors)) - os.remove(tempspice) - os.remove(tempgds) + if OPTS.purge_temp: + os.remove(tempspice) + os.remove(tempgds) return num_errors else: From a989ea63a02b33f42b7aea48cc454021fd9d04fc Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 9 Jul 2020 11:33:14 -0700 Subject: [PATCH 510/521] Move magic/netgen files to tech dir --- compiler/verify/magic.py | 6 +++--- technology/scn3me_subm/{mag_lib => tech}/.magicrc | 0 technology/scn3me_subm/{mag_lib => tech}/setup.tcl | 0 technology/scn4m_subm/{mag_lib => tech}/.magicrc | 0 technology/scn4m_subm/{mag_lib => tech}/setup.tcl | 0 5 files changed, 3 insertions(+), 3 deletions(-) rename technology/scn3me_subm/{mag_lib => tech}/.magicrc (100%) rename technology/scn3me_subm/{mag_lib => tech}/setup.tcl (100%) rename technology/scn4m_subm/{mag_lib => tech}/.magicrc (100%) rename technology/scn4m_subm/{mag_lib => tech}/setup.tcl (100%) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 5df6e698..ef98a09b 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -38,7 +38,7 @@ def filter_gds(cell_name, input_gds, output_gds): global OPTS # Copy .magicrc file into temp dir - magic_file = OPTS.openram_tech + "mag_lib/.magicrc" + magic_file = OPTS.openram_tech + "tech/.magicrc" if os.path.exists(magic_file): shutil.copy(magic_file, OPTS.openram_temp) else: @@ -135,7 +135,7 @@ def write_netgen_script(cell_name): global OPTS setup_file = "setup.tcl" - full_setup_file = OPTS.openram_tech + "mag_lib/" + setup_file + full_setup_file = OPTS.openram_tech + "tech/" + setup_file if os.path.exists(full_setup_file): # Copy setup.tcl file into temp dir shutil.copy(full_setup_file, OPTS.openram_temp) @@ -166,7 +166,7 @@ def run_drc(cell_name, gds_name, extract=True, final_verification=False): shutil.copy(gds_name, OPTS.openram_temp) # Copy .magicrc file into temp dir - magic_file = OPTS.openram_tech + "mag_lib/.magicrc" + magic_file = OPTS.openram_tech + "tech/.magicrc" if os.path.exists(magic_file): shutil.copy(magic_file, OPTS.openram_temp) else: diff --git a/technology/scn3me_subm/mag_lib/.magicrc b/technology/scn3me_subm/tech/.magicrc similarity index 100% rename from technology/scn3me_subm/mag_lib/.magicrc rename to technology/scn3me_subm/tech/.magicrc diff --git a/technology/scn3me_subm/mag_lib/setup.tcl b/technology/scn3me_subm/tech/setup.tcl similarity index 100% rename from technology/scn3me_subm/mag_lib/setup.tcl rename to technology/scn3me_subm/tech/setup.tcl diff --git a/technology/scn4m_subm/mag_lib/.magicrc b/technology/scn4m_subm/tech/.magicrc similarity index 100% rename from technology/scn4m_subm/mag_lib/.magicrc rename to technology/scn4m_subm/tech/.magicrc diff --git a/technology/scn4m_subm/mag_lib/setup.tcl b/technology/scn4m_subm/tech/setup.tcl similarity index 100% rename from technology/scn4m_subm/mag_lib/setup.tcl rename to technology/scn4m_subm/tech/setup.tcl From a3195c08272ae08480b6b939e1be93e6148fbfc3 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 13 Jul 2020 12:37:56 -0700 Subject: [PATCH 511/521] Add words_per_row and others in config file. --- compiler/openram.py | 5 ++++- compiler/options.py | 3 ++- compiler/sram/sram_config.py | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/compiler/openram.py b/compiler/openram.py index 4989feff..f046fdb1 100755 --- a/compiler/openram.py +++ b/compiler/openram.py @@ -54,7 +54,10 @@ from sram_config import sram_config c = sram_config(word_size=OPTS.word_size, num_words=OPTS.num_words, write_size=OPTS.write_size, - num_spare_rows=OPTS.num_spare_rows) + num_banks=OPTS.num_banks, + words_per_row=OPTS.words_per_row, + num_spare_rows=OPTS.num_spare_rows, + num_spare_cols=OPTS.num_spare_cols) debug.print_raw("Words per row: {}".format(c.words_per_row)) output_extensions = ["lvs", "sp", "v", "lib", "py", "html", "log"] diff --git a/compiler/options.py b/compiler/options.py index d229b96e..d97ea300 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -44,8 +44,9 @@ class options(optparse.Values): # word_size = 0 # You can manually specify banks, but it is better to auto-detect it. num_banks = 1 + words_per_row = None num_spare_rows = 0 - # num_spare_cols = 0 + num_spare_cols = 0 ################### # Optimization options diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index 3af2fd9c..fa70d730 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -14,7 +14,7 @@ from sram_factory import factory class sram_config: """ This is a structure that is used to hold the SRAM configuration options. """ - def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None, num_spare_rows=0, num_spare_cols=None): + def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None, num_spare_rows=0, num_spare_cols=0): self.word_size = word_size self.num_words = num_words self.write_size = write_size From 2011974e010908f4dd8f7162993577ca5aeb2dd1 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 13 Jul 2020 12:49:24 -0700 Subject: [PATCH 512/521] Make drc and lvs errors a member variable. Run only once. --- compiler/base/hierarchy_design.py | 18 +++++++++------- compiler/characterizer/lib.py | 6 +----- .../example_config_1rw_2mux_scn4m_subm.py | 21 +++++++++++++++++++ compiler/sram/sram_base.py | 2 +- 4 files changed, 33 insertions(+), 14 deletions(-) create mode 100644 compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 001093dd..5ae2f26e 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -72,26 +72,28 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): self.lvs_write(tempspice) self.gds_write(tempgds) # Final verification option does not allow nets to be connected by label. - num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) - num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) + self.drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) + self.lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) # force_check is used to determine decoder height and other things, so we shouldn't fail # if that flag is set if OPTS.inline_lvsdrc and not force_check: - debug.check(num_drc_errors == 0, + debug.check(self.drc_errors == 0, "DRC failed for {0} with {1} error(s)".format(self.name, - num_drc_errors)) - debug.check(num_lvs_errors == 0, + self.drc_errors)) + debug.check(self.lvs_errors == 0, "LVS failed for {0} with {1} errors(s)".format(self.name, - num_lvs_errors)) + self.lvs_errors)) if OPTS.purge_temp: os.remove(tempspice) os.remove(tempgds) - return (num_drc_errors, num_lvs_errors) else: - return ("skipped", "skipped") + self.drc_errors = "skipped" + self.lvs_errors = "skipped" + + return (self.drc_errors, self.lvs_errors) def DRC(self, final_verification=False): """Checks DRC for a module""" diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 92882db7..525f2180 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -658,11 +658,7 @@ class lib: # information of checks # run it only the first time - try: - datasheet.write("{0},{1},".format(self.drc_errors, self.lvs_errors)) - except AttributeError: - (self.drc_errors, self.lvs_errors) = self.sram.DRC_LVS(final_verification=True) - datasheet.write("{0},{1},".format(self.drc_errors, self.lvs_errors)) + datasheet.write("{0},{1},".format(self.sram.drc_errors, self.sram.lvs_errors)) # write area datasheet.write(str(self.sram.width * self.sram.height) + ',') diff --git a/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py b/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py new file mode 100644 index 00000000..a09edfdb --- /dev/null +++ b/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py @@ -0,0 +1,21 @@ +word_size = 4 +num_words = 64 +words_per_row = 2 + +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 + +tech_name = "scn4m_subm" +nominal_corners_only = False +process_corners = ["TT"] +supply_voltages = [5.0] +temperatures = [25] + +# route_supplies = True +check_lvsdrc = True + +output_path = "temp" +output_name = "sram_1rw_{0}_{1}_{2}".format(word_size, + num_words, + tech_name) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 89ecfaaf..b16c28fa 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -129,7 +129,7 @@ class sram_base(design, verilog, lef): start_time = datetime.datetime.now() # We only enable final verification if we have routed the design - self.DRC_LVS(final_verification=OPTS.route_supplies) + self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=True) if not OPTS.is_unit_test: print_time("Verification", datetime.datetime.now(), start_time) From 716798baae3a7f1e5e912de9d9d5a33223d07fd0 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 13 Jul 2020 13:01:00 -0700 Subject: [PATCH 513/521] Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors. --- compiler/base/hierarchy_design.py | 35 +++++++++++++++++-------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 5ae2f26e..38e30981 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -58,14 +58,17 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # No layout to check if OPTS.netlist_only: - return ("skipped", "skipped") + self.drc_errors = "skipped" + self.lvs_errors = "skipped" # Unit tests will check themselves. - if not force_check and OPTS.is_unit_test: - return ("skipped", "skipped") - if not force_check and not OPTS.check_lvsdrc: - return ("skipped", "skipped") + elif not force_check and OPTS.is_unit_test: + self.drc_errors = "skipped" + self.lvs_errors = "skipped" + elif not force_check and not OPTS.check_lvsdrc: + self.drc_errors = "skipped" + self.lvs_errors = "skipped" # Do not run if disabled in options. - if (OPTS.inline_lvsdrc or force_check or final_verification): + elif (OPTS.inline_lvsdrc or force_check or final_verification): tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) @@ -104,9 +107,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # No layout to check if OPTS.netlist_only: - return "skipped" - - if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): + self.drc_errors = "skipped" + elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) self.gds_write(tempgds) num_errors = verify.run_drc(self.name, tempgds, final_verification=final_verification) @@ -117,9 +119,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if OPTS.purge_temp: os.remove(tempgds) - return num_errors else: - return "skipped" + self.drc_errors = "skipped" + + return self.drc_errors def LVS(self, final_verification=False): """Checks LVS for a module""" @@ -130,9 +133,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # No layout to check if OPTS.netlist_only: - return "skipped" - - if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): + self.lvs_errors = "skipped" + elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) self.lvs_write(tempspice) @@ -145,9 +147,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): os.remove(tempspice) os.remove(tempgds) - return num_errors else: - return "skipped" + self.lvs_errors = "skipped" + + return self.lvs_errors def init_graph_params(self): """Initializes parameters relevant to the graph creation""" From e49236f8fcf4fb2571722ca9820631af93c1c101 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 13 Jul 2020 14:08:00 -0700 Subject: [PATCH 514/521] Default drc and lvs errors is skipped. --- compiler/base/hierarchy_design.py | 32 ++++++++----------------------- compiler/pgates/ptx.py | 14 ++++++-------- 2 files changed, 14 insertions(+), 32 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 38e30981..79b5a53a 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -36,6 +36,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): else: self.lvs_file = self.sp_file + self.drc_errors = "skipped" + self.lvs_errors = "skipped" + self.name = name hierarchy_spice.spice.__init__(self, name) hierarchy_layout.layout.__init__(self, name) @@ -58,15 +61,12 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # No layout to check if OPTS.netlist_only: - self.drc_errors = "skipped" - self.lvs_errors = "skipped" + return # Unit tests will check themselves. elif not force_check and OPTS.is_unit_test: - self.drc_errors = "skipped" - self.lvs_errors = "skipped" + return elif not force_check and not OPTS.check_lvsdrc: - self.drc_errors = "skipped" - self.lvs_errors = "skipped" + return # Do not run if disabled in options. elif (OPTS.inline_lvsdrc or force_check or final_verification): @@ -92,12 +92,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): os.remove(tempspice) os.remove(tempgds) - else: - self.drc_errors = "skipped" - self.lvs_errors = "skipped" - - return (self.drc_errors, self.lvs_errors) - def DRC(self, final_verification=False): """Checks DRC for a module""" import verify @@ -107,7 +101,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # No layout to check if OPTS.netlist_only: - self.drc_errors = "skipped" + return elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) self.gds_write(tempgds) @@ -119,11 +113,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if OPTS.purge_temp: os.remove(tempgds) - else: - self.drc_errors = "skipped" - - return self.drc_errors - def LVS(self, final_verification=False): """Checks LVS for a module""" import verify @@ -133,7 +122,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # No layout to check if OPTS.netlist_only: - self.lvs_errors = "skipped" + return elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) @@ -146,11 +135,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if OPTS.purge_temp: os.remove(tempspice) os.remove(tempgds) - - else: - self.lvs_errors = "skipped" - - return self.lvs_errors def init_graph_params(self): """Initializes parameters relevant to the graph creation""" diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 8be003b2..ad741870 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -12,7 +12,6 @@ from vector import vector from sram_factory import factory import contact import logical_effort -import os from globals import OPTS from pgate import pgate @@ -120,11 +119,10 @@ class ptx(design.design): def create_netlist(self): pin_list = ["D", "G", "S", "B"] if self.tx_type == "nmos": - body_dir = 'GROUND' + body_dir = "GROUND" else: - # Assumed that the check for either pmos or nmos is done elsewhere. - body_dir = 'POWER' - dir_list = ['INOUT', 'INPUT', 'INOUT', body_dir] + body_dir = "POWER" + dir_list = ["INOUT", "INPUT", "INOUT", body_dir] self.add_pin_list(pin_list, dir_list) # Just make a guess since these will actually @@ -135,9 +133,9 @@ class ptx(design.design): # sky130 simulation cannot use the mult parameter in simulation (self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], - self.mults, - self.tx_width, - drc("minwidth_poly")) + self.mults, + self.tx_width, + drc("minwidth_poly")) # Perimeters are in microns # Area is in u since it is microns square area_str = "pd={0:.2f} ps={0:.2f} as={1:.2f}u ad={1:.2f}u".format(perimeter_sd, From 2b7d89d2c155a2ffd7918c93309bd38dcf50912b Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 13 Jul 2020 14:59:31 -0700 Subject: [PATCH 515/521] Fix netlist_only in sky130 --- compiler/pgates/pinv_dec.py | 4 ---- compiler/pgates/ptx.py | 4 ++-- compiler/pgates/single_level_column_mux.py | 26 ++++++++++++++-------- compiler/verify/__init__.py | 6 +++-- 4 files changed, 23 insertions(+), 17 deletions(-) diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py index 3ce6ad80..4d4f2229 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/pgates/pinv_dec.py @@ -13,10 +13,6 @@ from vector import vector from globals import OPTS from sram_factory import factory -if(OPTS.tech_name == "sky130"): - from tech import nmos_bins, pmos_bins - - class pinv_dec(pinv.pinv): """ This is another version of pinv but with layout for the decoder. diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index ad741870..ce8591fd 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -129,7 +129,7 @@ class ptx(design.design): # be decided in the layout later. area_sd = 2.5 * self.poly_width * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width - if OPTS.tech_name == "sky130" and OPTS.lvs_exe[0] == "calibre": + if OPTS.tech_name == "sky130" and OPTS.lvs_exe and OPTS.lvs_exe[0] == "calibre": # sky130 simulation cannot use the mult parameter in simulation (self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], @@ -150,7 +150,7 @@ class ptx(design.design): self.spice_device = main_str + area_str self.spice.append("\n* ptx " + self.spice_device) - if OPTS.tech_name == "sky130" and OPTS.lvs_exe[0] == "calibre": + if OPTS.tech_name == "sky130" and OPTS.lvs_exe and OPTS.lvs_exe[0] == "calibre": # sky130 requires mult parameter too self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult={1}".format(spice[self.tx_type], self.mults, diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index b594f2e4..ca7c3e51 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -56,7 +56,8 @@ class single_level_column_mux(pgate.pgate): self.pin_height = 2 * self.pin_width self.width = self.bitcell.width self.height = self.nmos_upper.uy() + self.pin_height - + + self.place_ptx() self.connect_poly() self.add_bitline_pins() self.connect_bitlines() @@ -104,20 +105,27 @@ class single_level_column_mux(pgate.pgate): """ Create the two pass gate NMOS transistors to switch the bitlines""" # Space it in the center - nmos_lower_position = self.nmos.active_offset.scale(0, 1) \ - + vector(0.5 * self.bitcell.width- 0.5 * self.nmos.active_width, 0) self.nmos_lower = self.add_inst(name="mux_tx1", - mod=self.nmos, - offset=nmos_lower_position) + mod=self.nmos) self.connect_inst(["bl", "sel", "bl_out", "gnd"]) # This aligns it directly above the other tx with gates abutting - nmos_upper_position = nmos_lower_position \ - + vector(0, self.nmos.active_height + max(self.active_space, self.poly_space)) self.nmos_upper = self.add_inst(name="mux_tx2", - mod=self.nmos, - offset=nmos_upper_position) + mod=self.nmos) self.connect_inst(["br", "sel", "br_out", "gnd"]) + + def place_ptx(self): + """ Create the two pass gate NMOS transistors to switch the bitlines""" + + # Space it in the center + nmos_lower_position = self.nmos.active_offset.scale(0, 1) \ + + vector(0.5 * self.bitcell.width- 0.5 * self.nmos.active_width, 0) + self.nmos_lower.place(nmos_lower_position) + + # This aligns it directly above the other tx with gates abutting + nmos_upper_position = nmos_lower_position \ + + vector(0, self.nmos.active_height + max(self.active_space, self.poly_space)) + self.nmos_upper.place(nmos_upper_position) if OPTS.tech_name == "sky130": self.add_implants() diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index a28581d8..4d9eb151 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -30,13 +30,15 @@ if not OPTS.check_lvsdrc: OPTS.drc_exe = None OPTS.lvs_exe = None OPTS.pex_exe = None + if OPTS.tech_name == "sky130": + OPTS.magic_exe = None else: debug.info(1, "Finding DRC/LVS/PEX tools.") OPTS.drc_exe = get_tool("DRC", ["calibre", "assura", "magic"], drc_name) OPTS.lvs_exe = get_tool("LVS", ["calibre", "assura", "netgen"], lvs_name) OPTS.pex_exe = get_tool("PEX", ["calibre", "magic"], pex_name) if OPTS.tech_name == "sky130": - OPTS.magic_exe = get_tool("GDS", ["magic"], None) + OPTS.magic_exe = get_tool("GDS", ["magic"]) if not OPTS.drc_exe: from .none import run_drc, print_drc_stats @@ -71,7 +73,7 @@ else: debug.warning("Did not find a supported PEX tool.") if OPTS.tech_name == "sky130": - if "magic"==OPTS.magic_exe[0]: + if OPTS.magic_exe and "magic"==OPTS.magic_exe[0]: from .magic import filter_gds else: debug.warning("Did not find Magic.") From e502ee02be2a2fa2cf9b524fa73e1bb3f1062519 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 13 Jul 2020 15:51:46 -0700 Subject: [PATCH 516/521] Place before computing height of col mux. --- compiler/pgates/single_level_column_mux.py | 30 ++++++++++------------ 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index ca7c3e51..d2dbacc1 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -39,7 +39,6 @@ class single_level_column_mux(pgate.pgate): return "br" def create_netlist(self): - self.add_modules() self.add_pins() self.add_ptx() @@ -54,16 +53,18 @@ class single_level_column_mux(pgate.pgate): self.pin_pitch = getattr(self, "{}_pitch".format(self.pin_layer)) self.pin_width = getattr(self, "{}_width".format(self.pin_layer)) self.pin_height = 2 * self.pin_width + + self.place_ptx() + self.width = self.bitcell.width self.height = self.nmos_upper.uy() + self.pin_height - self.place_ptx() self.connect_poly() self.add_bitline_pins() self.connect_bitlines() self.add_pn_wells() - def add_modules(self): + def add_ptx(self): self.bitcell = factory.create(module_type="bitcell") # Adds nmos_lower,nmos_upper to the module @@ -72,6 +73,16 @@ class single_level_column_mux(pgate.pgate): width=self.ptx_width) self.add_mod(self.nmos) + # Space it in the center + self.nmos_lower = self.add_inst(name="mux_tx1", + mod=self.nmos) + self.connect_inst(["bl", "sel", "bl_out", "gnd"]) + + # This aligns it directly above the other tx with gates abutting + self.nmos_upper = self.add_inst(name="mux_tx2", + mod=self.nmos) + self.connect_inst(["br", "sel", "br_out", "gnd"]) + def add_pins(self): self.add_pin_list(["bl", "br", "bl_out", "br_out", "sel", "gnd"]) @@ -100,19 +111,6 @@ class single_level_column_mux(pgate.pgate): layer=self.pin_layer, offset=br_pos, height=self.pin_height) - - def add_ptx(self): - """ Create the two pass gate NMOS transistors to switch the bitlines""" - - # Space it in the center - self.nmos_lower = self.add_inst(name="mux_tx1", - mod=self.nmos) - self.connect_inst(["bl", "sel", "bl_out", "gnd"]) - - # This aligns it directly above the other tx with gates abutting - self.nmos_upper = self.add_inst(name="mux_tx2", - mod=self.nmos) - self.connect_inst(["br", "sel", "br_out", "gnd"]) def place_ptx(self): """ Create the two pass gate NMOS transistors to switch the bitlines""" From bb8157b3b7ec940f27514cc97e868fad26070814 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 14 Jul 2020 08:38:49 -0700 Subject: [PATCH 517/521] Exit on DRC not run, check for LVSDRC before running in sram_base. --- compiler/sram/sram_base.py | 2 +- compiler/verify/none.py | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index b16c28fa..12af7cf6 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -129,7 +129,7 @@ class sram_base(design, verilog, lef): start_time = datetime.datetime.now() # We only enable final verification if we have routed the design - self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=True) + self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc) if not OPTS.is_unit_test: print_time("Verification", datetime.datetime.now(), start_time) diff --git a/compiler/verify/none.py b/compiler/verify/none.py index 41e5780e..f82d59ae 100644 --- a/compiler/verify/none.py +++ b/compiler/verify/none.py @@ -20,7 +20,7 @@ pex_warned = False def run_drc(cell_name, gds_name, extract=False, final_verification=False): global drc_warned if not drc_warned: - debug.warning("DRC unable to run.") + debug.error("DRC unable to run.", -1) drc_warned=True # Since we warned, return a failing test. return 1 @@ -29,7 +29,7 @@ def run_drc(cell_name, gds_name, extract=False, final_verification=False): def run_lvs(cell_name, gds_name, sp_name, final_verification=False): global lvs_warned if not lvs_warned: - debug.warning("LVS unable to run.") + debug.error("LVS unable to run.", -1) lvs_warned=True # Since we warned, return a failing test. return 1 @@ -38,7 +38,7 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): def run_pex(name, gds_name, sp_name, output=None, final_verification=False): global pex_warned if not pex_warned: - debug.warning("PEX unable to run.") + debug.error("PEX unable to run.", -1) pex_warned=True # Since we warned, return a failing test. return 1 From c7bc01c3a973c75e942f3a8f20034a50fe7395ea Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 15 Jul 2020 17:15:42 -0700 Subject: [PATCH 518/521] Clean up binning. Fix mults to 1 for certain gates. --- compiler/pgates/pgate.py | 100 ++++++++++++++++++++--------------- compiler/pgates/pinv.py | 8 +-- compiler/pgates/pinv_dec.py | 6 +-- compiler/pgates/pnand2.py | 4 +- compiler/pgates/pnand3.py | 4 +- compiler/pgates/pnor2.py | 4 +- compiler/pgates/precharge.py | 5 +- compiler/pgates/ptx.py | 2 +- 8 files changed, 70 insertions(+), 63 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 985c8a86..1e55d5fb 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -372,66 +372,78 @@ class pgate(design.design): self.width = width @staticmethod - def bin_width(tx_type, target_width): + def best_bin(tx_type, target_width): + """ + Determine the width transistor that meets the accuracy requirement and is larger than target_width. + """ + + # Find all of the relavent scaled bins and multiples + scaled_bins = pgate.scaled_bins(tx_type, target_width) + for (scaled_width, multiple) in scaled_bins: + if abs(target_width - scaled_width) / target_width <= 1 - OPTS.accuracy_requirement: + break + else: + debug.error("failed to bin tx size {}, try reducing accuracy requirement".format(target_width), 1) + + debug.info(2, "binning {0} tx, target: {4}, found {1} x {2} = {3}".format(tx_type, + multiple, + scaled_width / multiple, + scaled_width, + target_width)) + + return(scaled_width / multiple, multiple) + + @staticmethod + def scaled_bins(tx_type, target_width): + """ + Determine a set of widths and multiples that could be close to the right size + sorted by the fewest number of fingers. + """ if tx_type == "nmos": bins = nmos_bins[drc("minwidth_poly")] elif tx_type == "pmos": bins = pmos_bins[drc("minwidth_poly")] else: debug.error("invalid tx type") - + + # Prune out bins that are too big, except for one bigger bins = bins[0:bisect_left(bins, target_width) + 1] + + # Determine multiple of target width for each bin if len(bins) == 1: - selected_bin = bins[0] - scaling_factor = math.ceil(target_width / selected_bin) - scaled_bin = bins[0] * scaling_factor - + scaled_bins = [(bins[0], math.ceil(target_width / bins[0]))] else: - base_bins = [] scaled_bins = [] - scaling_factors = [] + # Add the biggest size as 1x multiple + scaled_bins.append((bins[-1], 1)) + # Compute discrete multiple of other sizes + for width in reversed(bins[:-1]): + multiple = math.ceil(target_width / width) + scaled_bins.append((multiple * width, multiple)) - for width in bins: - m = math.ceil(target_width / width) - base_bins.append(width) - scaling_factors.append(m) - scaled_bins.append(m * width) - - select = -1 - for i in reversed(range(0, len(scaled_bins))): - if abs(target_width - scaled_bins[i])/target_width <= 1-OPTS.accuracy_requirement: - select = i - break - if select == -1: - debug.error("failed to bin tx size {}, try reducing accuracy requirement".format(target_width), 1) - scaling_factor = scaling_factors[select] - scaled_bin = scaled_bins[select] - selected_bin = base_bins[select] - - debug.info(2, "binning {0} tx, target: {4}, found {1} x {2} = {3}".format(tx_type, selected_bin, scaling_factor, selected_bin * scaling_factor, target_width)) - - return(selected_bin, scaling_factor) - - def permute_widths(self, tx_type, target_width): + return(scaled_bins) + @staticmethod + def nearest_bin(tx_type, target_width): + """ + Determine the nearest width to the given target_width + while assuming a single multiple. + """ if tx_type == "nmos": bins = nmos_bins[drc("minwidth_poly")] elif tx_type == "pmos": bins = pmos_bins[drc("minwidth_poly")] else: - debug.error("invalid tx type") - bins = bins[0:bisect_left(bins, target_width) + 1] - if len(bins) == 1: - scaled_bins = [(bins[0], math.ceil(target_width / bins[0]))] - else: - scaled_bins = [] - scaled_bins.append((bins[-1], 1)) - for width in bins[:-1]: - m = math.ceil(target_width / width) - scaled_bins.append((m * width, m)) + debug.error("invalid tx type") - return(scaled_bins) - - def bin_accuracy(self, ideal_width, width): - return 1-abs((ideal_width - width)/ideal_width) + # Find the next larger bin + bin_loc = bisect_left(bins, target_width) + if bin_loc < len(bins): + return bins[bin_loc] + else: + return bins[-1] + + @staticmethod + def bin_accuracy(ideal_width, width): + return 1 - abs((ideal_width - width) / ideal_width) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index aa0f7d9a..4caf2a18 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -14,15 +14,11 @@ from vector import vector from math import ceil from globals import OPTS from utils import round_to_grid -from bisect import bisect_left import logical_effort from sram_factory import factory from errors import drc_error -if(OPTS.tech_name == "sky130"): - from tech import nmos_bins, pmos_bins - class pinv(pgate.pgate): """ Pinv generates gds of a parametrically sized inverter. The @@ -164,8 +160,8 @@ class pinv(pgate.pgate): else: self.nmos_width = self.nmos_size * drc("minwidth_tx") self.pmos_width = self.pmos_size * drc("minwidth_tx") - nmos_bins = self.permute_widths("nmos", self.nmos_width) - pmos_bins = self.permute_widths("pmos", self.pmos_width) + nmos_bins = self.scaled_bins("nmos", self.nmos_width) + pmos_bins = self.scaled_bins("pmos", self.pmos_width) valid_pmos = [] for bin in pmos_bins: diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py index 4d4f2229..672bde2d 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/pgates/pinv_dec.py @@ -13,6 +13,7 @@ from vector import vector from globals import OPTS from sram_factory import factory + class pinv_dec(pinv.pinv): """ This is another version of pinv but with layout for the decoder. @@ -50,9 +51,8 @@ class pinv_dec(pinv.pinv): self.nmos_width = self.nmos_size * drc("minwidth_tx") self.pmos_width = self.pmos_size * drc("minwidth_tx") if OPTS.tech_name == "sky130": - (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) - (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) - return + self.nmos_width = self.nearest_bin("nmos", self.nmos_width) + self.pmos_width = self.nearest_bin("pmos", self.pmos_width) # Over-ride the route input gate to call the horizontal version. # Other top-level netlist and layout functions are not changed. diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 3974d95b..fb6bb210 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -39,8 +39,8 @@ class pnand2(pgate.pgate): self.tx_mults = 1 if OPTS.tech_name == "sky130": - (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) - (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) + self.nmos_width = self.nearest_bin("nmos", self.nmos_width) + self.pmos_width = self.nearest_bin("pmos", self.pmos_width) # Creates the netlist and layout pgate.pgate.__init__(self, name, height, add_wells) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index ff988d88..e4e71e61 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -42,8 +42,8 @@ class pnand3(pgate.pgate): self.tx_mults = 1 if OPTS.tech_name == "sky130": - (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) - (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) + self.nmos_width = self.nearest_bin("nmos", self.nmos_width) + self.pmos_width = self.nearest_bin("pmos", self.pmos_width) # Creates the netlist and layout pgate.pgate.__init__(self, name, height, add_wells) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 908bba82..aad405e8 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -38,8 +38,8 @@ class pnor2(pgate.pgate): self.tx_mults = 1 if OPTS.tech_name == "sky130": - (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width) - (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width) + self.nmos_width = self.nearest_bin("nmos", self.nmos_width) + self.pmos_width = self.nearest_bin("pmos", self.pmos_width) # Creates the netlist and layout pgate.pgate.__init__(self, name, height, add_wells) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index b3d25865..52d24390 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -9,11 +9,10 @@ import contact import design import debug from pgate import pgate -from tech import parameter +from tech import parameter, drc from vector import vector from globals import OPTS from sram_factory import factory -from tech import drc, layer class precharge(design.design): @@ -81,7 +80,7 @@ class precharge(design.design): Initializes the upper and lower pmos """ if(OPTS.tech_name == "sky130"): - (self.ptx_width, self.ptx_mults) = pgate.bin_width("pmos", self.ptx_width) + self.ptx_width = pgate.nearest_bin("pmos", self.ptx_width) self.pmos = factory.create(module_type="ptx", width=self.ptx_width, mults=self.ptx_mults, diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index ce8591fd..b6f839f3 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -131,7 +131,7 @@ class ptx(design.design): perimeter_sd = 2 * self.poly_width + 2 * self.tx_width if OPTS.tech_name == "sky130" and OPTS.lvs_exe and OPTS.lvs_exe[0] == "calibre": # sky130 simulation cannot use the mult parameter in simulation - (self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) + (self.tx_width, self.mults) = pgate.best_bin(self.tx_type, self.tx_width) main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], self.mults, self.tx_width, From ba3d32fa0cae6455665770a7f5c2a54ad50e065a Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 16:42:25 -0700 Subject: [PATCH 519/521] Starting to implement minimizing channel router (not done) --- compiler/base/channel_route.py | 265 +++++++++++++++++++++------------ compiler/sram/sram_1bank.py | 30 ++-- 2 files changed, 191 insertions(+), 104 deletions(-) diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py index cd4bbdc1..5ea5de78 100644 --- a/compiler/base/channel_route.py +++ b/compiler/base/channel_route.py @@ -12,6 +12,69 @@ from vector import vector import design +class channel_net(): + def __init__(self, net_name, pins, vertical): + self.name = net_name + self.pins = pins + self.vertical = vertical + + # Keep track of the internval + if vertical: + self.min_value = min(i.by() for i in pins) + self.max_value = max(i.uy() for i in pins) + else: + self.min_value = min(i.lx() for i in pins) + self.max_value = max(i.rx() for i in pins) + + # Keep track of the conflicts + self.conflicts = [] + + def __str__(self): + return self.name + + def __repr__(self): + return self.name + + def __lt__(self, other): + return self.min_value < other.min_value + + def vcg_pin_overlap(self, pin1, pin2, pitch): + """ Check for vertical or horizontal overlap of the two pins """ + + # FIXME: If the pins are not in a row, this may break. + # However, a top pin shouldn't overlap another top pin, + # for example, so the extra comparison *shouldn't* matter. + + # Pin 1 must be in the "BOTTOM" set + x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x - pin2.center().x) < pitch + + # Pin 1 must be in the "LEFT" set + y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y - pin2.center().y) < pitch + overlaps = (not self.vertical and x_overlap) or (self.vertical and y_overlap) + return overlaps + + def vcg_nets_overlap(self, other, pitch): + """ + Check all the pin pairs on two nets and return a pin + overlap if any pin overlaps. + """ + + for pin1 in self.pins: + for pin2 in other.pins: + if self.vcg_pin_overlap(pin1, pin2, pitch): + return True + + return False + + def hcg_nets_overlap(self, other): + """ + Check if the horizontal span of the two nets overlaps eachother. + """ + min_overlap = self.min_value >= other.min_value and self.min_value <= other.max_value + max_overlap = self.max_value >= other.min_value and self.max_value <= other.max_value + return min_overlap or max_overlap + + class channel_route(design.design): unique_id = 0 @@ -86,104 +149,112 @@ class channel_route(design.design): # FIXME: This is O(n^2), so maybe optimize it. for other_pin, conflicts in g.items(): if pin in conflicts: - conflicts.remove(pin) - g[other_pin]=conflicts + g[other_pin].remove(pin) return g + + def route(self): + # Create names for the nets for the graphs + nets = [] + index = 0 + # print(self.netlist) + for pin_list in self.netlist: + nets.append(channel_net("n{}".format(index), pin_list, self.vertical)) + index += 1 - def vcg_nets_overlap(self, net1, net2): - """ - Check all the pin pairs on two nets and return a pin - overlap if any pin overlaps. - """ + # Create the (undirected) horizontal constraint graph + hcg = collections.OrderedDict() + for net1 in nets: + for net2 in nets: + if net1.name == net2.name: + continue + if net1.hcg_nets_overlap(net2): + try: + hcg[net1.name].append(net2.name) + except KeyError: + hcg[net1.name] = [net2.name] + try: + hcg[net2.name].append(net1.name) + except KeyError: + hcg[net2.name] = [net1.name] + + # Initialize the vertical conflict graph (vcg) + # and make a list of all pins + vcg = collections.OrderedDict() + + # print("Nets:") + # for net_name in nets: + # print(net_name, [x.name for x in nets[net_name]]) + + # Find the vertical pin conflicts + # FIXME: O(n^2) but who cares for now if self.vertical: pitch = self.horizontal_nonpref_pitch else: pitch = self.vertical_nonpref_pitch - for pin1 in net1: - for pin2 in net2: - if self.vcg_pin_overlap(pin1, pin2, pitch): - return True + for net in nets: + vcg[net.name] = [] - return False - - def route(self): - # FIXME: Must extend this to a horizontal conflict graph - # too if we want to minimize the - # number of tracks! - # hcg = {} - - # Initialize the vertical conflict graph (vcg) - # and make a list of all pins - vcg = collections.OrderedDict() - - # Create names for the nets for the graphs - nets = collections.OrderedDict() - index = 0 - # print(netlist) - for pin_list in self.netlist: - net_name = "n{}".format(index) - index += 1 - nets[net_name] = pin_list - - # print("Nets:") - # for net_name in nets: - # print(net_name, [x.name for x in nets[net_name]]) - - # Find the vertical pin conflicts - # FIXME: O(n^2) but who cares for now - for net_name1 in nets: - if net_name1 not in vcg.keys(): - vcg[net_name1] = [] - for net_name2 in nets: - if net_name2 not in vcg.keys(): - vcg[net_name2] = [] + for net1 in nets: + for net2 in nets: # Skip yourself - if net_name1 == net_name2: + if net1.name == net2.name: continue - if self.vcg_nets_overlap(nets[net_name1], - nets[net_name2]): - vcg[net_name2].append(net_name1) + + if net1.vcg_nets_overlap(net2, pitch): + vcg[net2.name].append(net1.name) current_offset = self.offset - - # list of routes to do - while vcg: + + # Sort nets by left edge value + nets.sort() + while len(nets) > 0: + + current_offset_value = current_offset.y if self.vertical else current_offset.x + # from pprint import pformat # print("VCG:\n", pformat(vcg)) + # for name,net in vcg.items(): + # print(name, net.min_value, net.max_value, net.conflicts) + # print(current_offset) # get a route from conflict graph with empty fanout set - net_name = None - for net_name, conflicts in vcg.items(): - if len(conflicts) == 0: - vcg = self.remove_net_from_graph(net_name, vcg) + for net in nets: + # If it has no conflicts and the interval is to the right of the current offset in the track + if net.min_value > current_offset_value and len(vcg[net.name]) == 0: + # print("Routing {}".format(net.name)) + # Add the trunk routes from the bottom up for + # horizontal or the left to right for vertical + if self.vertical: + self.add_vertical_trunk_route(net.pins, + current_offset, + self.vertical_nonpref_pitch) + current_offset = vector(current_offset.x, net.max_value + self.horizontal_nonpref_pitch) + else: + self.add_horizontal_trunk_route(net.pins, + current_offset, + self.horizontal_nonpref_pitch) + current_offset = vector(net.max_value + self.vertical_nonpref_pitch, current_offset.y) + + # Remove the net from other constriants in the VCG + vcg = self.remove_net_from_graph(net.name, vcg) + nets.remove(net) + break else: - # FIXME: We don't support cyclic VCGs right now. - debug.error("Cyclic VCG in channel router.", -1) - - # These are the pins we'll have to connect - pin_list = nets[net_name] - # print("Routing:", net_name, [x.name for x in pin_list]) - - # Remove the net from other constriants in the VCG - vcg = self.remove_net_from_graph(net_name, vcg) - - # Add the trunk routes from the bottom up for - # horizontal or the left to right for vertical - if self.vertical: - self.add_vertical_trunk_route(pin_list, - current_offset, - self.vertical_nonpref_pitch) - # This accounts for the via-to-via spacings - current_offset += vector(self.horizontal_nonpref_pitch, 0) - else: - self.add_horizontal_trunk_route(pin_list, - current_offset, - self.horizontal_nonpref_pitch) - # This accounts for the via-to-via spacings - current_offset += vector(0, self.vertical_nonpref_pitch) + # If we made a full pass and the offset didn't change... + current_offset_value = current_offset.y if self.vertical else current_offset.x + initial_offset_value = self.offset.y if self.vertical else self.offset.x + if current_offset_value == initial_offset_value: + # FIXME: We don't support cyclic VCGs right now. + debug.error("Cyclic VCG in channel router.", -1) + # Increment the track and reset the offset to the start (like a typewriter) + if self.vertical: + current_offset = vector(current_offset.x + self.horizontal_nonpref_pitch, self.offset.y) + else: + current_offset = vector(self.offset.x, current_offset.y + self.vertical_nonpref_pitch) + # Return the size of the channel if self.vertical: self.width = 0 @@ -226,6 +297,17 @@ class channel_route(design.design): self.add_path(self.vertical_layer, [vector(min_x - half_layer_width, trunk_offset.y), vector(max_x + half_layer_width, trunk_offset.y)]) + + # Route each pin to the trunk + for pin in pins: + if pin.cy() < trunk_offset.y: + pin_pos = pin.uc() + else: + pin_pos = pin.bc() + + # No bend needed here + mid = vector(pin_pos.x, trunk_offset.y) + self.add_path(self.vertical_layer, [pin_pos, mid]) else: # Add the horizontal trunk self.add_path(self.horizontal_layer, @@ -269,6 +351,17 @@ class channel_route(design.design): self.add_path(self.horizontal_layer, [vector(trunk_offset.x, min_y - half_layer_width), vector(trunk_offset.x, max_y + half_layer_width)]) + + # Route each pin to the trunk + for pin in pins: + # Find the correct side of the pin + if pin.cx() < trunk_offset.x: + pin_pos = pin.rc() + else: + pin_pos = pin.lc() + # No bend needed here + mid = vector(trunk_offset.x, pin_pos.y) + self.add_path(self.horizontal_layer, [pin_pos, mid]) else: # Add the vertical trunk self.add_path(self.vertical_layer, @@ -292,18 +385,4 @@ class channel_route(design.design): to_layer=self.horizontal_layer, offset=pin_pos) - def vcg_pin_overlap(self, pin1, pin2, pitch): - """ Check for vertical or horizontal overlap of the two pins """ - - # FIXME: If the pins are not in a row, this may break. - # However, a top pin shouldn't overlap another top pin, - # for example, so the extra comparison *shouldn't* matter. - - # Pin 1 must be in the "BOTTOM" set - x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x - pin2.center().x) < pitch - - # Pin 1 must be in the "LEFT" set - y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y - pin2.center().y) < pitch - overlaps = (not self.vertical and x_overlap) or (self.vertical and y_overlap) - return overlaps diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index a9731ed5..18f3414c 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -384,6 +384,14 @@ class sram_1bank(sram_base): bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] route_map.extend(list(zip(bank_pins, sram_pins))) + # spare wen dff + if self.num_spare_cols > 0 and port in self.write_ports: + dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)] + dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names] + bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)] + bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + route_map.extend(list(zip(bank_pins, dff_pins))) + if self.num_wmasks > 0 and port in self.write_ports: layer_stack = self.m3_stack else: @@ -401,17 +409,17 @@ class sram_1bank(sram_base): offset=offset, layer_stack=layer_stack) - # Route these separately because sometimes the pin pitch on the write driver is too narrow for M3 (FreePDK45) - # spare wen dff - if self.num_spare_cols > 0 and port in self.write_ports: - dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)] - dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names] - bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)] - bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] - route_map = zip(bank_pins, dff_pins) - self.create_horizontal_channel_route(netlist=route_map, - offset=offset, - layer_stack=self.m1_stack) + # # Route these separately because sometimes the pin pitch on the write driver is too narrow for M3 (FreePDK45) + # # spare wen dff + # if self.num_spare_cols > 0 and port in self.write_ports: + # dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)] + # dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names] + # bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)] + # bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + # route_map = zip(bank_pins, dff_pins) + # self.create_horizontal_channel_route(netlist=route_map, + # offset=offset, + # layer_stack=self.m1_stack) def route_clk(self): """ Route the clock network """ From 9d5d632d1a58d57605ec7d3271f106950c738cae Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Jul 2020 14:23:48 -0700 Subject: [PATCH 520/521] Pins may be below the channel. --- compiler/base/channel_route.py | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py index 5ea5de78..f2711222 100644 --- a/compiler/base/channel_route.py +++ b/compiler/base/channel_route.py @@ -169,13 +169,13 @@ class channel_route(design.design): continue if net1.hcg_nets_overlap(net2): try: - hcg[net1.name].append(net2.name) + hcg[net1.name].add(net2.name) except KeyError: - hcg[net1.name] = [net2.name] + hcg[net1.name] = set([net2.name]) try: - hcg[net2.name].append(net1.name) + hcg[net2.name].add(net1.name) except KeyError: - hcg[net2.name] = [net1.name] + hcg[net2.name] = set([net1.name]) # Initialize the vertical conflict graph (vcg) @@ -194,7 +194,7 @@ class channel_route(design.design): pitch = self.vertical_nonpref_pitch for net in nets: - vcg[net.name] = [] + vcg[net.name] = set() for net1 in nets: for net2 in nets: @@ -203,9 +203,19 @@ class channel_route(design.design): continue if net1.vcg_nets_overlap(net2, pitch): - vcg[net2.name].append(net1.name) + vcg[net2.name].add(net1.name) - current_offset = self.offset + # Check if there are any cycles net1 <---> net2 in the VCG + + + # Some of the pins may be to the left/below the channel offset, + # so adjust if this is the case + min_value = min([n.min_value for n in nets]) + if self.vertical: + real_channel_offset = vector(self.offset.x, min_value) + else: + real_channel_offset = vector(min_value, self.offset.y) + current_offset = real_channel_offset # Sort nets by left edge value nets.sort() @@ -221,7 +231,7 @@ class channel_route(design.design): # get a route from conflict graph with empty fanout set for net in nets: # If it has no conflicts and the interval is to the right of the current offset in the track - if net.min_value > current_offset_value and len(vcg[net.name]) == 0: + if net.min_value >= current_offset_value and len(vcg[net.name]) == 0: # print("Routing {}".format(net.name)) # Add the trunk routes from the bottom up for # horizontal or the left to right for vertical @@ -244,16 +254,16 @@ class channel_route(design.design): else: # If we made a full pass and the offset didn't change... current_offset_value = current_offset.y if self.vertical else current_offset.x - initial_offset_value = self.offset.y if self.vertical else self.offset.x + initial_offset_value = real_channel_offset.y if self.vertical else real_channel_offset.x if current_offset_value == initial_offset_value: # FIXME: We don't support cyclic VCGs right now. debug.error("Cyclic VCG in channel router.", -1) # Increment the track and reset the offset to the start (like a typewriter) if self.vertical: - current_offset = vector(current_offset.x + self.horizontal_nonpref_pitch, self.offset.y) + current_offset = vector(current_offset.x + self.horizontal_nonpref_pitch, real_channel_offset.y) else: - current_offset = vector(self.offset.x, current_offset.y + self.vertical_nonpref_pitch) + current_offset = vector(real_channel_offset.x, current_offset.y + self.vertical_nonpref_pitch) # Return the size of the channel if self.vertical: From 80070dff41ab59b8857065f90e9871053a468e61 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Jul 2020 14:47:14 -0700 Subject: [PATCH 521/521] Move write_driver din left to avoid control signal in spare columns. --- technology/freepdk45/gds_lib/write_driver.gds | Bin 20480 -> 20332 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/technology/freepdk45/gds_lib/write_driver.gds b/technology/freepdk45/gds_lib/write_driver.gds index 86015e7a7991ff9a3775c8e11fa1fee5ce5113a1..5e4fb15ab9f9db68a2b602c6ffd296e1ef35ad41 100644 GIT binary patch delta 315 zcmZoz!1!h!V;ln;0~1pOgA5}R`x6Fs1_1^>1|0@vWHtj26I)7ZT4HHV2?K)&Gpn7# zk=aWh2OqFhiV?ryyXGB(3@c8(8{>p@CRZ7XZa%N`iEDDXjuh*eGiOd0OrEBry?MF? zFXQAVmTM-<*b8lbXZ4O{a)5=Xq5%UKFac>s2?hqHJqQ{k!DKMG%|c$)8Ys#M#2|Vq zR27VdiE~b}P*(w4$G{`Q>a+!7FawVOGf+bVkmtt0A<34KnK${rxdzl-56s=6EFBA# U$!r#iP#%+mD}=S#$3cM~0HTpkTmS$7 delta 475 zcmaDekFj9^V;ln;0}~L-FfuXl16cwL+zh4+S`5Mr91NTcTnyR_#tb}6Y$>T}iKRIu z3=AU7tab`VW-oml{LNA+M*M>Bns*E`tV|4iKz))x9U2TK$a*)%3F%BOFjr(f%K!wE zr}xLt70I!8hq89qtC(>xFtG75G4L|5@i76_>j*G2Ffdhvv_fb`2?hpc zb_NC*4H2Kb!A^eidGr5DjBP+EP9O%+Q=v*>G+2DHft}psa~5kRyV)zMg5AWxBg5*n z1#ANY0}t53(?Fg#1BWDAN@gCz<`PRbR*-V2GnpJ*A*{_l4hsDBP>lmciDI=F0GQ=B AhX4Qo