From ddeb40c9bf8b67838122f4fa0db427498db81001 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 4 Mar 2019 16:27:10 -0800 Subject: [PATCH] Added lib test which generates multiple corner models. Only does process currently. --- compiler/characterizer/lib.py | 21 +- .../tests/23_lib_sram_model_corners_test.py | 69 ++++ ..._16_1_freepdk45_FF_1p0V_25C_analytical.lib | 321 ++++++++++++++++++ ..._16_1_freepdk45_SS_1p0V_25C_analytical.lib | 321 ++++++++++++++++++ ...16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 321 ++++++++++++++++++ ...16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 321 ++++++++++++++++++ 6 files changed, 1363 insertions(+), 11 deletions(-) create mode 100755 compiler/tests/23_lib_sram_model_corners_test.py create mode 100644 compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib create mode 100644 compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib create mode 100644 compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib create mode 100644 compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 00b39af5..d24c931d 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -483,17 +483,16 @@ class lib: self.lib.write(" }\n") def compute_delay(self): - """ Do the analysis if we haven't characterized the SRAM yet """ - if not hasattr(self,"d"): - self.d = delay(self.sram, self.sp_file, self.corner) - if self.use_model: - char_results = self.d.analytical_delay(self.slews,self.loads) - self.char_sram_results, self.char_port_results = char_results - else: - probe_address = "1" * self.sram.addr_size - probe_data = self.sram.word_size - 1 - char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads) - self.char_sram_results, self.char_port_results = char_results + """Compute SRAM delays for current corner""" + self.d = delay(self.sram, self.sp_file, self.corner) + if self.use_model: + char_results = self.d.analytical_delay(self.slews,self.loads) + self.char_sram_results, self.char_port_results = char_results + else: + probe_address = "1" * self.sram.addr_size + probe_data = self.sram.word_size - 1 + char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads) + self.char_sram_results, self.char_port_results = char_results def compute_setup_hold(self): """ Do the analysis if we haven't characterized a FF yet """ diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py new file mode 100755 index 00000000..431555bc --- /dev/null +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -0,0 +1,69 @@ +#!/usr/bin/env python3 +""" +Check the .lib file for an SRAM +""" + +import unittest +from testutils import header,openram_test +import sys,os,re +sys.path.append(os.path.join(sys.path[0],"..")) +import globals +from globals import OPTS +import debug + +class model_corners_lib_test(openram_test): + + def runTest(self): + globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + + from characterizer import lib + from sram import sram + from sram_config import sram_config + c = sram_config(word_size=2, + num_words=16, + num_banks=1) + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank") + s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) + tempspice = OPTS.openram_temp + "temp.sp" + s.sp_write(tempspice) + + #Set the corners. Lib will create a power set of the lists. + if OPTS.tech_name == "scn4m_subm": + OPTS.process_corners = ["TT", "SS", "FF"] + OPTS.supply_voltages = [5.0] + OPTS.temperatures = [25] + elif OPTS.tech_name == "freepdk45": + OPTS.process_corners = ["TT", "SS", "FF"] + OPTS.supply_voltages = [1.0] + OPTS.temperatures = [25] + + lib(out_dir=OPTS.openram_temp, sram=s.s, sp_file=tempspice, use_model=True) + + # get all of the .lib files generated + files = os.listdir(OPTS.openram_temp) + nametest = re.compile("\.lib$", re.IGNORECASE) + lib_files = filter(nametest.search, files) + + # and compare them with the golden model + for filename in lib_files: + newname = filename.replace(".lib","_analytical.lib") + libname = "{0}/{1}".format(OPTS.openram_temp,filename) + golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname) + self.assertTrue(self.isapproxdiff(libname,golden,0.15)) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main() + + + + + + diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib new file mode 100644 index 00000000..88b54eca --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -0,0 +1,321 @@ +library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 1.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.00125, 0.005, 0.04"); + index_2("0.052275, 0.2091, 1.6728"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.00125, 0.005, 0.04"); + index_2("0.00125, 0.005, 0.04"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_freepdk45){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 1124.88; + + leakage_power () { + when : "CSb0"; + value : 0.000167; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 0.2091; + memory_write(){ + address : ADDR0; + clocked_on : clk0; + } + pin(DIN0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 1.6728; + min_capacitance : 0.052275; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk0"; + timing_type : falling_edge; + cell_rise(CELL_TABLE) { + values("0.088, 0.088, 0.088",\ + "0.088, 0.088, 0.088",\ + "0.088, 0.088, 0.088"); + } + cell_fall(CELL_TABLE) { + values("0.088, 0.088, 0.088",\ + "0.088, 0.088, 0.088",\ + "0.088, 0.088, 0.088"); + } + rise_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 0.2091; + max_transition : 0.04; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 0.2091; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 0.2091; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk0){ + clock : true; + direction : input; + capacitance : 0.2091; + internal_power(){ + when : "!CSb0 & clk0 & !WEb0"; + rise_power(scalar){ + values("0.033101244168888884"); + } + fall_power(scalar){ + values("0.033101244168888884"); + } + } + internal_power(){ + when : "!CSb0 & !clk0 & WEb0"; + rise_power(scalar){ + values("0.033101244168888884"); + } + fall_power(scalar){ + values("0.033101244168888884"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.009"); + } + fall_constraint(scalar) { + values("0.009"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.018"); + } + fall_constraint(scalar) { + values("0.018"); + } + } + } + + } +} diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib new file mode 100644 index 00000000..e78fe8d3 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -0,0 +1,321 @@ +library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 1.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.00125, 0.005, 0.04"); + index_2("0.052275, 0.2091, 1.6728"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.00125, 0.005, 0.04"); + index_2("0.00125, 0.005, 0.04"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_freepdk45){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 1124.88; + + leakage_power () { + when : "CSb0"; + value : 0.000167; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 0.2091; + memory_write(){ + address : ADDR0; + clocked_on : clk0; + } + pin(DIN0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 1.6728; + min_capacitance : 0.052275; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk0"; + timing_type : falling_edge; + cell_rise(CELL_TABLE) { + values("0.107, 0.107, 0.107",\ + "0.107, 0.107, 0.107",\ + "0.107, 0.107, 0.107"); + } + cell_fall(CELL_TABLE) { + values("0.107, 0.107, 0.107",\ + "0.107, 0.107, 0.107",\ + "0.107, 0.107, 0.107"); + } + rise_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 0.2091; + max_transition : 0.04; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 0.2091; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 0.2091; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk0){ + clock : true; + direction : input; + capacitance : 0.2091; + internal_power(){ + when : "!CSb0 & clk0 & !WEb0"; + rise_power(scalar){ + values("0.033101244168888884"); + } + fall_power(scalar){ + values("0.033101244168888884"); + } + } + internal_power(){ + when : "!CSb0 & !clk0 & WEb0"; + rise_power(scalar){ + values("0.033101244168888884"); + } + fall_power(scalar){ + values("0.033101244168888884"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.0105"); + } + fall_constraint(scalar) { + values("0.0105"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.021"); + } + fall_constraint(scalar) { + values("0.021"); + } + } + } + + } +} diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib new file mode 100644 index 00000000..5cbecd94 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -0,0 +1,321 @@ +library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 73068.14000000001; + + leakage_power () { + when : "CSb0"; + value : 0.000167; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk0; + } + pin(DIN0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk0"; + timing_type : falling_edge; + cell_rise(CELL_TABLE) { + values("0.241, 0.241, 0.241",\ + "0.241, 0.241, 0.241",\ + "0.241, 0.241, 0.241"); + } + cell_fall(CELL_TABLE) { + values("0.241, 0.241, 0.241",\ + "0.241, 0.241, 0.241",\ + "0.241, 0.241, 0.241"); + } + rise_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + fall_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk0){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk0 & !WEb0"; + rise_power(scalar){ + values("4.99880645"); + } + fall_power(scalar){ + values("4.99880645"); + } + } + internal_power(){ + when : "!CSb0 & !clk0 & WEb0"; + rise_power(scalar){ + values("4.99880645"); + } + fall_power(scalar){ + values("4.99880645"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.024"); + } + fall_constraint(scalar) { + values("0.024"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.048"); + } + fall_constraint(scalar) { + values("0.048"); + } + } + } + + } +} diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib new file mode 100644 index 00000000..3324f119 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -0,0 +1,321 @@ +library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 73068.14000000001; + + leakage_power () { + when : "CSb0"; + value : 0.000167; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk0; + } + pin(DIN0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk0"; + timing_type : falling_edge; + cell_rise(CELL_TABLE) { + values("0.294, 0.294, 0.294",\ + "0.294, 0.294, 0.294",\ + "0.294, 0.294, 0.294"); + } + cell_fall(CELL_TABLE) { + values("0.294, 0.294, 0.294",\ + "0.294, 0.294, 0.294",\ + "0.294, 0.294, 0.294"); + } + rise_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + fall_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk0){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk0 & !WEb0"; + rise_power(scalar){ + values("4.99880645"); + } + fall_power(scalar){ + values("4.99880645"); + } + } + internal_power(){ + when : "!CSb0 & !clk0 & WEb0"; + rise_power(scalar){ + values("4.99880645"); + } + fall_power(scalar){ + values("4.99880645"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.0295"); + } + fall_constraint(scalar) { + values("0.0295"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.059"); + } + fall_constraint(scalar) { + values("0.059"); + } + } + } + + } +}