From dd79fc560be1890c617446885870bf2ac8c42c3d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 26 Nov 2018 15:35:29 -0800 Subject: [PATCH] Corretct modules for add_inst --- compiler/modules/control_logic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 16c2dbe9..ed2c3fed 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -249,7 +249,7 @@ class control_logic(design.design): self.connect_inst(["clk","clk_buf","vdd","gnd"]) self.gated_clk_inst = self.add_inst(name="gated_clkbuf", - mod=self.pbuf1) + mod=self.nand2) self.connect_inst(["cs","clk_buf","gated_clk","vdd","gnd"]) def place_clkbuf_row(self,row): @@ -360,7 +360,7 @@ class control_logic(design.design): # input: we, gated_clk output: pre_w_en if self.port_type == "rw": self.pre_w_en_inst = self.add_inst(name="and_pre_w_en", - mod=self.pand2) + mod=self.and2) self.connect_inst(["we", "gated_clk", "pre_w_en", "vdd", "gnd"]) input_name = "pre_w_en" else: