PEP8 updates

compiler/modules/sense_amp_array.py

@@ -13,6 +13,7 @@ import debug
 from globals import OPTS
 import logical_effort
 
+
 class sense_amp_array(design.design):
     """
     Array of sense amplifiers to read the bitlines through the column mux.
@@ -121,7 +122,6 @@ class sense_amp_array(design.design):
             amp_position = vector(xoffset, 0)
             self.local_insts[i].place(offset=amp_position, mirror=mirror)
 
-
     def add_layout_pins(self):
         for i in range(len(self.local_insts)):
             inst = self.local_insts[i]
@@ -157,7 +157,6 @@ class sense_amp_array(design.design):
                                 width=dout_pin.width(),
                                 height=dout_pin.height())
 
-
     def route_rails(self):
         # add sclk rail across entire array
         sclk = self.amp.get_pin(self.amp.en_name)

compiler/modules/write_driver_array.py

@@ -5,14 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from math import log
 import design
-from tech import drc
 import debug
 from sram_factory import factory
 from vector import vector
 from globals import OPTS
 
+
 class write_driver_array(design.design):
     """
     Array of tristate drivers to write to the bitlines through the column mux.
@@ -119,7 +118,6 @@ class write_driver_array(design.design):
                                    self.get_br_name() + "_{0}".format(index),
                                    self.en_name, "vdd", "gnd"])
 
-
     def place_write_array(self):
         from tech import cell_properties
         if self.bitcell.width > self.driver.width:
@@ -139,7 +137,6 @@ class write_driver_array(design.design):
             base = vector(xoffset, 0)
             self.driver_insts[index].place(offset=base, mirror=mirror)
 
-
     def add_layout_pins(self):
         for i in range(self.word_size):
             inst = self.driver_insts[i]
@@ -193,9 +190,6 @@ class write_driver_array(design.design):
                                 offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1),
                                 width=self.width)
 
-
-
-
     def get_w_en_cin(self):
         """Get the relative capacitance of all the enable connections in the bank"""
         # The enable is connected to a nand2 for every row.