From d916322b74a6aec0472b13eb173f1bcd279ba0f6 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 31 Mar 2020 10:15:46 -0700 Subject: [PATCH] PEP8 updates --- compiler/modules/sense_amp_array.py | 31 +++++++++++----------- compiler/modules/write_driver_array.py | 36 +++++++++++--------------- 2 files changed, 30 insertions(+), 37 deletions(-) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 1c9c7d19..d8cb2869 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -13,6 +13,7 @@ import debug from globals import OPTS import logical_effort + class sense_amp_array(design.design): """ Array of sense amplifiers to read the bitlines through the column mux. @@ -69,7 +70,7 @@ class sense_amp_array(design.design): self.DRC_LVS() def add_pins(self): - for i in range(0,self.word_size): + for i in range(0, self.word_size): self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT") self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT") self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT") @@ -88,7 +89,7 @@ class sense_amp_array(design.design): def create_sense_amp_array(self): self.local_insts = [] - for i in range(0,self.word_size): + for i in range(0, self.word_size): name = "sa_d{0}".format(i) self.local_insts.append(self.add_inst(name=name, @@ -105,7 +106,7 @@ class sense_amp_array(design.design): else: amp_spacing = self.amp.width * self.words_per_row - for i in range(0,self.word_size): + for i in range(0, self.word_size): xoffset = amp_spacing * i # align the xoffset to the grid of bitcells. This way we @@ -119,20 +120,19 @@ class sense_amp_array(design.design): mirror = "" amp_position = vector(xoffset, 0) - self.local_insts[i].place(offset=amp_position,mirror=mirror) - + self.local_insts[i].place(offset=amp_position, mirror=mirror) def add_layout_pins(self): for i in range(len(self.local_insts)): inst = self.local_insts[i] - self.add_power_pin(name = "gnd", - loc = inst.get_pin("gnd").center(), + self.add_power_pin(name="gnd", + loc=inst.get_pin("gnd").center(), start_layer="m2", vertical=True) - self.add_power_pin(name = "vdd", - loc = inst.get_pin("vdd").center(), + self.add_power_pin(name="vdd", + loc=inst.get_pin("vdd").center(), start_layer="m2", vertical=True) @@ -157,16 +157,15 @@ class sense_amp_array(design.design): width=dout_pin.width(), height=dout_pin.height()) - def route_rails(self): # add sclk rail across entire array sclk = self.amp.get_pin(self.amp.en_name) - sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1) + sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0, 1) self.add_layout_pin(text=self.en_name, - layer=sclk.layer, - offset=sclk_offset, - width=self.width, - height=drc("minwidth_" + sclk.layer)) + layer=sclk.layer, + offset=sclk_offset, + width=self.width, + height=drc("minwidth_" + sclk.layer)) def input_load(self): return self.amp.input_load() @@ -179,6 +178,6 @@ class sense_amp_array(design.design): def get_drain_cin(self): """Get the relative capacitance of the drain of the PMOS isolation TX""" from tech import parameter - #Bitcell drain load being used to estimate PMOS drain load + # Bitcell drain load being used to estimate PMOS drain load drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap']) return drain_load diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index c83bd130..d1244aed 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -5,21 +5,20 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from math import log import design -from tech import drc import debug from sram_factory import factory from vector import vector from globals import OPTS + class write_driver_array(design.design): """ Array of tristate drivers to write to the bitlines through the column mux. Dynamically generated write driver array of all bitlines. """ - def __init__(self, name, columns, word_size,write_size=None): + def __init__(self, name, columns, word_size, write_size=None): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) @@ -31,7 +30,7 @@ class write_driver_array(design.design): self.words_per_row = int(columns / word_size) if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(self.word_size / self.write_size) self.create_netlist() if not OPTS.netlist_only: @@ -97,9 +96,9 @@ class write_driver_array(design.design): self.driver_insts = {} w = 0 windex=0 - for i in range(0,self.columns,self.words_per_row): + for i in range(0, self.columns, self.words_per_row): name = "write_driver{}".format(i) - index = int(i/self.words_per_row) + index = int(i / self.words_per_row) self.driver_insts[index]=self.add_inst(name=name, mod=self.driver) @@ -119,15 +118,14 @@ class write_driver_array(design.design): self.get_br_name() + "_{0}".format(index), self.en_name, "vdd", "gnd"]) - def place_write_array(self): from tech import cell_properties if self.bitcell.width > self.driver.width: self.driver_spacing = self.bitcell.width else: self.driver_spacing = self.driver.width - for i in range(0,self.columns,self.words_per_row): - index = int(i/self.words_per_row) + for i in range(0, self.columns, self.words_per_row): + index = int(i / self.words_per_row) xoffset = i * self.driver_spacing if cell_properties.bitcell.mirror.y and i % 2: @@ -139,7 +137,6 @@ class write_driver_array(design.design): base = vector(xoffset, 0) self.driver_insts[index].place(offset=base, mirror=mirror) - def add_layout_pins(self): for i in range(self.word_size): inst = self.driver_insts[i] @@ -166,16 +163,16 @@ class write_driver_array(design.design): for n in ["vdd", "gnd"]: pin_list = self.driver_insts[i].get_pins(n) for pin in pin_list: - self.add_power_pin(name = n, - loc = pin.center(), + self.add_power_pin(name=n, + loc=pin.center(), vertical=True, - start_layer = "m2") + start_layer="m2") if self.write_size: for bit in range(self.num_wmasks): - inst = self.driver_insts[bit*self.write_size] + inst = self.driver_insts[bit * self.write_size] en_pin = inst.get_pin(inst.mod.en_name) # Determine width of wmask modified en_pin with/without col mux - wmask_en_len = self.words_per_row*(self.write_size * self.driver_spacing) + wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing) if (self.words_per_row == 1): en_gap = self.driver_spacing - en_pin.width() else: @@ -184,19 +181,16 @@ class write_driver_array(design.design): self.add_layout_pin(text=self.en_name + "_{0}".format(bit), layer=en_pin.layer, offset=en_pin.ll(), - width=wmask_en_len-en_gap, + width=wmask_en_len - en_gap, height=en_pin.height()) else: inst = self.driver_insts[0] self.add_layout_pin(text=self.en_name, layer="m1", - offset=inst.get_pin(inst.mod.en_name).ll().scale(0,1), + offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1), width=self.width) - - - def get_w_en_cin(self): """Get the relative capacitance of all the enable connections in the bank""" - #The enable is connected to a nand2 for every row. + # The enable is connected to a nand2 for every row. return self.driver.get_w_en_cin() * len(self.driver_insts)