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OpenRAM
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PEP8 updates

This commit is contained in:
mrg 2020-03-31 10:15:46 -07:00
parent b0d2946c80
commit d916322b74
2 changed files with 30 additions and 37 deletions
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3
compiler/modules/sense_amp_array.py
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@ -13,6 +13,7 @@ import debug
from globals import OPTS from globals import OPTS
import logical_effort import logical_effort
class sense_amp_array(design.design): class sense_amp_array(design.design):
""" """
Array of sense amplifiers to read the bitlines through the column mux. Array of sense amplifiers to read the bitlines through the column mux.
@ -121,7 +122,6 @@ class sense_amp_array(design.design):
amp_position = vector(xoffset, 0) amp_position = vector(xoffset, 0)
self.local_insts[i].place(offset=amp_position, mirror=mirror) self.local_insts[i].place(offset=amp_position, mirror=mirror)
def add_layout_pins(self): def add_layout_pins(self):
for i in range(len(self.local_insts)): for i in range(len(self.local_insts)):
inst = self.local_insts[i] inst = self.local_insts[i]
@ -157,7 +157,6 @@ class sense_amp_array(design.design):
width=dout_pin.width(), width=dout_pin.width(),
height=dout_pin.height()) height=dout_pin.height())
def route_rails(self): def route_rails(self):
# add sclk rail across entire array # add sclk rail across entire array
sclk = self.amp.get_pin(self.amp.en_name) sclk = self.amp.get_pin(self.amp.en_name)

8
compiler/modules/write_driver_array.py
View File

@ -5,14 +5,13 @@
# (acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
# All rights reserved. # All rights reserved.
# #
from math import log
import design import design
from tech import drc
import debug import debug
from sram_factory import factory from sram_factory import factory
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
class write_driver_array(design.design): class write_driver_array(design.design):
""" """
Array of tristate drivers to write to the bitlines through the column mux. Array of tristate drivers to write to the bitlines through the column mux.
@ -119,7 +118,6 @@ class write_driver_array(design.design):
self.get_br_name() + "_{0}".format(index), self.get_br_name() + "_{0}".format(index),
self.en_name, "vdd", "gnd"]) self.en_name, "vdd", "gnd"])
def place_write_array(self): def place_write_array(self):
from tech import cell_properties from tech import cell_properties
if self.bitcell.width > self.driver.width: if self.bitcell.width > self.driver.width:
@ -139,7 +137,6 @@ class write_driver_array(design.design):
base = vector(xoffset, 0) base = vector(xoffset, 0)
self.driver_insts[index].place(offset=base, mirror=mirror) self.driver_insts[index].place(offset=base, mirror=mirror)
def add_layout_pins(self): def add_layout_pins(self):
for i in range(self.word_size): for i in range(self.word_size):
inst = self.driver_insts[i] inst = self.driver_insts[i]
@ -193,9 +190,6 @@ class write_driver_array(design.design):
offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1), offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1),
width=self.width) width=self.width)
def get_w_en_cin(self): def get_w_en_cin(self):
"""Get the relative capacitance of all the enable connections in the bank""" """Get the relative capacitance of all the enable connections in the bank"""
# The enable is connected to a nand2 for every row. # The enable is connected to a nand2 for every row.