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Fix clock fanout to include internal FF. Update delays in golden tests.

This commit is contained in:
Matt Guthaus 2019-01-28 08:48:32 -08:00
parent 881c449c7c
commit d77bba3af2
3 changed files with 33 additions and 33 deletions
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6
compiler/modules/control_logic.py
View File

@ -87,11 +87,11 @@ class control_logic(design.design):
height=dff_height) height=dff_height)
self.add_mod(self.and2) self.add_mod(self.and2)
# Special gates: inverters for buffering
# clk_buf drives a flop for every address and control bit # clk_buf drives a flop for every address and control bit
# plus about 5 fanouts for the control logic # plus about 5 fanouts for the control logic
clock_fanout = math.log(self.num_words,2) + math.log(self.words_per_row,2) \ # each flop internally has a FO 4 approximately
+ self.num_control_signals + 5 clock_fanout = 4*(math.log(self.num_words,2) + math.log(self.words_per_row,2) \
+ self.num_control_signals) + 5
self.clk_buf_driver = factory.create(module_type="pdriver", self.clk_buf_driver = factory.create(module_type="pdriver",
fanout=clock_fanout, fanout=clock_fanout,
height=dff_height) height=dff_height)

20
compiler/tests/21_hspice_delay_test.py
View File

@ -53,16 +53,16 @@ class timing_sram_test(openram_test):
data.update(port_data[0]) data.update(port_data[0])
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [0.2011], golden_data = {'delay_hl': [0.2152017],
'delay_lh': [0.2011], 'delay_lh': [0.2152017],
'leakage_power': 0.002, 'leakage_power': 0.0022907,
'min_period': 0.41, 'min_period': 0.488,
'read0_power': [0.63604], 'read0_power': [0.47437749999999995],
'read1_power': [0.6120599999999999], 'read1_power': [0.45026109999999997],
'slew_hl': [0.10853], 'slew_hl': [0.0846786],
'slew_lh': [0.10853], 'slew_lh': [0.0846786],
'write0_power': [0.51742], 'write0_power': [0.40809259999999997],
'write1_power': [0.51095]} 'write1_power': [0.4078904]}
elif OPTS.tech_name == "scn4m_subm": elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.3911], golden_data = {'delay_hl': [1.3911],
'delay_lh': [1.3911], 'delay_lh': [1.3911],

40
compiler/tests/21_ngspice_delay_test.py
View File

@ -51,27 +51,27 @@ class timing_sram_test(openram_test):
data.update(port_data[0]) data.update(port_data[0])
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [0.20443139999999999], golden_data = {'delay_hl': [0.221699],
'delay_lh': [0.20443139999999999], 'delay_lh': [0.221699],
'leakage_power': 0.0017840640000000001, 'leakage_power': 0.001467648,
'min_period': 0.41, 'min_period': 0.605,
'read0_power': [0.6435831], 'read0_power': [0.3879335],
'read1_power': [0.6233463], 'read1_power': [0.3662724],
'slew_hl': [0.1138734], 'slew_hl': [0.08562444999999999],
'slew_lh': [0.1138734], 'slew_lh': [0.08562444999999999],
'write0_power': [0.5205761], 'write0_power': [0.3362456],
'write1_power': [0.5213689]} 'write1_power': [0.3372035]}
elif OPTS.tech_name == "scn4m_subm": elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.610911], golden_data = {'delay_hl': [1.7951730000000001],
'delay_lh': [1.610911], 'delay_lh': [1.7951730000000001],
'leakage_power': 0.0023593859999999998, 'leakage_power': 0.001669513,
'min_period': 3.281, 'min_period': 3.594,
'read0_power': [20.763569999999998], 'read0_power': [17.03022],
'read1_power': [20.32745], 'read1_power': [16.55897],
'slew_hl': [0.7986348999999999], 'slew_hl': [0.7079951],
'slew_lh': [0.7986348999999999], 'slew_lh': [0.7079951],
'write0_power': [17.58272], 'write0_power': [15.16726],
'write1_power': [18.523419999999998]} 'write1_power': [16.13527]}
else: else:
self.assertTrue(False) # other techs fail self.assertTrue(False) # other techs fail