From d77bba3af212138aec5497f2e81052eda670d4c1 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Mon, 28 Jan 2019 08:48:32 -0800
Subject: [PATCH] Fix clock fanout to include internal FF. Update delays in
 golden tests.

---
 compiler/modules/control_logic.py       |  6 ++--
 compiler/tests/21_hspice_delay_test.py  | 20 ++++++-------
 compiler/tests/21_ngspice_delay_test.py | 40 ++++++++++++-------------
 3 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index 805cbea9..d4597cf9 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -87,11 +87,11 @@ class control_logic(design.design):
                                    height=dff_height)
         self.add_mod(self.and2)
         
-        # Special gates: inverters for buffering
         # clk_buf drives a flop for every address and control bit
         # plus about 5 fanouts for the control logic
-        clock_fanout = math.log(self.num_words,2) + math.log(self.words_per_row,2) \
-                       + self.num_control_signals + 5
+        # each flop internally has a FO 4 approximately
+        clock_fanout = 4*(math.log(self.num_words,2) + math.log(self.words_per_row,2) \
+                       + self.num_control_signals) + 5
         self.clk_buf_driver = factory.create(module_type="pdriver",
                                              fanout=clock_fanout,
                                              height=dff_height)
diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py
index edbd6a55..7592186c 100755
--- a/compiler/tests/21_hspice_delay_test.py
+++ b/compiler/tests/21_hspice_delay_test.py
@@ -53,16 +53,16 @@ class timing_sram_test(openram_test):
         data.update(port_data[0])
         
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'delay_hl': [0.2011],
-                         'delay_lh': [0.2011],
-                         'leakage_power': 0.002,
-                         'min_period': 0.41,
-                         'read0_power': [0.63604],
-                         'read1_power': [0.6120599999999999],
-                         'slew_hl': [0.10853],
-                         'slew_lh': [0.10853],
-                         'write0_power': [0.51742],
-                         'write1_power': [0.51095]}
+            golden_data = {'delay_hl': [0.2152017],
+                           'delay_lh': [0.2152017],
+                           'leakage_power': 0.0022907,
+                           'min_period': 0.488,
+                           'read0_power': [0.47437749999999995],
+                           'read1_power': [0.45026109999999997],
+                           'slew_hl': [0.0846786],
+                           'slew_lh': [0.0846786],
+                           'write0_power': [0.40809259999999997],
+                           'write1_power': [0.4078904]}
         elif OPTS.tech_name == "scn4m_subm":
             golden_data = {'delay_hl': [1.3911],
                          'delay_lh': [1.3911],
diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py
index 20ba14cc..aac42fa6 100755
--- a/compiler/tests/21_ngspice_delay_test.py
+++ b/compiler/tests/21_ngspice_delay_test.py
@@ -51,27 +51,27 @@ class timing_sram_test(openram_test):
         data.update(port_data[0])
 
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'delay_hl': [0.20443139999999999],
-                         'delay_lh': [0.20443139999999999],
-                         'leakage_power': 0.0017840640000000001,
-                         'min_period': 0.41,
-                         'read0_power': [0.6435831],
-                         'read1_power': [0.6233463],
-                         'slew_hl': [0.1138734],
-                         'slew_lh': [0.1138734],
-                         'write0_power': [0.5205761],
-                         'write1_power': [0.5213689]}
+            golden_data = {'delay_hl': [0.221699],
+                           'delay_lh': [0.221699],
+                           'leakage_power': 0.001467648,
+                           'min_period': 0.605,
+                           'read0_power': [0.3879335],
+                           'read1_power': [0.3662724],
+                           'slew_hl': [0.08562444999999999],
+                           'slew_lh': [0.08562444999999999],
+                           'write0_power': [0.3362456],
+                           'write1_power': [0.3372035]}
         elif OPTS.tech_name == "scn4m_subm":
-            golden_data = {'delay_hl': [1.610911],
-                         'delay_lh': [1.610911],
-                         'leakage_power': 0.0023593859999999998,
-                         'min_period': 3.281,
-                         'read0_power': [20.763569999999998],
-                         'read1_power': [20.32745],
-                         'slew_hl': [0.7986348999999999],
-                         'slew_lh': [0.7986348999999999],
-                         'write0_power': [17.58272],
-                         'write1_power': [18.523419999999998]}
+            golden_data = {'delay_hl': [1.7951730000000001],
+                           'delay_lh': [1.7951730000000001],
+                           'leakage_power': 0.001669513,
+                           'min_period': 3.594,
+                           'read0_power': [17.03022],
+                           'read1_power': [16.55897],
+                           'slew_hl': [0.7079951],
+                           'slew_lh': [0.7079951],
+                           'write0_power': [15.16726],
+                           'write1_power': [16.13527]}
         else:
             self.assertTrue(False) # other techs fail