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Fix clock fanout to include internal FF. Update delays in golden tests.

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This commit is contained in:
Matt Guthaus
2019-01-28 08:48:32 -08:00
parent 881c449c7c
commit d77bba3af2
3 changed files with 33 additions and 33 deletions
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compiler/modules/control_logic.py
+3 -3
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@@ -87,11 +87,11 @@ class control_logic(design.design):
height=dff_height)
self.add_mod(self.and2)
# Special gates: inverters for buffering
# clk_buf drives a flop for every address and control bit
# plus about 5 fanouts for the control logic
clock_fanout = math.log(self.num_words,2) + math.log(self.words_per_row,2) \
+ self.num_control_signals + 5
# each flop internally has a FO 4 approximately
clock_fanout = 4*(math.log(self.num_words,2) + math.log(self.words_per_row,2) \
+ self.num_control_signals) + 5
self.clk_buf_driver = factory.create(module_type="pdriver",
fanout=clock_fanout,
height=dff_height)