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Update golden results for FreePDK45 tests.

This commit is contained in:
Matt Guthaus 2018-07-27 14:25:52 -07:00
parent 642a5cfe73
commit d75d17bc8a
6 changed files with 106 additions and 94 deletions
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20
compiler/tests/21_hspice_delay_test.py
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@ -51,16 +51,16 @@ class timing_sram_test(openram_test):
data = d.analyze(probe_address, probe_data, slews, loads) data = d.analyze(probe_address, probe_data, slews, loads)
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'leakage_power': 0.0006964536000000001, golden_data = {'delay_hl': [2.5614],
'delay_lh': [0.0573055], 'delay_lh': [0.22929839999999999],
'read0_power': [0.0337812], 'leakage_power': 0.0020326,
'read1_power': [0.032946500000000004], 'min_period': 4.844,
'write1_power': [0.0361529], 'read0_power': [0.0497676],
'write0_power': [0.026179099999999997], 'read1_power': [0.0463576],
'slew_hl': [0.0285185], 'slew_hl': [0.1119293],
'min_period': 0.205, 'slew_lh': [0.0237043],
'delay_hl': [0.070554], 'write0_power': [0.0494321],
'slew_lh': [0.0190073]} 'write1_power': [0.0457268]}
elif OPTS.tech_name == "scn3me_subm": elif OPTS.tech_name == "scn3me_subm":
golden_data = {'delay_hl': [6.473300000000001], golden_data = {'delay_hl': [6.473300000000001],
'delay_lh': [1.0442000000000002], 'delay_lh': [1.0442000000000002],

20
compiler/tests/21_ngspice_delay_test.py
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@ -50,16 +50,16 @@ class timing_sram_test(openram_test):
data = d.analyze(probe_address, probe_data, slews, loads) data = d.analyze(probe_address, probe_data, slews, loads)
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'leakage_power': 0.0007348262, golden_data = {'delay_hl': [2.562671],
'delay_lh': [0.05799613], 'delay_lh': [0.2320771],
'read0_power': [0.0384102], 'leakage_power': 0.00102373,
'read1_power': [0.03279848], 'min_period': 4.844,
'write1_power': [0.03693655], 'read0_power': [0.047404110000000006],
'write0_power': [0.02717752], 'read1_power': [0.0438884],
'slew_hl': [0.03607912], 'slew_hl': [0.1140206],
'min_period': 0.742, 'slew_lh': [0.02492785],
'delay_hl': [0.3929995], 'write0_power': [0.04765188],
'slew_lh': [0.02160862]} 'write1_power': [0.04434999]}
elif OPTS.tech_name == "scn3me_subm": elif OPTS.tech_name == "scn3me_subm":
golden_data = {'delay_hl': [11.69536], golden_data = {'delay_hl': [11.69536],
'delay_lh': [1.260921], 'delay_lh': [1.260921],

58
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
View File

@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 1032.3999375; area : 948.52275;
leakage_power () { leakage_power () {
when : "CSb"; when : "CSb";
value : 0.0008128352; value : 0.0021292;
} }
cell_leakage_power : 0; cell_leakage_power : 0;
bus(DATA){ bus(DIN){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : in;
max_capacitance : 1.6728; max_capacitance : 1.6728;
min_capacitance : 0.052275; min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
clocked_on : clk; clocked_on : clk;
} }
bus(DOUT){
bus_type : DATA;
direction : out;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
memory_read(){ memory_read(){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DOUT[1:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -130,26 +134,26 @@ cell (sram_2_16_1_freepdk45){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
timing_type : falling_edge; timing_type : rising_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.055, 0.056, 0.063",\ values("0.229, 0.23, 0.234",\
"0.056, 0.057, 0.063",\ "0.23, 0.23, 0.234",\
"0.061, 0.062, 0.069"); "0.236, 0.236, 0.24");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.067, 0.068, 0.076",\ values("2.555, 2.556, 2.568",\
"0.067, 0.068, 0.077",\ "2.555, 2.557, 2.569",\
"0.073, 0.074, 0.082"); "2.562, 2.563, 2.575");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.013, 0.015, 0.026",\ values("0.02, 0.021, 0.028",\
"0.013, 0.015, 0.026",\ "0.02, 0.021, 0.028",\
"0.014, 0.015, 0.026"); "0.02, 0.021, 0.028");
} }
fall_transition(CELL_TABLE) { fall_transition(CELL_TABLE) {
values("0.023, 0.024, 0.037",\ values("0.111, 0.112, 0.115",\
"0.023, 0.024, 0.037",\ "0.111, 0.111, 0.115",\
"0.024, 0.024, 0.037"); "0.111, 0.111, 0.116");
} }
} }
} }
@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
internal_power(){ internal_power(){
when : "!CSb & clk & !WEb"; when : "!CSb & clk & !WEb";
rise_power(scalar){ rise_power(scalar){
values("0.0175059861111"); values("0.027431397222222223");
} }
fall_power(scalar){ fall_power(scalar){
values("0.0175059861111"); values("0.027431397222222223");
} }
} }
internal_power(){ internal_power(){
when : "!CSb & !clk & WEb"; when : "!CSb & !clk & WEb";
rise_power(scalar){ rise_power(scalar){
values("0.0218644166667"); values("0.026240397222222222");
} }
fall_power(scalar){ fall_power(scalar){
values("0.0218644166667"); values("0.026240397222222222");
} }
} }
internal_power(){ internal_power(){
@ -326,20 +330,20 @@ cell (sram_2_16_1_freepdk45){
timing_type :"min_pulse_width"; timing_type :"min_pulse_width";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("0.117"); values("2.422");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("0.117"); values("2.422");
} }
} }
timing(){ timing(){
timing_type :"minimum_period"; timing_type :"minimum_period";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("0.234"); values("4.844");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("0.234"); values("4.844");
} }
} }
} }

42
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
View File

@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 1032.3999375; area : 948.52275;
leakage_power () { leakage_power () {
when : "CSb"; when : "CSb";
value : 0.000173; value : 0.000168;
} }
cell_leakage_power : 0; cell_leakage_power : 0;
bus(DATA){ bus(DIN){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : in;
max_capacitance : 1.6728; max_capacitance : 1.6728;
min_capacitance : 0.052275; min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
clocked_on : clk; clocked_on : clk;
} }
bus(DOUT){
bus_type : DATA;
direction : out;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
memory_read(){ memory_read(){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DOUT[1:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -130,16 +134,16 @@ cell (sram_2_16_1_freepdk45){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
timing_type : falling_edge; timing_type : rising_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.123, 0.124, 0.133",\ values("0.103, 0.104, 0.113",\
"0.123, 0.124, 0.133",\ "0.103, 0.104, 0.113",\
"0.123, 0.124, 0.133"); "0.103, 0.104, 0.113");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.123, 0.124, 0.133",\ values("0.103, 0.104, 0.113",\
"0.123, 0.124, 0.133",\ "0.103, 0.104, 0.113",\
"0.123, 0.124, 0.133"); "0.103, 0.104, 0.113");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\ values("0.006, 0.007, 0.018",\
@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
internal_power(){ internal_power(){
when : "!CSb & clk & !WEb"; when : "!CSb & clk & !WEb";
rise_power(scalar){ rise_power(scalar){
values("0.065526962224"); values("0.0739870044551111");
} }
fall_power(scalar){ fall_power(scalar){
values("0.065526962224"); values("0.0739870044551111");
} }
} }
internal_power(){ internal_power(){
when : "!CSb & !clk & WEb"; when : "!CSb & !clk & WEb";
rise_power(scalar){ rise_power(scalar){
values("0.065526962224"); values("0.0739870044551111");
} }
fall_power(scalar){ fall_power(scalar){
values("0.065526962224"); values("0.0739870044551111");
} }
} }
internal_power(){ internal_power(){
@ -336,10 +340,10 @@ cell (sram_2_16_1_freepdk45){
timing_type :"minimum_period"; timing_type :"minimum_period";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("0.0"); values("0");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("0.0"); values("0");
} }
} }
} }

58
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
View File

@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 1032.3999375; area : 948.52275;
leakage_power () { leakage_power () {
when : "CSb"; when : "CSb";
value : 0.0008128352; value : 0.0021292;
} }
cell_leakage_power : 0; cell_leakage_power : 0;
bus(DATA){ bus(DIN){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : in;
max_capacitance : 1.6728; max_capacitance : 1.6728;
min_capacitance : 0.052275; min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
clocked_on : clk; clocked_on : clk;
} }
bus(DOUT){
bus_type : DATA;
direction : out;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
memory_read(){ memory_read(){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DOUT[1:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -130,26 +134,26 @@ cell (sram_2_16_1_freepdk45){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
timing_type : falling_edge; timing_type : rising_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.054, 0.055, 0.061",\ values("0.227, 0.227, 0.231",\
"0.055, 0.056, 0.062",\ "0.227, 0.228, 0.232",\
"0.06, 0.061, 0.068"); "0.233, 0.234, 0.238");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.066, 0.067, 0.075",\ values("2.555, 2.557, 2.569",\
"0.067, 0.068, 0.076",\ "2.556, 2.557, 2.569",\
"0.072, 0.073, 0.082"); "2.562, 2.563, 2.576");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.013, 0.014, 0.026",\ values("0.02, 0.021, 0.028",\
"0.013, 0.015, 0.026",\ "0.02, 0.021, 0.028",\
"0.013, 0.015, 0.026"); "0.02, 0.021, 0.028");
} }
fall_transition(CELL_TABLE) { fall_transition(CELL_TABLE) {
values("0.023, 0.024, 0.037",\ values("0.11, 0.11, 0.114",\
"0.023, 0.024, 0.037",\ "0.109, 0.11, 0.113",\
"0.024, 0.024, 0.037"); "0.11, 0.11, 0.114");
} }
} }
} }
@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
internal_power(){ internal_power(){
when : "!CSb & clk & !WEb"; when : "!CSb & clk & !WEb";
rise_power(scalar){ rise_power(scalar){
values("0.0159801855389"); values("0.025181683333333333");
} }
fall_power(scalar){ fall_power(scalar){
values("0.0159801855389"); values("0.025181683333333333");
} }
} }
internal_power(){ internal_power(){
when : "!CSb & !clk & WEb"; when : "!CSb & !clk & WEb";
rise_power(scalar){ rise_power(scalar){
values("0.0171325605389"); values("0.024945991666666667");
} }
fall_power(scalar){ fall_power(scalar){
values("0.0171325605389"); values("0.024945991666666667");
} }
} }
internal_power(){ internal_power(){
@ -326,20 +330,20 @@ cell (sram_2_16_1_freepdk45){
timing_type :"min_pulse_width"; timing_type :"min_pulse_width";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("0.1125"); values("2.422");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("0.1125"); values("2.422");
} }
} }
timing(){ timing(){
timing_type :"minimum_period"; timing_type :"minimum_period";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("0.225"); values("4.844");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("0.225"); values("4.844");
} }
} }
} }

2
compiler/tests/testutils.py
View File

@ -79,7 +79,7 @@ class openram_test(unittest.TestCase):
if not data_matches: if not data_matches:
import pprint import pprint
data_string=pprint.pformat(data) data_string=pprint.pformat(data)
debug.error("Data exceeded {:.1f}% tolerance:\n".format(error_tolerance*100)+data_string) debug.error("Results exceeded {:.1f}% tolerance compared to golden results:\n".format(error_tolerance*100)+data_string)
return data_matches return data_matches