diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py
index 68f24ef2..55030c45 100755
--- a/compiler/tests/21_hspice_delay_test.py
+++ b/compiler/tests/21_hspice_delay_test.py
@@ -51,16 +51,16 @@ class timing_sram_test(openram_test):
         data = d.analyze(probe_address, probe_data, slews, loads)
 
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'leakage_power': 0.0006964536000000001,
-                           'delay_lh': [0.0573055],
-                           'read0_power': [0.0337812],
-                           'read1_power': [0.032946500000000004],
-                           'write1_power': [0.0361529],
-                           'write0_power': [0.026179099999999997],
-                           'slew_hl': [0.0285185],
-                           'min_period': 0.205,
-                           'delay_hl': [0.070554],
-                           'slew_lh': [0.0190073]}
+            golden_data = {'delay_hl': [2.5614],
+                            'delay_lh': [0.22929839999999999],
+                            'leakage_power': 0.0020326,
+                            'min_period': 4.844,
+                            'read0_power': [0.0497676],
+                            'read1_power': [0.0463576],
+                            'slew_hl': [0.1119293],
+                            'slew_lh': [0.0237043],
+                            'write0_power': [0.0494321],
+                            'write1_power': [0.0457268]}
         elif OPTS.tech_name == "scn3me_subm":
             golden_data = {'delay_hl': [6.473300000000001],
                             'delay_lh': [1.0442000000000002],
diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py
index c65af315..72bdbc65 100755
--- a/compiler/tests/21_ngspice_delay_test.py
+++ b/compiler/tests/21_ngspice_delay_test.py
@@ -50,16 +50,16 @@ class timing_sram_test(openram_test):
         data = d.analyze(probe_address, probe_data, slews, loads)
 
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'leakage_power': 0.0007348262,
-                           'delay_lh': [0.05799613],
-                           'read0_power': [0.0384102],
-                           'read1_power': [0.03279848],
-                           'write1_power': [0.03693655],
-                           'write0_power': [0.02717752],
-                           'slew_hl': [0.03607912],
-                           'min_period': 0.742,
-                           'delay_hl': [0.3929995],
-                           'slew_lh': [0.02160862]}
+            golden_data = {'delay_hl': [2.562671],
+                            'delay_lh': [0.2320771],
+                            'leakage_power': 0.00102373,
+                            'min_period': 4.844,
+                            'read0_power': [0.047404110000000006],
+                            'read1_power': [0.0438884],
+                            'slew_hl': [0.1140206],
+                            'slew_lh': [0.02492785],
+                            'write0_power': [0.04765188],
+                            'write1_power': [0.04434999]}
         elif OPTS.tech_name == "scn3me_subm":
             golden_data = {'delay_hl': [11.69536],
                             'delay_lh': [1.260921],
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
index d65b5ab0..cf9df15f 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
@@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 1032.3999375;
+    area : 948.52275;
 
     leakage_power () {
       when : "CSb";
-      value : 0.0008128352;
+      value : 0.0021292;
     }
     cell_leakage_power : 0;
-    bus(DATA){
+    bus(DIN){
         bus_type  : DATA; 
-        direction  : inout; 
+        direction  : in; 
         max_capacitance : 1.6728;  
         min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
         memory_write(){ 
             address : ADDR; 
             clocked_on  : clk; 
         }
+    bus(DOUT){
+        bus_type  : DATA; 
+        direction  : out; 
+        max_capacitance : 1.6728;  
+        min_capacitance : 0.052275;  
         memory_read(){ 
             address : ADDR; 
         }
-        pin(DATA[1:0]){
+        pin(DOUT[1:0]){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk"; 
@@ -130,26 +134,26 @@ cell (sram_2_16_1_freepdk45){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk"; 
-            timing_type : falling_edge; 
+            timing_type : rising_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.055, 0.056, 0.063",\
-                   "0.056, 0.057, 0.063",\
-                   "0.061, 0.062, 0.069");
+            values("0.229, 0.23, 0.234",\
+                   "0.23, 0.23, 0.234",\
+                   "0.236, 0.236, 0.24");
             }
             cell_fall(CELL_TABLE) {
-            values("0.067, 0.068, 0.076",\
-                   "0.067, 0.068, 0.077",\
-                   "0.073, 0.074, 0.082");
+            values("2.555, 2.556, 2.568",\
+                   "2.555, 2.557, 2.569",\
+                   "2.562, 2.563, 2.575");
             }
             rise_transition(CELL_TABLE) {
-            values("0.013, 0.015, 0.026",\
-                   "0.013, 0.015, 0.026",\
-                   "0.014, 0.015, 0.026");
+            values("0.02, 0.021, 0.028",\
+                   "0.02, 0.021, 0.028",\
+                   "0.02, 0.021, 0.028");
             }
             fall_transition(CELL_TABLE) {
-            values("0.023, 0.024, 0.037",\
-                   "0.023, 0.024, 0.037",\
-                   "0.024, 0.024, 0.037");
+            values("0.111, 0.112, 0.115",\
+                   "0.111, 0.111, 0.115",\
+                   "0.111, 0.111, 0.116");
             }
         }
         }
@@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
         internal_power(){
             when : "!CSb & clk & !WEb"; 
             rise_power(scalar){
-                values("0.0175059861111");
+                values("0.027431397222222223");
             }
             fall_power(scalar){
-                values("0.0175059861111");
+                values("0.027431397222222223");
             }
         }
         internal_power(){
             when : "!CSb & !clk & WEb"; 
             rise_power(scalar){
-                values("0.0218644166667");
+                values("0.026240397222222222");
             }
             fall_power(scalar){
-                values("0.0218644166667");
+                values("0.026240397222222222");
             }
         }
         internal_power(){
@@ -326,20 +330,20 @@ cell (sram_2_16_1_freepdk45){
             timing_type :"min_pulse_width"; 
             related_pin  : clk; 
             rise_constraint(scalar) {
-                values("0.117"); 
+                values("2.422"); 
             }
             fall_constraint(scalar) {
-                values("0.117"); 
+                values("2.422"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk; 
             rise_constraint(scalar) {
-                values("0.234"); 
+                values("4.844"); 
             }
             fall_constraint(scalar) {
-                values("0.234"); 
+                values("4.844"); 
             }
          }
     }
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
index 5143e33a..c14afc35 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
@@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 1032.3999375;
+    area : 948.52275;
 
     leakage_power () {
       when : "CSb";
-      value : 0.000173;
+      value : 0.000168;
     }
     cell_leakage_power : 0;
-    bus(DATA){
+    bus(DIN){
         bus_type  : DATA; 
-        direction  : inout; 
+        direction  : in; 
         max_capacitance : 1.6728;  
         min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
         memory_write(){ 
             address : ADDR; 
             clocked_on  : clk; 
         }
+    bus(DOUT){
+        bus_type  : DATA; 
+        direction  : out; 
+        max_capacitance : 1.6728;  
+        min_capacitance : 0.052275;  
         memory_read(){ 
             address : ADDR; 
         }
-        pin(DATA[1:0]){
+        pin(DOUT[1:0]){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk"; 
@@ -130,16 +134,16 @@ cell (sram_2_16_1_freepdk45){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk"; 
-            timing_type : falling_edge; 
+            timing_type : rising_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.123, 0.124, 0.133",\
-                   "0.123, 0.124, 0.133",\
-                   "0.123, 0.124, 0.133");
+            values("0.103, 0.104, 0.113",\
+                   "0.103, 0.104, 0.113",\
+                   "0.103, 0.104, 0.113");
             }
             cell_fall(CELL_TABLE) {
-            values("0.123, 0.124, 0.133",\
-                   "0.123, 0.124, 0.133",\
-                   "0.123, 0.124, 0.133");
+            values("0.103, 0.104, 0.113",\
+                   "0.103, 0.104, 0.113",\
+                   "0.103, 0.104, 0.113");
             }
             rise_transition(CELL_TABLE) {
             values("0.006, 0.007, 0.018",\
@@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
         internal_power(){
             when : "!CSb & clk & !WEb"; 
             rise_power(scalar){
-                values("0.065526962224");
+                values("0.0739870044551111");
             }
             fall_power(scalar){
-                values("0.065526962224");
+                values("0.0739870044551111");
             }
         }
         internal_power(){
             when : "!CSb & !clk & WEb"; 
             rise_power(scalar){
-                values("0.065526962224");
+                values("0.0739870044551111");
             }
             fall_power(scalar){
-                values("0.065526962224");
+                values("0.0739870044551111");
             }
         }
         internal_power(){
@@ -336,10 +340,10 @@ cell (sram_2_16_1_freepdk45){
             timing_type :"minimum_period"; 
             related_pin  : clk; 
             rise_constraint(scalar) {
-                values("0.0"); 
+                values("0"); 
             }
             fall_constraint(scalar) {
-                values("0.0"); 
+                values("0"); 
             }
          }
     }
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
index c856cf58..1cd10b44 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
@@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 1032.3999375;
+    area : 948.52275;
 
     leakage_power () {
       when : "CSb";
-      value : 0.0008128352;
+      value : 0.0021292;
     }
     cell_leakage_power : 0;
-    bus(DATA){
+    bus(DIN){
         bus_type  : DATA; 
-        direction  : inout; 
+        direction  : in; 
         max_capacitance : 1.6728;  
         min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
         memory_write(){ 
             address : ADDR; 
             clocked_on  : clk; 
         }
+    bus(DOUT){
+        bus_type  : DATA; 
+        direction  : out; 
+        max_capacitance : 1.6728;  
+        min_capacitance : 0.052275;  
         memory_read(){ 
             address : ADDR; 
         }
-        pin(DATA[1:0]){
+        pin(DOUT[1:0]){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk"; 
@@ -130,26 +134,26 @@ cell (sram_2_16_1_freepdk45){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk"; 
-            timing_type : falling_edge; 
+            timing_type : rising_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.054, 0.055, 0.061",\
-                   "0.055, 0.056, 0.062",\
-                   "0.06, 0.061, 0.068");
+            values("0.227, 0.227, 0.231",\
+                   "0.227, 0.228, 0.232",\
+                   "0.233, 0.234, 0.238");
             }
             cell_fall(CELL_TABLE) {
-            values("0.066, 0.067, 0.075",\
-                   "0.067, 0.068, 0.076",\
-                   "0.072, 0.073, 0.082");
+            values("2.555, 2.557, 2.569",\
+                   "2.556, 2.557, 2.569",\
+                   "2.562, 2.563, 2.576");
             }
             rise_transition(CELL_TABLE) {
-            values("0.013, 0.014, 0.026",\
-                   "0.013, 0.015, 0.026",\
-                   "0.013, 0.015, 0.026");
+            values("0.02, 0.021, 0.028",\
+                   "0.02, 0.021, 0.028",\
+                   "0.02, 0.021, 0.028");
             }
             fall_transition(CELL_TABLE) {
-            values("0.023, 0.024, 0.037",\
-                   "0.023, 0.024, 0.037",\
-                   "0.024, 0.024, 0.037");
+            values("0.11, 0.11, 0.114",\
+                   "0.109, 0.11, 0.113",\
+                   "0.11, 0.11, 0.114");
             }
         }
         }
@@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
         internal_power(){
             when : "!CSb & clk & !WEb"; 
             rise_power(scalar){
-                values("0.0159801855389");
+                values("0.025181683333333333");
             }
             fall_power(scalar){
-                values("0.0159801855389");
+                values("0.025181683333333333");
             }
         }
         internal_power(){
             when : "!CSb & !clk & WEb"; 
             rise_power(scalar){
-                values("0.0171325605389");
+                values("0.024945991666666667");
             }
             fall_power(scalar){
-                values("0.0171325605389");
+                values("0.024945991666666667");
             }
         }
         internal_power(){
@@ -326,20 +330,20 @@ cell (sram_2_16_1_freepdk45){
             timing_type :"min_pulse_width"; 
             related_pin  : clk; 
             rise_constraint(scalar) {
-                values("0.1125"); 
+                values("2.422"); 
             }
             fall_constraint(scalar) {
-                values("0.1125"); 
+                values("2.422"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk; 
             rise_constraint(scalar) {
-                values("0.225"); 
+                values("4.844"); 
             }
             fall_constraint(scalar) {
-                values("0.225"); 
+                values("4.844"); 
             }
          }
     }
diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py
index be216761..64c1c2b4 100644
--- a/compiler/tests/testutils.py
+++ b/compiler/tests/testutils.py
@@ -79,7 +79,7 @@ class openram_test(unittest.TestCase):
         if not data_matches:
             import pprint
             data_string=pprint.pformat(data)
-            debug.error("Data exceeded {:.1f}% tolerance:\n".format(error_tolerance*100)+data_string)
+            debug.error("Results exceeded {:.1f}% tolerance compared to golden results:\n".format(error_tolerance*100)+data_string)
         return data_matches