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Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers

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Michael Timothy Grimes
2018-09-03 17:31:12 -07:00
parent f3cca7eea0
commit d3441c7ba4
4 changed files with 35 additions and 14 deletions
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compiler/tests/10_write_driver_array_test.py
+5 -5
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@@ -29,18 +29,18 @@ class write_driver_test(openram_test):
# check write driver array in multi-port
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 1
OPTS.w_ports = 1
OPTS.r_ports = 1
OPTS.w_ports = 0
OPTS.r_ports = 0
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
a = write_driver_array.write_driver_array(columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
a = write_driver_array.write_driver_array(columns=16, word_size=8)
self.local_check(a)
#globals.end_openram()
globals.end_openram()
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":