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Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers
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@@ -58,6 +58,12 @@ class wordline_driver(design.design):
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self.nand2 = pnand2()
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self.add_mod(self.nand2)
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from importlib import reload
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell = self.mod_bitcell()
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self.add_mod(self.bitcell)
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def route_vdd_gnd(self):
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""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
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@@ -125,16 +131,20 @@ class wordline_driver(design.design):
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nand2_xoffset = inv1_xoffset + self.inv.width
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inv2_xoffset = nand2_xoffset + self.nand2.width
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self.width = inv2_xoffset + self.inv.width
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self.height = self.inv.height * self.rows
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self.width = inv2_xoffset + self.inv.height
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if self.bitcell.height > self.inv.height:
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self.height = self.bitcell.height * self.rows
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driver_height = self.bitcell.height
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else:
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self.height = self.inv.height * self.rows
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driver_height = self.inv.height
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for row in range(self.rows):
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if (row % 2):
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y_offset = self.inv.height*(row + 1)
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y_offset = driver_height*(row + 1)
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inst_mirror = "MX"
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else:
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y_offset = self.inv.height*row
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y_offset = driver_height*row
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inst_mirror = "R0"
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inv1_offset = [inv1_xoffset, y_offset]
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