From cf8c486cea4513faf181ecf28626b544b4393d30 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 22 Dec 2021 16:00:59 -0800 Subject: [PATCH] merge sky130_dummy_array --- technology/sky130/modules/sky130_dummy_array.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/technology/sky130/modules/sky130_dummy_array.py b/technology/sky130/modules/sky130_dummy_array.py index f1097855..c53b0fc3 100644 --- a/technology/sky130/modules/sky130_dummy_array.py +++ b/technology/sky130/modules/sky130_dummy_array.py @@ -94,7 +94,7 @@ class sky130_dummy_array(sky130_bitcell_base_array): self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), mod=self.strap3) alternate_strap = 1 - self.connect_inst(self.get_strap_pins(row, col, name)) + self.connect_inst(self.get_strap_pins(row, col)) if alternate_bitcell == 0: alternate_bitcell = 1 else: @@ -103,11 +103,11 @@ class sky130_dummy_array(sky130_bitcell_base_array): def add_pins(self): # bitline pins are not added because they are floating - for bl_name in self.get_bitline_names(): - self.add_pin(bl_name, "INOUT") for wl_name in self.get_wordline_names(): self.add_pin(wl_name, "INPUT") - + for bl in range(self.column_size): + self.add_pin("dummy_bl_{}".format(bl)) + self.add_pin("dummy_br_{}".format(bl)) self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND")