Convert bitcells to 1port and 2port

compiler/base/custom_cell_properties.py

@@ -48,7 +48,7 @@ class _pgate:
 
 
 class _bitcell:
-    def __init__(self, mirror, cell_s8_6t, cell_6t, cell_1rw1r, cell_1w1r):
+    def __init__(self, mirror, cell_6t, cell_1rw1r, cell_1w1r):
         self.mirror = mirror
         self._6t = cell_6t
         self._1rw1r = cell_1rw1r
@@ -75,16 +75,11 @@ class _bitcell:
                            'wl0': 'wl0',
                            'wl1': 'wl1'})
 
-        return _bitcell(cell_s8_6t=cell_s8_6t,
+        return _bitcell(cell_6t=cell_6t,
-                        cell_6t=cell_6t,
                         cell_1rw1r=cell_1rw1r,
                         cell_1w1r=cell_1w1r,
                         mirror=axis)
 
-    @property
-    def cell_s8_6t(self):
-        return self._s8_6t
-
     @property
     def cell_6t(self):
         return self._6t

compiler/bitcells/bitcell_1port.py

@@ -10,7 +10,7 @@ from tech import cell_properties as props
 import bitcell_base
 
 
-class bitcell(bitcell_base.bitcell_base):
+class bitcell_1port(bitcell_base.bitcell_base):
     """
     A single bit cell (6T, 8T, etc.)  This module implements the
     single memory cell used in the design. It is a hand-made cell, so

compiler/bitcells/bitcell_2port.py

@@ -10,7 +10,7 @@ from tech import cell_properties as props
 import bitcell_base
 
 
-class bitcell_1w_1r(bitcell_base.bitcell_base):
+class bitcell_2port(bitcell_base.bitcell_base):
     """
     A single bit cell (6T, 8T, etc.)  This module implements the
     single memory cell used in the design. It is a hand-made cell, so
@@ -18,21 +18,21 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
     library.
     """
 
-    pin_names = [props.bitcell.cell_1w1r.pin.bl0,
+    pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
-                 props.bitcell.cell_1w1r.pin.br0,
+                 props.bitcell.cell_1rw1r.pin.br0,
-                 props.bitcell.cell_1w1r.pin.bl1,
+                 props.bitcell.cell_1rw1r.pin.bl1,
-                 props.bitcell.cell_1w1r.pin.br1,
+                 props.bitcell.cell_1rw1r.pin.br1,
-                 props.bitcell.cell_1w1r.pin.wl0,
+                 props.bitcell.cell_1rw1r.pin.wl0,
-                 props.bitcell.cell_1w1r.pin.wl1,
+                 props.bitcell.cell_1rw1r.pin.wl1,
-                 props.bitcell.cell_1w1r.pin.vdd,
+                 props.bitcell.cell_1rw1r.pin.vdd,
-                 props.bitcell.cell_1w1r.pin.gnd]
+                 props.bitcell.cell_1rw1r.pin.gnd]
-    type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
+    type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
                  "INPUT", "INPUT", "POWER", "GROUND"]
     storage_nets = ['Q', 'Q_bar']
 
     def __init__(self, name):
         super().__init__(name)
-        debug.info(2, "Create bitcell with 1W and 1R Port")
+        debug.info(2, "Create bitcell with 1RW and 1R Port")
 
         self.nets_match = self.do_nets_exist(self.storage_nets)
 
@@ -46,7 +46,7 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
         Creates a list of connections in the bitcell,
         indexed by column and row, for instance use in bitcell_array
         """
-        pin_name = props.bitcell.cell_1w1r.pin
+        pin_name = props.bitcell.cell_1rw1r.pin
         bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
                         "{0}_{1}".format(pin_name.br0, col),
                         "{0}_{1}".format(pin_name.bl1, col),
@@ -59,64 +59,68 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
 
     def get_all_wl_names(self):
         """ Creates a list of all wordline pin names """
-        return [props.bitcell.cell_1w1r.pin.wl0,
+        return [props.bitcell.cell_1rw1r.pin.wl0,
-                props.bitcell.cell_1w1r.pin.wl1]
+                props.bitcell.cell_1rw1r.pin.wl1]
 
     def get_all_bitline_names(self):
         """ Creates a list of all bitline pin names (both bl and br) """
-        return [props.bitcell.cell_1w1r.pin.bl0,
+        return [props.bitcell.cell_1rw1r.pin.bl0,
-                props.bitcell.cell_1w1r.pin.br0,
+                props.bitcell.cell_1rw1r.pin.br0,
-                props.bitcell.cell_1w1r.pin.bl1,
+                props.bitcell.cell_1rw1r.pin.bl1,
-                props.bitcell.cell_1w1r.pin.br1]
+                props.bitcell.cell_1rw1r.pin.br1]
 
     def get_all_bl_names(self):
         """ Creates a list of all bl pins names """
-        return [props.bitcell.cell_1w1r.pin.bl0,
+        return [props.bitcell.cell_1rw1r.pin.bl0,
-                props.bitcell.cell_1w1r.pin.bl1]
+                props.bitcell.cell_1rw1r.pin.bl1]
 
     def get_all_br_names(self):
         """ Creates a list of all br pins names """
-        return [props.bitcell.cell_1w1r.pin.br0,
+        return [props.bitcell.cell_1rw1r.pin.br0,
-                props.bitcell.cell_1w1r.pin.br1]
+                props.bitcell.cell_1rw1r.pin.br1]
 
     def get_read_bl_names(self):
         """ Creates a list of bl pin names associated with read ports """
-        return [props.bitcell.cell_1w1r.pin.bl0,
+        return [props.bitcell.cell_1rw1r.pin.bl0,
-                props.bitcell.cell_1w1r.pin.bl1]
+                props.bitcell.cell_1rw1r.pin.bl1]
 
     def get_read_br_names(self):
         """ Creates a list of br pin names associated with read ports """
-        return [props.bitcell.cell_1w1r.pin.br0,
+        return [props.bitcell.cell_1rw1r.pin.br0,
-                props.bitcell.cell_1w1r.pin.br1]
+                props.bitcell.cell_1rw1r.pin.br1]
 
     def get_write_bl_names(self):
         """ Creates a list of bl pin names associated with write ports """
-        return [props.bitcell.cell_1w1r.pin.bl0]
+        return [props.bitcell.cell_1rw1r.pin.bl0]
 
     def get_write_br_names(self):
         """ Creates a list of br pin names asscociated with write ports"""
-        return [props.bitcell.cell_1w1r.pin.br1]
+        return [props.bitcell.cell_1rw1r.pin.br1]
 
     def get_bl_name(self, port=0):
         """Get bl name by port"""
+        debug.check(port < 2, "Two ports for bitcell_2port only.")
         return self.bl_names[port]
 
     def get_br_name(self, port=0):
         """Get bl name by port"""
+        debug.check(port < 2, "Two ports for bitcell_2port only.")
         return self.br_names[port]
 
     def get_wl_name(self, port=0):
         """Get wl name by port"""
-        debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
+        debug.check(port < 2, "Two ports for bitcell_2port only.")
         return self.wl_names[port]
 
     def build_graph(self, graph, inst_name, port_nets):
         """Adds edges to graph. Multiport bitcell timing graph is too complex
            to use the add_graph_edges function."""
         pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
-        pins = props.bitcell.cell_1w1r.pin
         # Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
+        pins = props.bitcell.cell_1rw1r.pin
+        graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
+        graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
+        # Port 1 edges
         graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
         graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
-        # Port 1 is a write port, so its timing is not considered here.

compiler/bitcells/dummy_bitcell_1w_1r.py

@@ -1,37 +0,0 @@
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-import debug
-from tech import cell_properties as props
-import bitcell_base
-
-
-class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
-    """
-    A single bit cell which is forced to store a 0.
-    This module implements the single memory cell used in the design. It
-    is a hand-made cell, so the layout and netlist should be available in
-    the technology library. """
-
-    pin_names = [props.bitcell.cell_1w1r.pin.bl0,
-                 props.bitcell.cell_1w1r.pin.br0,
-                 props.bitcell.cell_1w1r.pin.bl1,
-                 props.bitcell.cell_1w1r.pin.br1,
-                 props.bitcell.cell_1w1r.pin.wl0,
-                 props.bitcell.cell_1w1r.pin.wl1,
-                 props.bitcell.cell_1w1r.pin.vdd,
-                 props.bitcell.cell_1w1r.pin.gnd]
-    type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
-                 "INPUT", "INPUT", "POWER", "GROUND"]
-
-    def __init__(self, name):
-        super().__init__(name)
-        debug.info(2, "Create dummy bitcell 1w+1r object")
-
-
-
-

compiler/bitcells/dummy_bitcell_2port.py

@@ -0,0 +1,31 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import debug
+from tech import cell_properties as props
+import bitcell_base
+
+
+class dummy_bitcell(bitcell_base.bitcell_base):
+    """
+    A single bit cell (6T, 8T, etc.)  This module implements the
+    single memory cell used in the design. It is a hand-made cell, so
+    the layout and netlist should be available in the technology
+    library.
+    """
+    pin_names = [props.bitcell.cell_6t.pin.bl,
+                 props.bitcell.cell_6t.pin.br,
+                 props.bitcell.cell_6t.pin.wl,
+                 props.bitcell.cell_6t.pin.vdd,
+                 props.bitcell.cell_6t.pin.gnd]
+    type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
+
+    def __init__(self, name):
+        super().__init__(name)
+        debug.info(2, "Create dummy bitcell")
+
+

compiler/bitcells/replica_bitcell_2port.py

@@ -12,26 +12,23 @@ from tech import parameter, drc
 import logical_effort
 
 
-class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
+class replica_bitcell(bitcell_base.bitcell_base):
     """
-    A single bit cell which is forced to store a 0.
+    A single bit cell (6T, 8T, etc.)
     This module implements the single memory cell used in the design. It
     is a hand-made cell, so the layout and netlist should be available in
     the technology library. """
 
-    pin_names = [props.bitcell.cell_1w1r.pin.bl0,
+    pin_names = [props.bitcell.cell_6t.pin.bl,
-                 props.bitcell.cell_1w1r.pin.br0,
+                 props.bitcell.cell_6t.pin.br,
-                 props.bitcell.cell_1w1r.pin.bl1,
+                 props.bitcell.cell_6t.pin.wl,
-                 props.bitcell.cell_1w1r.pin.br1,
+                 props.bitcell.cell_6t.pin.vdd,
-                 props.bitcell.cell_1w1r.pin.wl0,
+                 props.bitcell.cell_6t.pin.gnd]
-                 props.bitcell.cell_1w1r.pin.wl1,
+    type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
-                 props.bitcell.cell_1w1r.pin.vdd,
-                 props.bitcell.cell_1w1r.pin.gnd]
-    type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"]
 
     def __init__(self, name):
         super().__init__(name)
-        debug.info(2, "Create replica bitcell 1w+1r object")
+        debug.info(2, "Create replica bitcell object")
 
     def get_stage_effort(self, load):
         parasitic_delay = 1
@@ -44,18 +41,17 @@ class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
         """Return the relative capacitance of the access transistor gates"""
 
         # FIXME: This applies to bitline capacitances as well.
-        # FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
         access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
         return 2 * access_tx_cin
 
+    def analytical_power(self, corner, load):
+        """Bitcell power in nW. Only characterizes leakage."""
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        dynamic = 0 # FIXME
+        total_power = self.return_power(dynamic, leakage)
+        return total_power
+
     def build_graph(self, graph, inst_name, port_nets):
-        """Adds edges to graph. Multiport bitcell timing graph is too complex
+        """Adds edges based on inputs/outputs. Overrides base class function."""
-           to use the add_graph_edges function."""
+        self.add_graph_edges(graph, port_nets)
-        debug.info(1, 'Adding edges for {}'.format(inst_name))
-        pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
-        pins = props.bitcell.cell_1w1r.pin
-        # Edges hardcoded here. Essentially wl->bl/br for the read port.
-        # Port 1 edges
-        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
-        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
-        # Port 0 is a write port, so its timing is not considered here.

compiler/globals.py

@@ -214,21 +214,8 @@ def setup_bitcell():
     # and the user didn't over-ride the bitcell manually,
     # figure out the right bitcell to use
     if OPTS.bitcell == "bitcell":
-        if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0):
+        num_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
-            OPTS.bitcell = "bitcell"
+        OPTS.bitcell = "bitcell_{}port".format(num_ports)
-        else:
-            ports = ""
-            if OPTS.num_rw_ports > 0:
-                ports += "{}rw_".format(OPTS.num_rw_ports)
-            if OPTS.num_w_ports > 0:
-                ports += "{}w_".format(OPTS.num_w_ports)
-            if OPTS.num_r_ports > 0:
-                ports += "{}r".format(OPTS.num_r_ports)
-
-            if ports != "":
-                OPTS.bitcell_suffix = "_" + ports
-            OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix
-
         OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell
         OPTS.replica_bitcell = "replica_" + OPTS.bitcell
     elif OPTS.bitcell == "pbitcell":
@@ -247,7 +234,8 @@ def setup_bitcell():
         OPTS.dummy_bitcell = "dummy_pbitcell"
         OPTS.replica_bitcell = "replica_pbitcell"
         if not OPTS.is_unit_test:
-            debug.warning("Using the parameterized bitcell which may have suboptimal density.")
+            msg = "Didn't find {0}rw {1}w {2}r port bitcell. ".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
+            debug.warning("{} Using the parameterized bitcell which may have suboptimal density.".format(msg))
     debug.info(1, "Using bitcell: {}".format(OPTS.bitcell))
 
 

compiler/options.py

@@ -151,7 +151,7 @@ class options(optparse.Values):
     bitcell_suffix = ""
     bank_select = "bank_select"
     bitcell_array = "bitcell_array"
-    bitcell = "bitcell"
+    bitcell = "bitcell_1port"
     buf_dec = "pbuf"
     column_mux_array = "column_mux_array"
     control_logic = "control_logic"

technology/freepdk45/sp_lib/cell_1rw_1r.sp

@@ -1,14 +0,0 @@
-
-.SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
-MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
-MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
-MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
-MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
-.ENDS
-

technology/freepdk45/sp_lib/cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
 MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
 MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1

technology/freepdk45/sp_lib/dummy_cell_1rw_1r.sp

@@ -1,14 +0,0 @@
-
-.SUBCKT dummy_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
-MM9 RA_to_R_right wl1 br1_noconn gnd NMOS_VTG W=180.0n L=50n m=1
-MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM6 RA_to_R_left wl1 bl1_noconn gnd NMOS_VTG W=180.0n L=50n m=1
-MM5 Q wl0 bl0_noconn gnd NMOS_VTG W=135.00n L=50n m=1
-MM4 Q_bar wl0 br0_noconn gnd NMOS_VTG W=135.00n L=50n m=1
-MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
-MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
-.ENDS
-

technology/freepdk45/sp_lib/dummy_cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT dummy_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT dummy_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1_noconn gnd NMOS_VTG W=180.0n L=50n m=1
 MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
 MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1

technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp

@@ -1,14 +0,0 @@
-
-.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
-MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
-MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
-MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM1 Q vdd gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM0 vdd Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1
-MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1
-.ENDS
-

technology/freepdk45/sp_lib/replica_cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT replica_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
 MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
 MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1

technology/freepdk45/tech/tech.py

@@ -35,6 +35,13 @@ cell_properties.bitcell.mirror.x = True
 cell_properties.bitcell.mirror.y = False
 cell_properties.bitcell_power_pin_directions = ("V", "V")
 
+cell_properties.names["bitcell_1port"] = "cell_6t"
+cell_properties.names["dummy_bitcell_1port"] = "dummy_cell_6t"
+cell_properties.names["replcia_bitcell_1port"] = "replica_cell_6t"
+cell_properties.names["bitcell_2port"] = "cell_2rw"
+cell_properties.names["dummy_bitcell_2port"] = "dummy_cell_2rw"
+cell_properties.names["replica_bitcell_2port"] = "replica_cell_2rw"
+
 ###################################################
 # Custom cell properties
 ###################################################

technology/scn4m_subm/sp_lib/cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
 MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
 MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u

technology/scn4m_subm/sp_lib/dummy_cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT dummy_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT dummy_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1_noconn gnd n w=1.2u l=0.4u
 MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
 MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u

technology/scn4m_subm/sp_lib/replica_cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT replica_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
 MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
 MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u

technology/scn4m_subm/tech/tech.py

@@ -33,6 +33,13 @@ cell_properties = cell_properties()
 cell_properties.bitcell.mirror.x = True
 cell_properties.bitcell.mirror.y = False
 
+cell_properties.names["bitcell_1port"] = "cell_6t"
+cell_properties.names["dummy_bitcell_1port"] = "dummy_cell_6t"
+cell_properties.names["replcia_bitcell_1port"] = "replica_cell_6t"
+cell_properties.names["bitcell_2port"] = "cell_2rw"
+cell_properties.names["dummy_bitcell_2port"] = "dummy_cell_2rw"
+cell_properties.names["replica_bitcell_2port"] = "replica_cell_2rw"
+
 ###################################################
 # Custom cell properties
 ###################################################