From cf63499e769d3b3f9174f2d47a73aeb40e21d55c Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 13 Nov 2020 08:09:21 -0800 Subject: [PATCH] Convert bitcells to 1port and 2port --- compiler/base/custom_cell_properties.py | 9 +-- .../bitcells/{bitcell.py => bitcell_1port.py} | 2 +- .../{bitcell_1w_1r.py => bitcell_2port.py} | 66 ++++++++++-------- ...ell_1rw_1r.py => col_cap_bitcell_2port.py} | 0 ...ummy_bitcell.py => dummy_bitcell_1port.py} | 0 compiler/bitcells/dummy_bitcell_1w_1r.py | 37 ---------- compiler/bitcells/dummy_bitcell_2port.py | 31 ++++++++ ...ca_bitcell.py => replica_bitcell_1port.py} | 0 ...cell_1w_1r.py => replica_bitcell_2port.py} | 42 +++++------ ...ell_1rw_1r.py => row_cap_bitcell_2port.py} | 0 compiler/globals.py | 20 ++---- compiler/options.py | 2 +- technology/freepdk45/gds_lib/cell_1rw_1r.gds | Bin 16384 -> 0 bytes .../gds_lib/{cell_1w_1r.gds => cell_2rw.gds} | Bin 16384 -> 15930 bytes .../freepdk45/gds_lib/dummy_cell_1rw_1r.gds | Bin 16384 -> 0 bytes ...ummy_cell_1w_1r.gds => dummy_cell_2rw.gds} | Bin 16384 -> 15672 bytes .../freepdk45/gds_lib/replica_cell_1rw_1r.gds | Bin 16384 -> 0 bytes ...ca_cell_1w_1r.gds => replica_cell_2rw.gds} | Bin 16384 -> 16002 bytes technology/freepdk45/sp_lib/cell_1rw_1r.sp | 14 ---- .../sp_lib/{cell_1w_1r.sp => cell_2rw.sp} | 2 +- .../freepdk45/sp_lib/dummy_cell_1rw_1r.sp | 14 ---- ...{dummy_cell_1w_1r.sp => dummy_cell_2rw.sp} | 2 +- .../freepdk45/sp_lib/replica_cell_1rw_1r.sp | 14 ---- ...lica_cell_1w_1r.sp => replica_cell_2rw.sp} | 2 +- technology/freepdk45/tech/tech.py | 7 ++ technology/scn4m_subm/gds_lib/cell_1rw_1r.gds | Bin 6330 -> 0 bytes technology/scn4m_subm/gds_lib/cell_1w_1r.gds | Bin 6406 -> 0 bytes technology/scn4m_subm/gds_lib/cell_2rw.gds | Bin 0 -> 6326 bytes .../scn4m_subm/gds_lib/dummy_cell_1rw_1r.gds | Bin 6086 -> 0 bytes .../scn4m_subm/gds_lib/dummy_cell_1w_1r.gds | Bin 6082 -> 0 bytes .../scn4m_subm/gds_lib/dummy_cell_2rw.gds | Bin 0 -> 6082 bytes .../gds_lib/replica_cell_1rw_1r.gds | Bin 6282 -> 0 bytes .../scn4m_subm/gds_lib/replica_cell_1w_1r.gds | Bin 8192 -> 0 bytes .../scn4m_subm/gds_lib/replica_cell_2rw.gds | Bin 0 -> 6278 bytes .../sp_lib/{cell_1rw_1r.sp => cell_2rw.sp} | 2 +- ...dummy_cell_1rw_1r.sp => dummy_cell_2rw.sp} | 2 +- ...ica_cell_1rw_1r.sp => replica_cell_2rw.sp} | 2 +- technology/scn4m_subm/tech/tech.py | 7 ++ 38 files changed, 113 insertions(+), 164 deletions(-) rename compiler/bitcells/{bitcell.py => bitcell_1port.py} (98%) rename compiler/bitcells/{bitcell_1w_1r.py => bitcell_2port.py} (63%) rename compiler/bitcells/{col_cap_bitcell_1rw_1r.py => col_cap_bitcell_2port.py} (100%) rename compiler/bitcells/{dummy_bitcell.py => dummy_bitcell_1port.py} (100%) delete mode 100644 compiler/bitcells/dummy_bitcell_1w_1r.py create mode 100644 compiler/bitcells/dummy_bitcell_2port.py rename compiler/bitcells/{replica_bitcell.py => replica_bitcell_1port.py} (100%) rename compiler/bitcells/{replica_bitcell_1w_1r.py => replica_bitcell_2port.py} (50%) rename compiler/bitcells/{row_cap_bitcell_1rw_1r.py => row_cap_bitcell_2port.py} (100%) delete mode 100644 technology/freepdk45/gds_lib/cell_1rw_1r.gds rename technology/freepdk45/gds_lib/{cell_1w_1r.gds => cell_2rw.gds} (77%) delete mode 100644 technology/freepdk45/gds_lib/dummy_cell_1rw_1r.gds rename technology/freepdk45/gds_lib/{dummy_cell_1w_1r.gds => dummy_cell_2rw.gds} (85%) delete mode 100644 technology/freepdk45/gds_lib/replica_cell_1rw_1r.gds rename technology/freepdk45/gds_lib/{replica_cell_1w_1r.gds => replica_cell_2rw.gds} (77%) delete mode 100644 technology/freepdk45/sp_lib/cell_1rw_1r.sp rename technology/freepdk45/sp_lib/{cell_1w_1r.sp => cell_2rw.sp} (91%) delete mode 100644 technology/freepdk45/sp_lib/dummy_cell_1rw_1r.sp rename technology/freepdk45/sp_lib/{dummy_cell_1w_1r.sp => dummy_cell_2rw.sp} (90%) delete mode 100644 technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp rename technology/freepdk45/sp_lib/{replica_cell_1w_1r.sp => replica_cell_2rw.sp} (89%) delete mode 100644 technology/scn4m_subm/gds_lib/cell_1rw_1r.gds delete mode 100644 technology/scn4m_subm/gds_lib/cell_1w_1r.gds create mode 100644 technology/scn4m_subm/gds_lib/cell_2rw.gds delete mode 100644 technology/scn4m_subm/gds_lib/dummy_cell_1rw_1r.gds delete mode 100644 technology/scn4m_subm/gds_lib/dummy_cell_1w_1r.gds create mode 100644 technology/scn4m_subm/gds_lib/dummy_cell_2rw.gds delete mode 100644 technology/scn4m_subm/gds_lib/replica_cell_1rw_1r.gds delete mode 100644 technology/scn4m_subm/gds_lib/replica_cell_1w_1r.gds create mode 100644 technology/scn4m_subm/gds_lib/replica_cell_2rw.gds rename technology/scn4m_subm/sp_lib/{cell_1rw_1r.sp => cell_2rw.sp} (88%) rename technology/scn4m_subm/sp_lib/{dummy_cell_1rw_1r.sp => dummy_cell_2rw.sp} (88%) rename technology/scn4m_subm/sp_lib/{replica_cell_1rw_1r.sp => replica_cell_2rw.sp} (86%) diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index 8530ee64..efff1786 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -48,7 +48,7 @@ class _pgate: class _bitcell: - def __init__(self, mirror, cell_s8_6t, cell_6t, cell_1rw1r, cell_1w1r): + def __init__(self, mirror, cell_6t, cell_1rw1r, cell_1w1r): self.mirror = mirror self._6t = cell_6t self._1rw1r = cell_1rw1r @@ -75,16 +75,11 @@ class _bitcell: 'wl0': 'wl0', 'wl1': 'wl1'}) - return _bitcell(cell_s8_6t=cell_s8_6t, - cell_6t=cell_6t, + return _bitcell(cell_6t=cell_6t, cell_1rw1r=cell_1rw1r, cell_1w1r=cell_1w1r, mirror=axis) - @property - def cell_s8_6t(self): - return self._s8_6t - @property def cell_6t(self): return self._6t diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell_1port.py similarity index 98% rename from compiler/bitcells/bitcell.py rename to compiler/bitcells/bitcell_1port.py index b2a96356..e1e4bec8 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell_1port.py @@ -10,7 +10,7 @@ from tech import cell_properties as props import bitcell_base -class bitcell(bitcell_base.bitcell_base): +class bitcell_1port(bitcell_base.bitcell_base): """ A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It is a hand-made cell, so diff --git a/compiler/bitcells/bitcell_1w_1r.py b/compiler/bitcells/bitcell_2port.py similarity index 63% rename from compiler/bitcells/bitcell_1w_1r.py rename to compiler/bitcells/bitcell_2port.py index 64a629a2..93642788 100644 --- a/compiler/bitcells/bitcell_1w_1r.py +++ b/compiler/bitcells/bitcell_2port.py @@ -10,7 +10,7 @@ from tech import cell_properties as props import bitcell_base -class bitcell_1w_1r(bitcell_base.bitcell_base): +class bitcell_2port(bitcell_base.bitcell_base): """ A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It is a hand-made cell, so @@ -18,21 +18,21 @@ class bitcell_1w_1r(bitcell_base.bitcell_base): library. """ - pin_names = [props.bitcell.cell_1w1r.pin.bl0, - props.bitcell.cell_1w1r.pin.br0, - props.bitcell.cell_1w1r.pin.bl1, - props.bitcell.cell_1w1r.pin.br1, - props.bitcell.cell_1w1r.pin.wl0, - props.bitcell.cell_1w1r.pin.wl1, - props.bitcell.cell_1w1r.pin.vdd, - props.bitcell.cell_1w1r.pin.gnd] - type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", + pin_names = [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.bl1, + props.bitcell.cell_1rw1r.pin.br1, + props.bitcell.cell_1rw1r.pin.wl0, + props.bitcell.cell_1rw1r.pin.wl1, + props.bitcell.cell_1rw1r.pin.vdd, + props.bitcell.cell_1rw1r.pin.gnd] + type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Q_bar'] def __init__(self, name): super().__init__(name) - debug.info(2, "Create bitcell with 1W and 1R Port") + debug.info(2, "Create bitcell with 1RW and 1R Port") self.nets_match = self.do_nets_exist(self.storage_nets) @@ -46,7 +46,7 @@ class bitcell_1w_1r(bitcell_base.bitcell_base): Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ - pin_name = props.bitcell.cell_1w1r.pin + pin_name = props.bitcell.cell_1rw1r.pin bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col), "{0}_{1}".format(pin_name.br0, col), "{0}_{1}".format(pin_name.bl1, col), @@ -59,64 +59,68 @@ class bitcell_1w_1r(bitcell_base.bitcell_base): def get_all_wl_names(self): """ Creates a list of all wordline pin names """ - return [props.bitcell.cell_1w1r.pin.wl0, - props.bitcell.cell_1w1r.pin.wl1] + return [props.bitcell.cell_1rw1r.pin.wl0, + props.bitcell.cell_1rw1r.pin.wl1] def get_all_bitline_names(self): """ Creates a list of all bitline pin names (both bl and br) """ - return [props.bitcell.cell_1w1r.pin.bl0, - props.bitcell.cell_1w1r.pin.br0, - props.bitcell.cell_1w1r.pin.bl1, - props.bitcell.cell_1w1r.pin.br1] + return [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.bl1, + props.bitcell.cell_1rw1r.pin.br1] def get_all_bl_names(self): """ Creates a list of all bl pins names """ - return [props.bitcell.cell_1w1r.pin.bl0, - props.bitcell.cell_1w1r.pin.bl1] + return [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.bl1] def get_all_br_names(self): """ Creates a list of all br pins names """ - return [props.bitcell.cell_1w1r.pin.br0, - props.bitcell.cell_1w1r.pin.br1] + return [props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.br1] def get_read_bl_names(self): """ Creates a list of bl pin names associated with read ports """ - return [props.bitcell.cell_1w1r.pin.bl0, - props.bitcell.cell_1w1r.pin.bl1] + return [props.bitcell.cell_1rw1r.pin.bl0, + props.bitcell.cell_1rw1r.pin.bl1] def get_read_br_names(self): """ Creates a list of br pin names associated with read ports """ - return [props.bitcell.cell_1w1r.pin.br0, - props.bitcell.cell_1w1r.pin.br1] + return [props.bitcell.cell_1rw1r.pin.br0, + props.bitcell.cell_1rw1r.pin.br1] def get_write_bl_names(self): """ Creates a list of bl pin names associated with write ports """ - return [props.bitcell.cell_1w1r.pin.bl0] + return [props.bitcell.cell_1rw1r.pin.bl0] def get_write_br_names(self): """ Creates a list of br pin names asscociated with write ports""" - return [props.bitcell.cell_1w1r.pin.br1] + return [props.bitcell.cell_1rw1r.pin.br1] def get_bl_name(self, port=0): """Get bl name by port""" + debug.check(port < 2, "Two ports for bitcell_2port only.") return self.bl_names[port] def get_br_name(self, port=0): """Get bl name by port""" + debug.check(port < 2, "Two ports for bitcell_2port only.") return self.br_names[port] def get_wl_name(self, port=0): """Get wl name by port""" - debug.check(port < 2, "Two ports for bitcell_1rw_1r only.") + debug.check(port < 2, "Two ports for bitcell_2port only.") return self.wl_names[port] def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} - pins = props.bitcell.cell_1w1r.pin # Edges hardcoded here. Essentially wl->bl/br for both ports. # Port 0 edges + pins = props.bitcell.cell_1rw1r.pin + graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self) + graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self) + # Port 1 edges graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self) graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self) - # Port 1 is a write port, so its timing is not considered here. diff --git a/compiler/bitcells/col_cap_bitcell_1rw_1r.py b/compiler/bitcells/col_cap_bitcell_2port.py similarity index 100% rename from compiler/bitcells/col_cap_bitcell_1rw_1r.py rename to compiler/bitcells/col_cap_bitcell_2port.py diff --git a/compiler/bitcells/dummy_bitcell.py b/compiler/bitcells/dummy_bitcell_1port.py similarity index 100% rename from compiler/bitcells/dummy_bitcell.py rename to compiler/bitcells/dummy_bitcell_1port.py diff --git a/compiler/bitcells/dummy_bitcell_1w_1r.py b/compiler/bitcells/dummy_bitcell_1w_1r.py deleted file mode 100644 index 60d87728..00000000 --- a/compiler/bitcells/dummy_bitcell_1w_1r.py +++ /dev/null @@ -1,37 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import debug -from tech import cell_properties as props -import bitcell_base - - -class dummy_bitcell_1w_1r(bitcell_base.bitcell_base): - """ - A single bit cell which is forced to store a 0. - This module implements the single memory cell used in the design. It - is a hand-made cell, so the layout and netlist should be available in - the technology library. """ - - pin_names = [props.bitcell.cell_1w1r.pin.bl0, - props.bitcell.cell_1w1r.pin.br0, - props.bitcell.cell_1w1r.pin.bl1, - props.bitcell.cell_1w1r.pin.br1, - props.bitcell.cell_1w1r.pin.wl0, - props.bitcell.cell_1w1r.pin.wl1, - props.bitcell.cell_1w1r.pin.vdd, - props.bitcell.cell_1w1r.pin.gnd] - type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", - "INPUT", "INPUT", "POWER", "GROUND"] - - def __init__(self, name): - super().__init__(name) - debug.info(2, "Create dummy bitcell 1w+1r object") - - - - diff --git a/compiler/bitcells/dummy_bitcell_2port.py b/compiler/bitcells/dummy_bitcell_2port.py new file mode 100644 index 00000000..679509db --- /dev/null +++ b/compiler/bitcells/dummy_bitcell_2port.py @@ -0,0 +1,31 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +from tech import cell_properties as props +import bitcell_base + + +class dummy_bitcell(bitcell_base.bitcell_base): + """ + A single bit cell (6T, 8T, etc.) This module implements the + single memory cell used in the design. It is a hand-made cell, so + the layout and netlist should be available in the technology + library. + """ + pin_names = [props.bitcell.cell_6t.pin.bl, + props.bitcell.cell_6t.pin.br, + props.bitcell.cell_6t.pin.wl, + props.bitcell.cell_6t.pin.vdd, + props.bitcell.cell_6t.pin.gnd] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] + + def __init__(self, name): + super().__init__(name) + debug.info(2, "Create dummy bitcell") + + diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell_1port.py similarity index 100% rename from compiler/bitcells/replica_bitcell.py rename to compiler/bitcells/replica_bitcell_1port.py diff --git a/compiler/bitcells/replica_bitcell_1w_1r.py b/compiler/bitcells/replica_bitcell_2port.py similarity index 50% rename from compiler/bitcells/replica_bitcell_1w_1r.py rename to compiler/bitcells/replica_bitcell_2port.py index 59fa4676..74e121ee 100644 --- a/compiler/bitcells/replica_bitcell_1w_1r.py +++ b/compiler/bitcells/replica_bitcell_2port.py @@ -12,26 +12,23 @@ from tech import parameter, drc import logical_effort -class replica_bitcell_1w_1r(bitcell_base.bitcell_base): +class replica_bitcell(bitcell_base.bitcell_base): """ - A single bit cell which is forced to store a 0. + A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It is a hand-made cell, so the layout and netlist should be available in the technology library. """ - pin_names = [props.bitcell.cell_1w1r.pin.bl0, - props.bitcell.cell_1w1r.pin.br0, - props.bitcell.cell_1w1r.pin.bl1, - props.bitcell.cell_1w1r.pin.br1, - props.bitcell.cell_1w1r.pin.wl0, - props.bitcell.cell_1w1r.pin.wl1, - props.bitcell.cell_1w1r.pin.vdd, - props.bitcell.cell_1w1r.pin.gnd] - type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"] + pin_names = [props.bitcell.cell_6t.pin.bl, + props.bitcell.cell_6t.pin.br, + props.bitcell.cell_6t.pin.wl, + props.bitcell.cell_6t.pin.vdd, + props.bitcell.cell_6t.pin.gnd] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] def __init__(self, name): super().__init__(name) - debug.info(2, "Create replica bitcell 1w+1r object") + debug.info(2, "Create replica bitcell object") def get_stage_effort(self, load): parasitic_delay = 1 @@ -44,18 +41,17 @@ class replica_bitcell_1w_1r(bitcell_base.bitcell_base): """Return the relative capacitance of the access transistor gates""" # FIXME: This applies to bitline capacitances as well. - # FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed. access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"] return 2 * access_tx_cin + def analytical_power(self, corner, load): + """Bitcell power in nW. Only characterizes leakage.""" + from tech import spice + leakage = spice["bitcell_leakage"] + dynamic = 0 # FIXME + total_power = self.return_power(dynamic, leakage) + return total_power + def build_graph(self, graph, inst_name, port_nets): - """Adds edges to graph. Multiport bitcell timing graph is too complex - to use the add_graph_edges function.""" - debug.info(1, 'Adding edges for {}'.format(inst_name)) - pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} - pins = props.bitcell.cell_1w1r.pin - # Edges hardcoded here. Essentially wl->bl/br for the read port. - # Port 1 edges - graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self) - graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self) - # Port 0 is a write port, so its timing is not considered here. + """Adds edges based on inputs/outputs. Overrides base class function.""" + self.add_graph_edges(graph, port_nets) diff --git a/compiler/bitcells/row_cap_bitcell_1rw_1r.py b/compiler/bitcells/row_cap_bitcell_2port.py similarity index 100% rename from compiler/bitcells/row_cap_bitcell_1rw_1r.py rename to compiler/bitcells/row_cap_bitcell_2port.py diff --git a/compiler/globals.py b/compiler/globals.py index c6980d9e..74b578b0 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -214,21 +214,8 @@ def setup_bitcell(): # and the user didn't over-ride the bitcell manually, # figure out the right bitcell to use if OPTS.bitcell == "bitcell": - if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0): - OPTS.bitcell = "bitcell" - else: - ports = "" - if OPTS.num_rw_ports > 0: - ports += "{}rw_".format(OPTS.num_rw_ports) - if OPTS.num_w_ports > 0: - ports += "{}w_".format(OPTS.num_w_ports) - if OPTS.num_r_ports > 0: - ports += "{}r".format(OPTS.num_r_ports) - - if ports != "": - OPTS.bitcell_suffix = "_" + ports - OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix - + num_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports + OPTS.bitcell = "bitcell_{}port".format(num_ports) OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell OPTS.replica_bitcell = "replica_" + OPTS.bitcell elif OPTS.bitcell == "pbitcell": @@ -247,7 +234,8 @@ def setup_bitcell(): OPTS.dummy_bitcell = "dummy_pbitcell" OPTS.replica_bitcell = "replica_pbitcell" if not OPTS.is_unit_test: - debug.warning("Using the parameterized bitcell which may have suboptimal density.") + msg = "Didn't find {0}rw {1}w {2}r port bitcell. ".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports) + debug.warning("{} Using the parameterized bitcell which may have suboptimal density.".format(msg)) debug.info(1, "Using bitcell: {}".format(OPTS.bitcell)) diff --git a/compiler/options.py b/compiler/options.py index 89a801b6..cd9726e0 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -151,7 +151,7 @@ class options(optparse.Values): bitcell_suffix = "" bank_select = "bank_select" bitcell_array = "bitcell_array" - bitcell = "bitcell" + bitcell = "bitcell_1port" buf_dec = "pbuf" column_mux_array = "column_mux_array" control_logic = "control_logic" diff --git a/technology/freepdk45/gds_lib/cell_1rw_1r.gds b/technology/freepdk45/gds_lib/cell_1rw_1r.gds deleted file mode 100644 index 5f3e7213bfd476c5885eac8d75d77077df730c72..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16384 zcmeI2TZ~;*9meg#5+GyCNQYkqv--VEgRje0m->ul*)%>?pSL2bvNNh`$FAMG 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W=180.0n L=50n m=1 -MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1 -MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1 -MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1 -MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1 -MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1 -MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1 -MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1 -.ENDS - diff --git a/technology/freepdk45/sp_lib/cell_1w_1r.sp b/technology/freepdk45/sp_lib/cell_2rw.sp similarity index 91% rename from technology/freepdk45/sp_lib/cell_1w_1r.sp rename to technology/freepdk45/sp_lib/cell_2rw.sp index eb3803b4..a3a6954a 100644 --- a/technology/freepdk45/sp_lib/cell_1w_1r.sp +++ b/technology/freepdk45/sp_lib/cell_2rw.sp @@ -1,5 +1,5 @@ -.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +.SUBCKT cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1 MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1 MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1 diff --git a/technology/freepdk45/sp_lib/dummy_cell_1rw_1r.sp b/technology/freepdk45/sp_lib/dummy_cell_1rw_1r.sp deleted file mode 100644 index c3c082ee..00000000 --- a/technology/freepdk45/sp_lib/dummy_cell_1rw_1r.sp +++ /dev/null @@ -1,14 +0,0 @@ - -.SUBCKT dummy_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd -MM9 RA_to_R_right wl1 br1_noconn gnd NMOS_VTG W=180.0n L=50n m=1 -MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1 -MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1 -MM6 RA_to_R_left wl1 bl1_noconn gnd NMOS_VTG W=180.0n L=50n m=1 -MM5 Q wl0 bl0_noconn gnd NMOS_VTG W=135.00n L=50n m=1 -MM4 Q_bar wl0 br0_noconn gnd NMOS_VTG W=135.00n L=50n m=1 -MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1 -MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1 -MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1 -MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1 -.ENDS - diff --git a/technology/freepdk45/sp_lib/dummy_cell_1w_1r.sp b/technology/freepdk45/sp_lib/dummy_cell_2rw.sp similarity index 90% rename from technology/freepdk45/sp_lib/dummy_cell_1w_1r.sp rename to technology/freepdk45/sp_lib/dummy_cell_2rw.sp index 72d7553f..426ee3ef 100644 --- a/technology/freepdk45/sp_lib/dummy_cell_1w_1r.sp +++ b/technology/freepdk45/sp_lib/dummy_cell_2rw.sp @@ -1,5 +1,5 @@ -.SUBCKT dummy_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +.SUBCKT dummy_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd MM9 RA_to_R_right wl1 br1_noconn gnd NMOS_VTG W=180.0n L=50n m=1 MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1 MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1 diff --git a/technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp b/technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp deleted file mode 100644 index d108b7bf..00000000 --- a/technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp +++ /dev/null @@ -1,14 +0,0 @@ - -.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd -MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1 -MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1 -MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1 -MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1 -MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1 -MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1 -MM1 Q vdd gnd gnd NMOS_VTG W=205.0n L=50n m=1 -MM0 vdd Q gnd gnd NMOS_VTG W=205.0n L=50n m=1 -MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1 -MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1 -.ENDS - diff --git a/technology/freepdk45/sp_lib/replica_cell_1w_1r.sp b/technology/freepdk45/sp_lib/replica_cell_2rw.sp similarity index 89% rename from technology/freepdk45/sp_lib/replica_cell_1w_1r.sp rename to technology/freepdk45/sp_lib/replica_cell_2rw.sp index fd06db8c..97f18252 100644 --- a/technology/freepdk45/sp_lib/replica_cell_1w_1r.sp +++ b/technology/freepdk45/sp_lib/replica_cell_2rw.sp @@ -1,5 +1,5 @@ -.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +.SUBCKT replica_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1 MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1 MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1 diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 17a3b278..035e8b93 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -35,6 +35,13 @@ cell_properties.bitcell.mirror.x = True cell_properties.bitcell.mirror.y = False cell_properties.bitcell_power_pin_directions = ("V", "V") +cell_properties.names["bitcell_1port"] = "cell_6t" +cell_properties.names["dummy_bitcell_1port"] = "dummy_cell_6t" +cell_properties.names["replcia_bitcell_1port"] = "replica_cell_6t" +cell_properties.names["bitcell_2port"] = "cell_2rw" +cell_properties.names["dummy_bitcell_2port"] = "dummy_cell_2rw" +cell_properties.names["replica_bitcell_2port"] = "replica_cell_2rw" + ################################################### # Custom cell properties ################################################### diff --git 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l=0.4u MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u diff --git a/technology/scn4m_subm/sp_lib/dummy_cell_1rw_1r.sp b/technology/scn4m_subm/sp_lib/dummy_cell_2rw.sp similarity index 88% rename from technology/scn4m_subm/sp_lib/dummy_cell_1rw_1r.sp rename to technology/scn4m_subm/sp_lib/dummy_cell_2rw.sp index 9766a840..e07dac48 100644 --- a/technology/scn4m_subm/sp_lib/dummy_cell_1rw_1r.sp +++ b/technology/scn4m_subm/sp_lib/dummy_cell_2rw.sp @@ -1,5 +1,5 @@ -.SUBCKT dummy_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +.SUBCKT dummy_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd MM9 RA_to_R_right wl1 br1_noconn gnd n w=1.2u l=0.4u MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u diff --git a/technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp b/technology/scn4m_subm/sp_lib/replica_cell_2rw.sp similarity index 86% rename from technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp rename to technology/scn4m_subm/sp_lib/replica_cell_2rw.sp index 94bdb75e..9a00da3e 100644 --- a/technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp +++ b/technology/scn4m_subm/sp_lib/replica_cell_2rw.sp @@ -1,5 +1,5 @@ -.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +.SUBCKT replica_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index b1ba6795..724e3d50 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -33,6 +33,13 @@ cell_properties = cell_properties() cell_properties.bitcell.mirror.x = True cell_properties.bitcell.mirror.y = False +cell_properties.names["bitcell_1port"] = "cell_6t" +cell_properties.names["dummy_bitcell_1port"] = "dummy_cell_6t" +cell_properties.names["replcia_bitcell_1port"] = "replica_cell_6t" +cell_properties.names["bitcell_2port"] = "cell_2rw" +cell_properties.names["dummy_bitcell_2port"] = "dummy_cell_2rw" +cell_properties.names["replica_bitcell_2port"] = "replica_cell_2rw" + ################################################### # Custom cell properties ###################################################