luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix typos

This commit is contained in:
mrg 2020-11-24 10:35:14 -08:00
parent d2bc7340ed
commit cdcd115cec
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
compiler/base/custom_cell_properties.py
View File

@ -220,8 +220,8 @@ class cell_properties():
self._col_cap_1port_strap_ground = _cell(["gnd"],
["GROUND"])
self._row_cap_1port_cell = _cell(['vdd]'],
['POWRER'])
self._row_cap_1port_cell = _cell(['vdd'],
['POWER'])
self._row_cap_1port = _bitcell(["wl", "gnd"],
["INPUT", "POWER", "GROUND"])