From cdcd115cec5d5b6d41c7948a47e3daff287a4652 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 24 Nov 2020 10:35:14 -0800 Subject: [PATCH] Fix typos --- compiler/base/custom_cell_properties.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index 5dd0327a..b4d110f8 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -220,8 +220,8 @@ class cell_properties(): self._col_cap_1port_strap_ground = _cell(["gnd"], ["GROUND"]) - self._row_cap_1port_cell = _cell(['vdd]'], - ['POWRER']) + self._row_cap_1port_cell = _cell(['vdd'], + ['POWER']) self._row_cap_1port = _bitcell(["wl", "gnd"], ["INPUT", "POWER", "GROUND"])