Added analyical model test which compares measured delay to model delay.

compiler/tests/21_model_delay_test.py

@@ -11,25 +11,22 @@ import globals
 from globals import OPTS
 import debug
 
-class delay_model_test(openram_test):
+class model_delay_sram_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.spice_name="hspice"
+        #OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-        OPTS.trim_netlist = False
-        debug.info(1, "Trimming disabled for this test. Simulation could be slow.")
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer
         reload(characterizer)
-        
-        from characterizer import model_check
+        from characterizer import delay
         from sram import sram
         from sram_config import sram_config
-        c = sram_config(word_size=4,
+        c = sram_config(word_size=1,
                         num_words=16,
                         num_banks=1)
         c.words_per_row=1
@@ -45,15 +42,32 @@ class delay_model_test(openram_test):
         debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        mc = model_check(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
         import tech
         loads = [tech.spice["msflop_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        sram_data = mc.analyze(probe_address, probe_data, slews, loads)
-        #Combine info about port into all data
-
-        #debug.info(1,"Data:\n{}".format(wl_data))
+        spice_data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        spice_data.update(port_data[0])
+     
+        model_data, port_data = d.analytical_delay(slews, loads)
+        model_data.update(port_data[0])
+        
+        #Only compare the delays
+        spice_delays = {key:value for key, value in spice_data.items() if 'delay' in key}
+        model_delays = {key:value for key, value in model_data.items() if 'delay' in key}
+        debug.info(1,"Spice Delays={}".format(spice_delays))
+        debug.info(1,"Model Delays={}".format(model_delays))
+        if OPTS.tech_name == "freepdk45":
+            error_tolerance = .25
+        elif OPTS.tech_name == "scn4m_subm":
+            error_tolerance = .25
+        else:
+            self.assertTrue(False) # other techs fail
+        # Check if no too many or too few results
+        self.assertTrue(len(spice_delays.keys())==len(model_delays.keys()))
 
+        self.assertTrue(self.check_golden_data(spice_delays,model_delays,error_tolerance))
+        
         globals.end_openram()
         
 # run the test from the command line

compiler/tests/27_worst_case_delay_test.py

@@ -1,81 +0,0 @@
-#!/usr/bin/env python3
-"""
-Run a regression test on various srams
-"""
-
-import unittest
-from testutils import header,openram_test
-import sys,os
-sys.path.append(os.path.join(sys.path[0],".."))
-import globals
-from globals import OPTS
-import debug
-
-@unittest.skip("SKIPPING 27_worst_case_delay_test")
-class worst_case_timing_sram_test(openram_test):
-
-    def runTest(self):
-        OPTS.tech_name = "freepdk45"
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.spice_name="hspice"
-        OPTS.analytical_delay = False
-        OPTS.netlist_only = True
-        OPTS.trim_netlist = False
-        OPTS.check_lvsdrc = True
-        
-
-        # This is a hack to reload the characterizer __init__ with the spice version
-        from importlib import reload
-        import characterizer
-        reload(characterizer)
-        from characterizer import worst_case
-        if not OPTS.spice_exe:
-            debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
-
-        word_size, num_words, num_banks = 2, 16, 1
-        from sram import sram
-        from sram_config import sram_config
-        c = sram_config(word_size=word_size,
-                        num_words=num_words,
-                        num_banks=num_banks)
-        c.words_per_row=1
-        c.recompute_sizes()
-        debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
-                                                                       word_size, num_words, num_banks))
-        s = sram(c, name="sram1")
-        
-        sp_netlist_file = OPTS.openram_temp + "temp.sp"
-        s.sp_write(sp_netlist_file)
-        
-        if OPTS.use_pex:
-            gdsname = OPTS.output_path + s.name + ".gds"
-            s.gds_write(gdsname)
-            
-            import verify
-            reload(verify)
-            # Output the extracted design if requested
-            sp_pex_file = OPTS.output_path + s.name + "_pex.sp"
-            verify.run_pex(s.name, gdsname, sp_netlist_file, output=sp_pex_file)
-            sp_sim_file = sp_pex_file
-            debug.info(1, "Performing spice simulations with backannotated spice file.")
-        else:
-            sp_sim_file = sp_netlist_file
-            debug.info(1, "Performing spice simulations with spice netlist.")
-            
-        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        wc = worst_case(s.s, sp_sim_file, corner)
-        import tech
-        loads = [tech.spice["msflop_in_cap"]*4]
-        slews = [tech.spice["rise_time"]*2]
-        probe_address = "1" * s.s.addr_size
-        probe_data = s.s.word_size - 1
-        wc.analyze(probe_address, probe_data, slews, loads)
-
-        globals.end_openram()
-
-# run the test from the command line
-if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main()