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Uniquify bitcell array

This commit is contained in:
Matt Guthaus 2018-11-16 12:52:22 -08:00
parent e040fd12f9
commit ca750b698a
3 changed files with 10 additions and 4 deletions
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3
compiler/base/hierarchy_design.py
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@ -37,10 +37,11 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
ok_list = ['contact', ok_list = ['contact',
'ptx', 'ptx',
'pbitcell', 'pbitcell',
'bitcell', 'replica_pbitcell',
'sram', 'sram',
'hierarchical_predecode2x4', 'hierarchical_predecode2x4',
'hierarchical_predecode3x8'] 'hierarchical_predecode3x8']
# Library cells don't change # Library cells don't change
if self.is_library_cell: if self.is_library_cell:
return return

9
compiler/modules/bitcell_array.py
View File

@ -4,7 +4,7 @@ from tech import drc, spice
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
unique_id = 1
class bitcell_array(design.design): class bitcell_array(design.design):
""" """
@ -12,8 +12,13 @@ class bitcell_array(design.design):
and word line is connected by abutment. and word line is connected by abutment.
Connects the word lines and bit lines. Connects the word lines and bit lines.
""" """
unique_id = 1
def __init__(self, cols, rows, name=""):
def __init__(self, cols, rows, name="bitcell_array"): if name == "":
name = "bitcell_array_{0}x{1}_{2}".format(rows,cols,bitcell_array.unique_id)
bitcell_array.unique_id += 1
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))

2
compiler/modules/replica_bitline.py
View File

@ -90,7 +90,7 @@ class replica_bitline(design.design):
self.add_mod(self.bitcell) self.add_mod(self.bitcell)
# This is the replica bitline load column that is the height of our array # This is the replica bitline load column that is the height of our array
self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.bitcell_loads) self.rbl = bitcell_array(cols=1, rows=self.bitcell_loads)
self.add_mod(self.rbl) self.add_mod(self.rbl)
# FIXME: The FO and depth of this should be tuned # FIXME: The FO and depth of this should be tuned