diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py
index 7b95fbb1..68749693 100644
--- a/compiler/base/hierarchy_design.py
+++ b/compiler/base/hierarchy_design.py
@@ -37,10 +37,11 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         ok_list = ['contact',
                    'ptx',
                    'pbitcell',
-                   'bitcell',
+                   'replica_pbitcell',                   
                    'sram',
                    'hierarchical_predecode2x4',
                    'hierarchical_predecode3x8']
+
         # Library cells don't change
         if self.is_library_cell:
             return
diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index 1d9b1539..d42c134e 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -4,7 +4,7 @@ from tech import drc, spice
 from vector import vector
 from globals import OPTS
 
-
+unique_id = 1
 
 class bitcell_array(design.design):
     """
@@ -12,8 +12,13 @@ class bitcell_array(design.design):
     and word line is connected by abutment.
     Connects the word lines and bit lines.
     """
+    unique_id = 1
+    
+    def __init__(self, cols, rows, name=""):
 
-    def __init__(self, cols, rows, name="bitcell_array"):
+        if name == "":
+            name = "bitcell_array_{0}x{1}_{2}".format(rows,cols,bitcell_array.unique_id)
+            bitcell_array.unique_id += 1
         design.design.__init__(self, name)
         debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
 
diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py
index 5c14b14d..e349fa89 100644
--- a/compiler/modules/replica_bitline.py
+++ b/compiler/modules/replica_bitline.py
@@ -90,7 +90,7 @@ class replica_bitline(design.design):
         self.add_mod(self.bitcell)
 
         # This is the replica bitline load column that is the height of our array
-        self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.bitcell_loads)
+        self.rbl = bitcell_array(cols=1, rows=self.bitcell_loads)
         self.add_mod(self.rbl)
 
         # FIXME: The FO and depth of this should be tuned