From c8bbee884b6186a382f1559717080da296109308 Mon Sep 17 00:00:00 2001 From: jsowash Date: Wed, 24 Jul 2019 16:01:12 -0700 Subject: [PATCH] Removed layout related rw port's special pen. --- compiler/modules/control_logic.py | 34 +++++++++++++++---------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 3607f826..45e1f643 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -647,11 +647,11 @@ class control_logic(design.design): x_off = self.control_x_offset (y_off,mirror)=self.get_offset(row) - if self.port_type == "rw": - offset = vector(x_off, y_off) - self.pre_p_en_inst.place(offset, mirror) - - x_off += self.and2.width + # if self.port_type == "rw": + # offset = vector(x_off, y_off) + # self.pre_p_en_inst.place(offset, mirror) + # + # x_off += self.and2.width offset = vector(x_off,y_off) self.p_en_bar_inst.place(offset, mirror) @@ -659,18 +659,18 @@ class control_logic(design.design): self.row_end_inst.append(self.p_en_bar_inst) def route_pen(self): - if self.port_type == "rw": - # Connect the NAND gate inputs to the bus - pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", "we_bar"]) - self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets) - - out_pos = self.pre_p_en_inst.get_pin("Z").center() - in_pos = self.p_en_bar_inst.get_pin("A").lc() - mid1 = vector(out_pos.x,in_pos.y) - self.add_wire(("metal1","via1","metal2"),[out_pos,mid1,in_pos]) - else: - in_map = zip(["A"], ["gated_clk_buf"]) - self.connect_vertical_bus(in_map, self.p_en_bar_inst, self.rail_offsets) + # if self.port_type == "rw": + # # Connect the NAND gate inputs to the bus + # pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", "we_bar"]) + # self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets) + # + # out_pos = self.pre_p_en_inst.get_pin("Z").center() + # in_pos = self.p_en_bar_inst.get_pin("A").lc() + # mid1 = vector(out_pos.x,in_pos.y) + # self.add_wire(("metal1","via1","metal2"),[out_pos,mid1,in_pos]) + # else: + in_map = zip(["A"], ["gated_clk_buf"]) + self.connect_vertical_bus(in_map, self.p_en_bar_inst, self.rail_offsets) self.connect_output(self.p_en_bar_inst, "Z", "p_en_bar")