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Changed layout input names of s_en AND gate to match the schematic

This commit is contained in:
Hunter Nichols 2020-02-19 23:32:11 -08:00
parent df2f981a34
commit c1cb6bf512
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/control_logic.py
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@ -670,7 +670,7 @@ class control_logic(design.design):
if self.port_type=="rw": if self.port_type=="rw":
input_name = "we_bar" input_name = "we_bar"
else: else:
input_name = "cs_bar" input_name = "cs"
sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name]) sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name])
self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets) self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets)