From c1cb6bf51278ec1525e5ee675b08eb9096ed97c8 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 19 Feb 2020 23:32:11 -0800 Subject: [PATCH] Changed layout input names of s_en AND gate to match the schematic --- compiler/modules/control_logic.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 458b9b96..1612938d 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -670,7 +670,7 @@ class control_logic(design.design): if self.port_type=="rw": input_name = "we_bar" else: - input_name = "cs_bar" + input_name = "cs" sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name]) self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets)