diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index 458b9b96..1612938d 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -670,7 +670,7 @@ class control_logic(design.design):
         if self.port_type=="rw":
             input_name = "we_bar"
         else:
-            input_name = "cs_bar"
+            input_name = "cs"
             
         sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name])
         self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets)