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Fixed pbitcell graph edge formation.

This commit is contained in:
Hunter Nichols 2019-07-30 00:49:43 -07:00
parent 98878a0a27
commit c12dd987dc
3 changed files with 14 additions and 18 deletions
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7
compiler/bitcells/pbitcell.py
View File

@ -962,11 +962,16 @@ class pbitcell(design.design):
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges to graph for pbitcell. Only readwrite and read ports."""
if self.dummy_bitcell:
return
pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
# Edges added wl->bl, wl->br for every port except write ports
rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names)
r_pin_names = zip(self.rw_wl_names, self.rw_bl_names, self.rw_br_names)
for pin_zip in zip(rw_pin_names, r_pin_names):
for pin_zip in [rw_pin_names, r_pin_names]:
for wl,bl,br in pin_zip:
graph.add_edge(pin_dict[wl],pin_dict[bl])
graph.add_edge(pin_dict[wl],pin_dict[br])

7
compiler/characterizer/delay.py
View File

@ -285,12 +285,7 @@ class delay(simulation):
def get_bl_name(self, paths):
"""Gets the signal name associated with the bitlines in the bank."""
cell_mods = factory.get_mods(OPTS.bitcell)
if len(cell_mods)>=1:
cell_mod = self.get_primary_cell_mod(cell_mods)
elif len(cell_mods)==0:
debug.error("No bitcells found. Cannot determine bitline names.", 1)
cell_mod = factory.create(module_type=OPTS.bitcell)
cell_bl = cell_mod.get_bl_name()
cell_br = cell_mod.get_br_name()

14
compiler/characterizer/functional.py
View File

@ -413,7 +413,7 @@ class functional(simulation):
port = 0
self.graph.get_all_paths('{}{}'.format(tech.spice["clk"], port),
'{}{}_{}'.format(self.dout_name, port, 0))
'{}{}_{}'.format(self.dout_name, port, 0).lower())
self.sen_name = self.get_sen_name(self.graph.all_paths)
debug.info(2,"s_en name = {}".format(self.sen_name))
@ -422,7 +422,7 @@ class functional(simulation):
debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name))
self.q_name,self.qbar_name = self.get_bit_name()
debug.info(2,"q name={}\nqbar name={}".format(self.bl_name,self.br_name))
debug.info(2,"q name={}\nqbar name={}".format(self.q_name,self.qbar_name))
def get_bit_name(self):
""" Get a bit cell name """
@ -454,12 +454,7 @@ class functional(simulation):
def get_bl_name(self, paths):
"""Gets the signal name associated with the bitlines in the bank."""
cell_mods = factory.get_mods(OPTS.bitcell)
if len(cell_mods)>=1:
cell_mod = self.get_primary_cell_mod(cell_mods)
elif len(cell_mods)==0:
debug.error("No bitcells found. Cannot determine bitline names.", 1)
cell_mod = factory.create(module_type=OPTS.bitcell)
cell_bl = cell_mod.get_bl_name()
cell_br = cell_mod.get_br_name()
@ -494,8 +489,9 @@ class functional(simulation):
has_cell = has_cell or replica_cell.contains(bitcell, replica_cell.mods)
if not has_cell:
non_rbc_mods.append(bitcell)
if len(non_rbc_mods) != 1:
debug.error('Multiple bitcell mods found. Cannot distinguish for characterization',1)
debug.error('{} possible bitcell mods found. Cannot distinguish for characterization'.format(len(non_rbc_mods)),1)
return non_rbc_mods[0]
def are_mod_pins_equal(self, mods):