diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py
index 6d95a15f..3c59a9e3 100644
--- a/compiler/bitcells/pbitcell.py
+++ b/compiler/bitcells/pbitcell.py
@@ -962,11 +962,16 @@ class pbitcell(design.design):
 
     def build_graph(self, graph, inst_name, port_nets):        
         """Adds edges to graph for pbitcell. Only readwrite and read ports."""
+        
+        if self.dummy_bitcell:
+            return
+        
         pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} 
         # Edges added wl->bl, wl->br for every port except write ports
         rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names)
         r_pin_names = zip(self.rw_wl_names, self.rw_bl_names, self.rw_br_names)
-        for pin_zip in zip(rw_pin_names, r_pin_names): 
+
+        for pin_zip in [rw_pin_names, r_pin_names]: 
             for wl,bl,br in pin_zip:
                 graph.add_edge(pin_dict[wl],pin_dict[bl])
                 graph.add_edge(pin_dict[wl],pin_dict[br])
diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 09bf4571..854739cb 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -261,7 +261,7 @@ class delay(simulation):
         port = 0
         self.graph.get_all_paths('{}{}'.format(tech.spice["clk"], port), 
                                  '{}{}_{}'.format(self.dout_name, port, self.probe_data))
-
+        
         self.sen_name = self.get_sen_name(self.graph.all_paths)    
         debug.info(2,"s_en name = {}".format(self.sen_name))
         
@@ -285,12 +285,7 @@ class delay(simulation):
     def get_bl_name(self, paths):
         """Gets the signal name associated with the bitlines in the bank."""
         
-        cell_mods = factory.get_mods(OPTS.bitcell)
-        if len(cell_mods)>=1:
-            cell_mod = self.get_primary_cell_mod(cell_mods)
-        elif len(cell_mods)==0:
-            debug.error("No bitcells found. Cannot determine bitline names.", 1)
-            
+        cell_mod = factory.create(module_type=OPTS.bitcell)  
         cell_bl = cell_mod.get_bl_name()
         cell_br = cell_mod.get_br_name()
         
@@ -301,7 +296,7 @@ class delay(simulation):
         for int_net in [cell_bl, cell_br]:
             bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
                 
-        return bl_names[0], bl_names[1]          
+        return bl_names[0], bl_names[1]         
 
     
     def get_bl_name_search_exclusions(self):
diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py
index 0b3e7b4b..dc4fe48a 100644
--- a/compiler/characterizer/functional.py
+++ b/compiler/characterizer/functional.py
@@ -413,7 +413,7 @@ class functional(simulation):
         
         port = 0
         self.graph.get_all_paths('{}{}'.format(tech.spice["clk"], port), 
-                                 '{}{}_{}'.format(self.dout_name, port, 0))
+                                 '{}{}_{}'.format(self.dout_name, port, 0).lower())
 
         self.sen_name = self.get_sen_name(self.graph.all_paths)    
         debug.info(2,"s_en name = {}".format(self.sen_name))
@@ -422,7 +422,7 @@ class functional(simulation):
         debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name))
 
         self.q_name,self.qbar_name = self.get_bit_name()
-        debug.info(2,"q name={}\nqbar name={}".format(self.bl_name,self.br_name))
+        debug.info(2,"q name={}\nqbar name={}".format(self.q_name,self.qbar_name))
         
     def get_bit_name(self):
         """ Get a bit cell name """
@@ -454,12 +454,7 @@ class functional(simulation):
     def get_bl_name(self, paths):
         """Gets the signal name associated with the bitlines in the bank."""
         
-        cell_mods = factory.get_mods(OPTS.bitcell)
-        if len(cell_mods)>=1:
-            cell_mod = self.get_primary_cell_mod(cell_mods)
-        elif len(cell_mods)==0:
-            debug.error("No bitcells found. Cannot determine bitline names.", 1)
-            
+        cell_mod = factory.create(module_type=OPTS.bitcell)  
         cell_bl = cell_mod.get_bl_name()
         cell_br = cell_mod.get_br_name()
         
@@ -494,8 +489,9 @@ class functional(simulation):
                 has_cell = has_cell or replica_cell.contains(bitcell, replica_cell.mods)
             if not has_cell:
                 non_rbc_mods.append(bitcell)
+                
         if len(non_rbc_mods) != 1:
-            debug.error('Multiple bitcell mods found. Cannot distinguish for characterization',1)
+            debug.error('{} possible bitcell mods found. Cannot distinguish for characterization'.format(len(non_rbc_mods)),1)
         return non_rbc_mods[0]
 
     def are_mod_pins_equal(self, mods):