mirror of https://github.com/VLSIDA/OpenRAM.git
Retry routes with expanding detour allowed.
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parent
11384ef926
commit
c0ab0af201
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@ -865,7 +865,7 @@ class router(router_tech):
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debug.check(index<self.num_pin_components(pin_name),"Pin component index too large.")
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debug.check(index<self.num_pin_components(pin_name),"Pin component index too large.")
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pin_in_tracks = self.pin_groups[pin_name][index].grids
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pin_in_tracks = self.pin_groups[pin_name][index].grids
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debug.info(2, "Set target: " + str(pin_name) + " " + str(pin_in_tracks))
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debug.info(3, "Set target: " + str(pin_name) + " " + str(pin_in_tracks))
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self.rg.add_target(pin_in_tracks)
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self.rg.add_target(pin_in_tracks)
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def add_pin_component_target_except(self, pin_name, index):
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def add_pin_component_target_except(self, pin_name, index):
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@ -1012,12 +1012,9 @@ class router(router_tech):
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path_set = grid_utils.flatten_set(path)
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path_set = grid_utils.flatten_set(path)
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self.path_blockages.append(path_set)
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self.path_blockages.append(path_set)
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return True
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else:
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else:
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self.write_debug_gds("failed_route.gds")
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# clean up so we can try a reroute
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self.rg.reinit()
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return False
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return False
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return True
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def annotate_pin_and_tracks(self, pin, tracks):
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def annotate_pin_and_tracks(self, pin, tracks):
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""""
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""""
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@ -170,43 +170,28 @@ class supply_tree_router(router):
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def route_signal(self, pin_name, src_idx, dest_idx):
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def route_signal(self, pin_name, src_idx, dest_idx):
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debug.info(2, "Routing {0} to {1} on pin {2}".format(src_idx, dest_idx, pin_name))
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for detour_scale in [5 * pow(2, x) for x in range(5)]:
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debug.info(2, "Routing {0} to {1} with scale {2}".format(src_idx, dest_idx, detour_scale))
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# Clear everything in the routing grid.
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# Clear everything in the routing grid.
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self.rg.reinit()
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self.rg.reinit()
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# This is inefficient since it is non-incremental, but it was
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# This is inefficient since it is non-incremental, but it was
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# easier to debug.
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# easier to debug.
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self.prepare_blockages(pin_name)
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self.prepare_blockages(pin_name)
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# Add the single component of the pin as the source
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# Add the single component of the pin as the source
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# which unmarks it as a blockage too
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# which unmarks it as a blockage too
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self.add_pin_component_source(pin_name, src_idx)
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self.add_pin_component_source(pin_name, src_idx)
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# Marks all pin components except index as target
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# Marks all pin components except index as target
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self.add_pin_component_target(pin_name, dest_idx)
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self.add_pin_component_target(pin_name, dest_idx)
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# Add the prevous paths as a target too
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#self.add_path_target(self.paths)
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# print("SOURCE: ")
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# for k,v in self.rg.map.items():
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# if v.source:
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# print(k)
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# print("TARGET: ")
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# for k,v in self.rg.map.items():
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# if v.target:
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# print(k)
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# Actually run the A* router
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if not self.run_router(detour_scale=5):
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self.write_debug_gds("debug_route.gds", True)
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# if index==3 and pin_name=="vdd":
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# self.write_debug_gds("route.gds",False)
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# Actually run the A* router
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if self.run_router(detour_scale=detour_scale):
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return
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self.write_debug_gds("debug_route.gds", True)
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@ -445,7 +445,7 @@ class sram_1bank(sram_base):
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if port == 0:
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if port == 0:
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offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
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offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
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- self.data_bus_size[port] + 2 * self.m1_pitch)
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- self.data_bus_size[port] + 2 * self.m3_pitch)
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cr = channel_route.channel_route(netlist=route_map,
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cr = channel_route.channel_route(netlist=route_map,
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offset=offset,
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offset=offset,
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layer_stack=layer_stack,
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layer_stack=layer_stack,
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@ -460,7 +460,7 @@ class sram_1bank(sram_base):
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self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
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self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
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else:
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else:
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offset = vector(0,
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offset = vector(0,
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self.bank.height + 2 * self.m1_space)
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self.bank.height + self.m3_pitch)
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cr = channel_route.channel_route(netlist=route_map,
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cr = channel_route.channel_route(netlist=route_map,
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offset=offset,
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offset=offset,
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layer_stack=layer_stack,
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layer_stack=layer_stack,
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