diff --git a/compiler/router/router.py b/compiler/router/router.py
index bd99ab2c..d63e1739 100644
--- a/compiler/router/router.py
+++ b/compiler/router/router.py
@@ -865,7 +865,7 @@ class router(router_tech):
         debug.check(index<self.num_pin_components(pin_name),"Pin component index too large.")
 
         pin_in_tracks = self.pin_groups[pin_name][index].grids
-        debug.info(2, "Set target: " + str(pin_name) + " " + str(pin_in_tracks))
+        debug.info(3, "Set target: " + str(pin_name) + " " + str(pin_in_tracks))
         self.rg.add_target(pin_in_tracks)
 
     def add_pin_component_target_except(self, pin_name, index):
@@ -1012,12 +1012,9 @@ class router(router_tech):
 
             path_set = grid_utils.flatten_set(path)
             self.path_blockages.append(path_set)
+            return True
         else:
-            self.write_debug_gds("failed_route.gds")
-            # clean up so we can try a reroute
-            self.rg.reinit()
             return False
-        return True
 
     def annotate_pin_and_tracks(self, pin, tracks):
         """"
diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py
index d67ee9ce..4af2ed6a 100644
--- a/compiler/router/supply_tree_router.py
+++ b/compiler/router/supply_tree_router.py
@@ -170,43 +170,28 @@ class supply_tree_router(router):
 
     def route_signal(self, pin_name, src_idx, dest_idx):
         
-        debug.info(2, "Routing {0} to {1} on pin {2}".format(src_idx, dest_idx, pin_name))
-        
-        # Clear everything in the routing grid.
-        self.rg.reinit()
-
-        # This is inefficient since it is non-incremental, but it was
-        # easier to debug.
-        self.prepare_blockages(pin_name)
-
-        # Add the single component of the pin as the source
-        # which unmarks it as a blockage too
-        self.add_pin_component_source(pin_name, src_idx)
-
-        # Marks all pin components except index as target
-        self.add_pin_component_target(pin_name, dest_idx)
+        for detour_scale in [5 * pow(2, x) for x in range(5)]:
+            debug.info(2, "Routing {0} to {1} with scale {2}".format(src_idx, dest_idx, detour_scale))
             
-        # Add the prevous paths as a target too
-        #self.add_path_target(self.paths)
+            # Clear everything in the routing grid.
+            self.rg.reinit()
 
-        # print("SOURCE: ")
-        # for k,v in self.rg.map.items():
-        #     if v.source:
-        #         print(k)
-        
-        # print("TARGET: ")
-        # for k,v in self.rg.map.items():
-        #     if v.target:
-        #         print(k)
-
-        # Actually run the A* router
-        if not self.run_router(detour_scale=5):
-            self.write_debug_gds("debug_route.gds", True)
-
-        # if index==3 and pin_name=="vdd":
-        #    self.write_debug_gds("route.gds",False)
+            # This is inefficient since it is non-incremental, but it was
+            # easier to debug.
+            self.prepare_blockages(pin_name)
 
+            # Add the single component of the pin as the source
+            # which unmarks it as a blockage too
+            self.add_pin_component_source(pin_name, src_idx)
 
+            # Marks all pin components except index as target
+            self.add_pin_component_target(pin_name, dest_idx)
+            
+            # Actually run the A* router
+            if self.run_router(detour_scale=detour_scale):
+                return
+
+        self.write_debug_gds("debug_route.gds", True)
 
 
 
diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py
index 18b1da99..a7bc9c9e 100644
--- a/compiler/sram/sram_1bank.py
+++ b/compiler/sram/sram_1bank.py
@@ -445,7 +445,7 @@ class sram_1bank(sram_base):
 
             if port == 0:
                 offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
-                                - self.data_bus_size[port] + 2 * self.m1_pitch)
+                                - self.data_bus_size[port] + 2 * self.m3_pitch)
                 cr = channel_route.channel_route(netlist=route_map,
                                                  offset=offset,
                                                  layer_stack=layer_stack,
@@ -460,7 +460,7 @@ class sram_1bank(sram_base):
                     self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
             else:
                 offset = vector(0,
-                                self.bank.height + 2 * self.m1_space)
+                                self.bank.height + self.m3_pitch)
                 cr = channel_route.channel_route(netlist=route_map,
                                                  offset=offset,
                                                  layer_stack=layer_stack,