Added corner paramters to power functions. This commit does not compile (sorry)

compiler/pgates/pnand2.py

@@ -214,6 +214,6 @@ class pnand2(pgate.pgate):
         c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
         return self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew)
         
-    def analytical_power(self, slew, load=0.0):
+    def analytical_power(self, vdd, temp, load):
         #Adding a magic number until I can properly define this.
-        return 1
+        return self.return_power()

compiler/pgates/pnand3.py

@@ -234,6 +234,6 @@ class pnand3(pgate.pgate):
         c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
         return self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew)
         
-    def analytical_power(self, slew, load=0.0):
+    def analytical_power(self, vdd, temp, load):
         #Adding a magic number until I can properly define this.
-        return 2
+        return self.return_power()

compiler/pgates/pnor2.py

@@ -219,7 +219,8 @@ class pnor2(pgate.pgate):
     def input_load(self):
         return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"]
 
-    def analytical_delay(self, slew, load=0.0):
+    def analytical_delay(self, vdd, temp, load):
         r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"])
         c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
         return self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew)
+