diff --git a/compiler/base/design.py b/compiler/base/design.py index ad37dfe6..7d146fe0 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -121,10 +121,10 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout): text+=str(i)+",\n" return text - def analytical_power(self, slew, load): + def analytical_power(self, vdd, temp, load): """ Get total power of a module """ #print "Getting power for ",self.name," module" - total_module_power = 0 - for inst in self.insts: - total_module_power += inst.mod.analytical_power(slew, load) + total_module_power = self.return_power() + # for inst in self.insts: + # total_module_power += self.return_power()#inst.mod.analytical_power(vdd, temp, load) return total_module_power diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index dadebdab..52218884 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -215,7 +215,7 @@ class spice(verilog.verilog): def generate_rc_net(self,lump_num, wire_length, wire_width): return wire_spice_model(lump_num, wire_length, wire_width) - def return_power(self, dynamic, leakage): + def return_power(self, dynamic=0.0, leakage=0.0): return power_data(dynamic, leakage) class delay_data: diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 16091b60..1b2e416d 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -97,7 +97,7 @@ class control_logic(design.design): # GAP between main control and replica bitline self.replica_bitline_gap = 2*self.m2_pitch - + def add_modules(self): @@ -691,7 +691,10 @@ class control_logic(design.design): def analytical_power(self, vdd, temp, load): #This has yet to be fully determined. print "Instances:" + total_power = self.return_power() #empty power object for inst in self.insts: print inst.name," Instance" + total_power += inst.mod.analytical_power(vdd, temp, load) + #currently, only return flop array power - return 0 \ No newline at end of file + return total_power \ No newline at end of file diff --git a/compiler/modules/ms_flop.py b/compiler/modules/ms_flop.py index edb5e3d4..a9a86ddd 100644 --- a/compiler/modules/ms_flop.py +++ b/compiler/modules/ms_flop.py @@ -27,8 +27,11 @@ class ms_flop(design.design): result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"]) return result - def analytical_power(self, slew, load = 0.0): + def analytical_power(self, vdd, temp, load): #Value taken from tech file. from tech import spice - return spice["msflop_power"] + return self.return_power() + #return spice["msflop_power"] + + \ No newline at end of file diff --git a/compiler/modules/ms_flop_array.py b/compiler/modules/ms_flop_array.py index 8e29d846..f6297e0b 100644 --- a/compiler/modules/ms_flop_array.py +++ b/compiler/modules/ms_flop_array.py @@ -135,5 +135,5 @@ class ms_flop_array(design.design): def analytical_delay(self, slew, load=0.0): return self.ms.analytical_delay(slew=slew, load=load) - def analytical_power(self, slew, load): - return self.columns * self.ms.analytical_power(slew=slew, load=load) + # def analytical_power(self, vdd, temp, load): + # return self.columns * self.ms.analytical_power(slew=slew, load=load) diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index 6be7dc77..db1477a7 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -344,3 +344,14 @@ class replica_bitline(design.design): height=pin.height(), width=pin.width()) + + # def analytical_power(self, vdd, temp, load): + # #This has yet to be fully determined. + # print "Instances:" + # total_power = 0 + # for inst in self.insts: + # print inst.name," Instance" + # #total_power += inst.mod.analytical_power(vdd, temp, load) + + # #currently, only return flop array power + # return total_power \ No newline at end of file diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 87f8f006..dc1904dc 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -214,6 +214,6 @@ class pnand2(pgate.pgate): c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) - def analytical_power(self, slew, load=0.0): + def analytical_power(self, vdd, temp, load): #Adding a magic number until I can properly define this. - return 1 + return self.return_power() diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index a8216a45..509aa59d 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -234,6 +234,6 @@ class pnand3(pgate.pgate): c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) - def analytical_power(self, slew, load=0.0): + def analytical_power(self, vdd, temp, load): #Adding a magic number until I can properly define this. - return 2 + return self.return_power() diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 684a2b51..1ee6f64e 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -219,7 +219,8 @@ class pnor2(pgate.pgate): def input_load(self): return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"] - def analytical_delay(self, slew, load=0.0): + def analytical_delay(self, vdd, temp, load): r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) + \ No newline at end of file diff --git a/compiler/temp/sram_2_16_1_freepdk45_TT_10V_25C.lib b/compiler/temp/sram_2_16_1_freepdk45_TT_10V_25C.lib index 75a20561..57acdc7c 100644 --- a/compiler/temp/sram_2_16_1_freepdk45_TT_10V_25C.lib +++ b/compiler/temp/sram_2_16_1_freepdk45_TT_10V_25C.lib @@ -76,254 +76,3 @@ cell (sram_2_16_1_freepdk45){ dont_touch : true; area : 1756.7563625; - bus(DATA){ - bus_type : DATA; - direction : inout; - max_capacitance : 1.6728; - three_state : "!OEb & !clk"; - memory_write(){ - address : ADDR; - clocked_on : clk; - } - memory_read(){ - address : ADDR; - } - pin(DATA[1:0]){ - internal_power(){ - when : "OEb & !clk"; - rise_power(scalar){ - values("0"); - } - fall_power(scalar){ - values("0"); - } - } - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - internal_power(){ - when : "!OEb & !clk"; - rise_power(scalar){ - values("0"); - } - fall_power(scalar){ - values("0"); - } - } - timing(){ - timing_sense : non_unate; - related_pin : "clk"; - timing_type : falling_edge; - cell_rise(CELL_TABLE) { - values("0.167, 0.168, 0.177",\ - "0.167, 0.168, 0.177",\ - "0.167, 0.168, 0.177"); - } - cell_fall(CELL_TABLE) { - values("0.167, 0.168, 0.177",\ - "0.167, 0.168, 0.177",\ - "0.167, 0.168, 0.177"); - } - rise_transition(CELL_TABLE) { - values("0.006, 0.007, 0.018",\ - "0.006, 0.007, 0.018",\ - "0.006, 0.007, 0.018"); - } - fall_transition(CELL_TABLE) { - values("0.006, 0.007, 0.018",\ - "0.006, 0.007, 0.018",\ - "0.006, 0.007, 0.018"); - } - } - } - } - - bus(ADDR){ - bus_type : ADDR; - direction : input; - capacitance : 0.2091; - max_transition : 0.04; - fanout_load : 1.000000; - pin(ADDR[6:0]){ - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - } - } - - pin(CSb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - } - - pin(OEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - } - - pin(WEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - } - - pin(clk){ - clock : true; - direction : input; - capacitance : 0.2091; - timing(){ - timing_type :"min_pulse_width"; - related_pin : clk; - rise_constraint(scalar) { - values("0.0"); - } - fall_constraint(scalar) { - values("0.0"); - } - } - timing(){ - timing_type :"minimum_period"; - related_pin : clk; - rise_constraint(scalar) { - values("0.0"); - } - fall_constraint(scalar) { - values("0.0"); - } - } - } - } -}