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Added corner paramters to power functions. This commit does not compile (sorry)

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Hunter Nichols
2018-02-22 00:15:55 -08:00
parent d4a0f48d4f
commit beb7dad9bc
10 changed files with 34 additions and 267 deletions
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compiler/base/design.py
+4 -4
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@@ -121,10 +121,10 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
text+=str(i)+",\n"
return text
def analytical_power(self, slew, load):
def analytical_power(self, vdd, temp, load):
""" Get total power of a module """
#print "Getting power for ",self.name," module"
total_module_power = 0
for inst in self.insts:
total_module_power += inst.mod.analytical_power(slew, load)
total_module_power = self.return_power()
# for inst in self.insts:
# total_module_power += self.return_power()#inst.mod.analytical_power(vdd, temp, load)
return total_module_power
compiler/base/hierarchy_spice.py
+1 -1
View File
@@ -215,7 +215,7 @@ class spice(verilog.verilog):
def generate_rc_net(self,lump_num, wire_length, wire_width):
return wire_spice_model(lump_num, wire_length, wire_width)
def return_power(self, dynamic, leakage):
def return_power(self, dynamic=0.0, leakage=0.0):
return power_data(dynamic, leakage)
class delay_data: