From b7f1c8e8fc4b8f3328883187ba24c720ae65613f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 16 Jun 2021 19:07:56 -0700 Subject: [PATCH] Fix name for detecting single port --- compiler/characterizer/simulation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index be09ad89..9a8f00f8 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -577,7 +577,7 @@ class simulation(): Gets the signal name associated with the bitlines in the bank. """ # FIXME: change to a solution that does not depend on the technology - if OPTS.tech_name == "sky130" and self.total_ports == 1: + if OPTS.tech_name == "sky130" and len(self.all_ports) == 1: cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1") else: cell_mod = factory.create(module_type=OPTS.bitcell)