From b77f1682704263916236234a1ed202ab94ec5559 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 19 Nov 2020 15:12:02 -0800 Subject: [PATCH] Fix original pin name bug in bitcell too. --- compiler/bitcells/pbitcell.py | 3 ++- compiler/bitcells/replica_bitcell_2port.py | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index c5ac8cb6..a10af0b3 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -1120,7 +1120,7 @@ class pbitcell(bitcell_base.bitcell_base): def get_wl_name(self, port=0): """Get wl name by port""" - debug.check(port < 2, "Two ports for bitcell_1rw_1r only.") + debug.check(port < 2, "Two ports for bitcell_2port only.") return "wl{}".format(port) def get_stage_effort(self, load): @@ -1163,6 +1163,7 @@ class pbitcell(bitcell_base.bitcell_base): return pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} + # Edges added wl->bl, wl->br for every port except write ports rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names) r_pin_names = zip(self.rw_wl_names, self.rw_bl_names, self.rw_br_names) diff --git a/compiler/bitcells/replica_bitcell_2port.py b/compiler/bitcells/replica_bitcell_2port.py index 710a18d7..3a1c7cbf 100644 --- a/compiler/bitcells/replica_bitcell_2port.py +++ b/compiler/bitcells/replica_bitcell_2port.py @@ -41,7 +41,7 @@ class replica_bitcell_2port(bitcell_base.bitcell_base): def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" - pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)} + pin_dict = {pin: port for pin, port in zip(self.get_original_pin_names(), port_nets)} # Edges hardcoded here. Essentially wl->bl/br for both ports. # Port 0 edges graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)