Merge branch 'dev' into tech_migration

README.md

@@ -18,7 +18,7 @@ An open-source static random access memory (SRAM) compiler.
 # What is OpenRAM?
 <img align="right" width="25%" src="images/SCMOS_16kb_sram.jpg">
 
-OpenRAM is an open-source Python framework to create the layout,
+OpenRAM is an award winning open-source Python framework to create the layout,
 netlists, timing and power models, placement and routing models, and
 other views necessary to use SRAMs in ASIC design. OpenRAM supports
 integration in both commercial and open-source flows with both
@@ -195,7 +195,7 @@ specific technology (e.g., [FreePDK45]) should be a subdirectory
 + Report bugs by submitting [Github issues].
 + Develop new features (see [how to contribute](./CONTRIBUTING.md))
 + Submit code/fixes using a [Github pull request] 
-+ Follow our [project][Github projects].
++ Follow our [project][Github project].
 + Read and cite our [ICCAD paper][OpenRAMpaper]
 
 # Further Help
@@ -214,15 +214,7 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE).
 
 - [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
 - [James Stine] from [VLSIARCH] co-founded the project.
-- Hunter Nichols maintains and updates the timing characterization.
+- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera
-- Michael Grimes created and maintains the multiport netlist code.
-- Jennifer Sowash is creating the OpenRAM IP library.
-- Jesse Cirimelli-Low created the datasheet generation.
-- Samira Ataei created early multi-bank layouts and control logic.
-- Bin Wu created early parameterized cells.
-- Yusu Wang is porting parameterized cells to new technologies.
-- Brian Chen created early prototypes of the timing characterizer.
-- Jeff Butera created early prototypes of the bank layout.
 
 If I forgot to add you, please let me know!
 
@@ -236,7 +228,7 @@ If I forgot to add you, please let me know!
 
 [Github issues]:         https://github.com/VLSIDA/OpenRAM/issues
 [Github pull request]:   https://github.com/VLSIDA/OpenRAM/pulls
-[Github projects]:       https://github.com/VLSIDA/OpenRAM/projects
+[Github project]:       https://github.com/VLSIDA/OpenRAM
 
 [documentation]:         https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing
 [dev-group]:             mailto:openram-dev-group@ucsc.edu

compiler/base/hierarchy_layout.py

@@ -1201,10 +1201,16 @@ class layout():
         the given center location. The starting layer is specified to determine
         which vias are needed.
         """
+
+        # Force vdd/gnd via stack to be vertically or horizontally oriented
+        # Default: None, uses prefered metal directions
         if vertical:
             direction = ("V", "V")
-        else:
+        elif not vertical and vertical is not None:
             direction = ("H", "H")
+        else:
+            direction = None
+
 
         via = self.add_via_stack_center(from_layer=start_layer,
                                         to_layer=self.pwr_grid_layer,
@@ -1390,4 +1396,3 @@ class layout():
             debug.info(0, "name={0} : mod={1} : offset={2}".format(inst.name,
                                                                    inst.mod.name,
                                                                    inst.offset))
-

compiler/globals.py

@@ -19,7 +19,7 @@ import re
 import copy
 import importlib
 
-VERSION = "1.1.3"
+VERSION = "1.1.4"
 NAME = "OpenRAM v{}".format(VERSION)
 USAGE = "openram.py [options] <config file>\nUse -h for help.\n"
 

compiler/modules/bitcell_base_array.py

@@ -101,13 +101,20 @@ class bitcell_base_array(design.design):
                                     width=self.width,
                                     height=wl_pin.height())
 
-        # For every second row and column, add a via for gnd and vdd
+        # For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space
+        # Default uses prefered directions for each layer; this cell property is only currently used by s8 tech (03/20)
+        try:
+            force_power_pins_vertical = cell_properties.bitcell_force_power_pins_vertical
+        except AttributeError:
+            force_power_pins_vertical = None
+
+        # Add vdd/gnd via stacks
         for row in range(self.row_size):
             for col in range(self.column_size):
                 inst = self.cell_inst[row,col]
                 for pin_name in ["vdd", "gnd"]:
                     for pin in inst.get_pins(pin_name):
-                        self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer)
+                        self.add_power_pin(name=pin_name, loc=pin.center(), vertical=force_power_pins_vertical, start_layer=pin.layer)
 
     def _adjust_x_offset(self, xoffset, col, col_offset):
         tempx = xoffset